MC33887/D 20-LEAD 54-LEAD 44-LEAD PC33887DH/R2 PC33887FC/R2 PC33887DWB/R2 - Datasheet Archive

 

Order this document from Analog Marketing: MC33887/D Rev 2, 08/2002 SEMICONDUCTOR TECHNICAL DATA Preliminary Information 33887

 

MOTOROLA Order this document from Analog Marketing: MC33887/D MC33887/D Rev 2, 08/2002 SEMICONDUCTOR TECHNICAL DATA Preliminary Information 33887 6.0 A H-Bridge with Enable The 33887 is a monolithic H-Bridge with a Sleep Mode feature ideal for fractional horsepower DC-motor and bi-directional thrust solenoid control. The IC incorporates internal control logic, charge pump, gate drive, and low RDS(ON) MOSFET output circuitry. The 33887 is able to control continuous inductive DC load currents of 6.0 A. Output loads can be Pulse Width Modulation (PWM) controlled at frequencies to 10 kHz. An internal output current monitoring circuit provides a proportional (1/375th) feedback current output for the microcontroller to monitor the output current and provide closedloop control. 6.0 A H-BRIDGE WITH ENABLE A Fault Status output reports undervoltage, overcurrent, and overtemperature conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two disable inputs force the H-Bridge outputs to tristate (exhibit high impedance). The 33887 is parametrically specified over a temperature range of -40°C TA 125°C, 5.0 V VPWR 28 V, and is available in three different surface mount packages. Features · 5.0 V to 36 V Operation · 120 m RDS(ON) H-Bridge Switches · TTL/CMOS Compatible Inputs · PWM Frequencies to 10 kHz · Automatic PWM Overcurrent Limiting · Output Short Circuit Protection · Overtemperature Output Current Reduction with Shutdown · Undervoltage Shutdown · Fault Status Reporting · High-Side Current Feedback Output Provides Real-Time Current Monitoring DH SUFFIX 20-LEAD 20-LEAD HSOP CASE 979C 1 2 3 4 5 AGND FS IN1 VPWR VPWR 6 7 8 9 10 11 12 13 14 15 16 OUT1 OUT1 FB PGND PGND PGND PGND D2 OUT2 OUT2 VPWR CCP D1 IN2 EN QFN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FB PGND PGND PGND PGND PGND PGND PGND PGND D2 OUT2 OUT2 NC NC NC NC OUT2 OUT2 VPWR 21 CCP 22 D1 5.0 V FS EN IN1 IN2 D1 D2 FB 23 24 25 26 27 28 SOIC IN2 EN NC NC VPWR VPWR 29 VPWR 30 VPWR 31 32 33 34 35 36 NC NC AGND FS IN1 VPWR 37 VPWR 38 39 40 41 42 43 44 OUT1 OUT1 NC OUT1 OUT1 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PGND PGND PGND PGND NC NC NC D2 NC OUT2 OUT2 OUT2 OUT2 NC VPWR 28 29 30 31 32 33 34 35 36 37 39 VPWR 40 VPWR 41 42 43 44 45 46 47 48 49 50 51 52 53 54 18 VPWR 19 20 21 22 23 NC NC AGND FS IN1 NC NC NC NC VPWR 38 VPWR 16 VPWR 17 VPWR NC NC NC NC CCP 24 25 26 27 20 VPWR VPWR CCP DWB SUFFIX 54-LEAD 54-LEAD SOIC-EP CASE 1377 PIN CONNECTIONS HSOP 17 18 19 20 33887 Simplified Application Diagram FC SUFFIX 44-LEAD 44-LEAD QFN CASE 1310 D1 IN2 EN NC NC OUT1 OUT1 OUT1 OUT1 NC FB NC NC NC PGND PGND PGND PGND VPWR OUT1 ORDERING INFORMATION Motor OUT2 GND This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc. 2002 Temperature Range (TA) Package PC33887DH/R2 PC33887DH/R2 -40 to 125°C 20 HSOP PC33887FC/R2 PC33887FC/R2 -40 to 125°C 44 QFN PC33887DWB/R2 PC33887DWB/R2 MCU or DSP -40 to 125°C 54 SOIC-EP Device CCP VPWR Charge Pump 80 uA (each) Current Limit, Overcurrent Sense, & Feedback Circuit 5.0 V Regulator OUT1 IN1 IN2 Gate Drive OUT2 D1 D2 25 uA Control Logic Over Temperature Undervoltage FS FB AGND PGND Figure 1. 33887 Internal Block Diagram PIN FUNCTION DESCRIPTION HSOP QFN SOIC Pin Name 1 33 30 AGND 2 34 31 FS Open drain active LOW Fault Status output requiring a pull-up resistor to 5.0 V. 3 35 32 IN1 True Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). 4, 5, 16 19, 20, 27­30 15­18, 37­40 VPWR Positive power source connection. 6, 7 38, 39, 41, 42 42­45 OUT1 H-Bridge output 1. 8 1 47 FB 9­12 2­9, 36, 37 1­4, 51­54 PGND 13 10 8 D2 14, 15 11, 12, 17, 18 10­13 OUT2 17 21 23 CCP External reservoir capacitor connection for internal Charge Pump. 18 22 24 D1 Active HIGH input used to simultaneously tristate disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tristate. 19 23 25 IN2 True Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). 20 24 26 EN True Logic input Enable control of device (i.e., EN logic High = Full Operation, EN logic LOW = Sleep Mode). ­ 13­16, 25, 26, 31, 32, 40, 43, 44 5­7, 9, 14, 19­22, 27­29, 33­36, 41, 46, 48­50 NC No internal connection to this pin. 33887 2 Description Low current Analog signal ground. Current sensing feedback output providing ground referenced 1/375th (0.00266) of H-Bridge high-side output current. Device high current power ground. Active LOW input used to simultaneously tristate disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tristate. H-Bridge output 2. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit VPWR(SS) 36 V VPWR(t) 40 Input Voltage (Note 2) VIN 7.0 V FS Status Output (Note 3) V FS 7.0 V IOUT(CONT) 6.0 A VESD1 TBD V VESD2 200 TSTG -65 to 150 °C Ambient Temperature (Note 7) TA -40 to 125 °C Operating Junction Temperature TJ -40 to 150 °C TSOLDER 260 °C Power Supply Voltage Normal Operation (Steady-State) Transient (Note 1) Continuous Output Current (Note 4) ESD Voltage Human Body Model (Note 5) Machine Model (Note 6) Storage Temperature Lead Soldering Temperature (Note 8) Approximate Junction-to-Board Thermal Resistance (Note 9) RJ-B HSOP QFN SO-EP Notes: 1. 2. 3. 4. 5. ~5.0 ~18 °C/W ~12 Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device. Exceeding the pull-up resistor voltage on the open Drain FS pin may cause permanent damage to the device. Continuous output current capability so long as junction temperature is 150°C. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 100 pF, RZAP = 0 ). 7. 8. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. Lead soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Exposed heat sink pad plus the power and ground terminals comprise the main heat conduction paths. The actual RJ-B (junction-to-PC board) values will vary depending on solder thickness and composition and copper trace. 9. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 3 STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V VPWR 28 V and -40°C TA 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Steady-State Transient (t < 500 ms) (Note 11) VPWR(SS) 5.0 ­ 36 V VPWR(t) ­ ­ 40 V Sleep State Supply Current (Note 12) IPWR(sleep) ­ 25 50 µA ­ ­ 20 mA 4.15 4.4 4.65 V VPWR(thres-ON) 4.5 4.75 5.0 V VPWR(hys) 150 ­ ­ mV VCP - VPWR 3.35 ­ ­ V ­ ­ 20 V VIH 3.5 ­ ­ V VIL ­ ­ 1.4 V VHYS 0.7 1.0 ­ V IIN -200 -80 ­ µA I D2 ­ 25 100 µA Power Supply Operating Voltage Range (Note 10) VEN = 0 V, ILOUT = 0 A Standby Supply Current IPWR(standby) ILOUT = 0 A, VEN = 5.0 V Threshold Supply Voltage Switch-OFF Switch-ON Hysteresis VPWR(thres-OFF) Charge Pump Charge Pump Voltage VPWR = 4.15 V VPWR < 40 V Control Inputs Input Voltage (IN1, IN2, D1, D2) Threshold HIGH Threshold LOW Hysteresis Input Current (IN1, IN2, D1) VIN - 0.0 V Input Current (D2, EN) V D2 = 5.0 V Notes: 10. Parameter is guaranteed by design but not production tested. 11. Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. 12. IPWR(sleep) is with sleep mode function Enabled. 33887 4 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 5.0 V VPWR 28 V and -40°C TA 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit 5.0 V < VPWR < 28 V, TJ = 25°C ­ 8.0 V < VPWR < 28 V, TJ = 150°C ­ 120 ­ m ­ 225 ­ ­ 300 m m 5.0 V < VPWR < 8.0 V, TJ = 150°C ILATCH-OFF 6.0 7.0 8.5 A Output Latch-OFF Time ta 15 20.5 26 µs Output Blanking Time tb 12 16.5 21 µs High-Side Overcurrent Detection IOCD(H) 11 ­ ­ A Low-Side Overcurrent Detection IOCD(L) 9.0 ­ ­ A VOUT = VPWR ­ 100 200 µA VOUT = GND ­ 30 60 µA ­ ­ 2.0 V trr 100 ­ ­ ns TLIM 175 ­ ­ °C THYS 10 ­ 30 °C Power Outputs (OUT1, OUT2) Output-ON Resistance (Note 13) Output Latch-OFF Current Leakage Current (Note 14) Free-Wheeling Diode Forward Voltage Drop (Note 15) ROUT IOUT(leak) VF IOUT = 3.0 A Free-Wheeling Diode Reverse Recovery Time (Note 15) Switch-OFF Thermal Shutdown Hysteresis Notes: 13. Output-ON resistance as measured from output to VPWR and GND. 14. 15. Outputs switched OFF with D1 or D2. Parameter is guaranteed by design but not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 5 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 5.0 V VPWR 28 V and -40°C TA 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit High-Side Current Sense Feedback Feedback Current I FB ­ ­ 600 µA I LOAD = 500 mA 1.07 -1.33 1.60 mA I LOAD = 1.5 A 3.6 4.0 4.4 mA I LOAD = 3.0 A 7.2 8.0 8.8 mA I LOAD = 6.0 A 14.4 16.0 17.6 mA ­ ­ 10 µA ­ ­ 1.0 V I LOAD = 0 mA Fault Status (Note 16) Fault Status Leakage Current (Note 17) I FS(leak) V FS = 5.0 V Fault Status SET Voltage (Note 18) V FS(LOW) I FS = 300 µA Notes: 16. Fault Status output is an open Drain output requiring a pull-up resistor to 5.0 V. 17. Fault Status Leakage Current is measured with Fault Status HIGH and not SET. 18. Fault Status Set Voltage is measured with Fault Status LOW and SET with I FS = 300 µA. 33887 6 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V VPWR 28 V and -40°C TA 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit PWM Frequency (Note 19) fPWM ­ ­ 10 kHz Maximum Switching Frequency During Current Limit (Note 20) fMAX ­ ­ 20 kHz Output ON Delay (Note 21) td(ON) ­ ­ 18 µs ­ ­ 18 µs 2.0 5.0 8.0 µs td(disable) ­ ­ 8.0 µs tFAULT ­ 4.0 ­ µs tpod ­ 1.0 5.0 ms Timing Characteristics VPWR = 14 V Output OFF Delay (Note 21) td(OFF) VPWR = 14 V Output Rise and Fall Time (Note 22) tf, tr VPWR = 14 V, Iout = 3.0 A Disable Delay Time (Note 23) Over-Current/Temperature Turn-OFF Time (Note 24) Power-OFF Delay Time (Note 25) Notes: 19. The outputs can be PWM controlled from an external source. The PWM Frequency is the externally induced output switching frequency, the maximum frequency of which is limited by the internal charge pump. 20. The Maximum Switching Frequency during Current Limit is internally implemented. The internal control produces a constant OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency. 21. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the 10% point of the output response signal. See Figure 3. 22. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4. 23. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tristate response. See Figure 3. 24. Increasing output currents will become limited at 6.5 A. Hard shorts will breach the 6.5 A limit, forcing the output into an immediate tristate latch-OFF. See Figure 5 and Figure 6. Output current limiting will cause junction temperatures to rise. A junction temperature above 160°C will cause the output current limit to progressively "fold-back" or decrease to 2.5 A typical at 175°C where thermal latch-OFF will occur. See Figure 7. 25. This parameter has been characterized but is not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 7 VIN1, IN2 (V) 5.0 50% VOUT1, 2 (V) 0 50% td(OFF) td(ON) VPWR 90% 10% 0 TIME Figure 2. Output Delay Time VOUT1, 2 (V) Figure 3. Disable Delay Time V PWR tf tr 90% 90% 10% 10% 0 Figure 4. Output Switching Time 33887 8 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA ILOAD, OUTPUT CURRENT (A) IN, LOGIC IN D1, LOGIC IN D2, LOGIC IN FS, FAULT STATUS 8.0 Overcurrent (Minimum) 6.5 Hard Output Short Latch-OFF PWM Current Limiting (See Figure 6.) 0 [1] IN1 IN2 OR [0] IN2 IN1 [1] [0] [1] [0] [1] Outputs Operational (per Input Control Condition) Outputs Tristate Latched (H-Bridge Switches OFF) [0] TIME ILOAD, OUTPUT CURRENT (A) Figure 5. Output Load Current Limiting Versus Time 8.0 Overcurrent Minimum Threshold ta tb ta = Tristate Output OFF Time tb = Current Limit Blank Time 6.5 Typical PWM Load Current Limiting Waveform Hard Output Short Latch-OFF TIME Figure 6. PWM Current Limiting Detail MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 9 IMAX, OUTPUT CURRENT (A) 6.6 2.5 Thermal Shutdown 160 175 T J, JUNCTION TEMPERATURE (o C) Figure 7. Maximum Output Current Limiting Versus Temperature 33887 10 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Table 1. Truth Table The tristate conditions and the fault status are reset using D1 or D2. The truth table uses the following notations: L = Low, H = High, X = High or Low, and Z = High impedance (all output power transistors are switched off). Input Conditions Device State Status Outputs EN D1 D2 IN1 IN2 FS OUT1 OUT2 Forward H L H H L H H L Reverse H L H L H H L H Free Wheeling Low H L H L L H L L Free Wheeling High H L H H H H H H Disable 1 (D1) H H X X X L Z Z Disable 2 (D2) H X L X X L Z Z IN1 Disconnected H L H Z X H H X IN2 Disconnected H L H X Z H X H D1 Disconnected H Z X X X L Z Z D2 Disconnected H X Z X X L Z Z Undervoltage (Note 26) H X X X X L Z Z Overtemperature (Note 27) H X X X X L Z Z Overcurrent (Note 27) H X X X X L Z Z Sleep Mode EN L X X X X H Z Z EN Disconnected Z X X X X H Z Z Notes: 26. In the case of an undervoltage condition, the outputs tristate and the fault status is SET logic LOW. Upon undervoltage recovery, fault status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 27. When an overcurrent or overtemperature condition is detected, the power outputs are tristate latched-OFF independent of the input signals and the fault status flag is SET logic LOW. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 11 SYSTEM/APPLICATION INFORMATION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closedloop control), in addition to the 6.0 A output current capability, make the 33887 a very attractive cost-effective solution for controlling a broad range of fractional horsepower DC-motors. A pair of 33887 devices can be used to control bipolar stepper motors in both directions. In addition, the 33887 can be used to control permanent magnet solenoids in a push-pull variable force fashion using PWM control. The 33887 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 1, Internal Block Diagram, the 33887 is a fully protected monolithic H-Bridge with Enable, Fault Status reporting, and High-Side current sense feedback to accommodate closed-loop PWM control. For a DC-motor to run the input conditions need be as follows: Enable input logic HIGH, D1 input logic LOW, D2 input logic HIGH, FS flag cleared (logic HIGH), with one IN logic LOW and the IN other logic HIGH to define output polarity. The 33887 can execute Dynamic Breaking by simultaneously turning-ON either the two HighSide or the two Low-Side H-Bridge switches; e.g., IN1 and IN2 logic HIGH or IN1 and IN2 logic LOW. The 33887 outputs are capable of providing a continuous DC load current of 6.0 A from a 36 V VPWR source. An internal charge pump supports PWM frequencies to 10 kHz. An external pull-up resistor is required for the open drain FS pin for fault status reporting. The 33887 has a current feedback output (FB) for "real time" monitoring of output current to facilitate closedloop operation for motor speed and torque control. Two independent inputs (IN1 and IN2) provide control of the two totem-pole half-bridge outputs. Two disable inputs (D1 and D2) are for forcing the H-Bridge outputs to a high impedance state (all H-Bridge switches OFF). An EN pin controls an enable function that allows the 33887 to be placed in a powerconserving sleep mode. The 33887 has Undervoltage Shutdown with automatic recovery, Output Current Limiting, Output Short-Circuit LatchOFF, and Overtemperature Latch-OFF. An Undervoltage Shutdown, Output Short-Circuit Latch-OFF, or Overtemperature Latch-OFF fault condition will cause the outputs to turn-OFF (tristate) and the fault output flag to be set LOW. Either of the D inputs or VPWR must be "toggled" to clear the fault flag. The Overcurrent/Overtemperature Shutdown scheme is unique and best described as using a junction temperature dependent output current "fold back" protection scheme. When an overcurrent condition is experienced, the current limited output is "ramped down" as the junction temperature increases above 160°C, until at 175°C the output current has decreased to about 2.5 A. Above 175°C, the Overtemperature Shutdown (Latch-OFF) occurs. This feature allows the device to remain in operation for a longer time with unexpected loads, but with regressive output performance at junction temperatures above 160°C. FUNCTIONAL PIN DESCRIPTION PGND and AGND Fault Status (FS) Power and analog ground pins. The power and analog ground pins should be connected together with a very low impedance connection. This pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to 5.0 V. Refer to Table 1, Truth Table. VPWR IN1, IN2, D1, D2 VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. These pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complimentary inputs used to tristate disable the H-Bridge outputs. VPWR pins have an undervoltage threshold. If the supply voltage drops below a VPWR undervoltage threshold, the output power stage switches to a tristate condition and the fault status flag is SET and the Fault Status pin voltage switched to a logic LOW. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault status flag is automatically reset logic HIGH. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tristate disabled; however, the rest of the device circuitry is fully operational and the supply IPWR(standby) current is reduced to a few milli-amperes. See Table 1, Truth Table, and STATIC ELECTRICAL CHARACTERISTICS (continued) table. OUT1, OUT2 These pins are the outputs of the H-Bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The outputs have Pulse Width 33887 12 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Modulated (PWM) current limiting above 6.5 A. The outputs also have thermal shutdown (tristate latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time tb) incorporated to detect currents that are higher than current limit is activated at each output activation to facilitate detecting hard output short conditions. See Figure 6. CCP Charge pump output pin. A filter capacitor (up to 33 nF) can be connected from the CCP pin and PGND. The device can operate without the external capacitor, although the CCP capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and PWM frequency. EN The EN pin is used to place the device in a sleep mode so as to consume very low currents. When the EN pin voltage is a logic LOW state, the device is in the sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pull-down resistor maintains the device in sleep mode in the event EN is driven through a high impedance I/O or an unpowered microcontroller, or the EN input becomes disconnected. FB The device has a feedback output (FB) for "real time" monitoring of H-Bridge high-side output currents to facilitate closed-loop operation for motor speed and torque control. The FB pin provides current sensing feedback of the HBridge high-side drivers. When running in the forward or reverse direction, a ground referenced 1/375th (0.00266) of load current is output to this pin. Through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can "read" the current proportional voltage with its analog to digital converter (ADC). This is intended to provide the user with motor current feedback for motor torque control. The accuracy is ± 20% at load currents 1.5 A. If PWM-ing is implemented using the disable pin inputs (either D1 or D2), a small filter capacitor (