MC145151 MC145151-2 MC145152-2 MC145155-2 MC145156-2 MC145157-2 MC145158-2 - Datasheet Archive

 

Order this document by MC145151­2/D SEMICONDUCTOR TECHNICAL DATA MC145151-2 MC145152-2 MC145155-2 MC145156-2 MC145157-2

 

MOTOROLA Order this document by MC145151 MC145151­2/D SEMICONDUCTOR TECHNICAL DATA MC145151-2 MC145151-2 MC145152-2 MC145152-2 MC145155-2 MC145155-2 MC145156-2 MC145156-2 MC145157-2 MC145157-2 MC145158-2 MC145158-2 PLL Frequency Synthesizer Family CMOS The devices described in this document are typically used as low­power, phase­locked loop frequency synthesizers. When combined with an external low­pass filter and voltage­controlled oscillator, these devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher VCO frequency operation, a down mixer or a prescaler can be used between the VCO and the synthesizer IC. These frequency synthesizer chips can be found in the following and other applications: CATV TV Tuning AM/FM Radios Scanning Receivers Two­Way Radios Amateur Radio ÷R OSC CONTROL LOGIC ÷A ÷N ÷ P/P + 1 VCO OUTPUT FREQUENCY CONTENTS Page DEVICE DETAIL SHEETS MC145151 MC145151­2 Parallel­Input, Single­Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 MC145152 MC145152­2 Parallel­Input, Dual­Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MC145155 MC145155­2 Serial­Input, Single­Modulus (Not Recommended for New Designs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MC145156 MC145156­2 Serial­Input, Dual­Modulus (Not Recommended for New Designs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MC145157 MC145157­2 Serial­Input, Single­Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MC145158 MC145158­2 Serial­Input, Dual­Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FAMILY CHARACTERISTICS Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Detector/Lock Detector Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 25 26 27 27 DESIGN CONSIDERATIONS Phase­Locked Loop - Low­Pass Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Crystal Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Dual­Modulus Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 REV 3 1/99 © Motorola, Inc. 1998 MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 1 MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC145151-2 MC145151-2 Parallel-Input PLL Frequency Synthesizer P SUFFIX PLASTIC DIP CASE 710 Interfaces with Single­Modulus Prescalers 28 The MC145151 MC145151­2 is programmed by 14 parallel­input data lines for the N counter and three input lines for the R counter. The device features consist of a reference oscillator, selectable­reference divider, digital­phase detector, and 14­bit programmable divide­by­N counter. The MC145151 MC145151­2 is an improved­performance drop­in replacement for the MC145151 MC145151­1. The power consumption has decreased and ESD and latch­up performance have improved. · · · · · · · · · · · · Operating Temperature Range: ­ 40 to 85°C Low Power Consumption Through Use of CMOS Technology 3.0 to 9.0 V Supply Range On­ or Off­Chip Reference Oscillator Operation Lock Detect Signal ÷ N Counter Output Available Single Modulus/Parallel Programming 8 User­Selectable ÷ R Values: 8, 128, 256, 512, 1024, 2048, 2410, 8192 ÷ N Range = 3 to 16383 "Linearized" Digital Phase Detector Enhances Transfer Function Linearity Two Error Signal Options: Single­Ended (Three­State) or Double­Ended Chip Complexity: 8000 FETs or 2000 Equivalent Gates 1 DW SUFFIX SOG PACKAGE CASE 751F 28 1 ORDERING INFORMATION MC145151P2 MC145151P2 MC145151DW2 MC145151DW2 Plastic DIP SOG Package PIN ASSIGNMENT fin 1 28 LD VSS 2 27 OSCin VDD 3 26 OSCout PDout 4 25 N11 RA0 5 24 N10 RA1 6 23 N13 RA2 7 22 N12 R 8 21 T/R V 9 20 N9 fV 10 19 N8 N0 11 18 N7 N1 12 17 N6 N2 13 16 N5 N3 14 15 N4 REV 1 8/95 © Motorola, Inc. 1995 MC145151 MC145151­2 through MC145158 MC145158­2 2 MOTOROLA MC145151 MC145151­2 BLOCK DIAGRAM RA2 RA1 RA0 OSCout 14 x 8 ROM REFERENCE DECODER LOCK DETECT 14 LD 14­BIT ÷ R COUNTER OSCin PHASE DETECTOR A PDout 14­BIT ÷ N COUNTER fin VDD PHASE DETECTOR B 14 TRANSMIT OFFSET ADDER T/R V R fV N13 N11 N9 N7 N6 N4 N2 N0 NOTE: N0 ­ N13 inputs and inputs RA0, RA1, and RA2 have pull­up resistors that are not shown. sure that inputs left open remain at a logic 1 and require only an SPST switch to alter data to the zero state. PIN DESCRIPTIONS INPUT PINS fin Frequency Input (Pin 1) T/R Transmit/Receive Offset Adder Input (Pin 21) Input to the ÷ N portion of the synthesizer. fin is typically derived from loop VCO and is ac coupled into the device. For larger amplitude signals (standard CMOS logic levels) dc coupling may be used. This input controls the offset added to the data provided at the N inputs. This is normally used for offsetting the VCO frequency by an amount equal to the IF frequency of the transceiver. This offset is fixed at 856 when T/R is low and gives no offset when T/R is high. A pull­up resistor ensures that no connection will appear as a logic 1 causing no offset addition. RA0 ­ RA2 Reference Address Inputs (Pins 5, 6, 7) These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below. Pull­up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. RA2 RA1 RA0 Total Divide Value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 128 256 512 1024 2048 2410 8192 Reference Address Code N0 ­ N11 N Counter Programming Inputs (Pins 11 ­ 20, 22 ­ 25) These inputs provide the data that is preset into the ÷ N counter when it reaches the count of zero. N0 is the least significant and N13 is the most significant. Pull­up resistors en- MOTOROLA OSCin, OSCout Reference Oscillator Input/Output (Pins 27, 26) These pins form an on­chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC in to ground and OSC out to ground. OSC in may also serve as the input for an externally­generated reference signal. This signal is typically ac coupled to OSC in, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC out. OUTPUT PINS PDout Phase Detector A Output (Pin 4) Three­state output of phase detector for use as loop­error signal. Double­ended outputs are also available for this purpose (see V and R). Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High­Impedance State MC145151 MC145151­2 through MC145158 MC145158­2 3 R, V Phase Detector B Outputs (Pins 8, 9) nally connected to the phase detector input. With this output available, the ÷ N counter can be used independently. These phase detector outputs can be combined externally for a loop­error signal. A single­ended output is also available for this purpose (see PDout ). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by V pulsing low. R remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by R pulsing low. V remains essentially high. If the frequency of fV = fR and both are in phase, then both V and R remain high except for a small minimum time period when both pulse low in phase. LD Lock Detector Output (Pin 28) Essentially a high level when loop is locked (fR, fV of same phase and frequency). Pulses low when loop is out of lock. POWER SUPPLY VDD Positive Power Supply (Pin 3) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. VSS Negative Power Supply (Pin 2) fV N Counter Output (Pin 10) The most negative supply potential. This pin is usually ground. This is the buffered output of the ÷ N counter that is inter- TYPICAL APPLICATIONS 2.048 MHz NC OSCin OSCout RA2 RA1 fin NC RA0 MC145151 MC145151­2 VOLTAGE CONTROLLED OSCILLATOR PDout N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 5 ­ 5.5 MHz 0 1 1 1 0 0 0 1 0 0 0 = 5 MHz 1 0 1 0 1 1 1 1 1 0 0 = 5.5 MHz Figure 1. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz LOCK DETECT SIGNAL "1" OSCout RA2 +V REF. OSC. 10.0417 MHz (ON­CHIP OSC. OPTIONAL) OSCin VDD VSS "1" "0" RA1 RA0 LD fV PDout R fV fin MC145151 MC145151­2 T/R CHOICE OF DETECTOR ERROR SIGNALS LOOP FILTER T: 13.0833 ­ 18.0833 MHz R: 9.5167 ­ 14.5167 MHz TRANSMIT (ADDS 856 TO ÷ N VALUE) VCO X6 T: 73.3333 ­ 78.3333 MHz R: 69.7667 ­ 74.7667 MHz DOWN MIXER "0" "0" "1" RECEIVE TRANSMIT: 440.0 ­ 470.0 MHz RECEIVE: 418.6 ­ 448.6 MHz (25 kHz STEPS) CHANNEL PROGRAMMING ÷ N = 2284 TO 3484 X6 60.2500 MHz NOTES: 1. fR = 4.1667 kHz; ÷ R = 2410; 21.4 MHz low side injection during receive. 2. Frequency values shown are for the 440 ­ 470 MHz band. Similar implementation applies to the 406 ­ 440 MHz band. For 470 ­ 512 MHz, consider reference oscillator frequency X9 for mixer injection signal (90.3750 MHz). Figure 2. Synthesizer for Land Mobile Radio UHF Bands MC145151 MC145151­2 Data Sheet Continued on Page 23 MC145151 MC145151­2 through MC145158 MC145158­2 4 MOTOROLA MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC145152-2 MC145152-2 Parallel-Input PLL Frequency Synthesizer P SUFFIX PLASTIC DIP CASE 710 Interfaces with Dual­Modulus Prescalers 28 The MC145152 MC145152­2 is programmed by sixteen parallel inputs for the N and A counters and three input lines for the R counter. The device features consist of a reference oscillator, selectable­reference divider, two­output phase detector, 10­bit programmable divide­by­N counter, and 6­bit programmable ÷ A counter. The MC145152 MC145152­2 is an improved­performance drop­in replacement for the MC145152 MC145152­1. Power consumption has decreased and ESD and latch­up performance have improved. · · · · · · · · · · Operating Temperature Range: ­ 40 to 85°C Low Power Consumption Through Use of CMOS Technology 3.0 to 9.0 V Supply Range On­ or Off­Chip Reference Oscillator Operation Lock Detect Signal Dual Modulus/Parallel Programming 8 User­Selectable ÷ R Values: 8, 64, 128, 256, 512, 1024, 1160, 2048 ÷ N Range = 3 to 1023, ÷ A Range = 0 to 63 Chip Complexity: 8000 FETs or 2000 Equivalent Gates See Application Note AN980 AN980 1 DW SUFFIX SOG PACKAGE CASE 751F 28 1 ORDERING INFORMATION MC145152P2 MC145152P2 MC145152DW2 MC145152DW2 Plastic DIP SOG Package PIN ASSIGNMENT fin 1 28 LD VSS 2 27 OSCin VDD 3 26 OSCout RA0 4 25 A4 RA1 5 24 A3 RA2 6 23 A0 R 7 22 A2 V 8 21 A1 MC 9 20 N9 A5 10 19 N8 N0 11 18 N7 N1 12 17 N6 N2 13 16 N5 N3 14 15 N4 REV 1 8/95 © Motorola, Inc. 1995 MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 5 MC145152 MC145152­2 BLOCK DIAGRAM RA2 RA1 RA0 OSCout 12 x 8 ROM REFERENCE DECODER 12 LOCK DETECT 12­BIT ÷ R COUNTER OSCin LD MC CONTROL LOGIC PHASE DETECTOR V R fin 6­BIT ÷ A COUNTER A5 A3 A2 A0 10­BIT ÷ N COUNTER N0 N2 N4 N5 N7 N9 NOTE: N0 ­ N9, A0 ­ A5, and RA0 ­ RA2 have pull­up resistors that are not shown. Prescaling section). The A inputs all have internal pull­up resistors that ensure that inputs left open will remain at a logic 1. PIN DESCRIPTIONS INPUT PINS fin Frequency Input (Pin 1) Input to the positive edge triggered ÷ N and ÷ A counters. fin is typically derived from a dual­modulus prescaler and is ac coupled into the device. For larger amplitude signals (standard CMOS logic levels) dc coupling may be used. RA0, RA1, RA2 Reference Address Inputs (Pins 4, 5, 6) These three inputs establish a code defining one of eight possible divide values for the total reference divider. The total reference divide values are as follows: OSCin, OSCout Reference Oscillator Input/Output (Pins 27, 26) These pins form an on­chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC in to ground and OSC out to ground. OSC in may also serve as the input for an externally­generated reference signal. This signal is typically ac coupled to OSC in, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSCout. OUTPUT PINS RA2 RA1 RA0 Total Divide Value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 64 128 256 512 1024 1160 2048 Reference Address Code N0 ­ N9 N Counter Programming Inputs (Pins 11 ­ 20) The N inputs provide the data that is preset into the ÷ N counter when it reaches the count of 0. N0 is the least significant digit and N9 is the most significant. Pull­up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. A0 ­ A5 A Counter Programming Inputs (Pins 23, 21, 22, 24, 25, 10) The A inputs define the number of clock cycles of fin that require a logic 0 on the MC output (see Dual­Modulus MC145151 MC145151­2 through MC145158 MC145158­2 6 R, V Phase Detector B Outputs (Pins 7, 8) These phase detector outputs can be combined externally for a loop­error signal. If the frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by V pulsing low. R remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by R pulsing low. V remains essentially high. If the frequency of fV = fR and both are in phase, then both V and R remain high except for a small minimum time period when both pulse low in phase. MC Dual­Modulus Prescale Control Output (Pin 9) Signal generated by the on­chip control logic circuitry for controlling an external dual­modulus prescaler. The MC level will be low at the beginning of a count cycle and will remain low until the ÷ A counter has counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N counter has counted the rest of the way down from its programmed value (N ­ A additional counts since both ÷ N and ÷ A are counting down during the first MOTOROLA portion of the cycle). MC is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (NT) = N · P + A where P and P + 1 represent the dual­modulus prescaler divide values respectively for high and low MC levels, N the number programmed into the ÷ N counter, and A the number programmed into the ÷ A counter. POWER SUPPLY LD Lock Detector Output (Pin 28) VSS Negative Power Supply (Pin 2) Essentially a high level when loop is locked (fR, fV of same phase and frequency). Pulses low when loop is out of lock. The most negative supply potential. This pin is usually ground. VDD Positive Power Supply (Pin 3) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. TYPICAL APPLICATIONS NO CONNECTS "1" "1" "1" R2 OSCout RA2 RA1 RA0 LD R OSCin V MC145152 MC145152­2 VDD MC VSS +V fin N9 N0 A5 150 ­ 175 MHz 5 kHz STEPS LOCK DETECT SIGNAL 10.24 MHz NOTE 1 C R1 ­ R1 VCO + R2 MC33171 MC33171 NOTE 2 C A0 MC12017 MC12017 ÷ 64/65 PRESCALER CHANNEL PROGRAMMING NOTES: 1. Off­chip oscillator optional. 2. The R and V outputs are fed to an external combiner/loop filter. See the Phase­Locked Loop - Low­Pass Filter Design page for additional information. The R and V outputs swing rail­to­rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 1. Synthesizer for Land Mobile Radio VHF Bands MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 7 REF. OSC. 15.360 MHz (ON­CHIP OSC. OPTIONAL) RECEIVER 2ND L.O. 30.720 MHz NO CONNECTS X2 "1" "1" "1" R2 OSCout RA2 RA1 RA0 +V VDD VSS LD R OSCin MC145152 MC145152­2 NOTE 5 V MC fin N9 N0 A5 CHANNEL PROGRAMMING RECEIVER FIRST L.O. 825.030 844.980 MHz (30 kHz STEPS) LOCK DETECT SIGNAL A0 C R1 ­ X4 NOTE 6 VCO R1 + NOTE 7 R2 C TRANSMITTER MODULATION MC12017 MC12017 ÷ 64/65 PRESCALER NOTE 6 X4 NOTE 6 TRANSMITTER SIGNAL 825.030 844.980 MHz (30 kHz STEPS) NOTES: 1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection. 2. Duplex operation with 45 MHz receiver/transmit separation. 3. fR = 7.5 kHz; ÷ R = 2048. 4. Ntotal = N 64 + A = 27501 to 28166; N = 429 to 440; A = 0 to 63. 5. MC145158 MC145158­2 may be used where serial data entry is desired. 6. High frequency prescalers (e.g., MC12018 MC12018 [520 MHz] and MC12022 MC12022 [1 GHz]) may be used for higher frequency VCO and fref implementations. 7. The R and V outputs are fed to an external combiner/loop filter. See the Phase­Locked Loop - Low­Pass Filter Design page for additional information. The R and V outputs swing rail­to­rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 2. 666­Channel, Computer­Controlled, Mobile Radiotelephone Synthesizer for 800 MHz Cellular Radio Systems MC145152 MC145152­2 Data Sheet Continued on Page 23 MC145151 MC145151­2 through MC145158 MC145158­2 8 MOTOROLA MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC145155-2 MC145155-2 Serial-Input PLL Frequency Synthesizer P SUFFIX PLASTIC DIP CASE 707 Interfaces with Single­Modulus Prescalers The MC145155 MC145155­2 is programmed by a clocked, serial input, 16­bit data stream. The device features consist of a reference oscillator, selectable­reference divider, digital­phase detector, 14­bit programmable divide­by­N counter, and the necessary shift register and latch circuitry for accepting serial input data. The MC145155 MC145155­2 is an improved­performance drop­in replacement for the MC145155 MC145155­1. Power consumption has decreased and ESD and latch­up performance have improved. · · · · · · · · · · · · · Operating Temperature Range: ­ 40 to 85°C Low Power Consumption Through Use of CMOS Technology 3.0 to 9.0 V Supply Range On­ or Off­Chip Reference Oscillator Operation with Buffered Output Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs Lock Detect Signal Two Open­Drain Switch Outputs 8 User­Selectable ÷ R Values: 16, 512, 1024, 2048, 3668, 4096, 6144, 8192 Single Modulus/Serial Programming ÷ N Range = 3 to 16383 "Linearized" Digital Phase Detector Enhances Transfer Function Linearity Two Error Signal Options: Single­Ended (Three­State) or Double­Ended Chip Complexity: 6504 FETs or 1626 Equivalent Gates 18 1 DW SUFFIX SOG PACKAGE CASE 751D 20 1 ORDERING INFORMATION MC145155P2 MC145155P2 MC145155DW2 MC145155DW2 Plastic DIP SOG Package PIN ASSIGNMENTS PLASTIC DIP RA1 1 18 RA0 RA2 2 17 OSCin V 3 16 OSCout R 4 15 REFout NOT RECOMMENDED FOR NEW DESIGNS; PRODUCT TO BE PHASED OUT. Closest equivalents are the MC145157 MC145157­2, MC145170 MC145170­2, MC14519X MC14519X series, and MC14520X MC14520X series. VDD 5 14 SW2 PDout 6 13 SW1 VSS 7 12 ENB LD 8 11 DATA fin 9 10 CLK SOG PACKAGE RA1 1 20 RA0 RA2 2 19 OSCin V 3 18 OSCout R 4 17 REFout VDD 5 16 NC PDout 6 15 SW2 VSS 7 14 SW1 NC 8 13 ENB LD 9 12 DATA fin 10 11 CLK NC = NO CONNECTION REV 3 1/99 © Motorola, Inc. 1998 MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 9 MC145155 MC145155­2 BLOCK DIAGRAM RA2 RA1 RA0 14 x 8 ROM REFERENCE DECODER LOCK DETECT 14 OSCout LD 14­BIT ÷ R COUNTER OSCin fR fV REFout PHASE DETECTOR A PDout 14­BIT ÷ N COUNTER fin PHASE DETECTOR B 14 VDD V R SW2 ENB LATCH LATCH SW1 14 DATA 2­BIT SHIFT REGISTER 14­BIT SHIFT REGISTER CLK information for the 14­bit ÷ N counter and the two switch signals SW1 and SW2. The entry format is as follows: INPUT PINS These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below: RA2 RA1 RA0 Total Divide Value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 512 1024 2048 3668 4096 6144 8192 Reference Address Code CLK, DATA Shift Register Clock, Serial Data Inputs (PDIP ­ Pins 10, 11; SOG ­ Pins 11, 12) Each low­to­high transition clocks one bit into the on­chip 16­bit shift register. The Data input provides programming MC145151 MC145151­2 through MC145158 MC145158­2 10 SW1 SW2 ÷ RA0, RA1, RA2 Reference Address Inputs (PDIP ­ Pins 18, 1, 2; SOG ­ Pins 20, 1, 2) ÷ Input to the ÷ N portion of the synthesizer. fin is typically derived from loop VCO and is ac coupled into the device. For larger amplitude signals (standard CMOS logic levels) dc coupling may be used. ÷ N COUNTER BITS N LSB fin Frequency Input (PDIP ­ Pin 9, SOG ­ Pin 10) N MSB PIN DESCRIPTIONS LAST DATA BIT IN (BIT NO. 16) FIRST DATA BIT IN (BIT NO. 1) ENB Latch Enable Input (PDIP ­ Pin 12, SOG ­ Pin 13) When high (1), ENB transfers the contents of the shift register into the latches, and to the programmable counter inputs, and the switch outputs SW1 and SW2. When low (0), ENB inhibits the above action and thus allows changes to be made in the shift register data without affecting the counter programming and switch outputs. An on­chip pull­up establishes a continuously high level for ENB when no external signal is applied. ENB is normally low and is pulsed high to transfer data to the latches. OSCin, OSCout Reference Oscillator Input/Output (PDIP ­ Pins 17, 16; SOG ­ Pins 19, 18) These pins form an on­chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as the input for an externally­generated reference signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSCout. MOTOROLA OUTPUT PINS SW1, SW2 Band Switch Outputs (PDIP ­ Pins 13, 14; SOG ­ Pins 14, 15) PDout Phase Detector A Output (PDIP, SOG ­ Pin 6) Three­state output of phase detector for use as loop error signal. Double­ended outputs are also available for this purpose (see V and R). Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High­Impedance State R, V Phase Detector B Outputs (PDIP, SOG ­ Pins 4, 3) These phase detector outputs can be combined externally for a loop­error signal. A single­ended output is also available for this purpose (see PDout). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by V pulsing low. R remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by R pulsing low. V remains essentially high. If the frequency of fV = fR and both are in phase, then both V and R remain high except for a small minimum time period when both pulse low in phase. LD Lock Detector Output (PDIP ­ Pin 8, SOG ­ Pin 9) Essentially a high level when loop is locked (fR, fV of same phase and frequency). LD pulses low when loop is out of lock. SW1 and SW2 provide latched open­drain outputs corresponding to data bits numbers one and two. These outputs can be tied through external resistors to voltages as high as 15 V, independent of the VDD supply voltage. These are typically used for band switch functions. A logic 1 causes the output to assume a high­impedance state, while a logic 0 causes the output to be low. REFout Buffered Reference Oscillator Output (PDIP, SOG ­ Pin 15) Buffered output of on­chip reference oscillator or externally provided reference­input signal. POWER SUPPLY VDD Positive Power Supply (PDIP, SOG ­ Pin 5) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. VSS Negative Power Supply (PDIP, SOG ­ Pin 7) The most negative supply potential. This pin is usually ground. TYPICAL APPLICATIONS 4.0 MHz UHF/VHF TUNER OR CATV FRONT END MC12073/74 MC12073/74 PRESCALER fin DATA KEYBOARD MC145155 MC145155­2 CLK R V ­ + 1/2 MC1458 MC1458* ENB CMOS MPU/MCU 3 MC14489 MC14489 LED DISPLAY * The R and V outputs are fed to an external combiner/loop filter. See the Phase­Locked Loop - Low­Pass Filter Design page for additional information. The R and V outputs swing rail­to­rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 1. Microprocessor­Controlled TV/CATV Tuning System with Serial Interface MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 11 2.56 MHz FM OSC MC12019 MC12019 ÷ 20 PRESCALER AM OSC fin MC145155 MC145155­2 DATA KEYBOARD CLK R V ­ + 1/2 MC1458 MC1458* TO AM/FM OSCILLATORS ENB CMOS MPU/MCU TO DISPLAY * The R and V outputs are fed to an external combiner/loop filter. See the Phase­Locked Loop - Low­Pass Filter Design page for additional information. The R and V outputs swing rail­to­rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 2. AM/FM Radio Synthesizer MC145155 MC145155­2 Data Sheet Continued on Page 23 MC145151 MC145151­2 through MC145158 MC145158­2 12 MOTOROLA MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC145156-2 MC145156-2 Serial-Input PLL Frequency Synthesizer Interfaces with Dual­Modulus Prescalers The MC145156 MC145156­2 is programmed by a clocked, serial input, 19­bit data stream. The device features consist of a reference oscillator, selectable­reference divider, digital­phase detector, 10­bit programmable divide­by­N counter, 7­bit programmable divide­by­A counter, and the necessary shift register and latch circuitry for accepting serial input data. The MC145156 MC145156­2 is an improved­performance drop­in replacement for the MC145156 MC145156­1. Power consumption has decreased and ESD and latch­up performance have improved. · · · · · · · · · · · · · Operating Temperature Range: ­ 40 to 85°C Low Power Consumption Through Use of CMOS Technology 3.0 to 9.0 V Supply Range On­ or Off­Chip Reference Oscillator Operation with Buffered Output Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs Lock Detect Signal Two Open­Drain Switch Outputs Dual Modulus/Serial Programming 8 User­Selectable ÷ R Values: 8, 64, 128, 256, 640, 1000, 1024, 2048 ÷ N Range = 3 to 1023, ÷ A Range = 0 to 127 "Linearized" Digital Phase Detector Enhances Transfer Function Linearity Two Error Signal Options: Single­Ended (Three­State) or Double­Ended Chip Complexity: 6504 FETs or 1626 Equivalent Gates P SUFFIX PLASTIC DIP CASE 738 20 1 DW SUFFIX SOG PACKAGE CASE 751D 20 1 ORDERING INFORMATION MC145156P2 MC145156P2 MC145156DW2 MC145156DW2 Plastic DIP SOG Package PIN ASSIGNMENT RA1 1 20 RA0 RA2 2 19 OSCin V 3 18 OSCout R 4 17 REFout 5 16 TEST 6 15 SW2 VSS NOT RECOMMENDED FOR NEW DESIGNS; PRODUCT TO BE PHASED OUT. Closest equivalents are the MC145158 MC145158­2, MC145170 MC145170­2, MC14519X MC14519X series, and MC14520X MC14520X series. VDD PDout 7 14 SW1 MC 8 13 ENB LD 9 12 DATA fin 10 11 CLK REV 3 1/99 © Motorola, Inc. 1998 MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 13 MC145156 MC145156­2 BLOCK DIAGRAM RA2 RA1 RA0 12 x 8 ROM REFERENCE DECODER 12 12­BIT ÷ R COUNTER OSCin LOCK DETECT LD OSCout fR CONTROL LOGIC REFout fV MC 7­BIT ÷ A COUNTER fin 10­BIT ÷ N COUNTER ÷ A COUNTER LATCH ENB V PHASE DETECTOR B R SW2 ÷ N COUNTER LATCH 7 LATCH SW1 10 DATA 7­BIT SHIFT REGISTER PDout 10 7 VDD PHASE DETECTOR A 10­BIT SHIFT REGISTER 2­BIT SHIFT REGISTER CLK RA0, RA1, RA2 Reference Address Inputs (Pins 20, 1, 2) These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below: RA2 RA1 RA0 Total Divide Value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 64 128 256 640 1000 1024 2048 Reference Address Code CLK, DATA Shift Register Clock, Serial Data Inputs (Pins 11, 12) Each low­to­high transition clocks one bit into the on­chip 19­bit shift register. The data input provides programming information for the 10­bit ÷ N counter, the 7­bit ÷ A counter, and the two switch signals SW1 and SW2. The entry format is as follows: MC145151 MC145151­2 through MC145158 MC145158­2 14 SW1 ÷ Input to the positive edge triggered ÷ N and ÷ A counters. fin is typically derived from a dual­modulus prescaler and is ac coupled into the device. For larger amplitude signals (standard CMOS logic levels), dc coupling may be used. ÷ ÷ ÷ fin Frequency Input (Pin 10) N MSB SW2 A LSB INPUT PINS ÷ N COUNTER BITS A MSB N LSB ÷ A COUNTER BITS PIN DESCRIPTIONS LAST DATA BIT IN (BIT NO. 19) FIRST DATA BIT IN (BIT NO. 1) ENB Latch Enable Input (Pin 13) When high (1), ENB transfers the contents of the shift register into the latches, and to the programmable counter inputs, and the switch outputs SW1 and SW2. When low (0), ENB inhibits the above action and thus allows changes to be made in the shift register data without affecting the counter programming and switch outputs. An on­chip pull­up establishes a continuously high level for ENB when no external signal is applied. ENB is normally low and is pulsed high to transfer data to the latches. OSCin, OSCout Reference Oscillator Input/Output (Pins 19, 18) These pins form an on­chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as the input for an externally­generated reference signal. This signal is typically ac coupled to OSC in, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSCout. TEST Factory Test Input (Pin 16) Used in manufacturing. Must be left open or tied to VSS. MOTOROLA OUTPUT PINS PDout Phase Detector A Output (Pin 6) Three­state output of phase detector for use as loop­error signal. Double­ended outputs are also available for this purpose (see V and R). Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High­Impedance State R, V Phase Detector B Outputs (Pins 4, 3) These phase detector outputs can be combined externally for a loop­error signal. A single­ended output is also available for this purpose (see PDout ). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by V pulsing low. R remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by R pulsing low. V remains essentially high. If the frequency of fV = fR and both are in phase, then both V and R remain high except for a small minimum time period when both pulse low in phase. MC Dual­Modulus Prescale Control Output (Pin 8) Signal generated by the on­chip control logic circuitry for controlling an external dual­modulus prescaler. The MC level will be low at the beginning of a count cycle and will remain low until the ÷ A counter has counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N counter has counted the rest of the way down from its programmed value (N ­ A additional counts since both ÷ N and ÷ A are counting down during the first portion of the cycle). MC is then set back low, the counters MOTOROLA preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (NT) = N P + A where P and P + 1 represent the dual­modulus prescaler divide values respectively for high and low MC levels, N the number programmed into the ÷ N counter, and A the number programmed into the ÷ A counter. LD Lock Detector Output (Pin 9) Essentially a high level when loop is locked (fR, fV of same phase and frequency). LD pulses low when loop is out of lock. SW1, SW2 Band Switch Outputs (Pins 14, 15) SW1 and SW2 provide latched open­drain outputs corresponding to data bits numbers one and two. These outputs can be tied through external resistors to voltages as high as 15 V, independent of the VDD supply voltage. These are typically used for band switch functions. A logic 1 causes the output to assume a high­impedance state, while a logic 0 causes the output to be low. REFout Buffered Reference Oscillator Output (Pin 17) Buffered output of on­chip reference oscillator or externally provided reference­input signal. POWER SUPPLY VDD Positive Power Supply (Pin 5) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. VSS Negative Power Supply (Pin 7) The most negative supply potential. This pin is usually ground. MC145151 MC145151­2 through MC145158 MC145158­2 15 TYPICAL APPLICATIONS + 12 V LOCK DETECT SIGNAL 3.2 MHz NOTES 1 AND 2 +V OSCin OSCout RA2 RA1 RA0 LD SW1 SW2 PDout VDD REFout CLK KEY­ BOARD R MC145156 MC145156­2 VSS DATA fin ENB FM B + + 12 V AM B + OPTIONAL LOOP ERROR SIGNAL ­ VCO V + MC 1/2 MC1458 MC1458 NOTE 3 CMOS MPU/MCU MC12019 MC12019 ÷ 20/21 DUAL MODULUS PRESCALER TO DISPLAY DRIVER (e.g., MC14489 MC14489) NOTES: 1. For AM: channel spacing = 5 kHz, ÷ R = ÷ 640 (code 100). 2. For FM: channel spacing = 25 kHz, ÷ R = ÷ 128 (code 010). 3. The R and V outputs are fed to an external combiner/loop filter. See the Phase­Locked Loop - Low­Pass Filter Design page for additional information. The R and V outputs swing rail­to­rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 1. AM/FM Radio Broadcast Synthesizer 3.2 MHz (NOTE 3) NAV = 01 COM = 10 +V OSCin OSCout RA2 RA1 RA0 VDD REFout CLK R/T LD SW1 SW2 PDout R DATA ENB fin ­ V MC145156 MC145156­2 VSS VCO RANGE NAV: 97.300 ­ 107.250 MHz COM­T: 118.000 ­ 135.975 MHz COM­R: 139.400 ­ 157.375 MHz LOCK DETECT SIGNAL + VCO MC MC33171 MC33171 NOTE 5 CMOS MPU/MCU MC12016 MC12016 (NOTES 2 AND 4) ÷ 40/41 DUAL MODULUS PRESCALER CHANNEL SELECTION TO DISPLAY DRIVER (e.g., MC14489 MC14489) NOTES: 1. For NAV: fR = 50 kHz, ÷ R = 64 using 10.7 MHz lowside injection, Ntotal = 1946 ­ 2145. For COM­T: fR = 25 kHz, ÷ R = 128, Ntotal = 4720 ­ 5439. For COM­R: fR = 25 kHz, ÷ R = 128, using 21.4 MHz highside injection, Ntotal = 5576 ­ 6295. 2. A ÷ 32/33 dual modulus approach is provided by substituting an MC12015 MC12015 for the MC12016 MC12016. The devices are pin equivalent. 3. A 6.4 MHz oscillator crystal can be used by selecting ÷ R = 128 (code 010) for NAV and ÷ R = 256 (code 011) for COM. 4. MC12013 MC12013 + MC10131 MC10131 combination may also be used to form the ÷ 40/41 prescaler. 5. The R and V outputs are fed to an external combiner/loop filter. See the Phase­Locked Loop - Low­Pass Filter Design page for additional information. The R and V outputs swing rail­to­rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 2. Avionics Navigation or Communication Synthesizer MC145156 MC145156­2 Data Sheet Continued on Page 23 MC145151 MC145151­2 through MC145158 MC145158­2 16 MOTOROLA MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC145157-2 MC145157-2 Serial-Input PLL Frequency Synthesizer P SUFFIX PLASTIC DIP CASE 648 Interfaces with Single­Modulus Prescalers 16 The MC145157 MC145157­2 has a fully programmable 14­bit reference counter, as well as a fully programmable ÷ N counter. The counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. The MC145157 MC145157­2 is an improved­performance drop­in replacement for the MC145157 MC145157­1. Power consumption has decreased and ESD and latch­up performance have improved. · · · · · · · · · · · · Operating Temperature Range: ­ 40 to 85°C Low Power Consumption Through Use of CMOS Technology 3.0 to 9.0 V Supply Range Fully Programmable Reference and ÷ N Counters ÷ R Range = 3 to 16383 ÷ N Range = 3 to 16383 fV and fR Outputs Lock Detect Signal Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs "Linearized" Digital Phase Detector Single­Ended (Three­State) or Double­Ended Phase Detector Outputs Chip Complexity: 6504 FETs or 1626 Equivalent Gates 1 DW SUFFIX SOG PACKAGE CASE 751G 16 1 ORDERING INFORMATION MC145157P2 MC145157P2 MC145157DW2 MC145157DW2 Plastic DIP SOG Package PIN ASSIGNMENT OSCin 1 16 R OSCout 2 15 V fV 3 14 REFout VDD 4 13 fR PDout 5 12 S/Rout VSS 6 11 ENB LD 7 10 DATA fin 8 9 CLK REV 1 8/95 © Motorola, Inc. 1995 MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 17 MC145157 MC145157­2 BLOCK DIAGRAM 14­BIT SHIFT REGISTER 14 ENB fR REFERENCE COUNTER LATCH 14 LOCK DETECT 14­BIT ÷ R COUNTER OSCin PHASE DETECTOR A OSCout REFout 14­BIT ÷ N COUNTER fin 14 PHASE DETECTOR B ÷ N COUNTER LATCH DATA LD PDout V R fV 14 1­BIT CONTROL S/R S/Rout 14­BIT SHIFT REGISTER CLK if the control bit is at a logic low. A logic low on this pin allows the user to change the data in the shift registers without affecting the counters. ENB is normally low and is pulsed high to transfer data to the latches. PIN DESCRIPTIONS INPUT PINS fin Frequency Input (Pin 8) Input frequency from VCO output. A rising edge signal on this input decrements the ÷ N counter. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV p­p. For larger amplitude signals (standard CMOS logic levels), dc coupling may be used. CLK, DATA Shift Clock, Serial Data Inputs (Pins 9, 10) MSB LSB CONTROL Each low­to­high transition of the clock shifts one bit of data into the on­chip shift registers. The last data bit entered determines which counter storage latch is activated; a logic 1 selects the reference counter latch and a logic 0 selects the ÷ N counter latch. The entry format is as follows: FIRST DATA BIT INTO SHIFT REGISTER ENB Latch Enable Input (Pin 11) A logic high on this pin latches the data from the shift register into the reference divider or ÷ N latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the ÷ N latches are activated MC145151 MC145151­2 through MC145158 MC145158­2 18 OSCin, OSCout Reference Oscillator Input/Output (Pins 1, 2) These pins form an on­chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC in to ground and OSC out to ground. OSC in may also serve as the input for an externally­generated reference signal. This signal is typically ac coupled to OSC in, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC out. OUTPUT PINS PDout Single­Ended Phase Detector A Output (Pin 5) This single­ended (three­state) phase detector output produces a loop­error signal that is used with a loop filter to control a VCO. Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High­Impedance State R, V Double­Ended Phase Detector B Outputs (Pins 16, 15) These outputs can be combined externally for a loop­error signal. A single­ended output is also available for this purpose (see PDout ). MOTOROLA If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by V pulsing low. R remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by R pulsing low. V remains essentially high. If the frequency of fV = fR and both are in phase, then both V and R remain high except for a small minimum time period when both pulse low in phase. f R , fV R Counter Output, N Counter Output (Pins 13, 3) Buffered, divided reference and fin frequency outputs. The fR and fV outputs are connected internally to the ÷ R and ÷ N counter outputs respectively, allowing the counters to be used independently, as well as monitoring the phase detector inputs. LD Lock Detector Output (Pin 7) This output is essentially at a high level when the loop is locked (fR, fV of same phase and frequency), and pulses low when loop is out of lock. REFout Buffered Reference Oscillator Output (Pin 14) This output can be used as a second local oscillator, reference oscillator to another frequency synthesizer, or as the system clock to a microprocessor controller. S/Rout Shift Register Output (Pin 12) This output can be connected to an external shift register to provide band switching, control information, and counter programming code checking. POWER SUPPLY VDD Positive Power Supply (Pin 4) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. VSS Negative Power Supply (Pin 6) The most negative supply potential. This pin is usually ground. MC145157 MC145157­2 Data Sheet Continued on Page 23 MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 19 MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC145158-2 MC145158-2 Serial-Input PLL Frequency Synthesizer P SUFFIX PLASTIC DIP CASE 648 Interfaces with Dual­Modulus Prescalers 16 The MC145158 MC145158­2 has a fully programmable 14­bit reference counter, as well as fully programmable ÷ N and ÷ A counters. The counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. The MC145158 MC145158­2 is an improved­performance drop­in replacement for the MC145158 MC145158­1. Power consumption has decreased and ESD and latch­up performance have improved. · · · · · · · · · · · · · Operating Temperature Range: ­ 40 to 85°C Low Power Consumption Through Use of CMOS Technology 3.0 to 9.0 V Supply Range Fully Programmable Reference and ÷ N Counters ÷ R Range = 3 to 16383 ÷ N Range = 3 to 1023 Dual Modulus Capability; ÷ A Range = 0 to 127 fV and fR Outputs Lock Detect Signal Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs "Linearized" Digital Phase Detector Single­Ended (Three­State) or Double­Ended Phase Detector Outputs Chip Complexity: 6504 FETs or 1626 Equivalent Gates 1 DW SUFFIX SOG PACKAGE CASE 751G 16 1 ORDERING INFORMATION MC145158P2 MC145158P2 MC145158DW2 MC145158DW2 Plastic DIP SOG Package PIN ASSIGNMENT OSCin 1 16 R OSCout 2 15 V fV 3 14 REFout VDD 4 13 fR PDout 5 12 MC VSS 6 11 ENB LD 7 10 DATA fin 8 9 CLK REV 1 8/95 © Motorola, Inc. 1995 MC145151 MC145151­2 through MC145158 MC145158­2 20 MOTOROLA MC145158 MC145158­2 BLOCK DIAGRAM 14­BIT SHIFT REGISTER 14 ENB fR REFERENCE COUNTER LATCH LOCK DETECT 14 14­BIT ÷ R COUNTER OSCin PHASE DETECTOR A OSCout CONTROL LOGIC REFout 7­BIT ÷ A COUNTER fin 10­BIT ÷ N COUNTER ÷ A COUNTER ÷ N COUNTER LATCH LATCH 7 1­BIT CONTROL S/R PHASE DETECTOR B 10 7 DATA LD PDout V R fV 10 7­BIT S/R MC 10­BIT S/R CLK Input frequency from VCO output. A rising edge signal on this input decrements the ÷ A and ÷ N counters. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV p­p. For larger amplitude signals (standard CMOS logic levels), dc coupling may be used. CLK, DATA Shift Clock, Serial Data Inputs (Pins 9, 10) Each low­to­high transition of the CLK shifts one bit of data into the on­chip shift registers. The last data bit entered determines which counter storage latch is activated; a logic 1 selects the reference counter latch and a logic 0 selects the ÷ A, ÷ N counter latch. The data entry format is as follows: MSB LSB CONTROL ÷R FIRST DATA BIT INTO SHIFT REGISTER MOTOROLA MSB fin Frequency Input (Pin 8) LSB CONTROL INPUT PINS ÷N MSB LSB ÷A PIN DESCRIPTIONS FIRST DATA BIT INTO SHIFT REGISTER ENB Latch Enable Input (Pin 11) A logic high on this pin latches the data from the shift register into the reference divider or ÷ N, ÷ A latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the ÷ N, ÷ A latches are activated if the control bit is at a logic low. A logic low on this pin allows the user to change the data in the shift registers without affecting the counters. ENB is normally low and is pulsed high to transfer data to the latches. OSCin, OSCout Reference Oscillator Input/Output (Pins 1, 2) These pins form an on­chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC in to ground and OSC out to ground. OSC in may also serve as the input for an externally­generated reference signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC out. MC145151 MC145151­2 through MC145158 MC145158­2 21 OUTPUT PINS PDout Phase Detector A Output (Pin 5) This single­ended (three­state) phase detector output produces a loop­error signal that is used with a loop filter to control a VCO. Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High­Impedance State R, V Phase Detector B Outputs (Pins 16, 15) Double­ended phase detector outputs. These outputs can be combined externally for a loop­error signal. A single­ ended output is also available for this purpose (see PDout ). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by V pulsing low. R remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by R pulsing low. V remains essentially high. If the frequency of fV = fR and both are in phase, then both V and R remain high except for a small minimum time period when both pulse low in phase. MC Dual­Modulus Prescale Control Output (Pin 12) This output generates a signal by the on­chip control logic circuitry for controlling an external dual­modulus prescaler. The MC level is low at the beginning of a count cycle and remains low until the ÷ A counter has counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N counter has counted the rest of the way down from its programmed value (N ­ A additional counts since both ÷ N and ÷ A are counting down during the first portion of the cycle). MC is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (NT) = N P + A where P and P + 1 represent the MC145151 MC145151­2 through MC145158 MC145158­2 22 dual­modulus prescaler divide values respectively for high and low modulus control levels, N the number programmed into the ÷ N counter, and A the number programmed into the ÷ A counter. Note that when a prescaler is needed, the dual­ modulus version offers a distinct advantage. The dual­ modulus prescaler allows a higher reference frequency at the phase detector input, increasing system performance capability, and simplifying the loop filter design. f R , fV R Counter Output, N Counter Output (Pins 13, 3) Buffered, divided reference and fin frequency outputs. The fR and fV outputs are connected internally to the ÷ R and ÷ N counter outputs respectively, allowing the counters to be used independently, as well as monitoring the phase detector inputs. LD Lock Detector Output (Pin 7) This output is essentially at a high level when the loop is locked (fR, fV of same phase and frequency), and pulses low when loop is out of lock. REFout Buffered Reference Oscillator Output (Pin 14) This output can be used as a second local oscillator, reference oscillator to another frequency synthesizer, or as the system clock to a microprocessor controller. POWER SUPPLY VDD Positive Power Supply (Pin 4) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. VSS Negative Power Supply (Pin 6) The most negative supply potential. This pin is usually ground. MOTOROLA MC14515X MC14515X­2 FAMILY CHARACTERISTICS AND DESCRIPTIONS MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Value ­ 0.5 to + 10.0 V ­ 0.5 to VDD + 0.5 V ­ 0.5 to + 15 V Input or Output Current (DC or Transient), per Pin ± 10 mA IDD, ISS Supply Current, VDD or VSS Pins ± 30 mA PD Power Dissipation, per Package 500 mW Tstg Storage Temperature ­ 65 to + 150 °C 260 These devices contain protection circuitry to protect against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to these high­impedance circuits. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD except for SW1 and SW2. SW1 and SW2 can be tied through external resistors to voltages as high as 15 V, independent of the supply voltage. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD), except for inputs with pull­up devices. Unused outputs must be left open. Unit °C VDD Vin, Vout Vout Iin, Iout TL Parameter DC Supply Voltage Input or Output Voltage (DC or Transient) except SW1, SW2 Output Voltage (DC or Transient), SW1, SW2 (Rpull­up = 4.7 k) Lead Temperature, 1 mm from Case for 10 seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. Power Dissipation Temperature Derating: Plastic DIP: ­ 12 mW/°C from 65 to 85°C SOG Package: ­ 7 mW/°C from 65 to 85°C ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Symbol S b l VDD Parameter P ­ 40°C 25°C 85°C Power Supply Voltage Range Min Max Min Max Min Max Unit U i - Test C di i T Condition VDD V 3 9 3 9 3 9 V Iss Dynamic Supply Current fin = OSCin = 10 MHz, 1 V p­p ac coupled sine wave R = 128, A = 32, N = 128 3 5 9 - - - 3.5 10 30 - - - 3 7.5 24 - - - 3 7.5 24 mA ISS Quiescent Supply Current (not including pull­up current component) Vin = VDD or VSS Iout = 0 µA 3 5 9 - - - 800 1200 1600 - - - 800 1200 1600 - - - 1600 2400 3200 µA Vin Input Voltage - fin, OSCin Input ac coupled sine wave - 500 - 500 - 500 - mV p­p VIL Low­Level Input Voltage - fin, OSCin Vout 2.1 V Vout 3.5 V Vout 6.3 V Input dc coupled square wave 3 5 9 - - - 0 0 0 - - - 0 0 0 - - - 0 0 0 V VIH High­Level Input Voltage - fin, OSCin Vout 0.9 V Vout 1.5 V Vout 2.7 V Input dc coupled square wave 3 5 9 3.0 5.0 9.0 - - - 3.0 5.0 9.0 - - - 3.0 5.0 9.0 - - - V VIL Low­Level Input Voltage - except fin, OSCin 3 5 9 - - - 0.9 1.5 2.7 - - - 0.9 1.5 2.7 - - - 0.9 1.5 2.7 V VIH High­Level Input Voltage - except fin, OSCin 3 5 9 2.1 3.5 6.3 - - - 2.1 3.5 6.3 - - - 2.1 3.5 6.3 - - - V Iin Input Current (fin, OSCin) Vin = VDD or VSS 9 ±2 ± 50 ±2 ± 25 ±2 ± 22 µA IIL Input Leakage Current (Data, CLK, ENB - without pull­ups) Vin = VSS 9 - ­ 0.3 - ­ 0.1 - ­ 1.0 µA IIH Input Leakage Current (all inputs except fin, OSCin) Vin = VDD 9 - 0.3 - 0.1 - 1.0 µA (continued) MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 23 DC ELECTRICAL CHARACTERISTICS (continued) ­ 40°C 25°C 85°C VDD V Min Max Min Max Min Max Unit U i 9 ­ 20 ­ 400 ­ 20 ­ 200 ­ 20 ­ 170 µA - - 10 - 10 - 10 pF Iout 0 µA Vin = VDD 3 5 9 - - - 0.9 1.5 2.7 - - - 0.9 1.5 2.7 - - - 0.9 1.5 2.7 V High­Level Output Voltage - OSCout Iout 0 µA Vin = VSS 3 5 9 2.1 3.5 6.3 - - - 2.1 3.5 6.3 - - - 2.1 3.5 6.3 - - - V VOL Low­Level Output Voltage - Other Outputs Iout 0 µA 3 5 9 - - - 0.05 0.05 0.05 - - - 0.05 0.05 0.05 - - - 0.05 0.05 0.05 V VOH High­Level Output Voltage - Other Outputs Iout 0 µA 3 5 9 2.95 4.95 8.95 - - - 2.95 4.95 8.95 - - - 2.95 4.95 8.95 - - - V Drain­to­Source Breakdown Voltage - SW1, SW2 Rpull­up = 4.7 k - 15 - 15 - 15 - V IOL Low­Level Sinking Current - MC Vout = 0.3 V Vout = 0.4 V Vout = 0.5 V 3 5 9 1.30 1.90 3.80 - - - 1.10 1.70 3.30 - - - 0.66 1.08 2.10 - - - mA IOH High­Level Sourcing Current - MC Vout = 2.7 V Vout = 4.6 V Vout = 8.5 V 3 5 9 ­ 0.60 ­ 0.90 ­ 1.50 - - - ­ 0.50 ­ 0.75 ­ 1.25 - - - ­ 0.30 ­ 0.50 ­ 0.80 - - - mA IOL Low­Level Sinking Current - LD Vout = 0.3 V Vout = 0.4 V Vout = 0.5 V 3 5 9 0.25 0.64 1.30 - - - 0.20 0.51 1.00 - - - 0.15 0.36 0.70 - - - mA IOH High­Level Sourcing Current - LD Vout = 2.7 V Vout = 4.6 V Vout = 8.5 V 3 5 9 ­ 0.25 ­ 0.64 ­ 1.30 - - - ­ 0.20 ­ 0.51 ­ 1.00 - - - ­ 0.15 ­ 0.36 ­ 0.70 - - - mA IOL Low­Level Sinking Current - SW1, SW2 Vout = 0.3 V Vout = 0.4 V Vout = 0.5 V 3 5 9 0.80 1.50 3.50 - - - 0.48 0.90 2.10 - - - 0.24 0.45 1.05 - - - mA IOL Low­Level Sinking Current - Other Outputs Vout = 0.3 V Vout = 0.4 V Vout = 0.5 V 3 5 9 0.44 0.64 1.30 - - - 0.35 0.51 1.00 - - - 0.22 0.36 0.70 - - - mA IOH High­Level Sourcing Current - Other Outputs Vout = 2.7 V Vout = 4.6 V Vout = 8.5 V 3 5 9 ­ 0.44 ­ 0.64 ­ 1.30 - - - ­ 0.35 ­ 0.51 ­ 1.00 - - - ­ 0.22 ­ 0.36 ­ 0.70 - - - mA IOZ Output Leakage Current - PDout Vout = VDD or VSS Output in Off State 9 - ± 0.3 - ± 0.1 - ± 1.0 µA IOZ Output Leakage Current - SW1, SW2 Vout = VDD or VSS Output in Off State 9 - ± 0.3 - ± 0.1 - ± 3.0 µA Cout Output Capacitance - PDout PDout - Three­State - - 10 - 10 - 10 pF Symbol S b l Parameter P IIL Pull­up Current (all inputs with pull­ups) Cin Input Capacitance VOL Low­Level Output Voltage - OSCout VOH V(BR)DSS MC145151 MC145151­2 through MC145158 MC145158­2 24 Test C di i T Condition Vin = VSS MOTOROLA AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 10 ns) VDD V Guaranteed Limit 25°C Guaranteed Limit ­ 40 to 85°C Maximum Propagation Delay, fin to MC (Figures 1 and 4) 3 5 9 110 60 35 120 70 40 ns Maximum Propagation Delay, ENB to SW1, SW2 (Figures 1 and 5) 3 5 9 160 80 50 180 95 60 ns Output Pulse Width, R, V, and LD with fR in Phase with fV (Figures 2 and 4) 3 5 9 25 to 200 20 to 100 10 to 70 25 to 260 20 to 125 10 to 80 ns tTLH Maximum Output Transition Time, MC (Figures 3 and 4) 3 5 9 115 60 40 115 75 60 ns tTHL Maximum Output Transition Time, MC (Figures 3 and 4) 3 5 9 60 34 30 70 45 38 ns tTLH, tTHL Maximum Output Transition Time, LD (Figures 3 and 4) 3 5 9 180 90 70 200 120 90 ns tTLH, tTHL Maximum Output Transition Time, Other Outputs (Figures 3 and 4) 3 5 9 160 80 60 175 100 65 ns Symbol Parameter tPLH, tPHL tPHL tw Unit SWITCHING WAVEFORMS VDD INPUT 50% - VSS OUTPUT tw tPHL tPLH R, V, LD* 50% 50% * fR in phase with fV. Figure 1. Figure 2. tTLH ANY OUTPUT tTHL 90% 10% Figure 3. VDD TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT CL* * Includes all probe and fixture capacitance. Figure 4. Test Circuit MOTOROLA DEVICE UNDER TEST 15 k CL* * Includes all probe and fixture capacitance. Figure 5. Test Circuit MC145151 MC145151­2 through MC145158 MC145158­2 25 TIMING REQUIREMENTS (Input tr = tf = 10 ns unless otherwise indicated) Symbol VDD V Parameter Guaranteed Limit 25°C Guaranteed Limit ­ 40 to 85°C Unit fclk Serial Data Clock Frequency, Assuming 25% Duty Cycle NOTE: Refer to CLK tw(H) below (Figure 6) 3 5 9 dc to 5.0 dc to 7.1 dc to 10 dc to 3.5 dc to 7.1 dc to 10 MHz tsu Minimum Setup Time, Data to CLK (Figure 7) 3 5 9 30 20 18 30 20 18 ns th Minimum Hold Time, CLK to Data (Figure 7) 3 5 9 40 20 15 40 20 15 ns tsu Minimum Setup Time, CLK to ENB (Figure 7) 3 5 9 70 32 25 70 32 25 ns trec Minimum Recovery Time, ENB to CLK (Figure 7) 3 5 9 5 10 20 5 10 20 ns tw(H) Minimum Pulse Width, CLK and ENB (Figure 6) 3 5 9 50 35 25 70 35 25 ns Maximum Input Rise and Fall Times - Any Input (Figure 8) 3 5 9 5 4 2 5 4 2 µs tr, tf SWITCHING WAVEFORMS - VDD tw(H) DATA - VDD CLK, ENB 50% 50% VSS tsu th VSS 1 * 4 fclk - VDD CLK *Assumes 25% Duty Cycle. 50% FIRST CLK LAST CLK tsu VSS trec - VDD Figure 6. ENB 50% VSS tt ANY OUTPUT PREVIOUS DATA LATCHED tf - VDD 90% 10% VSS Figure 7. Figure 8. MC145151 MC145151­2 through MC145158 MC145158­2 26 MOTOROLA FREQUENCY CHARACTERISTICS (Voltages References to VSS, CL = 50 pF, Input tr = tf =10 ns unless otherwise indicated) ­ 40°C 25°C 85°C Input Frequency (fin, OSCin) Min Max Min Max Min Max Unit U i R 8, A 0, N 8 Vin = 500 mV p­p ac coupled sine wave 3 5 9 - - - 6 15 15 - - - 6 15 15 - - - 6 15 15 MHz 3 5 9 - - - 12 22 25 - - - 12 20 22 - - - 7 20 22 MHz R 8, A 0, N 8 Vin = VDD to VSS dc coupled square wave fi Parameter P VDD V R 8, A 0, N 8 Vin = 1 V p­p ac coupled sine wave Symbol S b l 3 5 9 - - - 13 25 25 - - - 12 22 25 - - - 8 22 25 MHz Test C di i T Condition NOTE: Usually, the PLL's propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency limit of the system. The upper frequency limit is found with the following formula: f = P / (tP + tset) where f is the upper frequency in Hz, P is the lower of the dual modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and tset is the prescaler setup time in seconds. For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A MC12028A prescaler is used, the setup time is 16 ns. Thus, if the 64/65 ratio is utilized, the upper frequency limit is f = P / (tP + tset) = 64/(70 + 16) = 744 MHz. fR REFERENCE OSC ÷ R VH VL VH fV FEEDBACK (fin ÷ N) * VL VH HIGH IMPEDANCE PDout VL VH R VL VH V VL VH LD VL VH = High Voltage Level. VL = Low Voltage Level. * At this point, when both fR and fV are in phase, the output is forced to near mid­supply. NOTE: The PDout generates error pulses during out­of­lock conditions. When locked in phase and frequency the output is high and the voltage at this pin is determined by the low­pass filter capacitor. Figure 9. Phase Detector/Lock Detector Output Waveforms MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 27 DESIGN CONSIDERATIONS PHASE­LOCKED LOOP - LOW­PASS FILTER DESIGN A) PDout R - n = VCO R1 C = V - F(s) = B) PDout R - VCO n = R1 R2 V - R2 PDout - R V Nn 2KKVCO 1 R1sC + 1 KKVCO NC(R1 + R2) = 0.5 n R2C + C F(s) = C) KKVCO NR1C R1 _ n = C +A VCO = N KKVCO R2sC + 1 (R1 + R2)sC + 1 KKVCO NCR1 nR2C 2 R1 R2 C ASSUMING GAIN A IS VERY LARGE, THEN: F(s) = R2sC + 1 R1sC NOTE: Sometimes R1 is split into two series resistors, each R1 ÷ 2. A capacitor CC is then placed from the midpoint to ground to further filter V and R. The value of CC should be such that the corner frequency of this network does not significantly affect n. The R and V outputs swing rail­to­rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. DEFINITIONS: N = Total Division Ratio in feedback loop K (Phase Detector Gain) = VDD/4 for PDout K (Phase Detector Gain) = VDD/2 for V and R 2fVCO KVCO (VCO Gain) = VVCO for a typical design wn (Natural Frequency) 2fr (at phase detector input). 10 Damping Factor: 1 RECOMMENDED READING: Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley­Interscience, 1979. Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley­Interscience, 1980. Blanchard, Alain, Phase­Locked Loops: Application to Coherent Receiver Design. New York, Wiley­Interscience, 1976. Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley­Interscience, 1981. Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice­Hall, 1983. Berlin, Howard M., Design of Phase­Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978. Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980. AN535 AN535, Phase­Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970. AR254 AR254, Phase­Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design, 1987. MC145151 MC145151­2 through MC145158 MC145158­2 28 MOTOROLA CRYSTAL OSCILLATOR CONSIDERATIONS The following options may be considered to provide a reference frequency to Motorola's CMOS frequency synthesizers. Use of a Hybrid Crystal Oscillator Commercially available temperature­compensated crystal oscillators (TCXOs) or crystal­controlled data clock oscillators provide very stable reference frequencies. An oscillator capable of sinking and sourcing 50 µA at CMOS logic levels may be direct or dc coupled to OSCin. In general, the highest frequency capability is obtained utilizing a direct­coupled square wave having a rail­to­rail (VDD to VSS) voltage swing. If the oscillator does not have CMOS logic levels on the outputs, capacitive or ac coupling to OSCin may be used. OSCout, an unbuffered output, should be left floating. For additional information about TCXOs and data clock oscillators, please consult the latest version of the eem Electronic Engineers Master Catalog, the Gold Book, or similar publications. C L values. The shunt load capacitance, C L , presented across the crystal can be estimated to be: CL = CinCout + Ca + Co + C1 · C2 C1 + C2 Cin + Cout where Cin = Cout = Ca = CO = 5 pF (see Figure 11) 6 pF (see Figure 11) 1 pF (see Figure 11) the crystal's holder capacitance (see Figure 12) C1 and C2 = external capacitors (see Figure 10) Ca Cin Cout Figure 11. Parasitic Capacitances of the Amplifier RS Design an Off­Chip Reference 1 The user may design an off­chip crystal oscillator using ICs specifically developed for crystal oscillator applications, such as the MC12061 MC12061 MECL device. The reference signal from the MECL device is ac coupled to OSCin. For large amplitude signals (standard CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest frequency capability is obtained with a direct­coupled square wave having rail­to­rail voltage swing. Use of the On­Chip Oscillator Circuitry The on­chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure 10. FREQUENCY SYNTHESIZER Rf OSCin C1 R1* OSCout C2 * May be deleted in certain cases. See text. Figure 10. Pierce Crystal Oscillator Circuit For VDD = 5.0 V, the crystal should be specified for a loading capacitance, CL, which does not exceed 32 pF for frequencies to approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to 15 MHz, and 10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic MOTOROLA 2 LS CS 1 2 CO 1 Re Xe 2 NOTE: Values are supplied by crystal manufacturer (parallel resonant crystal). Figure 12. Equivalent Crystal Networks The oscillator can be "trimmed" on­frequency by making a portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and OSCout pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. In some cases, stray capacitance should be added to the value for Cin and Cout. Power is dissipated in the effective series resistance of the crystal, Re, in Figure 12. The drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency. R1 in Figure 10 limits the drive level. The use of R1 may not be necessary in some cases (i.e., R1 = 0 ). To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a function of voltage at OSCout. (Care should be taken to minimize loading.) The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the oscillator start­up time is proportional to the value of R1. Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful (see Table 1). MC145151 MC145151­2 through MC145158 MC145158­2 29 Table 1. Partial List of Crystal Manufacturers Motorola - Internet Address http://motorola.com (Search for resonators) United States Crystal Corp. Crystek Crystal Statek Corp. Fox Electronics NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers. RECOMMENDED READING Technical Note TN­24, Statek Corp. Technical Note TN­7, Statek Corp. E. Hafner, "The Piezoelectric Crystal Unit ­ Definitions and Method of Measurement", Proc. IEEE, Vol. 57, No. 2 Feb., 1969. D. Kemper, L. Rosine, "Quartz Crystals for Frequency Control", Electro­Technology, June, 1969. P. J. Ottowitz, "A Guide to Crystal Selection", Electronic Design, May, 1966. DUAL­MODULUS PRESCALING OVERVIEW The technique of dual­modulus prescaling is well established as a method of achieving high performance frequency synthesizer operation at high frequencies. Basically, the approach allows relatively low­frequency programmable counters to be used as high­frequency programmable counters with speed capability of several hundred MHz. This is possible without the sacrifice in system resolution and performance that results if a fixed (single­modulus) divider is used for the prescaler. In dual­modulus prescaling, the lower speed counters must be uniquely configured. Special control logic is necessary to select the divide value P or P + 1 in the prescaler for the required amount of time (see modulus control definition). Motorola's dual­modulus frequency synthesizers contain this feature and can be used with a variety of dual­modulus prescalers to allow speed, complexity and cost to be tailored to the system requirements. Prescalers having P, P + 1 divide values in the range of ÷ 3/÷ 4 to ÷ 128/÷ 129 can be controlled by most Motorola frequency synthesizers. Several dual­modulus prescaler approaches suitable for use with the MC145152 MC145152­2, MC145156 MC145156­2, or MC145158 MC145158­2 are: MC12009 MC12009 MC12011 MC12011 MC12013 MC12013 MC12015 MC12015 MC12016 MC12016 MC12017 MC12017 MC12018 MC12018 MC12028A MC12028A MC12052A MC12052A MC12054A MC12054A ÷ 5/÷ 6 ÷ 8/÷ 9 ÷ 10/÷ 11 ÷ 32/÷ 33 ÷ 40/÷ 41 ÷ 64/÷ 65 ÷ 128/÷ 129 ÷ 32/33 or ÷ 64/65 ÷ 64/65 or ÷ 128/129 ÷ 64/65 or ÷ 128/129 MC145151 MC145151­2 through MC145158 MC145158­2 30 440 MHz 500 MHz 500 MHz 225 MHz 225 MHz 225 MHz 520 MHz 1.1 GHz 1.1 GHz 2.0 GHz DESIGN GUIDELINES The system total divide value, Ntotal (NT) will be dictated by the application: NT = frequency into the prescaler =NP+A frequency into the phase detector N is the number programmed into the ÷ N counter, A is the number programmed into the ÷ A counter, P and P + 1 are the two selectable divide ratios available in the dual­modulus prescalers. To have a range of NT values in sequence, the ÷ A counter is programmed from zero through P ­ 1 for a particular value N in the ÷ N counter. N is then incremented to N + 1 and the ÷ A is sequenced from 0 through P ­ 1 again. There are minimum and maximum values that can be achieved for NT. These values are a function of P and the size of the ÷ N and ÷ A counters. The constraint N A always applies. If Amax = P ­ 1, then Nmin P ­ 1. Then NTmin = (P ­ 1) P + A or (P ­ 1) P since A is free to assume the value of 0. NTmax = Nmax P + Amax To maximize system frequency capability, the dual­modulus prescaler output must go from low to high after each group of P or P + 1 input cycles. The prescaler should divide by P when its modulus control line is high and by P + 1 when its MC is low. For the maximum frequency into the prescaler (fVCOmax), the value used for P must be large enough such that: 1. fVCOmax divided by P may not exceed the frequency capability of fin (input to the ÷ N and ÷ A counters). 2. The period of fVCO divided by P must be greater than the sum of the times: a. Propagation delay through the dual­modulus prescaler. b. Prescaler setup or release time relative to its MC signal. c. Propagation time from fin to the MC output for the frequency synthesizer device. A sometimes useful simplification in the programming code can be achieved by choosing the values for P of 8, 16, 32, or 64. For these cases, the desired value of NT results when NT in binary is used as the program code to the ÷ N and ÷ A counters treated in the following manner: 1. Assume the ÷ A counter contains "a" bits where 2a P. 2. Always program all higher order ÷ A counter bits above "a" to 0. MOTOROLA 3. Assume the ÷ N counter and the ÷ A counter (with all the higher order bits above "a" ignored) combined into a single binary counter of n + a bits in length (n = number of divider stages in the ÷ N counter). The MSB of this "hypothetical" counter is to correspond to the MSB of ÷ N and the LSB is to correspond to the LSB of ÷ A. The system divide value, NT, now results when the value of NT in binary is used to program the "new" n + a bit counter. By using the two devices, several dual­modulus values are achievable (shown in Figure 13). MC DEVICE A DEVICE B DEVICE B DEVICE A MC12009 MC12009 MC10131 MC10131 ÷ 20/÷ 21 MC12011 MC12011 MC12013 MC12013 ÷ 32/÷ 33 ÷ 40/÷ 41 ÷ 50/÷ 51 ÷ 80/÷ 81 ÷ 100/÷ 101 MC10138 MC10138 NOTE: MC12009 MC12009, MC12011 MC12011, and MC12013 MC12013 are pin equivalent. MC12015 MC12015, MC12016 MC12016, and MC12017 MC12017 are pin equivalent. Figure 13. Dual­Modulus Values MOTOROLA MC145151 MC145151­2 through MC145158 MC145158­2 31 PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP CASE 648­08 (MC145157 MC145157­2, MC145158 MC145158­D) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. ­A­ 16 9 1 8 B F C DIM A B C D F G H J K L M S L S ­T­ SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 P SUFFIX PLASTIC DIP CASE 707­02 (MC145155 MC145155­2) 18 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 10 B 1 9 A L C N F H D G MC145151 MC145151­2 through MC145158 MC145158­2 32 SEATING PLANE K M J DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0° 15° 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0° 15° 0.020 0.040 MOTOROLA P SUFFIX PLASTIC DIP CASE 710­02 (MC145151 MC145151­2, MC145152 MC145152­2) 28 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 15 B 1 14 A DIM A B C D F G H J K L M N L C N H G F M K D J SEATING PLANE MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0° 15° 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0° 15° 0.020 0.040 P SUFFIX PLASTIC DIP CASE 738­03 (MC145156 MC145156­2) -A20 11 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 10 B C -T- L K SEATING PLANE M E G N F J 20 PL 0.25 (0.010) D 20 PL 0.25 (0.010) MOTOROLA M T A M M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 15° 0° 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0° 15° 1.01 0.51 MC145151 MC145151­2 through MC145158 MC145158­2 33 DW SUFFIX SOG PACKAGE CASE 751D­04 (MC145155 MC145155­2, MC145156 MC145156­2) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. ­A­ 20 11 ­B­ 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S DIM A B C D F G J K M P R J S F R X 45 _ C ­T­ 18X G SEATING PLANE MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M K DW SUFFIX SOG PACKAGE CASE 751F­04 (MC145151 MC145151­2, MC145152 MC145152­2) -A28 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 15 14X -B1 P 0.010 (0.25) M B M 14 28X D 0.010 (0.25) M T A S B M S R X 45° C -T26X -T26X -T- G K SEATING PLANE F J MC145151 MC145151­2 through MC145158 MC145158­2 34 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8° 0° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0° 8° 0.395 0.415 0.010 0.029 MOTOROLA DW SUFFIX SOG PACKAGE CASE 751G­02 (MC145157 MC145157­2, MC145158 MC145158­2) ­A­ 16 9 ­B­ 8X P 0.010 (0.25) 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. M B M 8 16X J D 0.010 (0.25) M T A S B S F R X 45 _ C ­T­ 14X MOTOROLA G K SEATING PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 MC145151 MC145151­2 through MC145158 MC145158­2 35 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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