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MC10ELT/100ELT22

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The sm all outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 m akes it ideal fo r applications w hich require the translation of a clock and a data signal. Because the m ature MOSAIC 1.5 process is used, low cost can be added to the list of features -
OCR Scan
MC10ELT/100ELT22 10ELT 100ELT MC10ELT22 MC100ELT22 10ELT1
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual T T L to differential PECL translator. Because PEC L (Positive ECL) levels are used only +5V and ground are required. The sm all outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 m akes it ideal fo r applications w hich require the translation of a clock and a data signal. Because the m ature M OSAIC 1.5 process is used, low cost can be -
OCR Scan
100ELT1 DL140
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to D ifferential PECL Translator M C10ELT22 M C100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low cost can be -
OCR Scan
BR1330
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low cost can be added to the -
OCR Scan
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low cost can be added to the -
OCR Scan

HLT22

Abstract: klt22 MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 HLT22 ALYW 1 1 8 KLT22 ALYW · · · · · · 1.2
ON Semiconductor
Original
MC100 AND8002/D MC10ELT22DR2 MC100ELT22D MC100ELT22DR2 MC10ELT22DT

DL140

Abstract: ELT22 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low cost can be added to the
Motorola
Original
MC10ELT22/D
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA D ual T T L to D iffe re n tia l PECL T ra n s la to r M C 10E L T 22 M C 100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low -
OCR Scan

HLT22

Abstract: KLT22 MC10ELT22, MC100ELT22 5VDual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. · · · · · · · · · · · http://onsemi.com MARKING DIAGRAMS* 1.2 ns Typical Propagation Delay
ON Semiconductor
Original
HT22 EIA/JESD78 AND8003/D

HLT22

Abstract: KLT22 MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. MARKING DIAGRAMS* Features · · · · · · · 1.2 ns Typical Propagation Delay 8 8 < 300 ps
ON Semiconductor
Original
ic so8 socket BRD8011/D

HLT22

Abstract: MC100-A MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 HLT22 ALYW 1 1 8 KLT22 ALYW · · · · · · · · · ·
ON Semiconductor
Original
MC100-A AN1400 UL-94

KLT22

Abstract: HLT22 MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* Features · · · · · · · 1.2 ns Typical Propagation Delay 8
ON Semiconductor
Original
Abstract: MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* Features â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ 1.2 ns Typical Propagation ON Semiconductor
Original

klt22

Abstract: HLT22 MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 HLT22 ALYW 1 1 8 KLT22 ALYW · · · · · · 1.2
ON Semiconductor
Original
MC10ELT22DTR2 MC100ELT22DT

klt22

Abstract: HLT22 MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. · · · · · · http://onsemi.com MARKING DIAGRAMS* 1.2 ns Typical Propagation Delay < 300 ps
ON Semiconductor
Original

HLT22

Abstract: klt22 MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* Features · · · · · · · 1.2 ns Typical Propagation Delay 8
ON Semiconductor
Original

HLT22

Abstract: klt22 MC10ELT22, MC100ELT22 5VDual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. · · · · · · · · · · · http://onsemi.com MARKING DIAGRAMS* 1.2 ns Typical Propagation Delay
ON Semiconductor
Original

decoder BCD-7 segments

Abstract: MC10216P ON Semiconductor Emitter-Coupled Logic, Receivers, Drivers and Modulator/Demodulator MC10ELT and MC100ELT: ECLinPS Lite Translators 10 K and 100 K Emitter-Coupled Logic in Picoseconds Integrated Circuits Mfr.'s Mfr.'s Type Type No. of No. of MC10ELT MC100ELT Description Leads MC10ELT MC100ELT Description Leads SOIC SOIC SOIC SOIC — MC100ELT21D Differential PECL To TTL Translator 8 — MC100ELT23D Dual Differential PECL-to-TTL Translator 8 MC10ELT22D MC100ELT22D Dual TTL To Differential PECL Translator 8
Allied Electronics Catalog
Original
MC10116P MC14513BCP decoder BCD-7 segments MC10216P mc1489ap CMOS BCD-to-7-Segment LED Latch Decoder Drivers MC100ELT25D MC10H MC10H101P MC10H125P MC10H115P MC10H115FN
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 1:2 Fanout D ifferen tial PECL to TTL Translator The MC10ELT/100ELT26 is a 1:2 fanout differential PECL to TTL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the 1:2 fanout design of the ELT23 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board. Because the mature MOSAIC 1.5 process is used, low cost can -
OCR Scan
MC10ELT/100ELT26 ELT26 C10ELT26 C100ELT26
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA P roduct Preview 1:2 F an o u t D iffe re n tia l PECL to T T L T ra n s la to r The MC10ELT/100ELT26 is a 1:2 fanout differential PECL to TTL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The sm all outline 8-lead SOIC package and the 1:2 fanout design of the ELT23 makes it ideal for applications w hich require the low skew duplication of a signal in a tightly packed PC board. Because the m ature MOSAIC 1.5 process -
OCR Scan
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