MC100LVEL30 100LVEL30 EIA/JESD78 AND8003/D AND8002/D MC100LVEL30DWR2 - Datasheet Archive

 

3.3VECL Triple D Flip-Flop with Set and Reset The MC100LVEL30 is a triple master­slave D flip flop with differential outputs.

 

MC100LVEL30 MC100LVEL30 3.3VECL Triple D Flip-Flop with Set and Reset The MC100LVEL30 MC100LVEL30 is a triple master­slave D flip flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs. · · · · · · · MARKING DIAGRAM* 20 1200 MHz Minimum Toggle Frequency 450 ps Typical Propagation Delays 100LVEL30 100LVEL30 AWLYYWW 20 ESD Protection: >2 KV HBM 1 1 The 100 Series Contains Temperature Compensation. SO­20 DW SUFFIX CASE 751D PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V NECL Mode Operating Range: VCC= 0 V with VEE= ­3.0 V to ­3.8 V Internal Input Pulldown Resistors · · Meets or Exceeds JEDEC Spec EIA/JESD78 EIA/JESD78 IC Latchup Test · Moisture Sensitivity Level 1 · http://onsemi.com For Additional Information, see Application Note AND8003/D AND8003/D Flammability Rating: UL­94 code V­0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 347 devices A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D AND8002/D ORDERING INFORMATION Device 1 SO­20 38 Units/Rail MC100LVEL30DWR2 MC100LVEL30DWR2 January, 2001 ­ Rev. 4 Shipping MC100LVEL30DW MC100LVEL30DW © Semiconductor Components Industries, LLC, 2001 Package SO­20 1000 Units/Reel Publication Order Number: MC100LVEL30/D MC100LVEL30/D MC100LVEL30 MC100LVEL30 Logic Diagram and Pinout: 20-Lead SOIC (Top View) VCC Q0 Q0 VCC Q1 Q1 VCC Q2 Q2 VEE 20 19 18 16 15 14 13 12 11 Q Q Q Q Q Q S 17 R S D 1 S012 2 R S D 3 D0 CLK0 4 5 R0 D1 R D 6 7 8 9 10 D2 CLK1 R1 CLK2 R2 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. PIN DESCRIPTION TRUTH TABLE PIN FUNCTION D0­D2 R0­R2 CLK0­CLK2 S012 Q0­Q2; Q0­Q2 VCC VEE ECL Data Inputs ECL Reset Inputs ECL Clock Inputs ECL Common Set Input ECL Differential Data Outputs Positive Supply Negative Supply R S D CLK Q Q L L H L H L L L H H L H X X X Z Z X X X L H L H Undef H L H L Undef Z = LOW to HIGH Transition X = Don't Care MAXIMUM RATINGS (Note 1.) Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V ­8 to 0 V VI PECL Mode Input Voltage C ode u o age VEE = 0 V VI VCC 6 to 0 o V NECL Mode Input Voltage VCC = 0 V VI VEE ­6 to 0 V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range ­40 to +85 °C Tstg Storage Temperature Range ­65 to +150 °C JA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 20 SOIC 20 SOIC 90 60 °C/W °C/W JC Thermal Resistance (Junction to Case) std bd 20 SOIC 30 to 35 °C/W Tsol Wave Solder