MB91403 MB91430 10/100M EEE802 LQFP-144 EXD10/PB10 EXD11/PB11 EXD12/PB12 - Datasheet Archive

 

Preliminary-1 CONTROLLER MANUAL MB91403 HARDWARE MANUAL MB91430 HARDWARE MANUAL FUJITSU LIMITED Chapter1 OVERVIEW Overview,

 

FUJITSU Preliminary-1 CONTROLLER MANUAL MB91403 MB91403 HARDWARE MANUAL MB91430 MB91430 HARDWARE MANUAL FUJITSU LIMITED Chapter1 OVERVIEW Overview, Features 1 Chapter1 OVERVIEW 1.1 Overview What is the MB91403 MB91403? The MB91403 MB91403 is a one-chip network security LSI with a Fujitsu 32bit RISC microcomputer: FR as a CPU core together with a 10/100Base-T MAC Controller and encryption and authentication macros as well as a large-capacity ROM/RAM. As a feature of this LSI, the MAC Controller has a packet filtering function to alleviate the CPU load encountered in response to ever-increasing packet filtering. Also, the encryption and authentication processing macro realizes high speed processing of the encryption and authentication processing communications (IKE/IPsec/SSL), which will be even more necessary in the future. Equipped with more features such as an External IF that enables high-speed data communications with wide-ranging external hosts as well as an external memory IF, I2C IF, generalpurpose IO port, the MB91403 MB91403 will find various applications. Note that FR is used as the core but its chip select function is limited. For more information, see "1.6 Address map". 2 Chapter1 OVERVIEW 1.2 Features FR Core · Fujitsu FR series instruction compatible 32-bit RISC core, 5-stage pipeline, executing one instruction per cycle · Instruction cache: 4KB, data RAM: 8KB · Operating frequency: Max. 33MHz · DMAC: 5ch, UART: 2ch, 16-bit reload timer: 3ch, peripheral functions of an interrupt controller mounted *For more information, see Chapter 2, "FR Core Functions." ETHERNET MAC INTERFACE Packet filtering function The MB91403 MB91403 provides the packet filtering function in L3/L4 and allows you to select to pass or not to pass data if you set addresses (IP and MAC). It also provides a function of receiving data not only from its own address but also from registered multicast addresses. · Built-in 10/100M 10/100M MAC compliant to EEE802 EEE802.3 · MII interface (for full and half duplex operations) · SMI interface for PHY device control Layer 3/4 filtering function (hardware-based). This function allows you to decide to pass or drop a packet when it has a matching condition, i.e., either the IP address in Layer 3 (Network Layer) or the TCP/UDP port number in Layer 4 (Transport Layer). Encryption and authentication processing function The MB91403 MB91403 provides hardware-based support for DES/3DES/AES, private-key encryption systems that perform encryption and decryption of data as well as HMAC-MD5/HMAC-SHA1 used for data authentication. Compared with software-only systems, this system offers a 30 to 40 times better performance. Furthermore, it has a built-in accelerator function that executes on a hardware basis processing frequently used in a public-key encryption system or other such algorithm that imposes a significantly heavy load in software-based processing. Compared with software-based processing time, this feature offers about 100 times higher speed. With these functions, the MB91403 MB91403 supports IPsec, a security function used in the Network Layer of the Internet. The encryption and authentication functions can be easily used as functions by host applications and can also be used to speed up encryption applications such as RSA and SSL. · Support of ECB/CBC mode of DES/3DES/AES(Key Length=128/192/256bit) · Support of MD5/SHA-1/HMAC-MD5/HMAC-SHA-1 modes 3 Chapter1 OVERVIEW · Support of DH group: 1(MODP 768bit)/2(1024bit) EXTERNAL INTERFACE External interface with a communication function The MB91403 MB91403 is equipped with a high-capacity send and receive FIFO buffer that realizes massive data send and receive as well as a communication register. With a 1.5-kilobyte buffer for reception and a 1.5-kilobyte buffer for sending, the device has a function of processing data while storing it in the buffer and a host function that stops receiving data when the buffer is full. This feature enables performing communication control even during data send and receive in order to alleviate CPU load and realize efficient communications. · 8/16-bit data port · Send and receive data port control function · Transfer rate: 89Mbps(MAX.) * When the interface is not used, it can be used as a general-purpose port (Port B). GENERAL PURPOSE IO The 4-bit general-purpose IO port (Port A) and the external interface can be used as a generalpurpose IO port of 22 bits at the maximum (Port B). · The input-output settings can be made for each bit. · When the input settings are made, a signal change can be used to generate an interrupt (only on Port A). MEMORY INTERFACE The memory interface can be connected with various external memory and IO ports. · Support of ROM/RAM/SDRAM/FCRAM IF · 2-chip select signal · 8/16-bit data bus · Address space settings [ROM/RAM setting] An address area from 64Kbyte to 8Mbyte can be set. [SDRAM/FCRAM setting] An address area from 64Kbyte to 128Mbyte can be set. I2C INTERFACE The I2C Interface is a serial interface that supports Inter IC Bus advocated by Philips. · Master/slave send and receive function · Supports standard mode (Max.100Kbps) and high-speed mode (Max.400Kbps). High-capacity ROM/RAM A high-capacity ROM/RAM is embedded in the chip. In addition to the main ROM for user programs, the chip has a ROM storing serial download programs. · ROM: 256Kbyte (for user programs) + 2Kbyte (for serial download programs) · RAM: 64Kbyte 4 Chapter1 OVERVIEW Clock · Built-in crystal oscillation circuit · Built-in PLL · Input clock: 10MHz to 50MHz * For the combinations of input clocks and PLL multiplication modes, see Chapter 2, "Guide to FR Core Functions." LSI overall specifications · 0.18µCMOS Al5-layer technology · LQFP 144-pin package · 3.3-V single-power specification · Operating frequency: CPU/Peripheral modules (external buses) - 33MHz (MAX) Built-in resources of FR core - 16.5MHz (MAX) Note: To enable 100Base communications using the MAC IF of a peripheral module, set the operating frequency of the peripheral module to higher than 25MHz. (33MHz greater-than or equal to peripheral module operating frequency > 25MHz) Power consumption: 250mW @ 33MHz (MAX) 5 Chapter1 OVERVIEW 1.3 Internal block diagram 1.3.1 Block diagram E I-Cache(4KB) D-RAM(8KB) R Serial IF (2ch) UART INT(2ch) B INT OSC CLK Cont DMAC Crystal oscillator/ external clock PLL Timer FR CORE T Encryption/ Authentication macro DSU 10/100 Ethernet MAC Controller DSU IF PHY DES/3DES/AES HMAC-MD5/SHA1 L2/L3/L4 Filtering DH I2C Bus I2C IF ROM 256KByte GPIO PORT MUX External IF External IF/PORT 8/16bit bus RAM 64KByte MB91403 MB91403 SRAM/ SDRAM ROM/ FLASH FR core: Peripheral resources: 6 CPU, U-Timer, UART, Timer, Interrupt Controller, DMAC, Bit Search, external interrupt, memory_IF, data-RAM, cache, bus controller LAN, External_IF, Encryption/Authentication Macro, PIO, I2C, Builtin ROM, Built-in RAM (Peripheral resources are connected to the bus of the bus controller.) Chapter1 OVERVIEW 1.4 1.4.1 Input-Output Pins Signal lines SYSTEM IN TXI 1 INT[7:6] 2 MDI[2:0] 3 OSCILLATOR X0 1 X1 1 ICE BREAKI 1 ICS[2:0] 3 ICLK 1 ICD[3:0] 4 TEST TEST[2:0] 3 XTEST 1 SM 1 VPD 1 UART SIN[1:0] 2 SOUT[1:0] 2 SCK[1:0] 2 ETHERNET MAC IF TXCLK 1 TXD[3:0] 4 TXEN 1 RXCLK 1 RXER 1 RXD[3:0] 4 RXDV 1 RXCRS 1 COL 1 MDCLK 1 MDIO 1 MB91403 MB91403 Signal lines 124 Pin Power supply/ GND 20 Pin N.C. 0 Pin MEMORY IF A[22:0] D[31:16] RDX WRX[1:0] CSX[7:6] WEX MCLKE SRASX SCASX MCLKO RDY I2C IF SDA SCL EXTERNAL IF/GPIO(Port B) EXCSX/PB[21] EXA/PB[20] EXRDX/PB[19] EXWRX/PB[18] DREQRX/PB[17] DREQTX/PB[16] EXD[15:0]/PB[15:0] GPIO (Port A) PA[3:0] VDD/GND VCC VSS C 23 16 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 4 10 9 1 LQFP-144 LQFP-144 1.4.2 Pin description This section describes the list of pin functions. Format example The pin function list uses the conventions shown in the following format example: Pin name Pin no. Polarity I/O Circuit Function/application Pin 1 1 Positive OUT C The general functions and applications of this pin are described here. 7 Chapter1 OVERVIEW Pin name Pin no. Polarity I/O Circuit Function/application Pin 2 8 Negative I/O D The general functions and applications of this pin are described here. Pin 3 2 Positive IN A The general functions and applications of this pin are described here. Pin name Shows the external pin name. Pin no. Shows the package pin number of the target external pin. Polarity Shows the polarity at which the input or output pin becomes active.Throughout this specification, an input level is indicated either as "1" or "0" and an output level is indicated either as "H" or "L". "Positive": Input level of "1" and output level of "H" "Negative": Input level of "0" and output level of "L" I/O Shows the input or output direction of a signal in reference to this LSI. "IN" : Shows that this pin is an input pin of this LSI. "OUT" : Shows that this pin is an output pin of this LSI. "I/O" : Shows that this pin is an input-output pin of this LSI. Circuit Shows the circuit type of the I/O buffer. Function/application Shows the outline of functions of the target external pin. Caution Unused input pins should be made inactive and unused output pins should be left open. 8 Chapter1 OVERVIEW 1.4.2.1 Pin name INITXI INT[7:6] MD I[2:0] SYSTEM (6 pins) Pin no. 7 Negative 8,9 Negative (default setting) 17,15,14 1.4.2.2 Pin name Polarity - I/O IN IN IN Circuit Function/application A Setting initialization reset input This pin inputs a signal to initialize the settings of the LSI. When turning on the power supply, apply "0" level to the pin until the power supply and the clock signal input to the X 0 pin becomes stable. If INITXI is asserted "0", all built-in registers and external pins are initialized. A External interrupt input These pins input an external interrupt request signal. For external interrupt detection, set the ENIR, EIRR, and ELVR registers of the FR core. A Mode pin These pins determine the operation mode of the LSI. Always set this bit to "00 1". OSCILLATOR (2 pins) Pin no. Polarity I/O Circuit Function/application X0 11 - IN H Crystal oscillation/external clock input This is a common input pin of X0 11 -IN H crystal oscillation cell and external clock. 10MHz to 50MHz frequency can be input. X1 13 - I/O H Crystal oscillation output Output pin of X1 13 -I/O H crystal oscillation cell. 1.4.2.3 ICE (9 pins) Pin name Pin no. Polarity I/O Circuit Function/application BREAKI 16 Positive IN B Emulator break request This pin inputs the emulator break request when an ICE is connected. ICS[2:0] 24,22,20 Positive OUT C Emulator chip status These pins output the emulator status when an ICE is connected. ICLK 19 - OUT D-3 Emulator clock This pin serves as the emulator clock pin when an ICE is connected. ICD[3:0] 28 - 25 - I/O E Emulator data These pins serve as the emulator data bus when an ICE is connected. 9 Chapter1 OVERVIEW 1.4.2.4 Pin name TEST (6 pins) Pin no. Polarity I/O Circuit Function/application TEST [2:0] 133 - 135 - IN A Test pin Use this pin to select the BOOT ROM. For more information, see Section 1.7.5, "Boot ROM selection." XTEST 5 - IN A SCAN test pin SCAN test pin. Normally, fix this pin to "0". SM 6 - IN A SCAN mode pin SCAN mode pin. Normally, fix this pin to "0". VPD 136 - IN A Through current prevention pin Normally, fix this pin to "0". 1.4.2.5 UART (6 pins) Pin name Pin no. Polarity I/O Circuit SIN [1:0] 29,30 - IN A Serial data input Serial data input pin of built-in UART of the FR core. SOUT [1:0] 31,32 - OUT C Serial data output Serial data output pin of built-in UART of the FR core. SCK [1:0] 34,35 - I/O D-2 Serial clock input-output Serial clock input-output pin of built-in UART of the FR core. 10 Function/application Chapter1 OVERVIEW 1.4.2.6 MEMORY IF (50 pins) Pin name Pin no. Polarity I/O Circuit Function/application A [22:0] 37 - 43, 45 - 60 - OUT D-1 Address output 23-bit address signal pins. D [31:16] 73 - 88 - I/O D-1 Data input-output 16-bit data input-output signal pins. CSX [7:6] 64,63 Negative OUT D-2 Chip select output 2-bit chip select signal pin. Outputs "L" level signals during access to external memory. RDX 61 Negative OUT D-2 Read strobe output Read strobe signal pin. Outputs "L" level signals during read access. D-2 Write byte strobe output Write byte strobe signal pin. Outputs "L" level signals during write access. * Serves as DQM on the SDRAM/FCRAM area. WRX [1:0] 71,72 Negative OUT WEX 69 Negative OUT D-2 Write enable output Write enable signal pin. Outputs "L" level signals during write access regardless of the bus size. * Serves as a write-strobe pin on SDRAM/FCRAM. MCLKE 65 Positive OUT D-2 Memory clock enable output * Serves as CKE on the SDRAM/FCRAM area. SRASX 67 Negative OUT D-2 RAS signal output * Serves as RAS on the SDRAM/FCRAM area. SCASX 68 Negative OUT D-2 CAS signal output * Serves as CAS on the SDRAM/FCRAM area. MCLKO 66 - OUT C Memory clock output Outputs the same frequency clock as the internal bus. RDY 36 Positive IN A External RDY input When the external bus cycle is not completed, inputting "0" extends the bus cycle. 11 Chapter1 OVERVIEW 1.4.2.7 ETHERNET MAC IF (17 pins) Pin name Pin no. Polarity I/O Circuit Function/application RXCLK 2 - IN A Input of clock for reception MII sync signal during reception. The frequency is 2.5MHz at 10Mbps and 25MHz at 100Mbps. RXER 139 Positive IN A Receive error Input When "1" is input from the PHY device during reception, it is recognized that the reception packet has an error. RXDV 140 Positive IN A Receive data effective input It is recognized that receive data is effective. RXCRS 141 Positive IN A Carrier sense input It is recognized that either reception or sending is in progress. RXD[3:0] 1,144 142 - IN A Receive data Input 4-bit data input from PHY device. COL 3 Positive IN A Collision detection input When TXEN signal is active and this signal is "1", a collision is recognized. Otherwise, it is ignored. TXCLK 4 - IN A Input of send clock MII sync signal during sending. The frequency is 2.5MHz at 10Mbps and 25MHz at 100Mbps. TXEN 124 Positive OUT C Send enable output Indicates that effective data is on the TXD bus. This signal is output in synchronization with TXCLK. TXD[3:0] 125,127 129 - OUT C Send data output 4-bit data bus for sending to PHY device. This signal is output in synchronization with TXCLK. MDCLK 130 - OUT C SMI clock output SMI IF clock pin. Connect this pin to SMI clock input pin of PHY device. MDIO 132 - I/O D-2 1.4.2.8 SMI data input-output SMI data input-output pin. Connect this pin to SMI data pin of PHY device. I2C IF (2 pins) Pin name Pin no. Polarity I/O Circuit SDA 121 - I/O G Serial data line input-output I2C bus data input-output pin. SCL 122 - I/O G Serial clock line input-output I2C bus block input-output pin. 12 Function/application Chapter1 OVERVIEW 1.4.2.9 EXTERNAL IF /GPIO (Port B) (22 pins) Pin name Pin no. EXCSX/ PB[21] 109 EXA/ PB[20] Polarity I/O Negative IN - I/O General-purpose input-output port. IN External address input Input pin for address signals from external host. "0": Register select "1": FIFO data select - 110 Circuit Function/application External chip select input Input pin for chip select signals from external host. F F I/O General-purpose input-output port. External read strobe input Input pin for read strobe signals from external host. I/O Negative 115 OUT OUT - DREQTX/ PB[16] I/O Negative 114 IN - DREQRX/ PB[17] I/O - 112 IN Negative 111 EXWRX/ PB[18] Negative - EXRDX/ PB[19] I/O General-purpose input-output port. I/O External data input-output Input-output pins for data bus bits [15:0] with an external host. 89,91 93,95 EXD[15:0]/ 98,100 PB[15:0] 103,105 108 1.4.3 Pin name PA [3:0] 1.4.4 - F General-purpose input-output port. External write strobe input Input pin for write strobe signals from external host. F General-purpose input-output port. External receive data request output Indicates that data can be written to the receive FIFO. F General-purpose input-output port. External send data request output Indicates that there is data in the send register and the send FIFO. F F General-purpose input-output port. GPIO(Port A) (4pins) Pin no. Polarity 117 - 120 - I/O I/O Circuit Function/application F GPIO input-output Input-output port. When the input signal settings are made, a signal change can be used to generate an interrupt. Power supply/GND (20 pins) Pin name Pin no. I/O Function/application VDDE 10,12,21,33,64,90, 99,113,123,131 Power supply 3.3V power supply pins. Use all of these pins at the same potential. VSS 18,23,44,70,94, 104,116,126,138 GND GND pins. Use all of these pins at the same potential. C 137 OUT Pin for connecting a capacitor for the built-in regulator. 13 Chapter1 OVERVIEW 1.4.5 A Input-output circuit types Digital input CMOS level input Digital input CMOS level input with pulldown Pullup resistance = about 33K (TYP) B Digital output CMOS level output IOL = 4mA C Digital output Digital output D-1 Digital output CMOS level output CMOS level input IOL = 2mA Digital input Digital output D-2 Digital output Digital input 14 CMOS level output CMOS level input IOL = 4mA Chapter1 OVERVIEW Digital output D-3 Digital output CMOS level output CMOS level input IOL = 8mA Digital input Digital output E Digital output With pulldown CMOS level output CMOS level input Pulldown resistance = about 33K (TYP) IOL = 4mA Digital input Digital output F Digital output With pullup CMOS level output CMOS level input Pullup resistance = about 33K (TYP) IOL = 4mA Digital input Digital input G Digital output I2C Bus Fast Mode I/O Buffer CMOS level output CMOS Schmitt trigger input IOL = 4mA Digital output 15 Chapter1 OVERVIEW Oscillation output H Oscillation circuit Feedback resistance of 1M X1 Built-in feedback resistor X0 16 Chapter1 OVERVIEW Pin Assignment Diagram EXD0/PB0 EXD1/PB1 EXD2/PB2 EXD3/PB3 VSS EXD4/PB4 EXD5/PB5 EXD6/PB6 EXD7/PB7 VDDE EXD8/PB8 EXD9/PB9 EXD10/PB10 EXD10/PB10 EXD11/PB11 EXD11/PB11 VSS EXD12/PB12 EXD12/PB12 EXD13/PB13 EXD13/PB13 EXD14/PB14 EXD14/PB14 VDDE EXD15/PB15 EXD15/PB15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 1.4.6 108 106 107 EXCSX/PB21 EXCSX/PB21 EXA/PB20 EXA/PB20 EXRDX/PB19 EXRDX/PB19 EXWRX/PB18 EXWRX/PB18 VDDE DREQRX/PB17 DREQRX/PB17 DREQTX/PB16 DREQTX/PB16 VSS PA3 PA2 PA1 PA0 SDA SCL VDDE TXEN TXD3 VSS TXD2 TXD1 TXD0 MDCLK VDDE MDIO TEST2 TEST1 TEST0 VPD C VSS RXER RXDV RXCRS RXD0 RXD1 RXD2 104 105 102 103 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 101 109 72 110 71 111 70 112 69 113 68 114 67 115 66 116 65 117 64 118 63 119 62 120 61 121 60 122 59 123 58 MB91403 MB91403 (Top View) 124 125 126 127 128 129 130 56 55 54 53 52 51 131 50 132 49 133 48 134 47 135 46 136 45 137 44 138 43 139 42 140 41 141 40 142 39 143 38 144 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 RDY SCK0 SCK1 VDDE SOUT0 SOUT1 SIN0 SIN1 ICD3 ICD2 ICD1 ICD0 ICS2 VSS ICS1 VDDE ICS0 ICLK VSS MDI2 MDI1 MDI0 X1 VDDE X0 VDDE INT6 INT7 INITXI SM XTEST TXCLK COL RXCLK RXD3 1.4.7 57 WRX1 WRX0 VSS WEX SCASX SRASX MCLKO MCLKE VDDE CSX6 CSX7 RDX A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 Pin number table Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 1 RXD3 37 A22 73 D31 109 EXCSX 2 RXCLK 38 A21 74 D30 110 EXA 3 COL 39 A20 75 D29 111 EXRDX 4 TXCLK 40 A19 76 D28 112 EXWRX 5 XTEST 41 A18 77 D27 113 VDDE 6 SM 42 A17 78 D26 114 DREQRX 7 INITXI 43 A16 79 D25 115 DREQTX 8 INT7 44 VSS 80 D24 116 VSS 9 INT6 45 A15 81 D23 117 PA3 10 VDDE 46 A14 82 D22 118 PA2 17 Chapter1 OVERVIEW Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 11 X0 47 A13 83 D21 119 PA1 12 VDDE 48 A12 84 D20 120 PA0 13 X1 49 A11 85 D19 121 SDA 14 MDI0 50 A10 86 D18 122 SCL 15 MDI1 51 A9 87 D17 123 VDDE 16 BREAKI 52 A8 88 D16 124 TXEN 17 MDI2 53 A7 89 EXD15 EXD15 125 TXD3 18 VSS 54 A6 90 VDDE 126 VSS 19 ICLK 55 A5 91 EXD14 EXD14 127 TXD2 20 ICS0 56 A4 92 EXD13 EXD13 128 TXD1 21 VDDE 57 A3 93 EXD12 EXD12 129 TXD0 22 ICS1 58 A2 94 VSS 130 MDCLK 23 VSS 59 A1 95 EXD11 EXD11 131 VDDE 24 ICS2 60 A0 96 EXD10 EXD10 132 MDIO 25 ICD0 61 RDX 97 EXD9 133 TEST2 26 ICD1 62 CSX7 98 EXD8 134 TEST1 27 ICD2 63 CSX6 99 VDDE 135 TEST0 28 ICD3 64 VDDE 100 EXD7 136 VPD 29 SIN1 65 MCLKE 101 EXD6 137 C 30 SIN0 66 MCLKO 102 EXD5 138 VSS 31 SOUT1 67 SRASX 103 EXD4 139 RXER 32 SOUT0 68 SCASX 104 VSS 140 RXDV 33 VDDE 69 WEX 105 EXD3 141 RXCRS 34 SCK1 70 VSS 106 EXD2 142 RXD0 35 SCK0 71 WRX0 107 EXD1 143 RXD1 36 RDY 72 WRX1 108 EXD0 144 RXD2 18 Chapter1 OVERVIEW 1.4.8 Outside dimensions Plastic mold 1.70mm MAX Weight 2003 FUJITSU LIMITED F176006S-c-4-6 Gull-wing Mounting height C 20.0 x 20.0mm Sealing method Plastic LQFP, 144-pin (FPT-144P-M08 FPT-144P-M08) 0.50mm Lead type (FPT-144P-M08 FPT-144P-M08) Lead pitch Package width by package length Plastic LQFP, 144-pin 1.20g Code (for your reference) P-LFQFP144-20 P-LFQFP144-20×20-0.50 Note 1: A dimension with an asterisk do not include resin residue.* The resin residue is +0.25 (.010) on one side at the maximum. Note 2: The width and thickness of a pin include the thickness of plating. Note 3: The width of a pin does not include tie bar cut residue. Unit: mm (inches) Note: Values in parentheses are reference values. 19 Chapter1 OVERVIEW 1.5 1.5.1 Precaution on use Preventing latch-up Latch-up may occur if a higher voltage than VDDE or a lower voltage than VSS is applied to the input pin or output pin of a CMOS IC or if a higher voltage than the ratings is applied to between VDDE to VSS. If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating during device operation. 1.5.2 1.5.2.1 Treatment of pins Treatment of unused pins Leaving unused input pins open may result in a malfunction. Apply pullup or pulldown treatment to such pins. 1.5.2.2 Treatment of output pins A large current may flow to an output pin if it is short-circuited with the power supply or other output pin or if it is connected to a large volume load. Leaving the output pin that way for an extended period of time degrades the device. Use meticulous care not to let any current exceed the maximum rating during device operation. 1.5.2.3 About mode (MDI[3:0]) pins and test (TEST[2:0], XTEST, SM, VPD) pins Connect these pins directly to VDDE or VSS. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between individual mode pins and VDDE or VSS on the PC board and connect them with as low an impedance as possible. 1.5.2.4 About power supply pins The power pins should be connected to VDDE and VSS of this device at the lowest possible impedance from the power supply source. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between VDDE and VSS near this device. 1.5.2.5 Crystal oscillation circuit Noise near the X0 and X1 pins may cause the MB91403 MB91403 to malfunction. Design the PC board so that the X0 and X1 pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a layout. 1.5.2.6 Connection specification of MB91403 MB91403 and ICE This section describes the recommended type and circuit composition, designing precautions, 20 Chapter1 OVERVIEW and wiring regulations for the emulator interface connector to be mounted on a user system. To use a flat cable, it is recommended that you select a combination of connectors with housing. Recommended connector type Attached cable Part number Remarks FPC cable FH10A-30S-1SH FH10A-30S-1SH (Maker: Hirose Electric Co., Ltd.) With latch Circuit composition When an ICE is connected, put a damping resistor of 15 in series with the ICLK signal to ensure stability of operation. When you design a PC board, mount the resistor near the ICLK pin of this LSI. Emulator interface connector MCU for evaluation MB2198-01 MB2198-01 and MB2197-01 MB2197-01 side VDDE FUSE UVcc MB91403 MB91403 1 VDDE 15 ICLK 3 ICLK ICS[2:0] ICS[2:0] ICD[3:0] ICD[3:0] BREAK BREAKI RST INITXI *2 XRSTIN FR (Open) GND Reset output circuit VSS *1: Use a wiring pattern with a higher capacity than the current rating. *2: See "Precaution on designing" for more information on a switch circuit, which may become necessary. *3: Mount the resistor near the ICLK pin of the MB91403 MB91403. 21 Chapter1 OVERVIEW Precaution on designing When you operate the evaluation MCU on a user system without an emulator connected, the input pins of the evaluation MCU connected to the emulator interface should be treated on the user system as shown below. During designing, therefore, note that a switch circuit, etc. may be necessary on the user system. The emulator interface pins should be treated as shown below. Table 1.5-1 Emulator interface pin treatment (DSU-3) Evaluation MCU pin name Pin treatment INITXI To be connected to the reset output circuit on the user system BREAKI To be connected to pulldown Other To be open Table 1.5-2 Emulator interface wiring regulations Signal line name Wiring regulation ICLK ICS[2:0] ICD[3:0] BREAKI · The total wiring length of each signal (from an evaluation MCU pin to an emulator interface connector pin) shall be not more than 50 mm. · The difference between the total wiring lengths of signals shall be not more than 2 cm and the total wiring length of ICLK shall be the shortest of all. UVCC · Use a wiring pattern with a higher capacity than the current rating. · Connecting a probe incorrectly may cause a short circuit or reverse connection between the power source and GND. For safety's sake, insert a fuse or other protective circuit in each power supply pattern. GND · To be directly connected to a power supply pattern such as the ground plane. Documents for reference For connection with an ICE, see also the following manuals: · DSU-FR Emulator MB2198-01 MB2198-01 Hardware Manual · FR20/30 FR20/30 Series MB2197-01 MB2197-01 Hardware Manual 22 Chapter1 OVERVIEW 1.5.3 Precaution on mounting a crystal oscillator The built-in crystal oscillation circuit of this LSI has the following configuration: MB91403 MB91403 OSC X0 X1 Rr To be added during overtone oscillation Crystal oscillator C1 C2 C3 Pin description Pins Function X0 Input pin of crystal oscillation cell (OSC) X1 Output pin of crystal oscillation cell (OSC) Circuit constants on external boards Circuit constant Description C1,C2,C3 External load capacity L Inductance Rr Damping resistor (to be added if necessary) Reference values Oscillation frequency C1,C2 C3 L Rr Up to 30MHz 5 to 33pF None None None 20MHz to 50MHz 5 to 15pF Around 10nF Around uH None C3 and L need to be added depending on the basic wave and overtone characteristics of a 20MHz to 30MHz oscillator. Note: These reference values are to be used only as a guide. The constants vary according to the characteristics of a crystal oscillator to be used. Fujitsu recommends, therefore, that you conduct preliminary evaluation using an evaluation sample to 23 Chapter1 OVERVIEW establish the circuit constants. To obtain an evaluation sample, contact the Fujitsu sales department. 1.5.3.1 Receiving clock input signals to the crystal oscillation cell from out of the LSI To use clock signals generated by an oscillation module outside the LSI, input external clock signals to the X0 pin and leave the X1 pin open as shown in the following figure. External clock X0 OPEN X1 MB91403 MB91403 If external signals to be input have such small-amplitude waveforms that they do not come across Vth (VDDE/2) of the inverter, the signals cannot be propagated to inside the LSI. In this case, you may need to take a necessary countermeasure such as inserting a capacitor of about 0.01µF between the oscillation module, etc. and the X0 pin on the board to shape the signals into an input waveform centered around Vth of the inverter before inputting it. 1.5.4 1.5.4.1 Precaution on handling power supply Power-on At the time of power-on, apply a setting initialization reset (INIT) from the INITXI pin. Input an "L" level to the INITXI pin until the input clock becomes stable. 1.5.4.2 Indeterminable output at power-on At power-on, the output pins may become indeterminable until the internal power supply becomes stable. 1.5.4.3 Built-in DC-DC regulator The MB91403 MB91403 has a built-in regulator. You need to supply 3.3V input to the VDDE pin 24 Chapter1 OVERVIEW and connect a bypass capacitor of about 4.7µF for the regulator to the C pin. 3.3V VDDE C 4.7µF VSS MB91403 MB91403 GND 1.5.5 1.5.5.1 Precaution on the device About the watchdog timer function The watchdog timer function of this macro is provided to check that a program delays a reset within a certain period of time and reset the CPU if the program runs away and fails to delay a reset.Once the watchdog timer function is enabled, therefore, it keeps running until a reset occurs. As an exception, a reset is automatically delayed under a condition that program execution is stopped on the CPU. For the conditions to which this exception applies, see the section on the function description for the watchdog timer. Note that a watchdog reset may not occur if the above status is reached due to system runaway. If so, apply a reset (INIT) from the external INITXI pin. 1.5.5.2 Restrictions Clock control block · Allow for clock stabilization time when you input "L" to INITXI. · To enter the standby mode, use the synchronous standby mode (set with the bit8 SYNCS bit in the TBCR: time-base counter control register) and then use the following sequence: (LDI #value_of_standby,R0); value_of_standby is write data to STCR. (LDI #_STCR,R12) ; _STCR is an address (481H) of STCR. STB R0,@R12 ; Write to standby control register (STCR). LDUB @R12,R0 ; STCR read for synchronous standby LDUB @R12,R0 ; Dummy re-read of STCR NOP NOP NOP NOP NOP In addition, set the I-flag and the ILM and ICR registers to branch to an interrupt handler after the interrupt handler triggers the microcontroller to return from the standby mode. 25 Chapter1 OVERVIEW · If you use the monitor debugger, observe the following precautions: Do not set a breakpoint within the above array of instructions. Do not single-step the above array of instructions. 26 Chapter1 OVERVIEW CPU · Since the instruction fetch is not done from D-bus, do not set the code area on DbusRAM. · Do not set a stack area or a vector table on the instruction RAM. · The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S instruction results in (a) acceptance of a user interrupt, (b) singlestepping, or (c) a break in response to a data event or emulator menu: (1)The D0 and D1 flags are updated in advance. (2)An EIT handling routine (user interrupt or emulator) is executed. (3)Upon returning from the EIT, the DIV0U/DIV0S instructions are executed and the D0/D1 flags are updated to the same value as in (1). · When a user interrupt factor exists, executing either of theORCCR, STILM and MOV Ri and PS instructions to enable an interrupt results in the following operations: (1)The PS register is updated in advance. (2)An EIT handling routine (user interrupt) is executed. (3)Upon returning from the EIT, the above instructions are executed and the PS registers are updated to the same value as in (1). · Since some instructions manipulate the PS register earlier, the following exceptions may cause a break in the interrupt handling routine or update the display content of the PS flag when the debugger is being used. In either case, the processing is conducted properly again after return from an EIT, the operations before and after the EIT are conducted as specified. 1.The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S instruction results in (a) acceptance of a user interrupt, (b) single-stepping, or (c) a break in response to a data event or emulator menu: (1)The D0 and D1 flags are updated in advance. (2)An EIT handling routine (user interrupt or emulator) is executed. (3)Upon returning from the EIT, the DIV0U/DIV0S instructions are executed and the D0/D1 flags are updated to the same value as in (1). 2. When a user interrupt factor exists, executing either of the ORCCR, STILM and MOV Ri and PS instructions to enable an interrupt results in the following operations: (1)The PS register is updated in advance. (2)An EIT handling routine (user interrupt) is executed. (3)Upon returning from the EIT, the above instructions are executed and the PS registers are updated to the same value as in (1). · Do not access data in the control register of the instruction cache and the cache memory in RAM mode immediately before the RETI instruction. 27 Chapter1 OVERVIEW · If one of the instructions listed below is executed, the SSU or USP (*1) value is not used as the R15 value and, as a result, an incorrect value is written to memory. This applies to only the following 10 types of instructions with R15 specified as Ri. AND R15,@Rj ANDH R15,@Rj ANDB R15,@Rj OR R15,@Rj ORH R15,@Rj ORB EOR R15,@Rj EORH R15,@Rj EORB R15,@Rj XCHB @Rj,R15 R15,@Rj (*1) R15 has no entity. When a program accesses R15, either SSP or USP is accessed depending on the state of "S" flag of the PS register. Specify a general-purpose register other than R15 when you write either of the above ten instructions in assembler. External bus interface · If the area set up as little endian has a 32-bit bus width, access the relevant area using only word (32-bit) access. · To enable prefetch to the area set up as little endian, access the relevant area using only word (32-bit) access. The area cannot be correctly accessed using byte or half-word access. DMA · Do not use DMA transfer to the instruction RAM. Bit search module · The BSD0, BSD1, and BDSC registers can be accessed using word access only. 1.5.6 1.5.6.1 Precautions related to debugging Single-stepping the RETI instruction If an interrupt occurs frequently during single-stepping, only the relevant processing routine is repeatedly executed after single-stepping RETI. Consequently, the main routine and lowinterrupt-level programs are no longer executed. To work around this problem, do not single-step the RETI instruction. Alternatively, perform debugging with the relevant interrupt disabled after the debugging of the relevant interrupt routine becomes unnecessary. 1.5.6.2 Operand break Do not apply a data event break to access to the area containing the address of a system stack pointer. 1.5.6.3 Interrupt handler for NMI request (tool) Add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor flag to be set only in response to a break request from the ICE is erroneously set, for example, by an adverse effect of noise to the DSU pin while the ICE is not connected. Note that the ICE can be used without problems after this program is added. 28 Chapter1 OVERVIEW Location to add this program The following interrupt handler Interrupt factor : NMI Request (tool) Interrupt number : 13(decimal), 0D(hexadecimal) Offset : 3C8H TBR is the default address : 000FFFC8H 000FFFC8H Program to be added STM (R0,R1) LDI #B00H,R0 ; B00H is the address of DSU break factor register. LDI #0,R1 STB R1,@R0 LDM (R0,R1) ; Clear the break factor register. RETI 1.5.6.4 Trace mode If, during debugging, the trace mode is set to "Full trace mode" (in which the trace memory of the ICE itself is used with the built-in FIFO as output buffer, thus preventing the loss of trace data), the electric current may be increased or D-busDMA access may be lost. Also, the trace data may be lost. To work around this problem, do not set the full trace mode. 1.5.6.5 Simultaneous occurrence of a software break and a user interrupt If a software break and a user interrupt occur simultaneously, the debugger may encounter the following phenomena: The debugger stops while pointing to a location other than the programmed breakpoints. The halted program is not re-executed correctly. If either of these phenomena occurs, use a hardware break in additino to a software break. If you are using the monitor debugger, do not set any break at the relevant location. 29 Chapter1 OVERVIEW 1.6 Address map The built-in FR core of this LSI can be configured to have eight chip select (CS) areas. The CS areas are allocated in this LSI as follows: · CS0-1,6-7: User area - Allocated to the CS0 built-in ROM area.(*1) - Allocated to the CS1 built-in RAM area. CS6-7: These areas are allocated to the external chip select signals: CSX[6]/CSX[7]. - CS6 CSX[6] - CS7 CSX[7] · CS2-5: Areas for management of this LSI (*1) CS0 can be allocated to an external area in the external pin (TEST[2:0]) setting. For more information, see Section 6.1, "Built-in and External Boot ROM selection." 1.6.1 Chip select area settings The areas for management of this LSI, which are allocated to the CS2-5 areas, consist of the registers and processing areas of peripheral modules of this LSI, such as the built-in MAC interface, encryption and authentication processing unit, I2C interface, and GPIO. Before configuring the registers of these modules, first configure the ASR (Area Select Register), ACR (Area Configuration Register), AWR (Area Wait Register) and define the CS areas. The following table shows the modules allocated to each of the CS0-5 areas and whether the RDY control of the FR core should be conducted. CS area Address Size RDY control CS0 Built-in ROM 0x000C_0000 0x000F_FFFF 256KB 256KB Not required CS1 Built-in RAM 0x0010_0000 0x0010_FFFF 64KB Not required CS2 I2C IF 0x010F_0000 0x010F_FFFF 64KB Not required CS3 MAC/MII IF Encryption and authentication processing unit 0x0110_0000 0x0113_FFFF 256KB 256KB Not required CS4 External IF/PORT 0x0114_0000 0x0114_FFFF 64KB Not required CS5 30 Module DH processing unit 0x0115_0000 0x0115_FFFF 64KB Not required Chapter1 OVERVIEW The areas for management of this LSI basically have 32-bit bus specifications. However, note that CS2 has 8-bit bus specifications. The following figures show the setting examples for the ASR, ACR, and AWR registers in the FR core. Setting values for CS registers (Examples) ASR0=0x000C ACR0=0x2940 AWR0=0x0148 ASR1=0x0010 ACR1=0x0920 AWR1=0x0148 ASR2=0x010F ACR2=0x0020 AWR2=0x2048 ASR3=0x0110 ACR3=0x2820 AWR3=0x1048 ASR4=0x0114 ACR4=0x0820 AWR4=0x2058 ASR5=0x0115 ACR5=0x0820 AWR5=0x2048 ASR (Area Select Register) setting example ASRx 15 A31 14 A30 13 A29 2 A18 1 A17 0 A16 CS0 : 16'h000C CS1 : 16'h0010 CS2 : 16'h010F CS3 : 16'h0110 CS4 : 16'h0114 CS5 : 16'h0115 31 Chapter1 OVERVIEW ACR (Area Configuration Register) setting example ACRx 15 ASZ3 14 ASZ2 13 ASZ1 12 ASZ0 CS0 : 4'h2 (256KB 256KB) CS1 : 4'h0 (64KB) CS2 : 4'h0 (64KB) CS3 : 4'h2 (256KB 256KB) CS4 : 4'h0 (64KB) CS5 : 4'h0 (64KB) ACRx 7 SREN 6 PFEN 10 DBW0 9 BST1 8 BST0 CS0 : 2'b10 (32bit) CS0 : 2'b01 (2burst) CS1 : 2'b10 (32bit) CS1 : 2'b01 (2burst) CS2 : 2'b00 (8bit) CS2-5 : 2'b00 CS3 : 2'b10 (32bit) (Single access) CS4 : 2'b10 (32bit) CS5 : 2'b10 (32bit) 5 WREN CS0-1:1'b1 1'b0 (No BRQ/ (Prefetch BGR NTX) enabled) 11 DBW1 4 0 3 TYP3 CS0:1'b0 (Write disabled) 2 TYP2 1 TYP1 0 TYP0 CS0-5 : 4'h0 (Normal access) Others:1'b0 Others:1'b1 (Write (Prefetch enabled) disabled) AWR (Area Wait Register) setting example AWRxH 15 W15 14 W14 13 W13 12 W12 11 W11 7 W07 6 W06 2'b01 (Idle cycle during successive read and write: 1) 5 W05 4 W04 CS0-3,5 : 2'b00 8 W08 (Burst access not supported) 3 W03 2 W02 1 W01 1'b1 1'b0 1'b0 1'b0 (CSX setup cycle: 0) (CSX hold cycle: 0) (Write recovery cycle: 0) (Asynchronous (Address write strobe setup output) cycle: 0) CS4 : 2'b01 (Write recovery cycle: 1) For W05-W04 W05-W04 of AWR4, 2' b00 must not be set. 32 9 W09 CS0 : 4'h1 (1 wait cycle) CS1 : 4'h1 (1 wait cycle) Others : 4'h0 CS0 : 4'h0 (0 wait cycle) CS1 : 4'h0 (0 wait cycle) CS2 : 4'h2 (2 wait cycles) CS3 : 4'h1 (1 wait cycle) CS4 : 4'h2 (2 wait cycles) CS5 : 4'h2 (2 wait cycles) AWRxL 10 W10 0 W00 Chapter1 OVERVIEW 1.6.2 Address map The following figure shows the address map of this LSI. Module Name Chip Select SIZE Wait Cycle 0000_0000H 0000H FR core area FR core internal area 0004_0000H 0000H 000C_0000H 0000H Built-in ROM CS[0] 256KB 256KB 0 Built-in RAM CS[1] 64KB 0 CS[2] 64KB 2 CS[3] 256KB 256KB 1 0010_0000H 0000H 010F_0000H 0000H I2C IF User area 0110_0000H 0000H 0111_0000H 0000H 0112_0000H 0000H MAC/MII IF Encryption and authentication processing unit Areas for management of this LSI 0113_0000H 0000H 0114_0000H 0000H External IF/GPIO CS[4] 64KB 2 DH processing unit CS[5] 64KB 2 0115_0000H 0000H 0116_0000H 0000H FFFF_FFFFH The built-in ROM (*1) and RAM and peripheral modules allocated to the areas for management of this LSI can also be set to other address spaces than shown in the above figure. In this case, the CS[5:2] areas need to have a start address that meets the following conditions: [ CS [3] start address setting condition] Address[17:16]= "00" [ CS[5:4,2] start address setting condition] Address[13:12]= "00" *1 The reset and mode vector table of the FR core are allocated to the following address areas. Therefore, the built-in ROM needs to have an address space that meets the following conditions: · Reset vector: 0x000F_FFFCH · Mode vector: 0x000F_FFF8H 33 Chapter1 OVERVIEW 1.7 Operation 1.7.1 Clock Clock generation control The internal clock is generated in the FR core as follows: · Selecting a source clock: Select a clock source. · Generating a base clock: Divide the source clock by two or cause PLL oscillation to generate a base clock. · Generating internal clocks: Divide the base clock to generate three operating clocks to be supplied to various parts of the device. The following sections describe the generation and control of these clocks. For detailed description of register flags listed in the explanation, see Sections 2.3.10.9, "Block diagram of clock generation control unit" and 2.3.10.10, "Registers of clock generation control unit." Source clock Self-excited oscillation mode (X0 and X1 pins input) In this mode, an oscillator is connected to the external oscillation pin and the original oscillation generated in the built-in oscillation circuit is used as the source clock. All the clock sources including the external bus clock are the FR core. External oscillation mode (X0 pin input and X1 pin open) In this mode, the clock generated by an oscillation module, etc. outside the LSI is used as the source clock. All the clock sources including the external bus clock are the FR core. If external signals to be input have such small-amplitude waveforms that they do not get across Vth (VDDE/2) of the inverter, the signals cannot be propagated to inside the LSI. In this case, you may need to take a necessary countermeasure such as inserting a capacitor of about 0.01µF in series between the oscillation module, etc. and the X0 pin on the board to shape the signals into an input waveform centered around Vth of the inverter before inputting it. Base clock Generate the internal base clock using either of the following source clocks. · Main clock divided by two · Main clock multiplied by PLL The source clock selection control is conducted according to the setting of the clock source control register (CLKR). 34 Chapter1 OVERVIEW 1.7.1.1 Block diagram of clock generation control unit The following figure shows the block diagram of the clock generation control unit. Clock generation unit Selector External bus clock division CPU clock Stop control Peripheral clock division Selector CPU clock division Selector DIVR0 and 1 registers Peripheral clock (in FR) External bus clock Peripheral clock (such as MAC IF) X0 X1 PLL Oscillation circuit 1/2 Selector CLKR register FR Core MB91403 MB91403 1.7.2 Reset When a reset factor occurs, this LSI stops the operations of all the programs and hardware and initializes the operation status. There are three types of reset operations, each of which has different generation triggers and initialization processes. 1.7.2.1 Setting initialization reset (INITXI pin) Asserting the "L" level input of the INITXI (reset) pin generates a reset and causes initialization. [ Initialization location] · FR core: Section 2.3.9.2.1, "Setting initialization reset (INIT)" is executed. · Peripheral macro: The information of all the registers, internal operations, and external pins is initialized. 35 Chapter1 OVERVIEW Power voltage X0 and X1 pins INITX pin Apply the "L" level input to the INITXI pin until the power voltage and the external clock input become stable. 1.7.2.2 Watchdog reset When the watchdog timer expires, a watchdog timer reset is generated and initialization is conducted. [ Initialization location] FR core: Section 2.3.9.2.1, "Setting initialization reset (INIT)" is executed. However, the reset factor flag is not cleared. 1.7.2.3 FR reset Due to a software reset in the FR core, a reset is generated and initialization is conducted. [ Initialization location] · FR core: Section 2.3.9.2.2, "Operation initialization reset (RST)" is executed. · Peripheral macro: The information of all the registers, internal operations, and external pins is initialized. 1.7.3 Interrupt The FR core has eight external interrupt pins, six of which are used for interrupts in this LSI and the remaining two of which are connected to external pins, being allocated to interrupts from outside this LSI. Interrupts in this LSI are connected to the external interrupt pins of the FR core, being allocated as shown in the following figure. The settings for external interrupt enable, interrupt request, and interrupt request detection are made in the ENIR (external interrupt enable register), EIRR (external interrupt factor register), and ELVR (request level setting register), respectively. 36 Chapter1 OVERVIEW MB91403 MB91403 FR Core INT[7:6] External interrupt pin : INT[7:6] INT[5] INT[4] I2C IF INT[3] External IF INT[2] reserved INT[1] Authentication processing unit INT[0] External interrupt pins (8) GPIO Ethernet MAC IF INT[7:6] External interrupt pins: Allocated to INT[7:6]. INT[5] Interrupt signals from GPIO (Port A) are input. INT[4] Interrupt signals from I2C IF are input. INT[3] Interrupt signals from External IF are input. INT[2] Reserved for future use INT[1] Interrupt signals from the authentication processing unit are input. INT[0] Interrupt signals from Ethernet MAC IF are input. Note: All the interrupt signals in this LSI are asserted "High" active. Therefore, set the ELVR register to "H" level detection. For information on the settings and processing of interrupts, see the manuals supplied with modules. 1.7.4 DMA transfer This LSI provides the DMA transfer function using the DMAC of the FR core. DMAC has five channels, two of which are used in the LSI. The FR core DMAC channels are allocated as follows: 1) DMA factors from ch0 Ethernet MAC IF The MAC IF (receive FIFO) to Memory supports the Fly-by (IO to Memory) mode. Note: The Memory to MAC IF (send FIFO) supports only DMA transfer through software activation. Note: In Fly-by mode, two I/O wait cycles need to be set in IOWR0 (I/O Wait Register for DMAC) in the CPU. 2) DMA factor from ch1 External IF The External IF (receive FIFO) to Memory supports Fly-by (IO to Memory) mode. 3) DMA factor other than ch2 DREQ 37 Chapter1 OVERVIEW 4) DMA factor other than ch3 DREQ 5) DMA factor other than ch4 DREQ MB91403 MB91403 FR Core DREQ0 DMAC (ch.0) DACKX0 IORDX Ethernet MAC IF EOPX0 EOTX0 DREQ1 DMAC (ch.1) DACKX1 IORDX EOPX1 External IF OPEN EOTX1 DMAC (ch.2-4) 38 * Factors other than DREQ Chapter3 LAN CONTROLLER Overview, Features 39 Chapter3 LAN CONTROLLER 3.1 Overview This is the Ethernet LAN controller compliant to IEEE802 IEEE802.3 with the built-in 10/ 100BASE-T 100BASE-T transceiver incorporating L3/4 filtering functions. LAN controller has the following features. · Packet filtering function · Packet filtering functions of L2/L3/L4 enable CPU load reduction. · 10/100M 10/100M MAC compliant to IEEE802 IEEE802.3 To perform 100M communication with this product, you must configure the settings for the operating frequency of LAN controller (external bus frequency of FR) to above 25MHz. · MII interface (for full and half duplex operations) · SMI interface for PHY device control When you conduct data communication with the outside through LAN, these interfaces will enable CPU load reduction by carrying out the following operations with hardware. · Convert send data to LAN data format/Convert from LAN data format to receive data. · Continuous sending and receiving process for multiple packets (buffer manager) Send buffer 1536Byte/Receive buffer 3072Byte · Error check · Retransmit when collision occurs (network management) 40 Chapter3 LAN CONTROLLER Block Diagram Remote operation from PCs/mobile phones FR CORE PLL UART 2ch INTC DSU RAM 8KB I-Cache 4KB DMAC Timer Internet Built-in ROM 256KByte 5ch External IF GPIO Built-in RAM 64KByte SMI EtherMAC -L2/L3/L4 Filtering Controlling devices such as PCs/internet appliances I 2C MII PHY 8/16 Memory controller 8/16 SRAM/ SDRAM ROM/ FLASH 41 Chapter3 LAN CONTROLLER 3.1.1 Features FR core interface FR core interface of LAN controller has data bus buffer to interface with FR core. DMA read operation (data reception operation) DMA read operation is the operation to transfer receive data in the buffer memory to the external memory (data reception operation). This allows you to receive the data with a single instruction. Buffer memory manager LAN interface normally has the buffer for sending and receiving data between data link controller and FR core face. LAN controller has the built-in dedicated hardware for managing and controlling the buffer memory (buffer memory manager) and RAM. Data link controller Data link controller (DLC) runs various functions that meet Ethernet standards of 10/100Mbps for IEEE802 IEEE802.3 CSMA/CD method. · Functions to convert send data in the buffer to LAN data format and send. · Functions to convert LAN data format to receive data in the buffer and receive. · Functions to retransmit by binary exponential back-off algorithm for the case of collision occurrence resulting in transmission failure. · Functions to receive data so long as the address is the registered multicast address, apart from your own address (multicast address filtering function). Moreover, with the filtering function implemented, it can receive the required data only. · Filtering function of layer 3/4 (implemented in hardware). Network management function You can manage the network from the internal register of LAN controller. From result status information, you can find out the following information. · Whether the transmission operation to network has succeeded. · Whether CRC error, alignment error (bit size is not the integral multiple of 8) etc. have occurred at the time of reception. · Whether collision has occurred at the time of transmission, and the number of times, if any. This allows you to find out error information of transmitted and received data. The processing by using this information should be created by user. Multicast receive address filtering function The function to filter by specifying low-order 6 bits used to calculate CRC of destination address 48 bits will enable you to narrow down the scope of the searches for filtering by L3/L4 filtering table and reduce the load. 42 Chapter3 LAN CONTROLLER Block Diagram Data Write signal Data Send data link controller Write signal Send buffer memory manager Control signal Data Status Buffer information Control signal Control signal Register block Data FR Core interface Data Error information Interrupt signal Data Filtering information Read signal Receive data link controller Filtering block Buffer information Read signal Buffer information Data Control signal Receive buffer memory manager SMI block This section describes 6 functional blocks for LAN controller. Data link controller part It runs the functions of data link layer defined by the IEEE802 IEEE802.3. When transmitting, it adds preamble and CRC code to the send data read out from the buffer memory and outputs them. And when collision occurs, it automatically executes the back-off algorithm and retransmits. When receiving, it checks the address match of the incoming packet to be received, then, after the error check, removes the preamble and CRC, converts to parallel data and writes into the buffer memory. In addition, the data link controller part has multicast address filtering function and can recognize multicast address groups of up to 64 groups. 43 Chapter3 LAN CONTROLLER Buffer manager part It has the built-in RAM to buffer send and receive data (the send buffer 1536byte, the receive buffer 3072byte). Buffer memory automatically conducts the arbitration of access from both FR core side and network side, update of buffer pointer, etc. by buffer manager with the send buffer of 1 port and the receive buffer of 2 ports. And the send buffer has packet chain function, which, once the send data for multiple packets are stored, allows you to consecutively transmit the packets in the buffer with a single instruction for starting the transmission. FR core interface part It inputs and outputs data bus and bus control signal for connceting to FR core bus. Byte order is also settable. LAN controller has three pairs of register sets that are data link control register, buffer memory port register and multicast address register, and are accessible through FR core interface. Also, receive data transfer between buffer memory port and FR core can be done by DMA transfer. Register block part It puts together the registers such as data link control register, buffer memory port register. You can find out individual status by address. And it also outputs interrupt signal. Filter block part The fact that the filtering processing to be done when receiving the packet, which has traditionally been performed by CPU, is implemented in hardware enables you to significantly reduce the processing load of CPU. It has the filtering function of L3/L4. SMI block part It is the block to read/write into PHY register through SMI interface. It draws different types of status (half-duplex/full-duplex, link status, 10/100 identification, etc.) information from PHY register and is also used when configuring the settings for device. 44 Chapter3 LAN CONTROLLER Table 3.1-1 Register list Address Register Name abbreviation Size R/W Initial Value Data Link Control Register 0 DLCR0 8bit R/W 8'b0-000000 _0001 Data Link Control Register 1 DLCR1 8bit R/W 8'b0 _0002 Data Link Control Register 2 DLCR2 8bit R/W 8'b0 _0003 Data Link Control Register 3 DLCR3 8bit R/W 8'b0 _0004 Data Link Control Register 4 DLCR4 8bit R/W 8'b00000010 _0005 Data Link Control Register 5 DLCR5 8bit R/W 8'b01000001 _0006 Data Link Control Register 6 DLCR6 8bit R/W 8'b10000000 _0007 Data Link Control Register 7 DLCR7 8bit R/W 8'b0 _0008 Data Link Control Register 8 DLCR8 8bit R/W 8'b0 _0009 Data Link Control Register 9 DLCR9 8bit R/W 8'b0 _000A Data Link Control Register A DLCR10 DLCR10 8bit R/W 8'b0 _000B Data Link Control Register B DLCR11 DLCR11 8bit R/W 8'b0 _000C Data Link Control Register C DLCR12 DLCR12 8bit R/W 8'b0 _000D Data Link Control Register D DLCR13 DLCR13 8bit R/W 8'b0 _0008 Multicast Address Register 1 MAR8 8bit R/W 8'b0 _0009 Multicast Address Register 2 MAR9 8bit R/W 8'b0 _000A Multicast Address Register 3 MAR10 MAR10 8bit R/W 8'b0 _000B Multicast Address Register 4 MAR11 MAR11 8bit R/W 8'b0 _000C Multicast Address Register 5 MAR12 MAR12 8bit R/W 8'b0 _000D Multicast Address Register 6 MAR13 MAR13 8bit R/W 8'b0 _000E Multicast Address Register 7 MAR14 MAR14 8bit R/W 8'b0 _000F Multicast Address Register 8 MAR15 MAR15 8bit R/W 8'b0 _0010 Buffer Memory Port Register 8 BMPR8 32bit R/W 32'h0 _000A Buffer Memory Port Register 10 BMPR10 BMPR10 8bit R/W 8'b0 BANK0 0x0110 _0000 BANK1 BANK2 _000B Reserved - - - - _000C Buffer Memory Port Register 12 BMPR12 BMPR12 8bit R/W 8'b0 _000E Buffer Memory Port Register 14 BMPR14 BMPR14 8bit R/W 8'b0 _0014 Filter Command Register FL_CMD 16bit R/W 16'b00000000-0-0 _0018 Filter Status Register FL_STATUS 1bit R 1'b0 _001C Filter Data Register FL_DATA 32bit R/W 32'b0 _0020 Filter mode Control Register FL_CONTROL 11bit R/W 11'b0 _0024 Filter Subnet Register FL_SUBNET 32bit R/W 32'hFFFFFFFF _0028 SMI Command Register _002C SMI Command Status Register SMI_CMD 16bit R/W 16'b0-00000-00000 SMI_CMD_ST 2bit R 2'b0 _0030 SMI Data Register SMI_DATA 16bit R/W 16'h0 _0034 SMI Polling Register SMI_POLLINTVL 16bit R/W 16'h0 _0038 SMI PHY Address Register SMI_PHY_ADD 5bit R/W 5'b0 _003C SMI Control Register SMI_CONTROL 3bit R/W 3'b111 _0040 SMI Status Register SMI_STATUS 5bit R 5'b01110 _0044 SMI Interrupt Enable Register SMI_INTENABLE 1bit R/W 1'b- _0048 SMI MDC Register SMI_MDCDIV 5bit R/W 5'b1011 45 Chapter3 LAN CONTROLLER About register bank I/O address space used exclusively by LAN controller is 32 byte, and is to be accessed by switching each register and I/O address space by bank switching. Register bank can be switched by register bank bit (DLCR7.RBNKn). Table 3.1-2 Register bank bit (DLCR7.RBNKn) BIT3 BIT2 Mode 0 0 0 1 Use bank 1 (register set for DLCR0-DLCR7, MAR8-MAR15 MAR8-MAR15) 1 - Use bank 2 (register set for DLCR0-DLCR7, BMPR10-BMPR14 BMPR10-BMPR14) Use bank 0 (register set for DLCR0-DLCR7, DLCR8-DLCR15 DLCR8-DLCR15) For buffer memory port register (BMPR8), packet filters and SMI interface register, they can be accessed using word access only. 46 Chapter3 LAN CONTROLLER 3.2 Register Details Explanation of the code expressing access limits to each bit of the register [Code] R : Read permitted R0 : Always 0 R1 : Always 1 RX : Indeterminate W : Write permitted W0 : Always write 0 W1 : Always write 1 WX : Write invalid [Combination] "/" and ", R/W: Written data can be read R,W : The significance of the bit changes according to whether it is read or write [Support for read modify write] using "(" ") R(RM1)/W : Possible to read written value (The reading is always 1 during RMW) R(RM1),W : Read is possible (always 1 during RMW), write is possible 47 Chapter3 LAN CONTROLLER 3.2.1 Detailed Explanation of the Register Transmission Status Register: DLCR0 DLCR0: Address 0110_0000H 0000H (access: Byte/Half-word) This is the register to display the transmission status of data link controller. 7 6 5 4 3 2 1 0 bit TMT OK NET BSY - - LTE COL COL - 0 X 0 0 0 0 RETRY OVER 0 0 R,W R/WX R0/WX R0/WX R,W R,W R,W R0/WX Initial value Attribute bit 7: Transmit O.K TMT OK Read operation Write operation 0 This bit was cleared No effect 1 Transmission of all the packets in the send buffer complete Clear this bit · If packet ready bit is "1", "1" is automatically set when the transmission of all the packets in the send buffer is complete, and is maintained until it is cleared. bit 6: Net busy NET BSY Read operation 0 Network is not used (carrier is not detected) 1 Network is used (carrier is detected) bit 5-4: Undefined.Writing does not affect the operation. The read value is always "0". bit 3: Late collision LTE COL Read operation Write operation 0 No late collision No effect 1 Late collision occurred Clear this bit bit 2: Collision error COL Read operation Write operation 0 No collision error No effect 1 Packet collision occurred on the network during packet transmission Clear this bit · When the collision error bit is "1", collisions of up to 16 times are automatically retransmitted by data link controller. You can find out number of times of collisions occurred by reading collision count bit (DLCR4.COLn). 48 Chapter3 LAN CONTROLLER bit 1: Retry over RETRY OVER Read operation Write operation 0 No collision error for 16 times No effect 1 Collision occurred 16 times in a row during packet transmission Clear this bit bit 0: Undefined.Writing does not affect the operation. The read value is always "0". Status bit for BIT7,BIT3-0 asserts external interrupt -INT of FR core by bit set if the corresponding bit of DLCR2 is set. Reception Status Register: DLCR1 DLCR1: Address 0110_0001h (access: Byte/Half-word) This is the register to display the reception status of data link controller. 7 6 5 4 3 PKT RDY RX ERR 0 0 FIL DROP 0 RX LNGPKT 0 RX SRTPKT 0 R,W R,W R,W R,W 2 R,W 1 0 ALG ERR CRC ERR bit OVRFL0 0 0 0 R,W R,W R,W Initial value Attribute bit 7: Packet ready PKT RDY Read operation Write operation 0 The packet received does not exist in the receive No effect buffer 1 Transfer to the receive buffer complete Clear this bit · When packet ready bit is "1", it means that the packet addressed to local is properly received and the transfer to the receive buffer is complete. That is, there is at least one packet of receive data in the receive buffer. · If you set packet ready bit to "1", it clears this bit. However, if the received packet still remains in the receive buffer after the host side reads out receive data for one packet from the receive buffer, this bit is automatically reset. bit 6: Communication error RX ERR Read operation Write operation 0 No communication error No effect 1 Communication error Clear this bit 49 Chapter3 LAN CONTROLLER bit 5: Filtering drop FIL DROP Read operation Write operation 0 No packet drop with filtering mechanism No effect 1 Packet was dropped with filtering mechanism Clear this bit bit 4: Long packet RX LNG PKT Read operation Write operation 0 No long packet error No effect 1 Long packet error Clear this bit · When long packet bit is "1", it means that the data length of received packet (address+data length+data body) exceeds the set maximum data length (1514byte). bit 3: Short packet RX SRT PKT Read operation Write operation 0 No short packet error No effect 1 Short packet error Clear this bit · When short packet bit is "1", it means that the data length of received packet (address+data length+data body) is less than the set minimum data length (60byte). If enable short packet receive bit [DLCR5:BIT3] is set, it is set in the case of being less than 16 byte. bit 2: Alignment error ALG ERR Read operation Write operation 0 No alignment error No effect 1 Alignment error Clear this bit · When alignment error bit is "1", it means that CRC of received packet is not correct and that the number of bits of received data is not multiples of 8. bit 1: CRC error CRC ERR Read operation Write operation 0 No CRC error No effect 1 CRC of received packet is not correct Clear this bit bit 0: Overflow error OVRFLO Read operation Write operation 0 No effect 1 50 No overflow error Overflow error present Clear this bit Chapter3 LAN CONTROLLER · When overflow error bit is "1", it means that the packet is erased because the data length of the received packet is larger than the free space of the receive buffer memory. Even after this bit is set, if the next packet is smaller than the free space of the buffer memory, it is properly received. If this bit is set, it means that the receive buffer memory is almost full, so urgently transfer the data in the buffer to the host system side. Status bit for BIT7-0 asserts external interrupt -INT of FR core by bit set if the corresponding bit of DLCR3 is set. Reception Status Register: Supplementary Explanation Of DLCR1 Short packet bit [DLCR1:BIT3] RX SRT PKT bit is set on the following conditions. R(K) < 20 byte RX SRT PKT Bit 20byte =minimum data length, check CRC error. 51 Chapter3 LAN CONTROLLER Transmit Interrupts Enable Register:DLCR2 DLCR2:Address 0110_0002h (access: Byte/Half-word) This is the register to enable transmit interrupts. 7 6 5 4 3 2 1 0 ENA TMT OK - - - ENA LTE COL ENACOL - 0 0 0 0 0 0 ENA RETRY OVER 0 0 R/W R0,WX R0,WX R0,WX R/W R/W R/W R/W bit Initial value Attribute bit 7: Transmit O.K interrupt occurrence enable ENA TMT OK Mode 0 TMT OK interrupt occurrence disable 1 TMT OK interrupt occurrence enable bit 6-4: Undefined.Writing does not affect the operation. The read value is always "0". bit 3: Late collision interrupt occurrence enable ENA LTE COL Mode 0 LTE COL interrupt occurrence disable 1 LTE COL interrupt occurrence enable bit 2: Collision error interrupt occurrence enable ENA COL Mode 0 COL interrupt occurrence disable 1 COL interrupt occurrence enable bit 1: Retry over interrupt occurrence enable ENA RETRY OVER Mode 0 RETRY OVER interrupt occurrence disable 1 RETRY OVER interrupt occurrence enable bit 0: Undefined.Writing does not affect the operation. The read value is always "0". By setting the bit that corresponds to the status bit of DLCR0 to "1", it asserts the external interrupt IRQX of FR core when setting the status bit. 52 Chapter3 LAN CONTROLLER Reception Interrupts Enable Register:DLCR3 DLCR3: Address 0110_0003h (access: Byte/Half-word) This is the register to enable reception interrupts. 7 6 5 4 3 2 1 0 ENA PKT RDY 0 ENA RX ERR 0 ENA FIL DROP 0 ENA RX LNG PKT 0 ENA RX SRT PKT 0 ENA ALG ERR 0 ENA CRC ERR 0 ENA OVRFLO 0 R/W R/W R/W R/W R/W R/W R/W R/W bit Initial value Attribute bit7: Packet ready interrupt occurrence enable ENA PKT RDY Mode 0 PKT RDY interrupt occurrence disable 1 PKT RDY interrupt occurrence enable bit 6: Communication error interrupt occurrence enable ENA RX ERR Mode 0 RX ERR interrupt occurrence disable 1 RX ERR interrupt occurrence enable bit 5: Filtering drop interrupt occurrence enable ENA FIL DROP Mode 0 FIL DROP interrupt occurrence disable 1 FIL DROP interrupt occurrence enable bit 4: Long packet interrupt occurrence enable ENA RX LNGPKT Mode 0 RX LNG PKT interrupt occurrence disable 1 RX LNG PKT interrupt occurrence enable bit 3: Short packet interrupt occurrence enable ENA RX SRTPKT Mode 0 RX SRT PKT interrupt occurrence disable 1 RX SRT PKT interrupt occurrence enable 53 Chapter3 LAN CONTROLLER bit 2: Alignment error interrupt occurrence enable ENA ALG ERR Mode 0 ALG ERR interrupt occurrence disable 1 ALG ERR interrupt occurrence enable bit 1: CRC error interrupt occurrence enable ENA CRC ERR Mode 0 CRC ERR interrupt occurrence disable 1 CRC ERR interrupt occurrence enable bit 0: Overflow interrupt occurrence enable ENA OVRFLO Mode 0 OVRFLO interrupt occurrence disable 1 OVRFLO interrupt occurrence enable By setting the bit that corresponds to the status bit of DLCR1 to "1", it asserts the external interrupt IRQX of FR core when setting the status bit. 54 Chapter3 LAN CONTROLLER Transmit Mode Register:DLCR4 DLCR4: Address 0110_0004h (access: Byte/Half-word) This is the register to display the setting of operation mode of transmitter and number of occurrences of collision. 7 6 5 4 3 2 1 0 COL3 0 COL2 0 COL1 0 COL0 0 0 0 LBC 1 0 R R R R R0,WX R0,WX R/W R0,WX bit Initial value Attribute bit 7-4: Collision count · It displays the number of times of collisions occurred by the time of transmission complete. It is cleared when the transmission is complete. bit 3-2: Undefined.Writing does not affect the operation. The read value is always "0". bit 1: Loop back control LBC Read operation/Write operation 0 Loop back mode 1 Normal sending and receiving operation · Data is also output to the external during loop back operation. bit 0: Undefined.Writing does not affect the operation. The read value is always "0". 55 Chapter3 LAN CONTROLLER Receive Mode Register:DLCR5 DLCR5: Address 0110_0005h (access: Byte/Half-word) This is the register to display the setting of operation mode of receiver and the status of the receive buffer memory. 7 6 5 4 3 2 1 0 - BUF EMP - - - AM1 AM0 0 1 0 0 ENA SRT PKT 0 0 0 1 R0,WX R,WX R0,WX R0,WX R/W R0,WX R/W R/W bit Initial value Attribute bit7: Undefined.Writing does not affect the operation. The read value is always "0". bit 6: Buffer empty BUF EMP Read operation 0 Valid data are still in the receive buffer memory 1 Valid data are not in the receive buffer memory bit 5-4: Undefined.Writing does not affect the operation. The read value is always "0". bit 3: Enable short packet reception ENA SRT PKT Read operation/Write operation 0 1 bit 2: Receive the packet of data length (address+data length+data body) 60 byte or more and not over 1514 byte. Receive the packet of data length (address+data length+data body) 16 byte or more and not over 1514 byte. Enable remote reset.Writing does not affect the operation. The read value is always "0". bit 1-0: Address match mode AM1 0 0 0 1 1 0 Receive the packet that is of physical address, broadcast address, multicast address and that is selected by multicast address register. 1 56 AM0 Address match detection mode 1 Receive all the packets irrespective of destination address Not receive packet. Reject all the packets received for unmatched address Chapter3 LAN CONTROLLER Control Register 1:DLCR6 DLCR6: Address 0110_0006h (access: Byte/Half-word) This is the register to set the sending and receiving operation start of LAN controller. 7 6 5 4 3 2 1 0 ENA DLC 1 0 0 0 0 0 0 0 R/W R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX bit Initial value Attribute bit 7: Enable data link controller ENA DLC Read operation/Write operation 0 LAN controller is ready for sending and receiving operation 1 LAN controller is not ready for sending and receiving operation · When this bit is 0, disable accessing to node ID register and filter table. bit 6-0: Undefined.Writing does not affect the operation. The read value is always "0". 57 Chapter3 LAN CONTROLLER Control Register 2:DLCR7 DLCR7: Address 0110_0007h (access: Byte/Half-word) This is the register to set each operation mode of LAN controller. 7 6 5 4 3 2 1 0 - - - - RBNK1 RBNK0 - 0 0 0 0 0 0 0 BYTE SWAP 0 R0,WX R0,WX R0,WX R0,WX R/W R/W R0,WX R/W bit Initial value Attribute bit 7-4: Undefined.Writing does not affect the operation. The read value is always "0". bit 3-2: Register bank RBNK1 RBNK0 Mode 0 0 Use register set of bank 0 (DLCR0-DLCR7, DLCR8-DLCR15 DLCR8-DLCR15) 0 1 Use register set of bank 1 (DLCR0-DLCR7, MAR8-MAR15 MAR8-MAR15) 1 - Use register set of bank 2 (DLCR0-DLCR7, BMPR10- BMPR10- MPR14 MPR14) · LAN controller has three types of internal register set, and from FR core side, each register set is accessible by bank switching with this bit. · DLCR0-DLCR7 and BMPR8 are always accessible irrespective of register bank. bit 1: Undefined.Writing does not affect the operation. The read value is always "0". bit 0: Byte swap BYTE SWAP Mode 0 Not byte swap for access to BMPR8 (Little endian) 1 Byte swap for access to BMPR8 and reverse high-order data and low-order data (Big endian) · Register access other than BMPR8 will not be byte swapped even if this bit is set. 58 Chapter3 LAN CONTROLLER Node ID Register 1-6:DLCR8-13 DLCR8-13 DLCR8 : Address 0110_0008h (access: Byte/Half-word) DLCR9 : Address 0110_0009 (access: Byte/Half-word) DLCR10 DLCR10: Address 0110_000A (access: Byte/Half-word) DLCR11 DLCR11: Address 0110_000B (access: Byte/Half-word) DLCR12 DLCR12: Address 0110_000C (access: Byte/Half-word) DLCR13 DLCR13: Address 0110_000D (access: Byte/Half-word) This is the register to store local node ID. 7 DLCR8 DLCR9 DLCR10 DLCR10 DLCR11 DLCR11 DLCR12 DLCR12 DLCR13 DLCR13 6 5 4 3 2 1 0 ID 7 ID 15 ID 23 ID 31 ID 39 ID 47 0 ID 6 ID 14 ID 22 ID 30 ID 38 ID 46 0 ID 5 ID 13 ID 21 ID 29 ID 37 ID 45 0 ID 4 ID 12 ID 20 ID 28 ID 36 ID 44 0 ID 3 ID 11 ID 19 ID 27 ID 35 ID 43 0 ID 2 ID 10 ID 18 ID 26 ID 34 ID 42 0 ID 1 ID 9 ID 17 ID 25 ID 33 ID 41 0 ID 0 ID 8 ID 16 ID 24 ID 32 ID 40 0 R/W R/W R/W R/W R/W R/W R/W R/W bit Initial value Attribute · This is the register to store local node ID · DLCR8-DLCR13 DLCR8-DLCR13 is the register to store local node ID. It compares the destination address in the received packet with the value of this register, and receives the matched packet according to the setting of address match mode bit (DLCR5:AMn). · DLCR8 will be LSB of node ID and DLCR13 DLCR13 will be MSB of node ID. · For Ethernet, destination address is sent from LSB side. · Only when the enable data link controller bit (DLCR6.-ENA DLC) is "1", it is possible to read/write. 59 Chapter3 LAN CONTROLLER Multicast Address Register 1-8:MAR8-15 MAR8-15 MAR8 :Address 0110_0008h (access: Byte/Half-word) MAR9 :Address 0110_0009h (access: Byte/Half-word) MAR10 MAR10:Address 0110_000Ah (access: Byte/Half-word) MAR11 MAR11:Address 0110_000Bh (access: Byte/Half-word) MAR12 MAR12:Address 0110_000Ch (access: Byte/Half-word) MAR13 MAR13:Address 0110_000Dh (access: Byte/Half-word) MAR14 MAR14:Address 0110_000Eh (access: Byte/Half-word) MAR15 MAR15:Address 0110_000Dh (access: Byte/Half-word) This is the register to select the multicast address packet that is received when the address match mode bit [DLCR5:BIT1-0] is set to "1,0". 7 6 5 4 3 2 1 0 MID 7 MID 15 MID 23 MID 31 MID 39 MID 47 MID 55 MID 63 0 MID 6 MID 14 MID 22 MID 30 MID 38 MID 46 MID 54 MID 62 0 MID 5 MID 13 MID 21 MID 29 MID 37 MID 45 MID 53 MID 61 0 MID 4 MID 12 MID 20 MID 28 MID 36 MID 44 MID 52 MID 60 0 MID 3 MID 11 MID 19 MID 27 MID 35 MID 43 MID 51 MID 59 0 MID 2 MID 10 MID 18 MID 26 MID 34 MID 42 MID 50 MID 58 0 MID 1 MID 9 MID 17 MID 25 MID 33 MID 41 MID 49 MID 57 0 MID 0 MID 8 MID 16 MID 24 MID 32 MID 40 MID 48 MID 56 0 R/W MAR8 MAR9 MAR10 MAR10 MAR11 MAR11 MAR12 MAR12 MAR13 MAR13 MAR14 MAR14 MAR15 MAR15 R/W R/W R/W R/W R/W R/W R/W bit Initial value Attribute · This is the register to select the multicast address packet that is received when the address match mode bit [DLCR5.AMn] is set to "1,0". · Multicast address is input to CRC circuit of 32 bits, and will be grouped into 64 groups by low-order 6 bits of CRC calculated. The xx of MIDxx is corresponding to the figure of CRC low-order 6 bits, therefore, if you set "1" to MID0, the packet for CRC low-order 6 bits "000000" will be enabled, and if you set "1" to MID63 MID63, the packet for CRC low-order 6 bits "111111" will be enabled. · Only when the enable data link controller bit (DLCR6.-ENA DLC) is "1", it is possible to read/write. Multicast operation With this function, if the first bit of destination address of the packet received is 1, CRC of destination address 48 bits is calculated by CRC circuit and low-order 6 bits is internally latched. And the value of this 6 bits is compared with multicast address register, then if the bits of the corresponding multicast register is set, the multicast packet will be received, and if the bits is not set, it will be dropped. This will enable all the multicast addresses to be divided into 64 groups and you can receive the multicast packet of a given group only. If all the bits of multicast addess register are 0, you cannot receive the multicast address packet. Or conversely, if you set all the bits to 1, you will receive all the multicast address packets. 60 Chapter3 LAN CONTROLLER · Caution with multicast address function - Generator polynomial of CRC is the same as CRC of 32 bits that is added to the end of packet. - G(x) = X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 - When all the bits of destination address are 1, the packets will be received irrespective of multicast address because they are broadcast address packets. 61 Chapter3 LAN CONTROLLER Buffer Memory Port Register: BMPR8 BMPR8: Address 0110_0010h (access: Byte/Half-word) This is the data port to transfer send and receive data between FR core and buffer memory. 7 6 5 4 3 2 1 0 BMP 7 BMP 15 BMP 23 BMP 31 0 BMP 6 BMP 14 BMP 22 BMP 30 0 BMP 5 BMP 13 BMP 21 BMP 29 0 BMP 4 BMP 12 BMP 20 BMP 28 0 BMP 3 BMP 11 BMP 19 BMP 27 0 BMP 2 BMP 10 BMP 18 BMP 26 0 BMP 1 BMP 9 BMP 17 BMP 25 0 BMP 0 BMP 8 BMP 16 BMP 24 0 R/W R/W R/W R/W R/W R/W R/W R/W bit Initial value Attribute · This is the data port to transfer send and receive data between FR core and buffer memory. This register can be accessed using word access only. · Setting byte swap bit (DLCR7.BYTE SWAP) will enable you to transpose the byte order of MSB and LSB of this register. 62 Chapter3 LAN CONTROLLER Transmitted Packet Count Register: BMPR10 BMPR10 BMPR10 BMPR10:Address 0110_000Ah (access: Byte/Half-word) This is the register to set start transmission bit and transmitted packet count. 7 6 5 4 3 2 1 0 TMST 0 TX PKT CNT 6 0 TX PKT CNT 5 0 TX PKT CNT 4 0 TX PKT CNT 3 0 TX PKT CNT 2 0 TX PKT CNT 1 0 TX PKT CNT 0 0 R0/W R/W R/W R/W R/W R/W R/W R/W bit Initial value Attribute bit 7: Start transmission bit TMST Write operation 0 No effect 1 Start packet transmission · Set it after transferring the transmitted packet from FR core to the send buffer. bit 6-0: Transmitted packet count · Each time one packet transmission is completed after the start of transmission, the count is decremented, and it displays the number of packets yet to be transmitted. When the transmission of all the packets is complete, the count will become 00H. · LAN controller is able to start the multiple packets transmission in a single command for the transmission. Write into this register the number of transmitted packets (the number of packets transferred to the buffer memory) while setting TMST bit. 63 Chapter3 LAN CONTROLLER DMA Enable Register:BMPR12 BMPR12 BMPR12 BMPR12:Address 0110_000Ch (access: Byte/Half-word) This is the register to control DMA transfer between FR core and LAN controller. 7 - 6 - 5 - 4 - 3 - 2 - 0 - bit 0 1 DMA RENA 0 0 0 0 0 0 0 R0,WX R/W R0,WX Initial value Attribute R0,WX R0,WX R0,WX R0,WX R0,WX bit 7-2: Undefined.Writing does not affect the operation. The read value is always "0". bit 1: DMA RENA TMST Write operation 0 DMA read operation disable 1 DMA read (read the receive buffer) operation enable bit 0: Undefined.Writing does not affect the operation. The read value is always "0". 64 Chapter3 LAN CONTROLLER Receive Buffer Pointer Control Register: BMPR14 BMPR14 BMPR14 BMPR14:Address 0110_000Eh (access: Byte/Half-word) This is the register to control DMA transfer between FR core and LAN controller. 7 6 5 4 3 2 1 0 - - - - - - - 0 0 0 0 0 SKI PRX PKT 0 0 0 R0,WX R0,WX R0,WX R0,WX R0,WX R/W R0/WX R0,WX bit Initial value Attribute bit 7-3: Undefined.Writing does not affect the operation. The read value is always "0". bit 2: Receive buffer pointer skip SKI PRX PKT Read operation Write operation 0 Receive buffer pointer skip complete No effect, the receive buffer pointer is not skipped. 1 Receive buffer pointer being skipped (being updated) Skip the receive buffer pointer to the top of the next packet · When the receive buffer pointer skip bit is "1", it means that the status is transient from the time 1 was written into this bit until the skip is complete. · After setting the receive buffer pointer skip bit to "1", this bit will be automatically cleared when the skip operation is complete. And if the packet you tried to skip is the end packet in the receive buffer, the receive buffer pointer will set buffer empty bit (DLCR5.BUF EMP) after skipping. bit 1-0: Undefined.Writing does not affect the operation. The read value is always "0". 65 Chapter3 LAN CONTROLLER 3.3 Operation Processing which is done automatically - Conversion from parallel data to serial data - Generate and add 64 bit preamble code - Generate and add 32 bit CRC code - Output to LAN Buffer memory manager (Hardware processing) Data link controller (Hardware processing) Send buffer memory (1536Byte) Packet length Send data packet n Packet length Send data packet n+1 Packet length Send data packet n+2 Free space Next send data packet is stored Packet length Memory LAN Receive buffer memory (3072Byte) Receive data packet n Packet length Processing which is done automatically Receive data packet n+1 - Conversion from serial data to parallel data - Compare addresses - Check and remove 32 bit CRC code - Remove 64 bit preamble code - Transfer to the receive buffer Receive data packet n+2 Buffer memory report register (BNPR8) Packet length Packet length Receive data packet n+3 Free space Next receive data packet is stored Figure 3.3-1 About buffer memory For LAN'3fBuffer memory transfer, since it is processed by hardware, users send and receive between register'3fbuffer memory register. 66 DMAFR Chapter3 LAN CONTROLLER Format For The Receive Data Packet 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Packet length Destination address (high-order 4 byte) Destination address (low-order 2 byte) Source address (high-order 2 byte) Source address (low-order 4 byte) Length/type Data body Data body Snip 2 1 0 bit Data body CRC Format For Packet Length (4 byte) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Packet length 11Bits · Packet length is denoted in 11 bits, so write "0" into the first 2 byte and high-order 5 bits of the third byte. · In transmission: Write into packet length the data length of address+data lengh+data body. · In reception: Into the head of each receive data, data length (address+data length+data body) information of 4 byte will be written. Packet Format Start Frame Delimiter Preamble 7 bytes 1 byte Destination Address Source Address Length/ Type *1 6 bytes 6 bytes 2 bytes Data Body CRC 46 - 1500 bytes 4 bytes 1 byte = 8 bits IEEE802 IEEE802.3 packet format Send data *2 Transmitted packet Received packet Receive data *3 *1: This is the field to set length/type of data body. In LAN controller operation, this value has no meaning. *2: Add byte count information of this send data to the head of send data and transfer to the send buffer. *3: Byte count of this receive data will be set to the data length in the reception status. 67 Chapter3 LAN CONTROLLER 3.3.1 Transmission Flow (Host Buffer Memory) 1. Clear status 2. Build send data on memory (RAM) - Destination Address - Source Address - Data Length - Data Body 3. Setting the operation mode of LAN controller 4. Put the built send data on the buffer (Transfer by program/DMA transfer) 5. Enable Transmit O.K. interrupt occurrence (Interrupt occurs when transmission is completed.) 6. Write the number of transmitted packets to register (Start transmission) 7. Automatically added by the hardware - Preamble - Start Frame Delimiter - CRC Have all the packets in the buffer been transmitted? (Hardware processing) Yes Figure 3.3-2 Main processing TMT OK ERROR Start interrupts 8. Clear various types of status (transmit O.K. status, etc.) Start interrupts Error processing 9. Disable interrupts RETI (Return) 10. Notify the transmission completion to the upper network protocol RETI (Return) Figure 3.3-3 Interrupt 68 Chapter3 LAN CONTROLLER Procedure [Packet transmission] Main processing 1. Clear each status 1) Setting the transmission status register (DLCR0):Setting value0x8A Bit Value Position of DLCR0 TMT OK "1" bit 7: LTE COL "1" bit 3: RETRY OVER "1" bit 1: 2) Write "1" (normal sending and receiving operation) into loop back control bit (DLCR4.LBC). 2. Build send data on memory (RAM) 1) Destination address 2) Source address 3) Length/type 4) Data body setting *If the send data length cannot be divided by 4 byte, add dummy data to the end of the send data. Start Frame Delimiter Preamble 7 bytes 1 byte Destination Address Source Address Length/ Type 6 bytes 6 bytes 2 bytes Data Body CRC 46 - 1500 bytes 4 bytes 3. Setting the operation mode of LAN controller Table 3.3-1 Setting the control register 2 (DLCR7) Bit Value Position of DLCR7 RBNK1 "1" (select bank 2) bit 3 RBNK2 "1" (select bank 2) bit 2 BYTESWAP Set byte swap if necessary bit 0 69 Chapter3 LAN CONTROLLER 4. Conduct DMA transfer to put send data on the buffer from external memory. DMA setting (transmission example) Configure the following settings for DMAC of FR core. 1) Transfer-source address setting: Set transfer-source address in transfer-source address setting register (DMASAn.DMASA). 2) Transfer-destination address setting: Set buffer memory port register (BMPR8) of MAC in transfer-destination address setting register (DMADAn.DMADA). 3) Enable DMA operation Set "1" (enable all the channels DMA transfer) in DMAC total operation enable register (DMACR,DMAE). 4) DMAC control/status register B (DMACBn) settings *Setting other than shown below means initial value. a. TYPE: Transfer type setting TYPE[1:0] = "00"(two-cycle transfer) b. MODE: Transfer mode setting MOD[1:0] = "01"(burst transfer mode) c. WS: Transfer data width selection WS[1:0] = "10"(transfer in WORD unit) d. SADM: Specifying transfer-source address count mode SADM = "0"(transfer-source address will increase) Note) It is necessary to be compliant with the transfer-source buffer. e. Reload and interrupt settings Configure the settings if necessary. f. SASZ: Specifying transfer-source address count size SASZ = "0x04"(transfer address increase and decrease range :4) Note) It is necessary to be compliant with the transfer-source buffer. g. DASZ: Specifying transfer-destination address count size DASZ = "0x00"(transfer address increase and decrease range :0) 5) DMAC control/status register A (DMACAn) settings *Setting other than shown below means initial value. a. DENB : DMA operation enable bit DENB = "1"(enable corresponding channel DMA operation) b. IS : Select transfer trigger IS[4:0] = "00000"(only software transfer request enabled) c. BLK:Specifying block size BLK[3:0] = "0x1"(block transfer is not conducted) d. DTC : Transfer count register Set send data length. Example) For 1536byte,1536/word = 384 DTC = "0x180 70 Chapter3 LAN CONTROLLER 6) Transfer request DMACAn.STRG:Transfer request STRG = "1"(DMA start request) 5. Transfer data to buffer (DMA setting) Write the number of transmitted packets 1) Setting the transmission interrupt enable register (DLCR2): Setting value0x8E Bit Value Position of DLCR2 ENA TMT OK "1" bit 7 ENA LTE COL "1" bit 3 ENA COL "1" bit 2 ENA RETRY OVER "1" bit 1 6. Start transmission 1) Write "0" (LAN controller is ready for sending and receiving) into enable data link controller bit (DLCR6.-ENA DLC). 3) Write into transmitted packet count bit (BMPR10 BMPR10.TX PKT CNTn) the number of packets to be transmitted from now. 4) Write "1" (start packet transmission) into start transmission bit (BMPR10 BMPR10.TMST). (Do not transfer the next send data to the send buffer or start the transmission operation until the packet transmission is completed) 5) Calculating the rest of the send buffer, repeat the processing of 3) and 4) until all the data is transferred. (7. Hardware processing) 1) Convert to packet transmission format By adding preamble, start frame delimiter and CRC, it is transmitted onto LAN network. 2) Packet transmission is carried out until the transmitted packet count bit (BMPR10 BMPR10.TX PKT CNTn) becomes "0". (Each time one packet is transmitted, the count is automatically decremented) 3) When the transmission is completed, transmission O.K. bit (DLCR0.TMT OK) becomes "1". 71 Chapter3 LAN CONTROLLER Transmission complete (interrupt occurred) 8. Status clear 1) Setting the transmission status register (DLCR0):Setting value0x8A Bit Value Position of DLCR0 TMT OK "1" bit 7 LTE COL "1" bit 3 RETRY OVER "1" bit 1 9. Disable interrupts 1) Write "0" (TMT OK interrupt occurrence disable) into Transmit O.K. interrupt occurrence enable bit (DLCR2.ENA TMT OK). 10. Notify to upper level 1) If necessary, notify the transmission complete to the upper level network protocol. 72 Chapter3 LAN CONTROLLER 3.3.2 Reception Flow (Buffer Memory Host) Main processing 1. Initial process (Clearing status) 2. Enable different types of interrupts 3. Setting LAN controller register 4. Start reception (automatically) (Interrupt occurs when reception is completed.) 5. Hardware processing - Checks the packet is to the local. - Deletes the preamble and CRC, and transfers it to the buffer memory. Interrupts ERROR PKT-RDY Start interrupts Start interrupts 6. Switch to disable interrupts Error processing 7. Read packet length RETI (Return) 8. DMA operation enable 9. Read data (DMA transfer) (Hardware processing) Receive 1 packets 10. Buffer empty No Yes (Buffer area is empty) 11. DMA operation disable 12. Clear various types of status 13. Enable interrupts RETI (Return) 73 Chapter3 LAN CONTROLLER Procedure [Packet received] Main processing 1. Clear each status 1) Setting the receive status register (DLCR1):Setting value0xFF Bit Value Position of DLCR1 PKT RDY "1" bit 7 RX ERR "1" bit 6 FIL DROP "1" bit 5 RX LNG PKT "1" bit 4 RX SRT PKT "1" bit 3 ALG ERR "1" bit 2 CRC ERR "1" bit 1 OVRFLO "1" bit 0 2. Enable different types of interrupts 1) Setting the receive interrupts enable register (DLCR3): Setting value0xCA Bit Value Position of DLCR3 ENA PKT RDY "1" bit 7 ENA RX ERR "1" bit 6 ENA FIL DROP "0" bit 5 ENA RX LNG PKT "0" bit 4 ENA RX SRT PKT "1" bit 3 ENA ALG ERR "0" bit 2 ENA CRC ERR "1" bit 1 ENA OVRFLO "0" bit 0 3. Setting LAN controller register 1) Write "1" (normal sending and receiving operation) into loop back control bit (DLCR4.LBC). 2) In address match mode bit (DLCR5.AM[1:0]), set to "10" (receive the packet selected) or to "11" (receive all the packets). 3) Write "0" (LAN controller is ready for sending and receiving) into enable data link controller bit (DLCR6.ENA DLC). (4. Hardware processing) · Start receiving (5. Hardware processing) · Check destination address with data link controller and confirm if the packet is addressed to the local. 74 Chapter3 LAN CONTROLLER · For the packet addressed to the local, transfer to the buffer memory by removing preamble and CRC. · At the same time, check for error in CRC, short packet, alignment, respectively, and if an error is detected, set the corresponding error status bit of the receive status register (DLCR1) and erase the packet data transmitted to the buffer memory. · When the reception is properly completed and all of the packet data is transferred to the buffer memory, the buffer memory manager will write the status information of 4 byte into the head of the packet data in the buffer memory, and packet ready bit (DLCR1.PKT RDY) will become "1". Reception complete (interrupts occur) 6. Disable interrupts 1) Write "00"H into reception interrupts enable register (DLCR3). (Disable all reception interrupts) 7. Read to