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CM43-10102-2E F2MC-16L 16-BIT MB90670/675 MB90670/5 F2MC-16 MB90675 MB90670 - Datasheet Archive
CM43-10102-2E CONTROLLER MANUAL F2MC-16L 16-BIT MICROCONTROLLER MB90670/675 SERIES USER'S MANUAL 1. The products described in
FUJITSU SEMICONDUCTOR CM43-10102-2E CM43-10102-2E CONTROLLER MANUAL F2MC-16L F2MC-16L 16-BIT 16-BIT MICROCONTROLLER MB90670/675 MB90670/675 SERIES USER'S MANUAL 1. The products described in this manual and the specifications thereof may be changed without prior notice. To obtain up-to-date information and/or specifications, contact your Fujitsu sales representative or Fujitsu authorized dealer. 2. Fujitsu will not be liable for infringement of copyright, industrial property rights, or other rights of a third party caused by the use of information or drawings described in this manual. 3. The contents of this manual may not be transferred or copied without the express permission of Fujitsu. 4. Some of the products described in this manual may be strategic materials (or special technology) as defined by the Foreign Exchange and Foreign Trade Control Law. In such cases, the products or portions thereof must not be exported without permission as defined under the Law. ©1995 FUJITSU LIMITED Printed in Japan CONTENTS CHAPTER 1 Outline .1 1.1 Features .1 1.2 Embedded Function Modules (Resources) .2 1.3 Model Range .2 1.4 Block Diagram .4 1.5 Pin Assignment .5 1.6 Pin Description .11 1.7 Device Operation .20 1.8 Mask Options .22 CHAPTER 2 Hardware .23 2.1 CPU .23 2.2 Map .62 2.3 Parallel Port .73 2.4 UART0 .82 2.5 UART1 (SCI) .100 2.6 10-Bit 8-Input A/D Converter (with 8-Bit Resolution Mode) .115 2.7 PPG .129 2.8 16-Bit Reload Timer (with Event Count Function) .141 2.9 24-Bit Free-Run Timer .152 2.10 OCU (Output Compare Unit) .158 2.11 ICU (Input Capture Unit) .167 2.12 DTP/External Interrupts .172 2.13 Wakeup Interrupt .179 2.14 Delay Interrupt Generation Module .182 2.15 I2C Interface .184 2.16 Watchdog Timer and Time-base Timer Functions .196 CHAPTER 3 Operation .203 3.1 Clock Generator .203 3.2 Reset .204 3.3 Memory Access Modes .207 3.4 External Memory Access .212 3.5 Low Power Consumption Modes .223 3.6 Pin Statuses for Sleep, Stop, Hold, and Reset .235 CHAPTER 4 Instructions . 239 4.1 Addressing . 239 4.2 Instructions . 244 4.3 Instruction Map . 264 CHAPTER 1 Outline The MB90670/5 MB90670/5 series is a general purpose, high performance 16-bit microcontroller designed for applications requiring high speed real time processing in industry, office equipment, process control, and other fields. The instruction set follows the F2MC-8 series AT architecture with enhanced performance through the addition of high level language support instructions, expanded addressing modes, enhanced multiplication and division instructions, and improved bit manipulation instructions. Furthermore, a 32-bit accumulator enables long-word data processing. The following lists the features and internal peripheral function modules (henceforth referred to as resources) for the MB90670/5 MB90670/5 series. 1.1 Features (1) Minimum instruction execution time: 62.5 ns/4 MHz oscillator (with a × 4 multiplier setting) Uses PLL clock multiplication (2) Instruction set optimized for controller applications · Wide range of addressing modes: 23 modes · High code efficiency · High accuracy operations are enhanced by use of a 32-bit accumulator. Enhanced high level language (C) and multitasking support Common to instructions the F2MC-16 F2MC-16 series · Use of a system stack pointer · Enhanced pointer indirect instructions · Barrel shift instructions Improved execution speed: Four byte instruction queue Powerful interrupt function with 32 channels and 8 levels Automatic data transfer function that is independent of the CPU (EI2OS) · (3) (4) (5) (6) Wide range of data types (bit, byte, word, and long word) (7) External interrupts: 4 channels (8) A range of standby modes (Sleep mode, intermittent CPU operation mode, psuedo-clock mode, and stop mode) (9) 18-bit time-base timer · (10) Watchdog timer function CMOS technology 1 1.2 Embedded Function Modules (Resources) (1) UART0. 1 channel · (2) UART1. 1 channel · (3) For either asynchronous or synchronous transfer. For either asynchronous or clocked serial transfer (I/O extended serial). A/D converter · 10/8-bit conversion mode, input8 channels (4) 24-bit free-run timer . 1 channel (5) ICU (Input Capture Unit). 4 channels (6) OCU (Output Compare Unit) . 8 channels (7) 8-bit PPG timer . 2 channels (8) 16-bit reload timer . 2 channels (9) I2C interface . 1 channel (MB90675 MB90675 series only) 1.3 Model Range 1.3.1 MB90670 MB90670 Series Model Range Table 1.3.1: MB90670 MB90670 Series Model Range Model Name MB90671 MB90671 Type MB90672 MB90672 MB90673 MB90673 High volume High volume High volume MB90P673 MB90P673 MB90V670 MB90V670 One-time Evaluation product product product product product ROM capacity 16 Kbytes 32 Kbytes 48 Kbytes 48 Kbytes RAM capacity 640 bytes 1.64 Kbytes 2 Kbytes 2 Kbytes 3 Kbytes _ _ _ _ UART0 (asynchronous/synchronous transfer) 1 channel UART1 (asynchronous/extended serial) 1 channel A/D converter (10/8-bit) input 24-bit free-run timer ICU (Input capture unit) OCU (Output compare unit) 8 channels 1 channel 4 channels 4 channels + 4 channels 8-bit PPG timer 2 channels 16-bit reload timer 2 channels I2C interface Package type 1 channel 2 QFP-80 QFP-80 QFP-80 QFP-80 QFP-80 QFP-80 QFP-80 QFP-80 PGA-256 PGA-256 SQFP-80 SQFP-80 SQFP-80 SQFP-80 SQFP-80 SQFP-80 SQFP-80 SQFP-80 Table 1.3.2: MB90675 MB90675 Series Model Range (Continued) Model Name MB90676 MB90676 Type MB90677 MB90677 MB90678 MB90678 High volume High volume High volume MB90P678 MB90P678 MB90V670 MB90V670 One-time Evaluation product product product product product ROM capacity 32 Kbytes 48 Kbytes 64 Kbytes 64 Kbytes RAM capacity 1.6 Kbytes 2 Kbytes 3 Kbytes 3 Kbytes 3 Kbytes UART0 (asynchronous/synchronous transfer) 1 channel UART1 (asynchronous/extended serial) 1 channel A/D converter (10/8-bit) input 24-bit free-run timer ICU (Input capture unit) OCU (Output compare unit) 8 channels 1 channel 4 channels 4 channels + 4 channels 8-bit PPG timer 2 channels 16-bit reload timer 2 channels I2C interface Package type 1 channel QFP-100 QFP-100 QFP-100 QFP-100 QFP-100 QFP-100 QFP-100 QFP-100 PGA-256 PGA-256 SQFP-100 SQFP-100 SQFP-100 SQFP-100 SQFP-100 SQFP-100 SQFP-100 SQFP-100 Purchase of FUJITSU Ltd. I2C components conveys a licence under the Philips I2C Patent Right to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 3 1.4 Block Diagram UART0 16-bit reload timer SIN1/P43 SIN1/P43 SOT1/P44 SCK1/P45 SCK1/P45 UART1 (SCI) 16-bit reload timer DOT0/P70 DOT0/P70 DOT1/P71 DOT1/P71 DOT2/P72 DOT2/P72 DOT3/P73 DOT3/P73 DOT4/P74 DOT4/P74 DOT5/P75 DOT5/P75 DOT6/P76 DOT6/P76 DOT7/P77 DOT7/P77 OCU OCU 24-bit free-run timer ASR0/P64 ASR0/P64 ASR1/P65 ASR1/P65 ASR2/P66 ASR2/P66 ASR3/P67 ASR3/P67 ICU PPG0/P46 PPG0/P46 8-bit PPG PPG1/P80 PPG1/P80 8-bit PPG F2MC-16 F2MC-16 series internal bus SIN0/P40 SIN0/P40 SOT0/P41 SCK0/P42 SCK0/P42 I 2C interface SCL/P91 SCL/P91 AN0/P50 AN0/P50 AN1/P51 AN1/P51 AN2/P52 AN2/P52 AN3/P53 AN3/P53 AN4/P54 AN4/P54 AN5/P55 AN5/P55 AN6/P56 AN6/P56 AN7/P57 AN7/P57 AVCC AVR+ AVR- AVSS TIN1/P25 TIN1/P25 TOT0/P26 TOT1/P27 INT0/P60 INT0/P60 External interrupt External interrupt INT1/P61 INT1/P61 External interrupt INT3/P63 INT3/P63 External bus interface F2MC -16L CPU RAM Not included in the MB90670 MB90670 series. ATG/P47 ATG/P47 TIN0/P24 TIN0/P24 External interrupt 16-bit P P G SDA/P90 SDA/P90 ROM 10/8-bit A/D converter Clock controller (including time-base timer) General purpose I/O ports INT2/P62 INT2/P62 AD00/P00 AD00/P00 AD01/P01 AD01/P01 AD02/P02 AD02/P02 AD03/P03 AD03/P03 AD04/P04 AD04/P04 AD05/P05 AD05/P05 AD06/P06 AD06/P06 AD07/P07 AD07/P07 AD08/P10 AD08/P10 AD09/P11 AD09/P11 AD10/P12 AD10/P12 AD11/P13 AD11/P13 AD12/P14 AD12/P14 AD13/P15 AD13/P15 AD14/P16 AD14/P16 AD15/P17 AD15/P17 A16/P20 A16/P20 A17/P21 A17/P21 A18/P22 A18/P22 A19/P23 A19/P23 ALE/P30 ALE/P30 RD/P31 RD/P31 WRL/P32 WRL/P32 WRH/P33 WRH/P33 HRQ/P34 HRQ/P34 HAK/P35 HAK/P35 RDY/P36 RDY/P36 CLK/P37 CLK/P37 X1 X0 RST HST MD2 MD1 MD0 PA0 to PA7 PB0 to PB2 Not included in the MB90670 MB90670 series. Figure 1.4.1 4 Block Diagram of the MB90670/5 MB90670/5 Internal Configuration MD0 MD1 MD2 HST P60/INT0 P60/INT0 P61/INT1 P61/INT1 P62/INT2 P62/INT2 P63/INT3 P63/INT3 P64/ASR0 P64/ASR0 P65/ASR1 P65/ASR1 P66/ASR2 P66/ASR2 P67/ASR3 P67/ASR3 P70/DOT0 P70/DOT0 P71/DOT1 P71/DOT1 P72/DOT2 P72/DOT2 P73/DOT3 P73/DOT3 P74/DOT4 P74/DOT4 P75/DOT5 P75/DOT5 P76/DOT6 P76/DOT6 P77/DOT7 P77/DOT7 P80/PPG1 P80/PPG1 RST Vss X0 1.5 Pin Assignment 1.5.1 QFP-80 QFP-80 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 X1 65 40 P57/AN7 P57/AN7 Vcc 66 39 P56/AN6 P56/AN6 P00/AD00 P00/AD00 67 38 P55/AN5 P55/AN5 P01/AD01 P01/AD01 68 37 P54/AN4 P54/AN4 P02/AD02 P02/AD02 69 36 P53/AN3 P53/AN3 P03/AD03 P03/AD03 70 35 P52/AN2 P52/AN2 P04/AD04 P04/AD04 71 34 Vss P05/AD05 P05/AD05 72 33 P51/AN1 P51/AN1 P06/AD06 P06/AD06 73 32 P50/AN0 P50/AN0 P07/AD07 P07/AD07 74 31 AVss P10/AD08/WI0 P10/AD08/WI0 75 30 AVR- P11/AD09/WI1 P11/AD09/WI1 76 29 AVR+ P12/AD10/WI2 P12/AD10/WI2 77 28 AVcc P13/AD11/WI3 P13/AD11/WI3 78 27 P47/ATG P47/ATG P14/AD12/WI4 P14/AD12/WI4 79 26 P46/PPG0 P46/PPG0 P15/AD13/WI5 P15/AD13/WI5 80 25 P45/SCK1 P45/SCK1 QFP-80 QFP-80 P43/SIN1 P43/SIN1 P42/SCK0 P42/SCK0 P41/SOT0 P41/SOT0 P40/SIN0 P40/SIN0 P37/CLK P37/CLK P36/RDY P36/RDY P35/HAK P35/HAK P34/HRQ P34/HRQ P33/WRH P33/WRH P32/WRL P32/WRL P31/RD P31/RD P30/ALE P30/ALE Vss 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P27/TOT1 P27/TOT1 8 P26/TOT0 P26/TOT0 7 P25/TIN1 P25/TIN1 6 P24/TIN0 P24/TIN0 5 P23/A19 P23/A19 4 P22/A18 P22/A18 2 P21/A17 P21/A17 3 P20/A16 P20/A16 P16/AD14/ P16/AD14/ WI6 1 P17/AD15/ P17/AD15/ WI7 Package code (mold) FPT-80P-M06 FPT-80P-M06 Figure 1.5.1 QFP-80 QFP-80 Pin Assignment MD2 HST P60/INT0 P60/INT0 P61/INT1 P61/INT1 P62/INT2 P62/INT2 P63/INT3 P63/INT3 P64/ASR0 P64/ASR0 P65/ASR1 P65/ASR1 P66/ASR2 P66/ASR2 P67/ASR3 P67/ASR3 P70/DOT0 P70/DOT0 P71/DOT1 P71/DOT1 P72/DOT2 P72/DOT2 P73/DOT3 P73/DOT3 P74/DOT4 P74/DOT4 P75/DOT5 P75/DOT5 P76/DOT6 P76/DOT6 P77/DOT7 P77/DOT7 P80/PPG1 P80/PPG1 RST 1.5.2 SQFP-80 SQFP-80 Pin Assignment 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Vss 61 40 MD1 X0 62 39 MD0 X1 63 38 P57/AN7 P57/AN7 Vcc 64 37 P56/AN6 P56/AN6 P00/AD00 P00/AD00 65 36 P55/AN5 P55/AN5 P01/AD01 P01/AD01 66 35 P54/AN4 P54/AN4 P02/AD02 P02/AD02 67 34 P53/AN3 P53/AN3 P03/AD03 P03/AD03 68 33 P52/AN2 P52/AN2 P04/AD04 P04/AD04 69 32 Vss P05/AD05 P05/AD05 70 31 P51/AN1 P51/AN1 P06/AD06 P06/AD06 71 30 P50/AN0 P50/AN0 P07/AD07 P07/AD07 72 29 AVss P10/AD08/WI0 P10/AD08/WI0 73 28 AVR- P11/AD09/WI1 P11/AD09/WI1 74 27 AVR+ P12/AD10/WI2 P12/AD10/WI2 75 26 AVcc P13/AD11/WI3 P13/AD11/WI3 76 25 P47/ATG P47/ATG P14/AD12/WI4 P14/AD12/WI4 77 24 P46/PPG0 P46/PPG0 P15/AD13/WI5 P15/AD13/WI5 78 23 P45/SCK1 P45/SCK1 P16/AD14/WI6 P16/AD14/WI6 79 22 P44/SOT1 P44/SOT1 P17/AD15/WI7 P17/AD15/WI7 80 21 P43/SIN1 P43/SIN1 SQFP-80 SQFP-80 P42/SCK0 P42/SCK0 P40/SIN0 P40/SIN0 P41/SOT0 P41/SOT0 P37/CLK P37/CLK P36/RDY P36/RDY P35/HAK P35/HAK P34/HRQ P34/HRQ P33/WRH P33/WRH P32/WRL P32/WRL P31/RD P31/RD P30/ALE P30/ALE 9 10 11 12 13 14 15 16 17 18 19 20 Vss P25/TIN1 P25/TIN1 7 8 P27/TOT1 P27/TOT1 6 P26/TOT0 P26/TOT0 4 5 P23/A19 P23/A19 P22/A18 P22/A18 2 3 P21/A17 P21/A17 P20/A16 P20/A16 1 P24/TIN0 P24/TIN0 Package code (mold) FPT-80P-M05 FPT-80P-M05 Figure 1.5.2 SQFP-80 SQFP-80 Pin Assignment 5 P60/INT0 P60/INT0 P64/ASR0 P64/ASR0 P63/INT3 P63/INT3 P62/INT2 P62/INT2 P61/INT1 P61/INT1 P67/ASR3 P67/ASR3 P66/ASR2 P66/ASR2 P65/ASR1 P65/ASR1 P73/DOT3 P73/DOT3 P72/DOT2 P72/DOT2 P71/DOT1 P71/DOT1 P70/DOT0 P70/DOT0 P76/DOT6 P76/DOT6 P75/DOT5 P75/DOT5 P74/DOT4 P74/DOT4 PA1 PA0 P77/DOT7 P77/DOT7 PA5 PA4 PA3 PA2 PA7 PA6 RST 1.5.3 SQFP-100 SQFP-100 Pin Assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB0 PB1 PB2 76 77 78 50 49 48 HST Vss X0 X1 Vcc 79 80 81 82 47 46 45 44 MD0 P91/SCL P91/SCL P90/SDA P90/SDA P57/AN7 P57/AN7 P00/AD00 P00/AD00 P01/AD01 P01/AD01 P02/AD02 P02/AD02 83 84 85 43 42 41 P56/AN6 P56/AN6 P55/AN5 P55/AN5 P54/AN4 P54/AN4 P03/AD03 P03/AD03 P04/AD04 P04/AD04 P05/AD05 P05/AD05 P06/AD06 P06/AD06 86 87 88 89 40 39 38 37 Vss P53/AN3 P53/AN3 P52/AN2 P52/AN2 P51/AN1 P51/AN1 P07/AD07 P07/AD07 P10/AD08/ P10/AD08/ WI0 P11/AD09/ P11/AD09/ WI1 90 91 92 36 35 34 P50/AN0 P50/AN0 AVss AVR- 93 94 95 33 32 31 AVR+ AVcc P86 96 97 98 99 30 29 28 27 P85 P84 P83 P82 26 P81 100 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P44/ SOT1 Vcc P45/ 5 P41/ SOT0 P42/ SCK0 P43/SIN1 P43/SIN1 4 P36/RDY P36/RDY P37/CLK P37/CLK P40/SIN0 P40/SIN0 3 P32/WRL P32/WRL P33/WRH P33/WRH P34/HRQ P34/HRQ P35/HAK P35/HAK 2 P22/A18 P22/A18 P23/A19 P23/A19 1 P30/ALE P30/ALE P31/RD P31/RD Vss P15/AD13/ P15/AD13/ WI5 Package code (mold) FPT-100P-M05 FPT-100P-M05 P24/TIN0 P24/TIN0 P25/TIN1 P25/TIN1 P26/ TOT0 P27/ TOT1 P12/AD10/ P12/AD10/ WI2 P13/AD11/ P13/AD11/ WI3 P14/AD12/ P14/AD12/ WI4 SQFP-100 SQFP-100 MD2 MD1 Figure 1.5.3 SQFP-100 SQFP-100 Pin Assignment MD2 HST PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 P77/DOT7 P77/DOT7 P76/DOT6 P76/DOT6 P75/DOT5 P75/DOT5 P74/DOT4 P74/DOT4 P73/DOT3 P73/DOT3 P72/DOT2 P72/DOT2 P71/DOT1 P71/DOT1 P70/DOT0 P70/DOT0 P67/ASR3 P67/ASR3 P66/ASR2 P66/ASR2 P65/ASR1 P65/ASR1 P64/ASR0 P64/ASR0 P63/INT3 P63/INT3 P62/INT2 P62/INT2 P61/INT1 P61/INT1 P60/INT0 P60/INT0 RST PB2 PB1 PB0 1.5.4 QFP-100 QFP-100 Pin Assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Vss X0 X1 81 82 83 50 49 48 MD1 MD0 P91/SCL P91/SCL Vcc P00/AD00 P00/AD00 P01/AD01 P01/AD01 P02/AD02 P02/AD02 84 85 86 87 47 46 45 44 P90/SDA P90/SDA P57/AN7 P57/AN7 P56/AN6 P56/AN6 P55/AN5 P55/AN5 P03/AD03 P03/AD03 P04/AD04 P04/AD04 P05/AD05 P05/AD05 88 89 90 43 42 41 P54/AN4 P54/AN4 Vss P53/AN3 P53/AN3 P06/AD06 P06/AD06 P07/AD07 P07/AD07 P10/AD08/ P10/AD08/ WI0 91 92 93 40 39 38 P52/AN2 P52/AN2 P51/AN1 P51/AN1 P50/AN0 P50/AN0 37 36 35 34 AVss AVR- AVR+ AVcc 33 32 31 P86 P85 P84 Package code (mold) FPT-100P-M06 FPT-100P-M06 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P20/A16 P20/A16 P21/A17 P21/A17 P22/A18 P22/A18 P23/A19 P23/A19 P24/TIN0 P24/TIN0 P25/TIN1 P25/TIN1 P26/TOT0 P26/TOT0 P27/TOT1 P27/TOT1 P30/ALE P30/ALE P31/RD P31/RD Vss P32/WRL P32/WRL P33/WRH P33/WRH P34/HRQ P34/HRQ P35/HAK P35/HAK P36/RDY P36/RDY P37/CLK P37/CLK P40/SIN0 P40/SIN0 P41/SOT0 P41/SOT0 P42/SCK0 P42/SCK0 P43/SIN1 P43/SIN1 P44/SOT1 P44/SOT1 Vcc P45/SCK1 P45/SCK1 P46/PPG0 P46/PPG0 P47/ATG P47/ATG P80/PPG1 P80/PPG1 P81 P82 P83 P11/AD09/ P11/AD09/ WI1 P12/AD10/ P12/AD10/ WI2 P13/AD11/ P13/AD11/ WI3 P14/AD12/ P14/AD12/ WI4 QFP-100 QFP-100 Figure 1.5.4 QFP-100 QFP-100 Pin Assignment 6 1.5.5 QFP-80 QFP-80 External Dimensions FPT-80P-M06 FPT-80P-M06 EIAJ Code: QFP080-P-1420-4 QFP080-P-1420-4 Lead pitch Package width × package length 14 × 20mm Lead configuration Gull wing Sealing Plastic mold Flat portion length Plastic QFP, 80 pins 0.80mm 0.80mm (FPT-80P-M06 FPT-80P-M06) Plastic QFP, 80 pins (FPT-80P-M06 FPT-80P-M06) © 1992 FUJITSU LIMITED F80010S-3C-1 F80010S-3C-1 Units: mm (inches) 7 1.5.6 SQFP-80 SQFP-80 External Dimensions FPT-80P-M05 FPT-80P-M05 EIAJ Code: QFP080-P-1212-1 QFP080-P-1212-1 Lead pitch Package width × package length 12 × 12mm Lead configuration Gull wing Sealing Plastic SQFP, 80 pins 0.50mm Plastic mold (FPT-80P-M05 FPT-80P-M05) Plastic SQFP, 80 pins (FPT-80P-M05 FPT-80P-M05) © 1992 FUJITSU LIMITED F80008S-2C-3 F80008S-2C-3 8 Units: mm (inches) 1.5.7 SQFP-100 SQFP-100 External Dimensions FPT-100P-M05 FPT-100P-M05 EIAJ Code: QFP100-P-1414-1 QFP100-P-1414-1 Lead pitch Package width × package length 14 × 14mm Lead configuration Gull wing Sealing Plastic SQFP, 100 pins 0.50mm Plastic mold (FPT-100P-M05 FPT-100P-M05) Plastic SQFP, 100 pins (FPT-100P-M05 FPT-100P-M05) © 1992 FUJITSU LIMITED F100007S-2C-1 F100007S-2C-1 Units: mm (inches) 9 1.5.8 QFP-100 QFP-100 External Dimensions FPT-100P-M06 FPT-100P-M06 EIAJ Code: QFP100-P-1420-4 QFP100-P-1420-4 Lead pitch Package width × package length 14 × 20mm Lead configuration Gull wing Sealing Plastic mold Flat portion length Plastic QFP, 100 pins 0.65mm 0.80mm (FPT-100P-M06 FPT-100P-M06) Plastic QFP, 100 pins (FPT-100P-M06 FPT-100P-M06) © 1992 FUJITSU LIMITED F100008-3C-1 F100008-3C-1 10 Units: mm (inches) 1.6 Pin Description Table 1.6.1: MB90670 MB90670 Pin Functions (1) Pin No. QFP SQFP 64 65 62 63 67 to 74 65 to 72 Pin Name X0 X1 Circuit Type Crystal oscillator pins A (Oscillator) P00 to P07 B AD00 to AD07 (CMOS) 75 to 80 1, 2 73 to 80 P10 to P17 AD08 to AD15 Function General purpose I/O ports. This function applies in single-chip mode. I/O pins for the lower 8 bits of the external address/data bus. This function applies in modes that use an external bus. General purpose I/O ports. This function applies in single-chip mode. B I/O pins for the upper 8 bits of the external address/data bus. This function applies in modes that use an external bus. (CMOS) I/O pins for the wakeup interrupts. This function applies in singlechip mode. As these inputs are used continuously when external interrupts are enabled, outputs to these pins from other functions must be stopped unless performed intentionally. WI0 to WI7 3 to 6 1 to 4 P20 to P23 B A16 to A19 (CMOS) 7, 8 5, 6 P24, P25 TIN0, TIN1 9, 10 7, 8 P26, P27 TOT0, TOT1 12 10 E Event input pins for reload timers 0 and 1. As these inputs are used continuously during reload timer input operation, outputs to these pins from other functions must be stopped unless performed inten(CMOS/H) tionally. E P30 (CMOS) P31 B RD (CMOS) 14 12 P32 B WRL (CMOS) 15 13 General purpose I/O ports. This function applies when the outputs for reload timers 0 and 1 are disabled. Output pins for reload timers 0 and 1. This function applies when (CMOS/H) the outputs for reload timers 0 and 1 are enabled. B 11 Output pins for A16 to 19 of the external address bus. This function applies in modes that use an external bus and when the address upper control register is set to "address". General purpose I/O ports. This function applies in all cases. ALE 13 General purpose I/O ports. This function applies in single-chip mode or when the address upper control register is set to "port". P33 General purpose I/O port. This function applies in single-chip mode. Address latch enable output pin. This function applies in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode. Read strobe output pin for the data bus. This function applies in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode or when WR pin output is disabled. Write strobe output pin for the lower 8 bits of the data bus. This function applies in modes that use an external bus and when WR pin output is enabled. General purpose I/O port. This function applies in single-chip mode, 8-bit external bus mode, or when WR pin output is disabled. B WRH Write strobe output pin for the upper 8 bits of the data bus. This function applies in modes that use an external bus in 16-bit external bus mode, and when WR pin output is enabled. (CMOS) 11 Table 1.6.1: MB90670 MB90670 Pin Functions (2) Pin No. QFP SQFP 16 14 Pin Name Circuit Type P34 B HRQ (CMOS) 17 15 P35 B HAK (CMOS) 18 16 P36 B RDY (CMOS) 19 17 P37 B CLK (CMOS) 20 18 P40 Function General purpose I/O port. This function applies in single-chip mode and when the hold function is disabled. Hold request input pin. This function applies when the hold function is enabled in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode and when the hold function is disabled. Hold acknowledge output pin. This function applies when the hold function is enabled in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode and when the external ready function is disabled. Ready input pin. This function applies when the external ready function is enabled in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode and when CLK output is disabled. CLK output pin. This function applies when CLK output is enabled in modes that use an external bus. General purpose I/O port. This function applies in all cases. SIN0 21 19 UART0 serial data input pin. As this input is used continuously during UART0 input operation, output to this pin from other functions (CMOS/H) must be stopped unless performed intentionally. P41 General purpose I/O port. This function applies when UART0 serial data output is disabled. E E SOT0 22 20 P42 SCK0 23 21 UART0 serial data output pin. This function applies when UART0 (CMOS/H) serial data output is enabled. General purpose I/O port. This function applies when UART0 clock output is disabled. E UART0 clock I/O pin. This function applies when the UART0 clock output is enabled. As this input is used continuously during UART0 input operation, output to this pin from other functions must be (CMOS/H) stopped unless performed intentionally. P43 General purpose I/O port. This function applies in all cases. SIN1 24 22 UART1 serial data input pin. As this input is used continuously during UART1 input operation, output to this pin from other functions (CMOS/H) must be stopped unless performed intentionally. P44 General purpose I/O port. This function applies when UART1 serial data output is disabled. E E SOT1 25 23 P45 SCK1 26 24 UART1 serial data output pin. This function applies when UART1 (CMOS/H) serial data output is enabled. General purpose I/O port. This function applies when UART1 clock output is disabled. E UART1 clock I/O pin. This function applies when UART1 clock output is enabled. As this input is used continuously during UART1 input operation, output to this pin from other functions must be (CMOS/H) stopped unless performed intentionally. P46 E PPG0 12 General purpose I/O port. This function applies when waveform output is disabled for PPG timer 0. PPG timer 0 output pin. This function applies when waveform out(CMOS/H) put is enabled for PPG timer 0. Table 1.6.1: MB90670 MB90670 Pin Functions (3) Pin No. QFP SQFP 27 25 Pin Name Circuit Type P47 Function General purpose I/O port. This function applies in all cases. ATG A/D converter trigger input pin. As this input is used continuously during A/D converter input operation, output to this pin from other (CMOS/H) functions must be stopped unless performed intentionally. Power sup- Analog circuit power supply. Do not switch this power supply on or off unless a voltage greater than AVCC is applied to VCC. ply E 28 26 AVCC 29 27 AVR+ Power supply Analog circuit reference voltage input. Do not switch this power supply on or off unless a voltage greater than AVR+ is applied to AVCC. 30 28 AVR- Power supply Analog circuit reference voltage input 31 29 AVSS Power supply Analog circuit ground level 32, 33, 30, 31, 35 to 40 33 to 38 P50 to P57 C AN0 to AN7 (AD) 41 to 43 39 to 41 MD0 to MD2 F Open drain I/O ports. The input function is valid only when "port" is specified in the analog input enable register. Analog input pins for the A/D converter. This function applies when "AD" is specified in the analog input enable register. Input pins for the operating mode specification. Connect directly to VCC or VSS. (CMOS) 44 42 45 to 48 43 to 46 HST P60 to P63 INT0 to INT3 49 to 52 47 to 50 Hardware standby input pin G (CMOS/H) General purpose I/O port. This function applies in all cases. External interrupt request input pins. As these inputs are used continuously when external interrupts are enabled, output to these pins from other functions must be stopped unless performed inten(CMOS/H) tionally. E P64 to P67 ASR0 to ASR3 General purpose I/O port. This function applies in all cases. E (CMOS/H) 53 to 60 51 to 58 P70 to P77 E DOT0 to DOT7 (CMOS/H) 61 59 P80 E PPG1 (CMOS/H) 62 60 RST H (CMOS/H) 66 64 VCC Power supply 11 34 63 9 32 61 VSS Data sampling input pins for ICU0 to 3. As these inputs are used continuously during ICU input operation, output to these pins from other functions must be stopped unless performed intentionally. General purpose I/O ports. This function applies when OCU waveform output is disabled. OCU0 and OCU1 waveform output pins. This function applies when the pins are set as port outputs and when OCU waveform output is enabled. General purpose I/O port. This function applies when waveform output is disabled for PPG timer 1. PPG timer 1 output pin. This function applies when waveform output is enabled for PPG timer 1. External reset request input Power supply Digital circuit power supply Digital circuit ground level 13 Table 1.6.2: MB90675 MB90675 Pin Functions (1) Pin No. QFP SQFP 82 83 80 81 85 to 92 83 to 90 Pin Name X0 X1 Circuit Type Crystal oscillator pin A (Oscillator) P00 to P07 B AD00 to AD07 (CMOS) 93 to 100 91 to 98 Function P10 to P17 General purpose I/O ports. This function applies in single-chip mode. I/O pins for the lower 8 bits of the external address/data bus. This function applies in modes that use an external bus. General purpose I/O ports. This function applies in single-chip mode. B I/O pins for the upper 8 bits of the external address/data bus. This function applies in modes that use an external bus. (CMOS) AD08 to AD15 I/O pins for the wakeup interrupts. This function applies in singlechip mode. As these inputs are used continuously when external interrupts are enabled, outputs to these pins from other functions must be stopped unless performed intentionally. WI0 to WI7 1 2 3 4 99 100 1 2 P20 to P23 B A16 to A19 (CMOS) 5, 6 3, 4 P24, P25 TIN0, TIN1 7, 8 5, 6 E Event input pins for reload timers 0 and 1. As these inputs are used continuously during reload timer input operation, outputs to these pins from other functions must be stopped unless performed inten(CMOS/H) tionally. E 9 7 P30 B (CMOS) 8 P31 B RD (CMOS) 12 10 P32 B WRL (CMOS) 13 11 P33 B General purpose I/O port. This function applies in single-chip mode. Address latch enable output pin. This function applies in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode. Read strobe output pin for the data bus. This function applies in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode or when WR pin output is disabled. Write strobe output pin for the lower 8 bits of the data bus. This function applies in modes that use an external bus and when WR pin output is enabled. General purpose I/O port. This function applies in single-chip mode, 8-bit external bus mode, or when WR pin output is disabled. Write strobe output pin for the upper 8 bits of the data bus. This function applies in modes that use an external bus in 16-bit external bus mode, and when WR pin output is enabled. WRH (CMOS) 14 General purpose I/O ports. This function applies when the outputs for reload timers 0 and 1 are disabled. Output pins for reload timers 0 and 1. This function applies when (CMOS/H) the outputs for reload timers 0 and 1 are enabled. ALE 10 Output pins for A16 to 19 of the external address bus. This function applies in modes that use an external bus and when the address upper control register is set to "address". General purpose I/O ports. This function applies in all cases. P26, P27 TOT0, TOT1 General purpose I/O ports. This function applies in single-chip mode or when the address upper control register is set to "port". Table 1.6.2: MB90675 MB90675 Pin Functions (2) Pin No. QFP SQFP 14 12 Pin Name Circuit Type P34 B HRQ (CMOS) 15 13 P35 B HAK (CMOS) 16 14 P36 B RDY (CMOS) 17 15 P37 B CLK (CMOS) 18 16 P40 Function General purpose I/O port. This function applies in single-chip mode and when the hold function is disabled. Hold request input pin. This function applies when the hold function is enabled in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode and when the hold function is disabled. Hold acknowledge output pin. This function applies when the hold function is enabled in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode and when the external ready function is disabled. Ready input pin. This function applies when the external ready function is enabled in modes that use an external bus. General purpose I/O port. This function applies in single-chip mode and when CLK output is disabled. CLK output pin. This function applies when CLK output is enabled in modes that use an external bus. General purpose I/O port. This function applies in all cases. SIN0 19 17 UART0 serial data input pin. As this input is used continuously during UART0 input operation, output to this pin from other functions (CMOS/H) must be stopped unless performed intentionally. P41 General purpose I/O port. This function applies when UART0 serial data output is disabled. E E SOT0 20 18 P42 SCK0 21 19 UART0 serial data output pin. This function applies when UART0 (CMOS/H) serial data output is enabled. General purpose I/O port. This function applies when UART0 clock output is disabled. E UART0 clock I/O pin. This function applies when UART0 clock output is enabled. As this input is used continuously during UART0 input operation, output to this pin from other functions must be (CMOS/H) stopped unless performed intentionally. P43 General purpose I/O port. This function applies in all cases. SIN1 22 20 UART1 serial data input pin. As this input is used continuously during UART1 input operation, output to this pin from other functions (CMOS/H) must be stopped unless performed intentionally. P44 General purpose I/O port. This function applies when UART1 serial data output is disabled. E E SOT1 24 22 UART1 serial data output pin. This function applies when UART1 (CMOS/H) serial data output is enabled. P45 SCK1 General purpose I/O port. This function applies when UART1 clock output is disabled. E UART1 clock I/O pin. This function applies when UART1 clock output is enabled. As this input is used continuously during UART1 input operation, output to this pin from other functions must be (CMOS/H) stopped unless performed intentionally. 15 Table 1.6.2: MB90675 MB90675 Pin Functions (3) Pin No. QFP SQFP 25 23 Pin Name Circuit Type P46 E PPG0 26 24 Function General purpose I/O port. This function applies when waveform output is disabled for PPG timer 0. PPG timer 0 output pin. This function applies when waveform out(CMOS/H) put is enabled for PPG timer 0. P47 General purpose I/O port. This function applies in all cases. ATG A/D converter trigger input pin. As this input is used continuously during A/D converter input operation, output to this pin from other (CMOS/H) functions must be stopped unless performed intentionally. E 34 32 AVCC Power sup- Analog circuit power supply. Do not switch this power supply on or off unless a voltage greater than AVCC is applied to VCC. ply 35 33 AVR+ Power sup- Analog circuit reference voltage input. Do not switch this power supply on or off unless a voltage greater than AVR+ is applied to ply AVCC. 36 34 AVR- Power sup- Analog circuit reference voltage input ply 37 35 AVSS Power sup- Analog circuit ground level ply 38 to 41, 36 to 39, P50 to P57 43 to 46 41 to 44 AN0 to AN7 Open drain I/O ports. Input functions are valid only when "port" is specified in the analog input enable register. C Analog input pins for the A/D converter. This function applies when "AD" is specified in the analog input enable register. (AD) 49 to 51 47 to 49 52 50 53 to 56 51 to 54 MD0 to MD2 HST General purpose I/O ports. This function applies in all cases. External interrupt request input pins. As these inputs are used continuously when external interrupts are enabled, output to these pins from other functions must be stopped unless performed inten(CMOS/H) tionally. E P64 to P67 ASR0 to ASR3 General purpose I/O ports. This function applies in all cases. E (CMOS/H) 61 to 68 59 to 66 P70 to P77 DOT0 to DOT7 E (CMOS/H) 27 25 P80 E PPG1 (CMOS/H) 28 to 33 26 to 31 P81 to P86 E (CMOS/H) 16 Input pins for the operating mode specification. Connect directly to VCC or VSS. G Hardware standby input pin (CMOS/H) P60 to P63 INT0 to INT3 57 to 60 55 to 58 F (CMOS) Data sampling input pins for ICU0-3. As these inputs are used continuously during ICU input operation, output to these pins from other functions must be stopped unless performed intentionally. General purpose I/O ports. This function applies when OCU waveform output is disabled. OCU0 and OCU1 waveform output pins. This function applies when the pins are set as port outputs and when OCU waveform output is enabled. General purpose I/O port. This function applies when waveform output is disabled for PPG timer 1. PPG timer 1 output pin. This function applies when waveform output is enabled for PPG timer 1. General purpose I/O ports. This function applies in all cases. Table 1.6.2: MB90675 MB90675 Pin Functions (4) Pin No. QFP SQFP 47 45 Pin Name P90 SDA 48 46 P91 SCL 69 to 76 67 to 74 Circuit Type PA0 to PA7 Function Open drain I/O ports. This function applies in all cases. Data I/O pins for the I2C interface. This function applies when I2C interface operation is enabled. Set the port outputs to Hi-Z (PDR = (NMOS/H) 1) when the I2C interface is in operation. Open drain I/O ports. This function applies in all cases. D Clock I/O pins for the I2C interface. This function applies when I2C interface operation is enabled. Set the port outputs to Hi-Z (PDR = (NMOS/H) 1) when the I2C interface is in operation. D E General purpose I/O ports. This function applies in all cases. (CMOS/H) 78 to 80 76 to 78 PB0 to PB2 E General purpose I/O ports. This function applies in all cases. (CMOS/H) 77 75 RST 23 84 21 82 VCC 11 42 81 9 40 79 VSS External reset request input H (CMOS/H) Power sup- Digital circuit power supply ply Digital circuit ground level Power supply 17 Table 1.6.3: I/O Circuit Configurations (1) Circuit Configuration Classification A Remarks · 3 MHz to 32 MHz · Oscillator feedback resistance: approximately 1 M · CMOS level I/O With standby control · Selectable pull-up option (with standby control) · N-channel open drain output CMOS level hysteresis input With AD control · clock input X1 NMOS open drain CMOS level hysteresis input With standby control X0 STANDBY CONTROL B digital output digital output digital input STANDBY CONTROL C digital output A/D input digital input A/D DISABLE D digital output digital input STANDBY CONTROL 18 Table 1.6.3: I/O Circuit Configurations (2) Circuit Configuration Classification E Remarks · CMOS level output CMOS level hysteresis input With standby control · Selectable pull-up option (with standby control) · CMOS level input No standby control · Selectable pull-up or pull-down option (no standby control) · For the MD2 pin, the mask ROM version is fixed as pull-down. No option setting is available for other versions. · CMOS level hysteresis input No standby control · CMOS level hysteresis input No standby control · Selectable pull-up option (no standby control) digital output digital output digital input STANDBY CONTROL F digital input G digital input H digital input 19 1.7 Device Operation (1) Preventing latch-up Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if the voltage applied between VCC and VSS exceeds the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation. For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage. (2) Connecting unused pins Leaving unused input pins unconnected can cause misoperation. Always pull-up or pulldown unused pins. (3) Cautions when using an external clock Drive the X0 pin only when using an external clock. Figure 1.7.1 shows an example of how to use an external clock. xo ¡ OPEN x1 MB90670/5 MB90670/5 Figure 1.7.1 Example of How to Use an External Clock (4) Power supply pin When multiple VCC and VSS pins are provided, connect all VCC and VSS pins to power supply or ground externally. Although pins at the same potential are connected together in the internal device design so as to prevent inadvertent operation such as latch-up, connecting all VCC and VSS pins appropriately minimizes unwanted radiation, prevents erratic operation of strobe signals due to increases in the ground level, and keeps the overall output current rating. Also, take care to connect VCC and VSS to a current source with the lowest possible impedance. Connection of a bypass capacitor of approximately 0.1 µF between VCC and VSS close to the device is recommended. 20 (5) Crystal oscillator circuit Noise in the vicinity of the X0 and X1 pins can be a cause of device misoperation. Place X0, X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground as close together as possible. Also, design the printed circuit board so that the wiring for the crystal oscillator circuit does not cross other wiring. A printed circuit board design that surrounds the X0 and X1 pins with ground provides for stable operation and is strongly recommended. (6) A/D converter power supply and the turn-on sequence for analog inputs Do not apply current to the A/D converter power supply (AVcc, AVR+, AVR-) or analog inputs (AN0 to AN7) until the digital power supply (Vcc) is turned on. When turning the device off, turn off the digital power supply after cutting the A/D converter power supply and analog inputs. When turning the power on or off, ensure that AVR+ does not exceed AVcc. (Turning the analog and digital power supplies on or off simultaneously does not cause a problem.) 21 1.8 Mask Options Table 1.8.1 lists the available option settings. The method of specifying options differs between products. Check the mask option table in the data sheet before using. Table 1.8.1: Mask Options MB90673 MB90673 MB90678 MB90678 MB90P673 MB90P673 MB90W673 MB90W673 MB90P678 MB90P678 MB90W678 MB90W678 Specify when ordering mask Set using an EPROM writer Setting not available 1 Pull-up resistance P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P86, PA0 to PA7, PB0 to PB2, RST, MD1, MD0 Selectable for each pin Selectable for each pin No pull-up resistance 2 Selectable for each pin Selectable for each pin No pull-down resistance Content No. Specification method 22 Pull-down resistance MD1, MD0 MB90V670 MB90V670 CHAPTER 2 Hardware 2.1 CPU 2.1.1 Memory Space s Outline of the CPU memory space The program, data, and I/O managed by the F2MC-16L F2MC-16L CPU are all located in the CPU's 16Mbyte memory space. The CPU can access the addresses for each resource via the 24-bit address bus (Figure 2.1.1). F2MC-16L F2MC-16L device Program F2MC-16L F2MC-16L Data CPU Interrupts Peripheral circuits General purpose ports [Device] FFFFFFH FF8000H FF8000H 810000H 810000H 800000H 800000H Program area Data area 0000C0H 0000C0H Interrupt controller 0000B0H 0000B0H Internal resources 000020H 000020H General purpose ports 000000H 000000H Figure 2.1.1 Example of the Relationship Between the F2MC-16L F2MC-16L System and Memory Map Note:The MB90670/5 MB90670/5 series can only output 20-bit addresses externally. This allows access to a maximum area of 1 Mbyte. 23 s Address generation modes Address generation in the F2MC-16L F2MC-16L can be broadly divided into two modes: linear addressing in which the instruction specifies the entire 24-bit address, and bank addressing in which the upper 8 bits of the address are set in a bank register as required by the application and the instruction specifies the lower 16 bits of the address. Linear addressing can be further divided into two types. In one method, the operand specifies the 24-bit address directly. In the other method, the lower 24 bits of a 32-bit general purpose register are used as the address. (Figure 2.1.2) Example 1: Linear addressing with a 24-bit address operand JMPP 123456H 123456H Old program counter + program bank 17452DH 17452DH 17 452D JMPP 123456H 123456H New program counter + program bank 12 Next instruction 3456 Example 2: Linear addressing using 32-bit register indirect addressing MOV A,@RL1+7 Old AL 090700H 090700H XXXX 3A +7 RL1 (Upper 8 bits ignored.) New AL 240906F9 240906F9 003A Figure 2.1.2 Example of Linear Address Generation 24 123456H 123456H s Bank addressing modes Bank addressing splits the 16-MByte address space into 256 banks of 64 Kbytes. The bank registers specify the bank address. Five types of bank registers are provided. Table 2.1.1 lists the accessed memory space and main application of each bank register. Table 2.1.1: Accessed Memory Space for Each Bank Register Bank Register Name Memory Space Name Main Application Initial Value after Reset Program bank register (PCB) Program (PC) space Stores instruction code, vector tables, and immediate data FFH Data bank register (DTB) Data (DT) space Stores readable and writable data. Accesses control registers and data registers for internal and external peripherals. 00H Area used for stack access such as by PUSH and POP instructions or register saving at interrupts. SSB is used when S=1 in CCR. USB is used when S=0 in CCR. 00H Stores data such as data that is too large for the data (DT) space. 00H User stack bank register (USB) Stack (SP) space System stack bank register (SSB) Additional bank register (ADB) Additional (AD) space 00H After a reset, the DT, SP, and AD spaces are allocated to bank 00 (000000 H to 00FFFFH 00FFFFH) and the PC space is allocated to bank FF (FF0000H FF0000H to FFFFFFH). To improve instruction code efficiency, instructions have a default space for each addressing mode. Table 2.1.2 lists the defaults. Prefix codes corresponding to each bank can be prefixed to instructions to specify a space other than the default for the current addressing mode. The system accesses the bank space corresponding to the prefix code. Table 2.1.2: Default Spaces Default Space Addressing Program space PC indirect, program access, branching Data space @A, addr16, dir, Addressing using @RW0, @RW1, @RW4, or @RW5 Stack space Addressing using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing using @RW2, @RW6 25 Figure 2.1.3 shows an example of the division of memory space into banks and each bank register. FFFFFFH Program space FF0000H FF0000H FFH : PCB (Program bank register) B3H : ADB (Additional bank register) 92H : USB (User stack bank register) 68H : DTB (Data bank register) 4BH : SSB (System stack bank register) B3FFFFH Additional space Physical addresses B30000H B30000H 92FFFFH 92FFFFH User stack space 920000H 920000H 68FFFFH 68FFFFH Data space 680000H 680000H 4BFFFFH System stack space 4B0000H 4B0000H 000000H 000000H Figure 2.1.3 Example of Physical Addresses of Each Memory Space 26 s Memory space layout for multi-byte data Figure 2.1.4 shows the data configuration of multi-byte data in memory. The lower 8 bits are placed at location n and subsequent bytes placed at locations n+1, n+2, n+3, etc. MSB H LSB 01010101 11001100 11111111 00010100 01010101 11001100 11111111 Location n 00010100 L Figure 2.1.4 Example of Memory Layout for Multi-Byte Data Memory is written to from the lowest address. Therefore, for 32-bit data, the lower 16 bits are transferred first, followed by the upper 16 bits. If a reset signal is input immediately after writing the lower data bits, writing the upper data bits may not occur. s Accessing multi-byte dat All access occurs within a bank. Therefore, for instructions that access multi-byte data, the next address after location FFFFH is location 0000H 0000H in the same bank. Figure 2.1.5 shows an execution example for an instruction that accesses multi-byte data. H 80FFFFH 80FFFFH AL before execution ? ? AL after execution 23H 01H 01H · · · 23H 800000H 800000H L Figure 2.1.5 Execution of MOVW A,080FFFFH 080FFFFH 27 2.1.2 Registers The F2MC-16L F2MC-16L registers can be broadly divided into two categories: special registers internal to the CPU and general purpose registers located in internal RAM. Special registers exist as dedicated hardware in the CPU and their use is limited by the CPU architecture. General purpose registers coexist with RAM in the CPU's address space. Like special registers, general purpose registers can be accessed without specifying an address. However, general purpose registers can also be used as specified by the user, in the same way as standard memory. Figure 2.1.6 shows the layout of the special and general purpose registers in the device. CPU Special registers RAM Accumulator User stack pointer System stack pointer General purpose registers Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register Internal bus Figure 2.1.6 Special and General Purpose Registers 28 s Special registers Table 2.1.3 lists the eleven special registers in the F2MC-16L F2MC-16L. Table 2.1.3 Special Registers Structure AH Register Name Function Accumulator 2 × 16-bit registers used to save operation results and similar. Can be combined as a single 32-bit register. USP User stack pointer 16-bit pointer that specifies the user stack area SSP System stack pointer AL 16-bit pointer that specifies the system stack area 16-bit register that indicates the system status PS PC Processor status Program counter 16-bit register that stores the address containing the program 8-bit register that specifies the direct page DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register 8-bit register that specifies the program space 8-bit register that specifies the data space 8-bit register that specifies the user stack space SSB System stack bank register ADB 8-bit register that specifies the system stack space Additional data bank register 8-bit register that specifies the additional space 29 s Accumulator(A) The accumulator consists of two 16-bit operation registers: AH and AL. The accumulator is used for temporary storage of operation results and data transfers. AH and AL can be combined for 32-bit data processing. For 16-bit word processing or 8-bit byte processing, the AL register only is used (see Figures 2.1.7 and 2.1.8). Operations can be performed on accumulator data and memory or register (Ri, RWi, or RLi) data. Like the F2MC-8, when word-length or shorter data is transferred to the F2MC-16 F2MC-16's AL register, the previous content of AL is automatically transferred to AH (the data keep function). The data keep function and AL-AH operations increase the processing efficiency of the device (see Figure 2.1.8). (This instruction performs a long-word read from the location specified by adding an 8-bit offset value to RW1 and places the data in the accumulator.) MOVL A,@RW1+6 Memory space MSB Accumulator before execution A61540H A61540H DTB 74H 2BH 52H RW1 XXXXH 8FH A6153EH A6153EH XXXXH 15H LSB 38H A6H +6 Accumulator after execution 8F74H 8F74H 2B52H 2B52H AH AL Figure 2.1.7 32-bit Data Transfer Example MOVW A,@RW1+6 (This instruction performs a single-word read from the location specified by adding an 8-bit offset value to RW1 and places the data in the accumulator.) Memory space MSB Accumulator before execution A61540H A61540H 1234H 1234H DTB 8FH 74H A6153EH A6153EH XXXXH 2BH 52H RW1 15H 38H A6H +6 Accumulator after execution 1234H 1234H 2B52H 2B52H AH AL Figure 2.1.8 AL-AH Transfer Example 30 LSB When transferring byte-length or shorter data to AL, the data placed in AL is sign extended or zero extended to a length of 16 bits. Data in AL can be treated as word-length or byte-length. When the CPU executes a byte-length arithmetic instruction on AL, the operation ignores the unprocessed upper 8 bits of AL and sets the upper 8 bits of the result to zero (see Figures 2.1.9 and 2.1.10). The accumulator is not initialized by a reset. The value of the accumulator after a reset is undefined. MOV A,3000H 3000H (This instruction zero extends the data at location 3000H 3000H and places the result in AL.) Memory space MSB Accumulator before execution XXXXH DTB Accumulator after execution B53000H B53000H 2456H 2456H 2456H 2456H 88H B5H 0088H 0088H AH 77H LSB AL Figure 2.1.9 Zero Extend Execution Example (This instruction sign extends the data at location 3000H 3000H and places the result in AL.) MOVX A,3000H 3000H MSB Accumulator before execution XXXXH DTB Accumulator after execution B53000H B53000H 2456H 2456H 2456H 2456H 77H LSB 88H B5H FF88H FF88H AH Memory space AL Figure 2.1.10 Sign Extend Execution Example 31 s User stack pointer (USP) and system stack pointer (SSP) The USP and SSP are 16-bit registers that specify the memory address for saving and restoring data at PUSH/POP instruction or subroutine execution. Stack instructions operate in the same way on both USP and SSP. The instructions use USP if the S flag in the processor status (PS) register is set to "0", or SSP if the S flag is set to "1" (see Figure 2.1.11). The S flag is set to "1" when an interrupt is received. Therefore, when an interrupt occurs, the processor always saves registers to the memory specified by SSP. Normally, stack processing in interrupt routines uses SSP and stack processing outside interrupt routines uses USP. If dividing the stack space is not necessary, use SSP only. Always set an even numbered address to the stack pointer. Setting an odd numbered address splits word access in two and reduces efficiency. SSB specifies the upper 8 bits of the stack address for SSP and USB specifies the upper 8 bits for USP. USP and SSP are not initialized by a reset. The values of USP and SSP after a reset are undefined. Example 1: Executing PUSHW A when the S flag is "0". MSB Before execution AL A624H A624H USB C6H USP F328H F328H 0 SSB 56H SSP AL A624H A624H USB C6H USP F326H F326H 0 SSB 56H SSP 1234H 1234H XX XX 1234H 1234H S flag After execution C6F326H C6F326H LSB S flag User stack used because S flag = "0". C6F326H C6F326H A6H 24H Example 2: Executing PUSHW A when the S flag is "1". MSB Before execution AL A624H A624H USB C6H USP F328H F328H 1 SSB 56H SSP AL A624H A624H USB C6H USP F328H F328H 1 SSB 56H SSP 1232H 1232H 561232H 561232H XX XX 561232H 561232H A6H 24H 1234H 1234H S flag After execution LSB S flag System stack used because S flag = "1". Figure 2.1.11 Stack Manipulation Instructions and Stack Pointers 32 s Processor status (PS) The processor status register consists of control bits that control the CPU operation and status bits that indicate the CPU status. Figure 2.1.12 shows the structure of PS. The upper byte contains the register bank pointer (RP), which indicates the top address of the register bank, and the interrupt level mask register (ILM). The lower byte contains the condition code register (CCR). The CCR consists of flags which are set to "0" or "1" by instruction execution results, interrupt generation, or other events. 15 PS Initial value x : 13 12 8 7 ILM 0 RP 000 Undefined value CCR 00000 - 0 1 x x x x x Figure 2.1.12 PS Structure (1) Condition code register (CCR) Figure 2.1.13 shows the structure of the condition code register. 7 5 4 3 2 1 0 - Initial value x : 6 I S T N Z V C - 0 1 x x x x x : CCR Undefined value Figure 2.1.13 Condition Code Register Structure I: Interrupt enable flag For all interrupts other than software interrupts, setting I to "1" enables the interrupts and setting I to "0" masks the interrupts. Cleared by a reset. S: Stack flag Stack operations use USP as a pointer if the S flag is set to "0", or SSP if the S flag is set to "1". Set by a reset or on receiving an interrupt. T: Sticky bit flag Set to "1" if the data shifted-out of carry during a logical or arithmetic right shift instruction contains one or more "1"s. Otherwise, set to "0". Also set to "0" if the shift amount is zero. N: Negative flag Set if the MSB of an operation result is "1", cleared if the MSB is "0". Z: Zero flag Set if an operation result is all "0"s, cleared otherwise. V: Overflow flag Set if an overflow occurs for a signed value as the result of the execution of an operation. Cleared if no overflow occurs. C: Carry flag Set if a carry-up or carry-down occurs for the MSB as the result of the execution of an operation. Cleared if no carry occurs. 33 (2) Register bank pointer (RP) The RP register specifies the relationship between the F2MC-16L F2MC-16L's general purpose registers and the addresses in internal RAM where the registers are located. The top memory address of the register bank currently in use is specified by the conversion formula: [000180H 000180H + (RP)*10H] (see Figure 2.1.14). RP consists of 5 bits and can be set in the range between 00H and 1FH. The register bank can be located in the memory range between 000180H 000180H and 00037FH 00037FH. However, addresses in this range cannot be used for general purpose registers unless the addresses point to internal RAM. RP is initialized to 00H by a reset. RP can be set by an 8-bit immediate move instruction but only the lower 5 bits are used. B4 Initial value B3 B2 B1 B0 0 0 0 0 0 : RP Figure 2.1.14 Register Bank Pointer (3) Interrupt Level Mask Register (ILM) ILM consists of 3 bits and specifies the interrupt mask level for the CPU. The CPU only receives interrupts with a higher priority level than the level specified in ILM. Zero is the highest interrupt level and seven is the lowest interrupt level (see Table 2.1.4). Therefore, to receive an interrupt, the level value of the interrupt request must be less than the value set in ILM. When an interrupt is received, the interrupt level value is set in ILM. This disables the subsequent reception of interrupts of the same or lower priority level. ILM is initialized to all zeros by a reset. ILM can be set by an 8-bit immediate move instruction but only the upper 3 bits are used. ILM2 Initial value ILM1 ILM0 0 0 0 : ILM Figure 2.1.15 Interrupt Level Register Table 2.1.4: Priority Levels for the Interrupt Level Mask Register (ILM) ILM2 ILM0 Level Value Allowed Interrupt Levels 0 0 0 0 Interrupts prohibited 0 0 1 1 0 only 0 1 0 2 Level 1 or less 0 1 1 3 Level 2 or less 1 0 0 4 Level 3 or less 1 0 1 5 Level 4 or less 1 1 0 6 Level 5 or less 1 34 ILM1 1 1 7 Level 6 or less s Program counter (PC) The PC is a 16-bit counter. The PC specifies the lower 16 bits of the instruction code to be executed by the CPU. PCB specifies the upper 8 bits of the address. Operations that update the content of the PC include conditional branch instructions, subroutine call instructions, interrupts, and resets. The PC can also be used as the base pointer for operand access. PC ABCDH FEH PCB FEABCDH Next instruction to execute Figure 2.1.16 Program Counter s Direct page register (DPR) DTB register DPR register Direct address in instruction As shown in Figure 2.1.17, the DPR specifies addr8 to addr15 of the operand for direct addressing instructions. DPR is an 8-bit register and is initialized to 01H by a reset. The DPR can be read from or written to by instructions. MSB 24-bit physical address LSB Figure 2.1.17 Physical Address Generation Using Direct Addressing s Program counter bank register (PCB) Data bank register (DTB) User stack bank register (USB) System stack bank register (SSB) Additional data bank register (ADB) The bank registers specify the memory banks for the PC space, DT space, SP space (user), SP space (system), and AD space respectively. All bank registers consist of 8 bits. PCB is initialized to FFH by a reset. Other bank registers are initialized to 00H by a reset. The bank registers other than PCB permit reading and writing. The PCB permits reading but not writing. The PCB is written to on the execution of branch instructions (JMPP, CALLP, RETP, and RETI) that operate in the total (16-MByte) memory space, on execution of a software interrupt instruction, and when exceptions or hardware interrupts occur. See Section 2.1.1 "Memory Space" for details on the operation of each register. 35 s General purpose registers The general purpose registers of the F2MC-16L F2MC-16L are located in RAM at 000180H 000180H to 00037FH 00037FH in the memory map. The register bank pointer (RP) specifies the section of memory that is currently used as the register bank. Each bank contains the following three register types. The registers are not independent. Figure 2.1.18 shows the relationship between the registers. MSB · R0 to 7 · RW0 to 7 : 16-bit general purpose registers LSB 16 bits : 8-bit general purpose registers Upper R7 R6 RW7 R5 R4 RW6 R3 R2 RW5 R1 R0 RW4 · RL0 to 3 : 32-bit general purpose registers RW3 RW2 RW1 Lower RW0 000180H 000180H + RP * 10H RL3 RL2 RL1 RL0 Top address of the general purpose registers Figure 2.1.18 General Purpose Registers s Register bank The register bank consists of eight 16 to bit registers: byte registers R0 to 7, word registers RW0 to 7, and long word registers RL0 to 3. The registers can be used as general purpose registers in various operations and as pointers in various instructions. RL0 to 3 can also be used as linear pointers to directly access the entire memory space. Table 2.1.5 lists the function of each register. As for standard RAM, the register contents are not initialized by a reset and the registers maintain the values that they had prior to the reset. However, the register contents are undefined at power on. Table 2.1.5: Register Functions Used as instruction operands. R0 to R7 Note: R0 is also used as the barrel shift counter and normalize instruction counter. Used as pointers. RW0 to RW7 Used as instruction operands. Note: RW0 is also used as the string instruction counter. Used as long pointers. RL0 to RL3 Used as instruction operands. 36 2.1.3 Prefix Codes By placing a prefix code in front of an instruction, part of the operation of the instruction can be modified. Three types of prefix codes are available: bank select prefixes, common register bank prefixes, and flag change inhibit prefixes. s Bank select prefix The memory space used for data access is determined by the addressing mode. Placing a bank select prefix in front of an instruction selects a specific memory space for data access by the instruction, irrespective of the addressing mode. Table 2.1.6 lists the memory space selected by each bank select prefix. Table 2.1.6: Bank Select Prefix Bank Select Prefix Memory Space PCB PC space DTB Data space ADB AD space SPB If the S flag in CCR is "0", selects the user stack space. If the S flag is "1", selects the system stack space. However, note that the instructions listed in Table 2.1.7 ignore the bank select prefix. Also, for the instructions listed in Table 2.1.8, the effect of the bank select prefix is passed on to the next instruction. Table 2.1.7: Instructions that Ignore the Bank Select Prefix Instruction Instruction Type Effect of the Bank Select Prefix String instructions MOVS SCEQ FILS MOVSW SCWEQ FILSW Uses the bank register specified in the operand, whether or not a prefix is present. Stack manipulation instructions PUSHW POPW Uses USB (if the S flag = 0) or SSB (if the S flag = 1), whether or not a prefix is present. I/O access instructions MOV MOVW MOV MOV MOVB SETB BBC WBTC Interrupt return instruction RETI A,io A,io io,A io,#imm8 A,io:bp io:bp io:bp, rel io:bp MOVX A,io MOVW MOVW MOVB CLRB BBS WBTS io,A io,#imm16 io:bp,A io:bp io:bp,rel io:bp Accesses the memory space 000000H 000000H to 0000FFH 0000FFH, whether or not a prefix is present. Uses SSB, whether or not a prefix is present. 37 Table 2.1.8: Instructions for Which the Effect of the Bank Select Prefix is Passed on to the Next Instruction Instruction Type Instruction Flag modify instructions AND CCR,#imm8 PS restore instruction POPW PS ILM set instruction MOV OR CCR,#imm8 ILM,#imm8 s When multiple prefix codes are specified When multiple conflicting prefix codes are specified, the final code specified is used. Prefix code ADB · · · · · DTB PCB ADD A,01H · · · · · The PCB prefix code is used. Figure 2.1.19: Multiple Prefix Codes s Common register bank prefix (CMR) To simplify data exchange between tasks, a predetermined common register bank is required that can be accessed by a comparatively simple procedure unaffected by the value of RP at the time. Placing CMR in front of an instruction that accesses a register bank changes the accessed register bank to the common bank located at 000180H 000180H to 00018FH 00018FH (the bank selected when RP = 0), irrespective of the current value of RP. However, care is required with the instructions listed in Table 2.1.9. Table 2.1.9: Instructions Requiring Care When Using the Common Register Bank Prefix Instruction Type Instruction Explanation String instructions MOVS SCEQ FILS Flag modify instructions AND PS restore instruction POPW PS The effect of the prefix is passed on to the next instruction. ILM set instruction MOV The effect of the prefix is passed on to the next instruction. 38 MOVSW SCWEQ FILSW CCR,#imm8 ILM,#imm8 Do not use the CMR prefix with string instructions. OR The effect of the prefix is passed on to the next instruction. CCR,#imm8 s Flag change inhibit prefix Use the flag change inhibit prefix code (NCC) to inhibit unwanted changes to the flags. Placing NCC in front of an instruction prevents instruction execution from changing the flags. The prefix inhibits changes to the T, N, Z, V, and C flags. However, care is required with the instructions listed in Table 2.1.10. Table 2.1.10: Instructions Requiring Care When Using the Flag Change Inhibit Prefix Instruction Type Explanation Instruction String instructions MOVS SCEQ FILS MOVSW SCWEQ FILSW Do not use the NCC prefix with string instructions. Flag modify instructions AND CCR,#imm8 OR The instruction changes CCR as specified, whether or not a prefix is present. The effect of the prefix is passed on to the next instruction. PS restore instruction POPW PS The instruction changes CCR as specified, whether or not a prefix is present. The effect of the prefix is passed on to the next instruction. ILM set instruction MOV ILM,#imm8 The effect of the prefix is passed on to the next instruction. Interrupt instructions Interrupt return instructions INT INT RETI #vct8 addr16 Context switch instruction JCTX @A INT9 ENTP CCR,#imm8 addr24 The instruction changes CCR as specified, whether or not a prefix is present. The instruction changes CCR as specified, whether or not a prefix is present. s Interrupt inhibiting instructions The ten types of instruction listed in Table 2.1.11 ignore interrupt requests, whether or not a hardware interrupt request is detected. Table 2.1.11: Hardware Interrupt Inhibiting Instructions MOV AND OR POPW ILM,#imm8 CCR,#imm8 CCR,#imm8 PS PCB ADB NCC DTB SPB CMR Therefore, if a valid hardware interrupt request occurs during execution of one of these instructions, interrupt processing does not start until after the execution of the next instruction of a type other than those listed above. Figure 2.1.20 shows an example. 39 Interrupt inhibiting instructions · · · · · · · · · · · · · (a) (a) Normal instructions Interrupt request occurs Interrupt received Figure 2.1.20 Interrupt Inhibiting Instructions s Restrictions for interrupt inhibiting instructions and prefix instructions If a prefix code is placed in front of an interrupt inhibiting instruction, the effect of the prefix code is passed on to the next instruction that is not an interrupt inhibiting instruction. Figure 2.1.21 shows an example. Interrupt inhibiting instructions MOV A,FFH NCC MOV ILM,#imm8 ···· ADD A,01H CCR: XXX10XX XXX10XX CCR: XXX10XX XXX10XX CCR is not modified due to the NCC prefix. Figure 2.1.21 Interrupt Inhibiting Instructions and Prefix Codes 40 2.1.4 Interrupts, Extended Intelligent I/O Service, and Exceptions The F2MC-16L F2MC-16L has functions that halt the currently executing processing and pass control to another defined program when an event or similar occurs. The functions can be divided into the following four types. · Hardware interrupt: Interrupt processing triggered by an event occurring in an internal resource circuit. · Software interrupt: Interrupt processing triggered by a software event instruction. · Data transfer processing triggered by an Extended intelligent I/O service (EI2OS): event occurring in an internal resource circuit. · Exception: Interrupt processing triggered by an exception. s Hardware interrupt (1) Outline The hardware interrupt function temporarily interrupts the program currently executing in the CPU in response to an interrupt request signal from an internal resource circuit, then transfers control to a user-defined interrupt handling program. To activate a hardware interrupt, the hardware compares the interrupt level of the interrupt request with the interrupt level mask register (ILM) in the PS register of the CPU and checks the value of the I flag in the PS register. The hardware interrupt activates if the conditions are valid. The CPU performs the following processing when a hardware interrupt occurs. · · The current interrupt level is stored in ILM in the PS register. · (2) The A, DPR, ADB, DTB, PCB, PC, and PS registers in the CPU are saved on the system stack. Execution branches to the corresponding interrupt vector. Configuration The mechanisms relating to hardware interrupts can be divided into the following three groups. · Internal resource circuits Interrupt enable bit and interrupt request bit: interrupt requests from internal resources. Controls · Interrupt controller ICR: Assigns interrupt levels and prioritizes simultaneous interrupts. · CPU I, ILM: Compares the level of the interrupt request with the current level. Identifies the interrupt enable status. Microcode: Executes the interrupt processing steps. Each mechanism is represented by the content of its respective registers: internal resource control registers for internal resource circuits, the ICR for the interrupt controller, and the CCR for the CPU. When using hardware interrupts, the program must first set values to these three register types. See "Interrupt Control Register (ICR)" in the "Extended Intelligent I/O Service" section for details on the ICR. The interrupt vector table referenced during interrupt processing is located in the memory area FFFC00H FFFC00H to FFFFFFH. The area is shared with software interrupts. Table 2.1.12 lists the allocation of interrupt numbers and interrupt vectors. 41 Table 2.1.12: Allocation of Interrupt Numbers and Interrupt Vectors Software Interrupt Instruction Vector Address M Vector Address H Mode Register FFFFFCH INT 0 Vector Address L FFFFFDH FFFFFEH Unused Interrupt Number #0 Hardware Interrupt None . . . . . . . INT 7 FFFFE0H FFFFE1H FFFFE2H Unused #7 None INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDF #8 (Reset vector) INT 9 FFFFD8H FFFFD9H FFFFDAH Unused #9 None INT 10 FFFFD4H FFFFD5H FFFFD6H Unused #10 INT 11 FFFFD0H FFFFD1H FFFFD2H Unused #11 Hardware interrupt #0 INT 12 FFFFCCH FFFFCDH FFFFCEH Unused #12 Hardware interrupt #1 INT 13 FFFFC8H FFFFC9H FFFFCAH Unused #13 Hardware interrupt #2 INT 14 FFFFC4H FFFFC5H FFFFC6H Unused #14 Hardware interrupt #3 . . . . . . . INT 254 FFFC04H FFFC04H FFFC05H FFFC05H FFFC06H FFFC06H Unused #254 Free INT 255 FFFC00H FFFC00H FFFC01H FFFC01H FFFC02H FFFC02H Unused #255 (3) Operation Internal resource circuit with a hardware interrupt function has an "interrupt request flag" that indicates whether an interrupt request is present and an "interrupt enable flag" for the CPU to select whether the resource circuit is to generate interrupt requests. The interrupt request flag is set by specific events in the internal resource circuit. If the interrupt enable flag is set to "enabled", the internal resource circuit passes the interrupt request to the interrupt controller. The interrupt controller compares the interrupt levels (IL) in the ICR for each simultaneously occurring interrupt request, selects the request with the highest level (the lowest IL value), and notifies the CPU. If more than one request occurs with the same level, the request with the lowest interrupt number has priority. See Section 2.2.3 "Interrupt Vector Allocation" for details on the relationship between each interrupt request and ICR. The CPU compares the received interrupt level with ILM in the PS register. If the interrupt level (IL) is less than ILM and the I flag in the PS register is "1", the CPU activates the interrupt processing microcode after completing execution of the current instruction. The head of interrupt processing microcode checks that the ISE bit in the ICR in the interrupt controller is set to "0" (indicating an interrupt), then activates the main body of interrupt processing. After saving the A, DPR, ADB, DTB, PCB, PC, and PS registers (12 bytes) to the memory area specified by SSB and SSP, interrupt processing reads the 3-byte interrupt vector and loads the vector to PC and PCB, changes ILM in the PS register to the level of the received interrupt request, sets the S flag to "1", then executes branch processing. As a result, the next executed instruction is the user-defined interrupt processing program. 42 Figure 2.1.22 shows the flow of processing from the generation of a hardware interrupt until the interrupt request is completed by the interrupt processing program. Figure 2.1.23 shows the operation flow for a hardware interrupt. PS, PC · · · · PS I ILM F2MC-16 F2MC-16 bus Microcode IR Check Comparator F2MC-16L F2MC-16L · CPU PS I ILM IR : : : : Processor status Interrupt enable flag Interrupt level mask register Instruction register AND Cause FF Internal peripheral Interrupt level IL Enable FF Level comparator . Internal resource Interrupt controller RAM Figure 2.1.22 A Hardware Interrupt from Generation to Release . A cause of interrupt generated in the internal resource. . If interrupts are enabled in the internal resource by the interrupt enable bit, the interrupt request is passed from the resource to the interrupt controller. . The interrupt controller receives the interrupt request, evaluates the priorities of any simultaneous interrupt requests, then passes the interrupt level of the highest priority interrupt to the CPU. . The CPU compares the level of the interrupt request from the interrupt controller with IL bit in the processor status register. . If the result of comparison is that the priority is higher than for the current interrupt processing level, the CPU then checks the I flag in the processor status register. . If checking the I flag in indicates that interrupts are enabled, the CPU waits until the current instruction completes executing, then sets the request level in ILM. . The CPU saves the registers, then passes control by branching to the interrupt processing routine. . The interrupt request completes when the user's interrupt processing routine software clears the interrupt request generated in . 43 I ILM IY IE : : : : ISE : IL : S : I & IY & IE = 1 AND ILM > IL Flag in CCR Interrupt level mask register in CPU Internal resource interrupt request Interrupt enable flag for the internal resource EI2OS enable flag Interrupt request level in the internal resource Flag in the CCR YES NO YES NO ISE = 1? Next instruction load and decode Hardware interrupt Extended intelligent I/O service processing Save PS, PC, PCB, DTB, ADB, DPR, and A to the SSP stack. Then set ILM = IL. INT instruction? YES Software interrupt NO Save PS, PC, PCB, DTB, ADB, DPR, and A to the SSP stack. Then set I = "0". Normal instruction execution NO String instruction iteration complete? S1 Load interrupt vector. Update PCB and PC. YES Update PC Figure 2.1.23 Interrupt Operation Flow 44 (4) Example procedure for using hardware interrupts Start Set system stack area Initialize internal resource Set ICR in interrupt controller Start internal resource operation Set the interrupt enable bit to "enabled" Set ILM and I in the PS register Interrupt processing program Stack processing Branch to interrupt vector Hardware processing Process the interrupt into the internal resource Clear the interrupt cause Interrupt return instruction (RETI) Interrupt request generated Figure 2.1.24 Example Procedure for Using Hardware Interrupts . Set the system stack area. . Initialize the internal resource that can generate interrupt requests. . Set ICR in the interrupt controller. . Set the internal resource to the operating state and set the interrupt enable bit to "enabled". . Set the ILM and I flag in the CPU to enable the reception of interrupts. . Generation of an interrupt in the internal resource triggers a hardware interrupt request. . The interrupt processing hardware saves the registers and branches to the interrupt processing program. . The interrupt processing program handles the internal resource that generated the interrupt. . Release the interrupt request from the internal resource circuit. . Execute the interrupt return instruction and return to the previous program. 45 (5) Hardware interrupt requests during a write to an internal resource area Hardware interrupt requests cannot be received during a write to an internal resource area. This is to prevent misoperation of CPU interrupt processing due to an interrupt request occurring during an update of the interrupt control register in an internal resource. The internal resource area refers to the area allocated for control and data registers for internal resources (not the I/O addressing area between 000000H 000000H and 0000FFH 0000FFH). Write instruction for an internal resource area · · MOV A,#08 MOV io,A Interrupt request generated here. MOV A,2000H 2000H Does not branch to the interrupt. Interrupt processing Branches to the interrupt. Figure 2.1.25 Hardware Interrupt Request during a Write to an Internal Resource Area (6) Interrupt inhibiting instructions Some F2MC-16L F2MC-16L instructions do not detect hardware interrupt requests. These are called interrupt inhibiting instructions. See Table 2.1.11 for details. (7) Multiple interrupts The F2MC-16L F2MC-16L CPU supports multiple interrupts. If, during the processing of an interrupt, a second interrupt with a higher priority level occurs, control passes to the second interrupt on completion of the currently executing instruction. Control returns to the original interrupt processing when the higher priority interrupt completes. If an interrupt of the same or lower priority occurs during interrupt processing, the new interrupt request is held until the current interrupt completes processing (unless the content of ILM or I flag has been modified by an instruction). The extended intelligent I/O service does not support overlapping operation. Any interrupt request or extended intelligent I/O service request that occurs during processing of the extended intelligent I/O service is held. 46 (8) Saved registers Figure 2.1.26 shows the order of the registers saved on the stack. Register save by an interrupt Word (16 bits) MSB LSB H SSP (Value of SSP before the interrupt) A H A L DPR ADB DTB PCB P C P S SSP (Value of SSP after the interrupt) L Figure 2.1.26 Registers Saved on the Stack (9) Cautions Reading the control or data registers of some internal resources clears interrupt requests. Clearing an interrupt request by performing a read after generation of an interrupt request but before control has passed to the interrupt processing hardware causes misoperation. Therefore, when using internal resources for which interrupt requests are cleared by register read operations, do not perform register read operations when interrupts are generated. 47 s Software interrupts (1) Overview The software interrupt function transfers control from the program currently executing in the CPU to a user-defined interrupt processing program on execution of a special instruction. Software interrupts are always activated by the execution of the software interrupt instruction. The CPU performs the following processing when a software interrupt occurs. · The A, DPR, ADB, DTB, PCB, PC, and PS registers in the CPU are saved on the system stack. · The I flag in the PS register is set to "0" to inhibit hardware interrupts. · Execution branches to the corresponding interrupt vector. Interrupt requests initiated by the software interrupt instruction (INT) do not have an interrupt request flag or interrupt enable flag. Executing the INT instruction always generates an interrupt request. The INT instruction does not have interrupt levels. Accordingly, the INT instruction does not modify ILM. Instead the INT instruction sets the I flag to "0" to hold any subsequent interrupt requests. (2) Configuration All software interrupt mechanisms exist within the CPU. The software interrupt instruction must be executed to use a software interrupt. As shown in Table 2.1.12, software and hardware interrupt vectors share the same area. For example, interrupt request number INT 11 is used by both hardware interrupt #0 and software interrupt INT #11. Therefore, hardware interrupt #0 and INT #11 call the same interrupt processing routine. (3) Operation On executing the software interrupt instruction, the CPU activates the software interrupt processing microcode. After saving the A, DPR, ADB, DTB, PCB, PC, and PS registers (12 bytes) to the memory area specified by SSB and SSP, the software interrupt processing microcode reads the 3-byte interrupt vector and loads the vector to PC and PCB, sets the I flag to "0" and the S flag to "1", then executes branch processing. As a result, the next executed instruction is the user-defined interrupt processing program. Figure 2.1.27 shows the flow of processing from the generation of a software interrupt until the interrupt request is completed by the interrupt processing program. 48 PS F2MC-16 F2MC-16 bus PS, PC · · · I S Microcode IR Queue Fetch PS I ILM IR : : : : Processor status Interrupt enable flag Interrupt level mask register Instruction register F2MC-16L F2MC-16L · CPU Save RAM Figure 2.1.27 A Software Interrupt from Generation to Release . A software interrupt instruction is executed. . The microcode for the software interrupt instruction saves the special registers. . Interrupt processing completes on execution of the RETI instruction in the user interrupt processing routine. (4) Cautions When the program bank register (PCB) is FFH, the vector area for the CALLV instruction overlaps the table for the INT #vct8 instruction. Take note of the address overlap of the CALLV and INT #vct8 instructions when developing software. 49 s Extended intelligent I/O service (EI2OS) The EI2OS function automatically transfers data between I/O and memory. The function provides DMA-style I/O data handling and replaces the conventional I/O data handling by interrupt processing programs. The function has the following advantages over the conventional interrupt processing. · No data transfer program is required. This reduces total program size. · Data transfer does not use internal registers. This increases transfer speed because register saving is not required. · The I/O can stop data transfer as required. This eliminates unnecessary data transfer. · Incrementing or no-change of the buffer address can be selected. · Incrementing or no-change of the I/O register address can be selected. On completion, EI2OS sets the completion conditions then automatically branches to an interrupt processing routine. This allows the user to determine the completion conditions. To implement EI2OS, hardware is distributed between two locations. Each block has the following registers and descriptors. · Interrupt control register: Located in the interrupt controller. Specifies the ISD address. · Extended intelligent I/O service descriptor (ISD): Located in RAM. Holds the transfer mode, I/O address and transfer count, and buffer address. Figure 2.1.28 shows an overview of the extended intelligent I/O service. Memory space by IOA I/O register . Peripheral I/O register Interrupt request CPU ISD by ICS Interrupt control register Interrupt controller The I/O requests a transfer. by BAP The interrupt controller selects the descriptor. Reads the transfer source and destination from the descriptor. Buffer by DCT Executes transfer between I/O and memory. Automatically clears the cause of interrupt. Figure 2.1.28 Overview of the Extended Intelligent I/O Service Note:The area that can be specified by IOA is 000000H 000000H to 00FFFFH 00FFFFH. The area that can be specified by BAP is 000000H 000000H to FFFFFFH. The maximum transfer count that can be specified by DCT is 65536. 50 s Interrupt control registers (ICR00 ICR00 to 15) The interrupt control registers are located in the interrupt controller and are provided for each I/ O that has an interrupt function. See Section 2.2.3 "Interrupt Vector Allocation" for details on the relationship between interrupts and ICRs. The registers perform the following three functions. · Sets the interrupt level for the corresponding internal resource. · Selects whether the corresponding internal resource uses a standard interrupt or the extended intelligent I/O service. · Selects the extended intelligent I/O service channel. Do not access these registers using read-modify-write instructions as this causes malfunction. Figure 2.1.29 shows the bit structure of the interrupt control registers. 7 6 5 4 3 2 1 0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 W W W W W W W W 7 6 5 4 3 2 1 0 - - S1 S0 ISE IL2 IL1 IL0 - - R R R R R When writing to an interrupt control register (ICR) Set to 00000111B 00000111B by a reset. R When reading from an interrupt control register (ICR) Set to XX000111B XX000111B by a reset. Note:ICS3 to 0 are only meaningful when EI2OS is active. Set ISE to "1" when EI2OS is active and set ISE to "0" when EI2OS is inactive. Any values can be set to ICS3 to 0 if EI2OS is inactive. Figure 2.1.29 Interrupt Control Registers (ICR) 51 [Bits 2 to 0] IL0, IL1, IL2: Interrupt level setting bits The interrupt level setting bits specify the interrupt level of the corresponding internal resource. The bits are readable and writable. The bits are initialized to level 7 (no interrupt) by a reset. Table 2.1.13 lists the relationship between the interrupt level setting bits and each interrupt level. Table 2.1.13: Correspondence Between Interrupt Level Setting Bits and Interrupt Levels IL2 IL1 IL0 Level Value 0 0 0 0 (Highest interrupt level) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (Lowest interrupt level) 1 1 1 7 (No interrupt) [Bit 3] ISE: Extended intelligent I/O service enable bit The EI2OS enable bit. The bit is readable and writable. The processor activates EI2OS if ISE is "1" when an interrupt occurs. If the ISE bit is "0", the processor activates the interrupt sequence. The ISE bit changes to "0" when EI2OS completes (count completion or completion by the internal resource). If the internal resource does not have an EI2OS function, set the ISE bit to "0" by software. The ISE bit is initialized to "0" by a reset. 52 [Bits 7 to 4] ICS3 to 0: Extended intelligent I/O service channel select bits The EI2OS channel select bits. The EI2OS channel select bits specify the EI2OS channel. The bits are write-only. The value set in ICS determines the address of the extended intelligent I/O service descriptor (ISD). ICS is initialized to "0000" by a reset. Table 2.1.14 lists the correspondence between ICS, the channel number, and the descriptor address. Table 2.1.14: Correspondence Between ICS, Channel Number, and Descriptor Address ICS3 ICS2 ICS1 ICS0 Channel to select Descriptor Address 0 0 0 0 0 000100H 000100H 0 0 0 1 1 000108H 000108H 0 0 1 0 2 000110H 000110H 0 0 1 1 3 000118H 000118H 0 1 0 0 4 000120H 000120H 0 1 0 1 5 000128H 000128H 0 1 1 0 6 000130H 000130H 0 1 1 1 7 000138H 000138H 1 0 0 0 8 000140H 000140H 1 0 0 1 9 000148H 000148H 1 0 1 0 10 000150H 000150H 1 0 1 1 11 000158H 000158H 1 1 0 0 12 000160H 000160H 1 1 0 1 13 000168H 000168H 1 1 1 0 14 000170H 000170H 1 1 1 1 15 000178H 000178H 53 [Bits 5, 4] S1, S0: Extended intelligent I/O service status The EI2OS status bit. The bits are read-only. The extended intelligent I/O service status bits can be referenced to determine the operation status and completion status of EI2OS. The bits are initialized to "00" by a reset. Table 2.1.15 lists the relationship between the S bits and EI2OS status. Table 2.1.15: S Bits and EI2OS Status EI2OS Status S1 S0 0 0 EI2OS active or inactive 0 1 Stopped due to count completion 1 0 Reserved 1 1 Stopped by request from the internal resource u Extended intelligent I/O service descriptor (ISD) The extended intelligent I/O service descriptors are located in internal RAM between 000100 H and 00017FH 00017FH. ISD consist of the following items. · Various control data for data transfer · Status data · Buffer address pointer Figure 2.1.30 shows the structure of the extended intelligent I/O service descriptor. Data counter (upper 8 bits) (DCTH) Data counter (lower 8 bits) (DCTL) I/O address pointer (upper 8 bits) (IOAH) I/O address pointer (lower 8 bits) (IOAL) 2 EI OS status (ISCS) Buffer address pointer (upper 8 bits) (BAPH) 000100H 000100H + 8 × ICS Buffer address pointer (middle 8 bits) (BAPM) ISD top address Buffer address pointer (lower 8 bits) (BAPL) Figure 2.1.30 Structure of the Extended Intelligent I/O Service Descriptor 54 H L r Data counter (DCT) A 16-bit register used as a counter for the number of data transferred. The counter is decremented by one before each data transfer. EI2OS completes when this counter reaches zero. Figure 2.1.31 shows the structure of the data counter. 15 14 13 12 11 10 9 8 7 6 5 DCTH 4 3 2 1 0 : DCT (undefined after a reset) DCTL Figure 2.1.31 Data Counter Structure r I/O register address pointer (IOA) A 16-bit register that indicates the lower 16 bits (A15 to A0) of the address of the I/O register for data transfer to or from the buffer. The upper address (A23 to A16) is all zeros. I/O can be specified anywhere between locations 000000H 000000H and 00FFFFH 00FFFFH. Figure 2.1.32 shows the structure of IOA. 15 14 13 12 IOAH 11 10 9 8 7 6 5 4 IOAL 3 2 1 0 : IOA (undefined after a reset) Figure 2.1.32 Structure of the I/O Register Address Pointer 55 r EI2OS status register (ISCS) An 8-bit register that specifies whether the buffer address pointer and I/O register address pointer are updated or fixed, the transfer data length (byte or word), and the transfer direction. Figure 2.1.33 shows the structure of ISCS. 7 6 5 Reserved Reserved Reserved 4 3 2 1 0 IF BW BF DIR SE : ISCS (undefined after a reset) Figure 2.1.33 ISCS Structure The meaning of each bit is as follows. [Bit 4] IF: Specifies whether the I/O register address pointer is updated or fixed. 0: Update the I/O register address pointer after data transfer. 1: Do not update the I/O register address pointer after data transfer. Note: Only incrementing is available. [Bit 3] BW: Specifies the data transfer length 0: Byte 1: Word [Bit 2] BF: Specifies whether the buffer address pointer is updated or fixed. 0: Update the buffer pointer after data transfer. 1: Do not update the buffer address pointer after data transfer. Note: Updating changes only the lower 16 bits of the buffer address pointer. Only incrementing is available. [Bit 1] DIR: Specifies the data transfer direction. 0: I/O address pointer Buffer address pointer 1: Buffer address pointer I/O address pointer [Bit 0] SE: Controls completion of the extended intelligent I/O service by request from the internal resource. 0: Do not terminate on request from the internal resource. 1: Terminate on request from the internal resource. 56 u Buffer address pointer (BAP) A 24-bit register that stores the address to use for the next EI2OS transfer. As an independent BAP is provided for each EI2OS channel, each EI2OS channel can perform data transfer to any location in the 16-Mbyte memory space. If updating is specified by the BF bit in ISCS, only the lower 16 bits of BAP are updated and BAPH does not change. Figure 2.1.34 shows the structure of BAP. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 BAPH BAPM (R/W) 1 BAPL (R/W) 2 0 :BAP (undefined after a reset) (R/W) Figure 2.1.34 Structure of the Buffer Address Pointer Figure 2.1.35 shows the operation flow of EI2OS. Figure 2.1.36 shows the procedure for using EI2OS. 57 BAP I/OA ISD ISCS DCT ISE S1, S0 Interrupt request generated by internal resource : : : : : : : Buffer address pointer I/O address pointer EI2OS descriptor EI2OS status Data counter EI2OS enable bit EI2OS completion status NO ISE=1? YES Interrupt sequence I S D / I S CS read YES Completion request from resource? NO SE=1? YES DIR=1? NO Data indicated by IOA (Data transfer) Memory indicated by BAP IF=0? Data indicated by BAP (Data transfer) Memory indicated by IOA YES NO Update value is determined by BW. Update IOA. YES BF=0? NO Update value is determined by BW. Decrement DCT. Update BAP. (-1) YES DCT=00? NO Set "01" to S1 and S0 Set "11" to S1 and S0 Set "00" to S1 and S0 Clear resource interrupt request Return to CPU operation Clear ISE to "0" Interrupt sequence Figure 2.1.35 EI2OS Operation Flow 58 Software processing Hardware processing Start Initialization Set system stack area Set EI2OS descriptor Initialize internal resource Set ICR in the interrupt controller Start internal resource operation Set the interrupt enable bit Set ILM and I in the PS register S1, S0= `00' Execute user program (Interrupt request) and (ISE=1) Data transfer No Determine whether to branch to interrupt depending on count-out or completion request from resource (Branch to interrupt vector) Reset the extended intelligent I/O service (Switch channels, etc.) Yes S1, S0= `01' or S1, S0= `11' Process data in buffer RETI Figure 2.1.36 Procedure for Using EI2OS 59 s Exception processing The F2MC-16L F2MC-16L generates exceptions in the following cases and performs exception processing. (1) Execution of an undefined instruction In princip