CM43-10106-1E F2MC-16L 16-BIT MB90610A F2MC-16 SQFP-100 QFP-100 MB90611A - Datasheet Archive

 

CONTROLLER MANUAL CM43-10106-1E F2MC-16L 16-BIT MICROCONTROLLER MB90610A SERIES HARDWARE MANUAL Preface Thank you for purchasing

 

FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM43-10106-1E CM43-10106-1E F2MC-16L F2MC-16L 16-BIT 16-BIT MICROCONTROLLER MB90610A MB90610A SERIES HARDWARE MANUAL Preface Thank you for purchasing a Fujitsu semiconductor product. The MB90610A MB90610A series has been developed as a general-purpose product in the F2MC-16L F2MC-16L series. The F2MC-16L F2MC-16L series are proprietary 16-bit single-chip microcontrollers that can be used as application specific ICs (ASICs). This manual describes the functions and operation of the MB90610A MB90610A series and is aimed at engineers who are using the chip to develop products. For details on the instruction set, see the "F2MC-16L F2MC-16L Programming Manual". *: F2MC stands for Fujitsu Flexible Microcontroller. This manual is organized as follows. Chapter 1 General Describes the MB90610A MB90610A series features, product range, block diagram, pin assignment, and notes on device operation. Chapter 2 Hardware Describes the internal structure of the F2MC-16L F2MC-16L series CPU and the internal hardware specifications of the MB90610A MB90610A series. Chapter 3 Operation Describes the clock generator, reset, interrupts, memory access modes, low power modes, and other features of the MB90610A MB90610A series. Chapter 4 Instructions Summarizes the F2MC-16L F2MC-16L series instruction set. 1. The products described in this manual and the specifications thereof may be changed without prior notice. To obtain up-to-date information and/or specifications, contact your Fujitsu sales representative or Fujitsu authorized dealer. 2. Fujitsu will not be liable for infringement of copyright, industrial property right, or other rights of a third party caused by the use of information or drawings described in this manual. 3. The contents of this manual may not be transferred or copied without the express permission of Fujitsu. 4. The products contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support. 5. Some of the products described in this manual may be strategic materials (or special technology) as defined by the Foreign Exchange and Foreign Trade Control Law. In such cases, the products or portions thereof must not be exported without permission as defined under the Law. © 1996 FUJITSU LIMITED Printed in Japan CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 General . 1 Features . 1 Product Range . 3 Block Diagram . 4 Pin Assignment . 5 Package Dimensions . 7 Pin Descriptions . 9 Device Operation . 15 CHAPTER 2 Hardware . 17 CPU . 17 Map . 55 Parallel Ports . 63 UART 0/1/2 (SCI) . 69 10-Bit 8-Input A/D Converter (With 8-Bit Resolution Mode) . 86 PPG . 104 16-Bit Reload Timer (With Event Count Function) . 116 Chip Select Function . 127 DTP/External Interrupts . 132 Delay Interrupt Generation Module . 139 Watchdog Timer and Timebase Timer Functions . 141 Low Power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization Delay Time, and Clock Multiplier Function) . 147 2.13 External Bus Pin Control Circuit . 154 2.14 Interrupt Controller . 159 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 CHAPTER 3 3.1 3.2 3.3 3.4 3.5 3.6 CHAPTER 4 4.1 4.2 4.3 Operation . 165 Clock Generator . 165 Resets . 166 Memory Access Modes . 169 External Memory Access . 174 Low Power Modes . 181 Pin States During Sleep, Stop, Hold, and Reset . 188 Instructions . 193 Addressing. 193 Instruction Set . 198 Instruction Map . 218 i 1.1 Features Chapter 1: General The MB90610A MB90610A series are general-purpose, high performance 16-bit microcontrollers designed for applications requiring high speed real-time processing in industry, office equipment, process control, and other fields. The instruction set follows the F2MC-8 series AT architecture with additional high level language instructions, enhanced addressing modes, improved multiplication and division instructions, and bit manipulation instructions. Furthermore, a 32-bit accumulator enables processing of long-word data. The internal peripheral resources consist of a 3-channel serial port incorporating a UART function (and supporting I/O expansion serial mode), 8-channel 10-bit A/D converter, 2-channel PPG, 2-channel 16-bit reload timer, 8-channel chip select output, and eight external interrupts. Also, multiplexed or non-multiplexed operation can be selected for the address/data bus. 1.1 Features (1) Minimum instruction execution time (Standard F2MC-16 F2MC-16 features): 62.5 nS at 16 MHz internal operation Uses PLL clock multiplication (2) Instruction set optimized for controller applications (Standard F2MC-16 F2MC-16 features) · Wide range of data types (bit, byte, word, and long word) · Wide range of addressing modes: 23 modes · High code efficiency · High accuracy operations are enhanced by use of a 32-bit accumulator. (3) Enhanced high level language (C) and multitasking support instructions (Standard F2MC-16 F2MC-16 features) · Use of a system stack pointer · Enhanced pointer indirect instructions · Barrel shift instructions (4) Improved execution speed (Standard F2MC-16 F2MC-16 features): Four byte instruction queue (5) Powerful interrupt function from 24 sources in 8 levels (Standard F2MC-16 F2MC-16 features) (6) Automatic data transfer that is independent of the CPU (Standard F2MC-16 F2MC-16 features) 1 1.1 Features (7) Multiplexed or non-multiplexed operation can be selected for the address/data bus (8) General-purpose ports Non-multiplexed mode: 36 ports max. Multiplexed mode: 52 ports max. (9) UART (SCI): 3ch · For either asynchronous or clocked serial transfer (I/O expansion serial) (10) A/D converter: 8ch (10-bit) · 8-bit conversion mode also available (11) PPG (programmable pulse generator): 2ch (12) 16-bit reload timer: 2ch (13) Chip select output: 8ch (14) External interrupts: 8ch (15) 18-bit timebase timer · Watchdog timer function (16) PLL clock multiplier function (17) CPU intermittent operation function (18) Various standby modes (19) SQFP-100 SQFP-100 or QFP-100 QFP-100 package (20) CMOS technology 2 Chapter 1: General 1.2 Product Range 1.2 Product Range Table 1.2.1 lists the MB90610A MB90610A series product range. Features other than ROM and RAM size are the same for all products. Table 1.2.1 MB90610A MB90610A Series Product Range MB90611A MB90611A MB90V610A MB90V610A ROM size - RAM size 1KB 4KB Other No ROM Evaluation device * At the time of writing this manual, actual product range details are still to be confirmed. The above product range is provisional and does not guarantee the future availability of products. 3 1.3 Block Diagram 1.3 Block Diagram X1 X0 RSTX HSTX MD2 MD1 MD0 SCK2/P95 SCK2/P95 SOT2/P94 SIN2/P93 SIN2/P93 SCK1/P92 SCK1/P92 SOT1/P91 SIN1/P90 SIN1/P90 SCK0/P86 SCK0/P86 SOT0/P85 SIN0/P84 SIN0/P84 AN0-7/P60-67 AN0-7/P60-67 ATGX/INT6/P76 ATGX/INT6/P76 Clock controller Reload timer F2MC-16 F2MC-16 bus UART 10/8-bit A/D converter Chip select outputs External bus interface PPG0/INT4/P74 PPG0/INT4/P74 PPG1/INT5/P75 PPG1/INT5/P75 External interrupts 8-bit PPG CS0 CS1-CS7/ PA1-PA7 A00-07/ A00-07/ P20-27 P20-27 A08-15/ A08-15/ P30-37 P30-37 A16-23/ A16-23/ P40-47 P40-47 RAM INT0-3/ P70-73 P70-73 TIT0/ INT7/P80 INT7/P80 TIT1/P81 TIT1/P81 TOT0/P82 TOT1/P83 F2MC -16L CPU ALE RDX WRLX/P55 WRLX/P55 WRHX/ P54 HRQ/P53 HRQ/P53 HAKX/P52 HAKX/P52 RDY/P51 RDY/P51 CLK/P50 CLK/P50 D00-07/ D00-07/ AD00-07 AD00-07 D08-15/ D08-15/ AD08-15/ AD08-15/ P10-17 P10-17 Fig. 1.3.1 Block Diagram of the MB90610A MB90610A Internal Structure 4 Chapter 1: General 1.4 Pin Assignment 1.4 Pin Assignment 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P21/A01 P21/A01 P20/A00 P20/A00 P17/D15/AD15 P17/D15/AD15 P16/D14/AD14 P16/D14/AD14 P15/D13/AD13 P15/D13/AD13 P14/D12/AD12 P14/D12/AD12 P13/D11/AD11 P13/D11/AD11 P12/D10/AD10 P12/D10/AD10 P11/D09/AD09 P11/D09/AD09 P10/D08/AD08 P10/D08/AD08 D07/AD07 D07/AD07 D06/AD06 D06/AD06 D05/AD05 D05/AD05 D04/AD04 D04/AD04 D03/AD03 D03/AD03 D02/AD02 D02/AD02 D01/AD01 D01/AD01 D00/AD00 D00/AD00 VCC X1 X0 VSS ALE RDX P55/WRLX P55/WRLX 1.4.1 SQFP-100 SQFP-100 Pin Assignment P22/A02 P22/A02 P23/A03 P23/A03 P24/A04 P24/A04 P25/A05 P25/A05 P26/A06 P26/A06 P27/A07 P27/A07 P30/A08 P30/A08 P31/A09 P31/A09 VSS P32/A10 P32/A10 P33/A11 P33/A11 P34/A12 P34/A12 P35/A13 P35/A13 P36/A14 P36/A14 P37/A15 P37/A15 P40/A16 P40/A16 P41/A17 P41/A17 P42/A18 P42/A18 P43/A19 P43/A19 P44/A20 P44/A20 VCC P45/A21 P45/A21 P46/A22 P46/A22 P47/A23 P47/A23 P70/INT0 P70/INT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SQFP-100 SQFP-100 MB90610A MB90610A series (TOP VIEW) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RSTX P54/WRHX P54/WRHX P53/HRQ P53/HRQ P52/HAKX P52/HAKX P51/RDY P51/RDY P50/CLK P50/CLK PA7/CS7 PA6/CS6 PA5/CS5 PA4/CS4 PA3/CS3 PA2/CS2 PA1/CS1 CS0 P95/SCK2 P95/SCK2 P94/SOT2 P94/SOT2 P93/SIN2 P93/SIN2 P92/SCK1 P92/SCK1 P91/SOT1 P91/SOT1 P90/SIN1 P90/SIN1 P86/SCK0 P86/SCK0 P85/SOT0 P85/SOT0 P84/SIN0 P84/SIN0 P83/TOT1 P83/TOT1 P82/TOT0 P82/TOT0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 HSTX MD2 MD1 MD0 P81/TIN1 P81/TIN1 P80/INT7/TIN0 P80/INT7/TIN0 P67/AN7 P67/AN7 P66/AN6 P66/AN6 P65/AN5 P65/AN5 P64/AN4 P64/AN4 VSS P63/AN3 P63/AN3 P62/AN2 P62/AN2 P61/AN1 P61/AN1 P60/AN0 P60/AN0 AVSS AVRAVR+ AVCC P76/INT6/ATGX P76/INT6/ATGX P75/INT5/PPG1 P75/INT5/PPG1 P74/INT4/PPG0 P74/INT4/PPG0 P73/INT3 P73/INT3 P72/INT2 P72/INT2 P71/INT1 P71/INT1 Fig. 1.4.1 SQFP-100 SQFP-100 Pin Assignment 5 1.4 Pin Assignment 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/D15/AD15 P17/D15/AD15 P16/D14/AD14 P16/D14/AD14 P15/D13/AD13 P15/D13/AD13 P14/D12/AD12 P14/D12/AD12 P13/D11/AD11 P13/D11/AD11 P12/D10/AD10 P12/D10/AD10 P11/D09/AD09 P11/D09/AD09 P10/D08/AD08 P10/D08/AD08 D07/AD07 D07/AD07 D06/AD06 D06/AD06 D05/AD05 D05/AD05 D04/AD04 D04/AD04 D03/AD03 D03/AD03 D02/AD02 D02/AD02 D01/AD01 D01/AD01 D00/AD00 D00/AD00 VCC X1 X0 VSS 1.4.2 QFP-100 QFP-100 Pin Assignment P20/A00 P20/A00 P21/A01 P21/A01 P22/A02 P22/A02 P23/A03 P23/A03 P24/A04 P24/A04 P25/A05 P25/A05 P26/A06 P26/A06 P27/A07 P27/A07 P30/A08 P30/A08 P31/A09 P31/A09 VSS P32/A10 P32/A10 P33/A11 P33/A11 P34/A12 P34/A12 P35/A13 P35/A13 P36/A14 P36/A14 P37/A15 P37/A15 P40/A16 P40/A16 P41/A17 P41/A17 P42/A18 P42/A18 P43/A19 P43/A19 P44/A20 P44/A20 VCC P45/A21 P45/A21 P46/A22 P46/A22 P47/A23 P47/A23 P70/INT0 P70/INT0 P71/INT1 P71/INT1 P72/INT2 P72/INT2 P73/INT3 P73/INT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 QFP-100 QFP-100 MB90610A MB90610A series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 MD1 MD0 P81/TIN1 P81/TIN1 P80/INT7/TIN0 P80/INT7/TIN0 P67/AN7 P67/AN7 P66/AN6 P66/AN6 P65/AN5 P65/AN5 P64/AN4 P64/AN4 VSS P63/AN3 P63/AN3 P62/AN2 P62/AN2 P61/AN1 P61/AN1 P60/AN0 P60/AN0 AVSS AVRAVR+ AVCC P76/INT6/ATGX P76/INT6/ATGX P75/INT5/PPG1 P75/INT5/PPG1 P74/INT4/PPG0 P74/INT4/PPG0 Fig. 1.4.2 QFP-100 QFP-100 Pin Assignment 6 Chapter 1: General ALE RDX P55/WRLX P55/WRLX RSTX P54/WRHX P54/WRHX P53/HRQ P53/HRQ P52/HAKX P52/HAKX P51/RDY P51/RDY P50/CLK P50/CLK PA7/CS7 PA6/CS6 PA5/CS5 PA4/CS4 PA3/CS3 PA2/CS2 PA1/CS1 CS0 P95/SCK2 P95/SCK2 P94/SOT2 P94/SOT2 P93/SIN2 P93/SIN2 P92/SCK1 P92/SCK1 P91/SOT1 P91/SOT1 P90/SIN1 P90/SIN1 P86/SCK0 P86/SCK0 P85/SOT0 P85/SOT0 P84/SIN0 P84/SIN0 P83/TOT1 P83/TOT1 P82/TOT0 P82/TOT0 HSTX MD2 1.5 Package Dimensions 1.5 Package Dimensions 1.5.1 SQFP-100 SQFP-100 Package Dimensions Reference FPT-100P- FPT-100P- EIAJ Code: *QFP100-P-1414-1 QFP100-P-1414-1 Plastic SQFP 100-pin Lead pitch 0.50 mm Package width × length 14 × 14 mm Lead shape Gull-wing Sealing Plastic mold (FPT-100P-M05 FPT-100P-M05) Plastic SQFP 100-pin (FPT-100P-M05 FPT-100P-M05) (mounted height) Units: mm (inches) * The above package dimensions are for reference only. Please confirm the actual dimensions separately. Fig. 1.5.1 SQFP-100 SQFP-100 Package Dimensions 7 1.5 Package Dimensions 1.5.2 QFP-100 QFP-100 Package Dimensions Reference FPT-100P- FPT-100P- EIAJ Code: *QFP100-P-1420-4 QFP100-P-1420-4 Plastic QFP 100-pin Lead pitch 0.65 mm Package width × length 14 × 20 mm Lead shape Gull-wing Sealing Plastic mold Length of pin flat section 0.80 mm (FPT-100P-M06 FPT-100P-M06) Plastic QFP 100-pin (FPT-100P-M06 FPT-100P-M06) (mounted height) Units: mm (inches) * The above package dimensions are for reference only. Please confirm the actual dimensions separately. Fig. 1.5.2 QFP-100 QFP-100 Package Dimensions 8 Chapter 1: General 1.6 Pin Descriptions 1.6 Pin Descriptions Table 1.6.1 MB90610A MB90610A Pin Descriptions (1) Pin No. Pin Name Circuit Type 80 81 X0 X1 A (Oscillator) 83 to 90 D00 to D07 QFP SQFP 82 83 85 to 92 AD00 to AD07 K (TTL) 91 to 98 D08 to D15 K (TTL) 99 100 1 to 6 P20 to P27 9 10 12 to 17 7 8 10 to 15 P30 to P37 18 to 22 24 to 26 16 to 20 22 to 24 27 to 30 25 to 28 A00 to A07 A08 to A15 B (CMOS) B (CMOS) B (CMOS) 29 30 INT4 to INT5 General-purpose I/O ports. This applies in multiplexed mode. In non-multiplexed mode, the output pins for the lower 8 bits of the external address bus. In non-multiplexed mode, the output pins for the upper 8 bits of the external address bus. The output pins for A16 to 23 of the external address bus. This applies when the upper address control register specifies address operation. General-purpose I/O ports. This applies in all cases. H (CMOS/H) External interrupt request input pins. As the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless doneintentionally. General-purpose I/O ports. This applies when the waveform outputs for PPG timers 0 and 1 are disabled. P74 to P75 31 32 In non-multiplexed mode, the I/O pins for the upper 8 bits of the external data bus. This applies when using a 16-bit external data bus. General-purpose I/O ports. This applies when the upper address control register specifies port operation. P70 to P73 INT0 to INT3 In multiplexed mode, the I/O pins for the lower 8 bits of the external address/data bus. General-purpose I/O ports. This applies in multiplexed mode. P40 to P47 A16 to A23 In non-multiplex mode, the I/O pins for the lower 8 bits ofthe external data bus. In multiplexed mode, the I/O pins for the upper 8 bits of the external address/data bus. AD08 to AD15 1 to 8 Crystal oscillator pins General-purpose I/O ports. This applies in non-multiplexed mode with an 8-bit external data bus. P10 to P17 93 to 100 Function H (CMOS/H) External interrupt request input pins. As the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless doneintentionally. Output pins for PPG timers 0 and 1. This applies when the waveform outputs for PPG timers 0 and 1 are enabled. PPG0 to PPG1 P76 INT6 33 General-purpose I/O port. This applies in all cases. External interrupt request input pin. As the input operatescontinuously when the external interrupt is enabled, outputto the pin from other functions must be stopped unless doneintentionally. 31 H (CMOS/H) Trigger input pin for the A/D converter. As the input operates continuously when the A/D converter inputs are operating, output to the pin from other functions must be stopped unless done intentionally. ATGX 34 32 AVCC Power supply Power supply for the analog circuits. Do not switch this power supply on or off unless a voltage greater than AVCC is applied to VCC. 35 33 AVR+ Power supply Analog circuit reference voltage input. Do not switch the voltage to this pin on or off unless a voltage greater than AVR+ is applied to AVCC. 36 34 AVR- Power supply Analog circuit reference voltage input 37 35 AVSS Power supply Ground level for the analog circuits 9 1.6 Pin Descriptions Table 1.6.1 MB90610A MB90610A Pin Descriptions (2) Pin No. QFP SQFP 38 to 41 43 to 46 36 to 39 41 to 44 Pin Name Circuit Type Open-drain output ports. This applies when port operation is specified in the analog input enable register. P60 to P67 AN0 to AN7 C (AD) P80 INT7 47 45 H (CMOS/H) General-purpose I/O port. This applies in all cases. D (CMOS/H) 48 46 49 to 51 47 to 49 MD0 to MD2 E (CMOS) 52 50 HSTX F (CMOS/H) 53 54 51 52 TOT0 to TOT1 D (CMOS/H) P84 55 53 SIN0 P85 56 54 SOT0 55 SCK0 D (CMOS/H) 56 SIN1 P91 59 57 SOT1 10 58 SCK1 Chapter 1: General Hardware standby input pin General-purpose I/O ports. This applies when output is disabled for reload timers 0 and 1. Output pins for reload timers 0 and 1. This applies when output is enabled for reload timers 0 and 1. Serial data input pin for UART0. As the input operates continuously when UART0 is set to input operation, output to thepin from other functions must be stopped unless done intentionally. General-purpose I/O port. This applies when serial data output is disabled for UART0. Serial data output pin for UART0. This applies when serial data output is enabled for UART0. Clock I/O pin for UART0. This applies when the UART0 clock output is enabled. As the input operates continuously when UART0 is set to input operation, output to the pin from otherfunctions must be stopped unless done intentionally. General-purpose I/O port. This applies in all cases. D (CMOS/H) D (CMOS/H) P92 60 Input pins for specifying the operation mode. Connect directly to VCC or VSS. General-purpose I/O port. This applies when the UART0 clockoutput is disabled. D (CMOS/H) P90 58 Event input pin for reload timer 1. As the input operates continuously when the reload timer is set to input operation,output to the pin from other functions must be stopped unless done intentionally. General-purpose I/O port. This applies in all cases. D (CMOS/H) P86 57 External interrupt request input pin. As the input operatescontinuously when the external interrupt is enabled, outputto the pin from other functions must be stopped unless doneintentionally. Event input pin for reload timer 0. As the input operates continuously when the reload timer is set to input operation,output to the pin from other functions must be stopped unless done intentionally. P81 P82 to P83 Analog input pins for the A/D converter. This applies when A/D operation is specified in the analog input enable register. General-purpose I/O port. This applies in all cases. TIN0 TIN1 Function Serial data input pin for UART1. As the input operates continuously when UART1 is set to input operation, output to thepin from other functions must be stopped unless done intentionally. General-purpose I/O port. This applies when serial data output is disabled for UART1. Serial data output pin for UART1. This applies when serial data output is enabled for UART1. General-purpose I/O port. This applies when the UART1 clockoutput is disabled. D (CMOS/H) Clock I/O pin for UART1. This applies when the UART1 clock output is enabled. As the input operates continuously when UART1 is set to input operation, output to the pin from otherfunctions must be stopped unless done intentionally. 1.6 Pin Descriptions Table 1.6.1 MB90610A MB90610A Pin Descriptions (3) Pin No. QFP SQFP Pin Name Circuit Type P93 61 59 SIN2 P94 62 60 SOT2 General-purpose I/O port. This applies in all cases. D (CMOS/H) D (CMOS/H) P95 63 61 64 62 CS0 65 to 71 63 to 69 PA1 to PA7 72 70 73 74 75 71 72 73 SCK2 CS1 to CS7 P50 CLK P51 RDY P52 HAKX P53 HRQ P54 76 74 WRHX RSTX Function Serial data input pin for UART2. As the input operates continuously when UART2 is set to input operation, output to thepin from other functions must be stopped unless done intentionally. General-purpose I/O port. This applies when serial data output is disabled for UART2. Serial data output pin for UART2. This applies when serial data output is enabled for UART2. General-purpose I/O port. This applies when the UART2 clockoutput is disabled. D (CMOS/H) J (CMOS) I (CMOS) I (CMOS) L (TTL) Clock I/O pin for UART2. This applies when the UART2 clock output is enabled. As the input operates continuously when UART2 is set to input operation, output to the pin from otherfunctions must be stopped unless done intentionally. Chip select pin for program ROM General-purpose I/O ports. This applies for pins with chip select output disabled by the chip select control register. Output pins for the chip select function. This applies for pins with chip select output enabled by the chip select control register. General-purpose I/O port. This applies when CLK output is disabled. CLK output pin. This applies when CLK output is enabled. General-purpose I/O port. This applies when the external ready function is disabled. Ready input pin. This applies when the external ready function is enabled. I (CMOS) General-purpose I/O port. This applies when the hold function is disabled. L (TTL) General-purpose I/O port. This applies when the hold function is disabled. I (CMOS) G (CMOS/H) Hold acknowledge output pin. This applies when the hold function is enabled. Hold request input pin. This applies when the hold functionis enabled. General-purpose I/O port. This applies in 8-bit external bus mode or when output is disabled for the WR pin. Write strobe output pin for the upper 8 bits of the data bus. This applies in 16-bit external bus mode and when output is enabled for the WR pin. 77 75 78 76 79 77 RDX J (CMOS) Read strobe output pin for the data bus 80 78 ALE J (CMOS) Address latch enable output pin 23 84 21 82 VCC Power supply Power supply for the digital circuits 11 42 81 9 40 79 VSS Power supply Ground level for the digital circuits P55 WRLX I (CMOS) External reset request input pin General-purpose I/O port. This applies when output is disabled for the WR pin. Write strobe output pin for the lower 8 bits of the data bus. This applies when output is enabled for the WR pin. 11 1.6 Pin Descriptions Table 1.6.3 I/O Circuit Configurations (1) Type Circuit Configuration Remarks · MAX. 3 MHz to 32 MHz X1 A Clock input · Oscillator feedback resistance: approximately 1 M X0 STANDBY CONTROL · CMOS level I/O With standby control Digital output Digital output B Digital input STANDBY CONTROL · N-channel open drain output CMOS level hysteresis input With AD control Digital output C A/D input Digital input A/D DISABLE · CMOS level output Digital output Digital output D Digital input STANDBY CONTROL 12 Chapter 1: General CMOS level hysteresis input With standby control 1.6 Pin Descriptions Table 1.6.3 I/O Circuit Configurations (2) Type Circuit Configuration Remarks · CMOS level input No standby control E Digital input · CMOS level hysteresis input No standby control F Digital input · CMOS level hysteresis input No standby control · With pull-up R G Digital input · CMOS level output · CMOS level hysteresis input Digital output H No standby control Digital output Digital input 13 1.7 Device Operation Table 1.6.3 I/O Circuit Configurations (3) Type Circuit Configuration Remarks · CMOS level I/O STANDBY CONTROL R · Pull-up resistor approximately 50 k Digital output · Pin goes to high impedance during stop mode. Digital output I Digital input STANDBY CONTROL · CMOS level output STANDBY CONTROL R · Pull-up resistor approximately 50 k Digital output · Pin goes to high impedance during stop mode. J Digital output · CMOS level output Digital output Digital output · TTL level input With standby control K Digital input STANDBY CONTROL · CMOS level output STANDBY CONTROL · TTL level input L Digital output · Pull-up resistor approximately 50 k Digital output R · Pin goes to high impedance during stop mode. Digital input STANDBY CONTROL Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the "L" level or when in the standby state. 1.7 Device Operation 14 Chapter 1: General 1.7 Device Operation (1) Preventing latch-up Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if the voltage applied across VCC and VSS exceeds the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation. For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage. (2) Connecting unused pins Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins. (3) Cautions when using an external clock Drive the X0 pin only when using an external clock. Figure 1.7.1 shows an example of how to use an external clock. X0 OPEN X1 MB90610A MB90610A Fig. 1.7.1 Example of Using an External Clock (4) Power supply pins When multiple VCC and VSS pins are provided, connect all VCC and VSS pins to supply or ground externally. Although pins at the same potential are connected together in the internal device design so as to prevent misoperation such as latch-up, connecting all VCC and VSS pins appropriately minimizes unwanted radiation, prevents misoperation of strobe signals due to increases in the ground level, and keeps the overall output current rating. Also, take care to connect VCC and VSS to a low impedance current source. Connection of a bypass capacitor (a ceramic capacitor of approximately 0.1 µF connected close to the device) between VCC and VSS is recommended. (5) Crystal oscillator circuit Noise in the vicinity of the X0 and X1 pins can be a cause of device misoperation. Place X0, X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground as close together as possible. Also, design the circuit board so that the wiring for the crystal oscillator circuit does not cross other wiring. A printed circuit board design that surrounds the X0 and X1 pins with ground provides for stable operation and is strongly recommended. (6) A/D converter power supply and the turn-on sequence for analog inputs Do not apply current to the A/D converter power supply (AVCC, AVR+, AVR-) or analog inputs (AN0 to 15 1.7 Device Operation AN7) until the digital power supply (VCC) is turned on. When turning the device off, turn off the digital power supply after cutting the A/D converter power supply and analog inputs. When turning the power on or off, ensure that AVR+ does not exceed AVCC. 16 Chapter 1: General 2.1 CPU Chapter 2: Hardware 2.1 CPU 2.1.1 Memory Space Outline of the CPU memory space The program, data, and I/O managed by the F2MC-16L F2MC-16L CPU are all located in the CPU's 16MB memory space. The CPU accesses each resource by setting the corresponding address on the 24-bit address bus (Figure 2.1.1). F2MC-16L F2MC-16L device FFFFFFH Program area Program F2MC-16L F2MC-16L FF8000H FF8000H Data 810000H 810000H CPU Data area Interrupts 800000H 800000H 0000C0H 0000C0H Peripheral circuits Interrupt controller 0000B0H 0000B0H Internal resources Generalpurpose ports 000020H 000020H General-purpose ports [Device] 000000H 000000H Fig. 2.1.1 Example of the Relationship Between the F2MC-16L F2MC-16L System and Memory Map 17 2.1 CPU Address generation modes Address generation in the F2MC-16L F2MC-16L can be broadly divided into two modes: linear addressing and bank addressing. In linear addressing, the instruction specifies the entire 24-bit address. In bank addressing, the upper 8 bits of the address are set in a bank register based on the application and the instruction specifies the lower 16 bits of the address. Linear addressing can be further divided into two types. In one method, the operand specifies the 24-bit address directly. In the other method, the lower 24 bits of a 32-bit general-purpose register are used as the address. (Figure 2.1.2) Example 1: Linear addressing with a 24-bit operand specified JMPP 123456H 123456H Old program counter + program bank 17452DH 17452DH 17 452D JMPP 123456H 123456H New program counter + program bank 17 123456H 123456H Next instruction 3456 Example 2: Linear addressing using 32-bit register indirect addressing MOV A,@RL1+7 Old AL XXXX 090700H 090700H 3A +7 RL1 New AL 003A 240906F9 240906F9 (Upper 8 bits ignored.) Fig. 2.1.2 Example of Linear Address Generation 18 Chapter 2: Hardware 2.1 CPU Bank addressing modes Bank addressing splits the 16MB address space into 256 banks of 64KB. The bank registers specify the bank address. Five types of bank register are provided. Table 2.1.1 lists the memory space accessed and the main use for each bank register. Table 2.1.1 Memory Space Accessed by Each Bank Register Memory Space Name Bank Register Name Main Application Initial Value After Reset Program bank register (PCB) Program (PC) space Stores instruction code, vector tables, and immediate data FFH Data bank register (DTB) Data (DT) space Stores readable and writable data. Accesses control registers and data registers for internal and external peripherals. 00H User stack bank register (USB) Stack (SP) space Area used for stack access such as by PUSH and POP instructions or register saving at interrupts. SSB is used when S=1 in CCR. USB is used when S=0 in CCR. Additional (AD) space Stores data such as data that is too large for the data (DT) space. System stack bank register (SSB) Additional bank register (ADB) 00H 00H 00H After a reset, the DT, SP, and AD spaces are allocated to bank 00 (000000H 000000H to 00FFFFH 00FFFFH) and the PC space is allocated to bank FF (FF0000H FF0000H to FFFFFFH). To improve instruction code efficiency, instructions have a default space for each addressing mode. Table 2.1.2 lists the defaults. Prefix codes can be prefixed to instructions to specify a space other than the default for the addressing mode used. The system accesses the space corresponding to the prefix code. Table 2.1.2 Default Memory Spaces Default Space Addressing Program space PC indirect, program access, branching Data space @A, addr16, dir, Addressing using @RW0, @RW1, @RW4, or @RW5 Stack space Addressing using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing using @RW2 or @RW6 19 2.1 CPU Figure 2.1.3 shows an example of the division of memory space into banks and each bank register. FFFFFFH Program space FF0000H FF0000H FFH : PCB (Program bank register) B3H : ADB (Additional bank register) 92H : USB (User stack bank register) 68H : DTB (Data bank register) 4BH : SSB (System stack bank register) Physical addresses B3FFFFH Additional space B30000H B30000H 92FFFFH 92FFFFH User stack space 920000H 920000H 68FFFFH 68FFFFH Data space 680000H 680000H 4BFFFFH System stack space 4B0000H 4B0000H 000000H 000000H Fig. 2.1.3 Example of Physical Addresses of Each Memory Space 20 Chapter 2: Hardware 2.1 CPU Memory space layout for multi-byte data Figure 2.1.4 shows the data configuration of multi-byte data in memory. The lower 8 bits are placed at location n and subsequent bytes placed at locations n+1, n+2, n+3, etc. MSB LSB 01010101 11001100 11111111 00010100 01010101 11001100 11111111 Location n 00010100 L Fig. 2.1.4 Example of Memory Layout for Multi-Byte Data Memory is written to from the lowest address. Therefore, for 32-bit data, the lower 16 bits are transferred first, followed by the upper 16 bits. If a reset signal is input immediately after writing the lower data bits, writing the upper data bits may not occur. Accessing multi-byte data All access occurs within a bank. Therefore, for instructions that access multi-byte data, the next address after location FFFFH is location 0000H 0000H in the same bank. Figure 2.1.5 shows an execution example for an instruction that accesses multi-byte data. H AL before execution 23H 01H 01H 800000H 800000H ? AL after execution 80FFFFH 80FFFFH ? 23H L Fig. 2.1.5 Execution of MOVW A,080FFFFH 080FFFFH 21 2.1 CPU 2.1.2 Registers The F2MC-16L F2MC-16L registers can be broadly divided into two categories: dedicated registers located in the CPU and general-purpose registers located in internal RAM. Dedicated registers exist as specific hardware in the CPU and their use is limited by the CPU architecture. In contrast, general-purpose registers are located in RAM in the CPU's address space. Like special registers, general-purpose registers can be accessed without specifying an address. However, general-purpose registers can also be used as specified by the user, in the same way as standard memory. Figure 2.1.6 shows the layout of the dedicated and general-purpose registers in the device. CPU Dedicated registers RAM Accumulator User stack pointer General-purpose registers System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register Internal bus Fig. 2.1.6 Special and General-Purpose Registers 22 Chapter 2: Hardware 2.1 CPU Dedicated registers Table 2.1.3 lists the eleven dedicated registers in the F2MC-16L F2MC-16L. Table 2.1.3 Dedicated Registers Structure AH Register Name Function AL Accumulator 2 × 16-bit registers used to save operation results and similar. Can be combined as a single 32-bit register. USP User stack pointer 16-bit pointer that specifies the user stack area SSP System stack pointer 16-bit pointer that specifies the system stack area PS Processor status 16-bit register that indicates the system status PC Program counter 16-bit register that stores the address containing the program DPR Direct page register 8-bit register that specifies the direct page PCB Program bank register 8-bit register that specifies the program space DTB Data bank register 8-bit register that specifies the data space USB User stack bank register 8-bit register that specifies the user stack space SSB System stack bank register 8-bit register that specifies the system stack space ADB Additional data bank register 8-bit register that specifies the additional space 23 2.1 CPU Accumulator (A) The accumulator consists of two 16-bit operation registers: AH and AL. The accumulator is used for temporary storage of operation results and data moves. AH and AL can be combined for 32-bit data processing. For 16-bit word processing or 8-bit byte processing, the AL register only is used. (See Figures 2.1.7 and 2.1.8.) Operations can be performed on accumulator data and memory or register (Ri, RWi, or RLi) data. Like the F2MC-8, when word-length or shorter data is transferred to the F2MC-16 F2MC-16's AL register, the previous content of AL is automatically transferred to AH (the data retention function). The data keep function and AL-AH operations increase the processing efficiency of the device. (Figure 2.1.8) MOVL A,@RW1+6 (This instruction performs a long-word read from the location specified by adding an 8-bit offset value to RW1 and places the data in the accumulator.) Memory space MSB Accumulator before execution XXXXH XXXXH A61540H A61540H 8FH 74H A6153EH A6153EH 2BH 52H RW1 A6H DTB LSB 15H 38H +6 Accumulator after execution 8F74H 8F74H 2B52H 2B52H AH AL Fig. 2.1.7 32-Bit Data Move Example MOVW A,@RW1+6 (This instruction performs a single-word read from the location specified by adding an 8-bit offset value to RW1 and places the data in the accumulator.) Memory space MSB Accumulator before execution XXXXH 1234H 1234H DTB LSB A61540H A61540H 74H A6153EH A6153EH A6H 8FH 2BH 52H RW1 15H 38H +6 Accumulator after execution 1234H 1234H 2B52H 2B52H AH AL Fig. 2.1.8 AL-AH Move Example 24 Chapter 2: Hardware 2.1 CPU When moving byte-length or shorter data to AL, the data placed in AL is sign extended or zero extended to a length of 16 bits. Data in AL can be treated as word-length or byte-length. When the CPU executes a byte-length arithmetic instruction on AL, the operation ignores the upper 8 bits of AL and sets the upper 8 bits of the result to zero. (See Figures 2.1.9 and 2.1.10.) The accumulator is not initialized by a reset. The value of the accumulator after a reset is undefined. MOV A,3000H 3000H (This instruction zero extends the data at location 3000H 3000H and places the result in AL.) Memory space MSB Accumulator before execution XXXXH 2456H 2456H B53000H B53000H 77H 88H B5H DTB Accumulator after execution LSB 2456H 2456H 0088H 0088H AH AL Fig. 2.1.9 Zero Extend Execution Example MOVX A,3000H 3000H (This instruction sign extends the data at location 3000H 3000H and places the result in AL.) Memory space MSB Accumulator before execution XXXXH B53000H B53000H DTB Accumulator after execution LSB 2456H 2456H 2456H 2456H 88H B5H FF88H FF88H AH 77H AL Fig. 2.1.10 Sign Extend Execution Example 25 2.1 CPU User stack pointer (USP) and system stack pointer (SSP) The USP and SSP are 16-bit registers that specify the memory address for saving and restoring data at PUSH/POP instruction or subroutine execution. Stack instructions operate in the same way on both USP and SSP. The instructions use USP if the S flag in the processor status (PS) register is set to "0" and SSP if the S flag is set to "1" (see Figure 2.1.11). The S flag is set to "1" when an interrupt is received. Therefore, when an interrupt occurs, the processor always saves registers to the memory specified by SSP. Normally, stack processing in interrupt routines uses SSP and stack processing other than in interrupt routines uses USP. If separate stack spaces are not necessary, use SSP only. Always set an even numbered address to the stack pointer. Setting an odd numbered address splits word access in two and reduces efficiency. SSB specifies the upper 8 bits of the stack address for SSP and USB specifies the upper 8 bits for USP. USP and SSP are not initialized by a reset. The values of USP and SSP after a reset are undefined. Example 1: Executing PUSHW A when the S flag is "0". MSB Before execution AL S flag After execution AL S flag A624H A624H USB C6H USP F328H F328H 0 SSB 56H SSP 1234H 1234H A624H A624H USB C6H USP F326H F326H 0 SSB 56H SSP 1234H 1234H LSB C6F326H C6F326H XX XX User stack used because S flag = "0". C6F326H C6F326H A6H 24H 561232H 561232H XX XX 561232H 561232H A6H 24H Example 2: Executing PUSHW A when the S flag is "1". Before execution AL S flag After execution AL S flag A624H A624H USB C6H USP F328H F328H 1 SSB 56H SSP 1234H 1234H A624H A624H USB C6H USP F328H F328H 1 SSB 56H SSP 1232H 1232H System stack used because S flag = "1". Fig. 2.1.11 Stack Manipulation Instructions and Stack Pointers 26 Chapter 2: Hardware 2.1 CPU Processor status (PS) The processor status register consists of control bits that control the CPU operation and status bits that indicate the CPU status. Figure 2.1.12 shows the structure of PS. The upper byte contains the register bank pointer (RP), which indicates the top address of the register bank, and the interrupt level mask register (ILM). The lower byte contains the condition code register (CCR). The CCR consists of flags which are set to "0" or "1" by instruction execution results, interrupt generation, or other events. 15 Initial value : 8 7 ILM PS X 13 12 0 RP 0 0 0 CCR 0 0 0 0 0 0 1 X X X X X Ideterminate value Fig. 2.1.12 PS Structure (1) Condition code register (CCR) Figure 2.1.13 shows the structure of the condition code register. 7 Initial value X : 6 5 4 3 2 1 0 - I S T N Z V C - 0 1 X X X X X : CCR Ideterminate value Fig. 2.1.13 Condition Code Register Structure I: Interrupt enable flag For all interrupts other than software interrupts, setting I to "1" enables the interrupts and setting I to "0" masks the interrupts. Cleared by a reset. S: Stack flag Stack operations use USP if the S flag is set to "0" and SSP if the S flag is set to "1". Set by a reset or on receiving an interrupt. T: Sticky bit flag Set to "1" if the data shifted out of carry during a logical or arithmetic right shift instruction contains one or more "1"s. Otherwise, set to "0". Also set to "0" if the shift amount is zero. N: Negative flag Set if the MSB of an operation result is "1", cleared if the MSB is "0". Z: Zero flag Set if an operation result is all "0"s, cleared otherwise. V: Overflow flag Set if an overflow occurs for a signed value as the result of the execution of an operation. Cleared if no overflow occurs. C: Carry flag Set if a carry-up or carry-down occurs for the MSB as the result of the execution of an operation. Cleared if no carry occurs. 27 2.1 CPU (2) Register bank pointer (RP) The RP register specifies the relationship between the F2MC-16L F2MC-16L's general-purpose registers and the addresses in internal RAM where the registers are located. The top memory address of the register bank currently in use is specified by the conversion formula: [000180H 000180H + (RP)*10H] (Figure 2.1.14). RP consists of 5 bits and can be set in the range 00H to 1FH. This allows register banks to be located in memory between 000180H 000180H and 00037FH 00037FH. However, addresses in this range can only be used as generalpurpose registers if the address is in internal RAM. RP is initialized to 00H by a reset. RP can be set by an 8-bit immediate move instruction but only the lower 5 bits are used. B4 Initial value B3 B2 B1 B0 0 0 0 0 : RP 0 Fig. 2.1.14 Register Bank Pointer (3) Interrupt Level Mask Register (ILM) The ILM consists of 3 bits and specifies the interrupt mask level for the CPU. The CPU only receives interrupts with a higher priority level than the level specified in ILM. Zero is the highest interrupt level and seven is the lowest interrupt level (see Table 2.1.4). Therefore, to receive an interrupt, the level value of the interrupt request must be less than the value set in ILM. When an interrupt is received, the interrupt level value is set in ILM. This disables the subsequent reception of interrupts of the same or lower priority. ILM is initialized to all zeros by a reset. Instruction allows 8-bit immediate value transfer to ILM but only the upper 3 bits are actually used. ILM2 ILM1 ILM0 Initial value 0 0 : ILM 0 Fig. 2.1.15 Interrupt Level Register Table 2.1.4 Priority Levels for the Interrupt Level Mask Register (ILM) ILM2 ILM0 Level Allowed Interrupt Levels 0 0 0 0 All interrupts prohibited 0 0 1 1 0 only 0 1 0 2 Level 1 or less 0 1 1 3 Level 2 or less 1 0 0 4 Level 3 or less 1 0 1 5 Level 4 or less 1 1 0 6 Level 5 or less 1 28 ILM1 1 1 7 Level 6 or less Chapter 2: Hardware 2.1 CPU Program counter (PC) The PC is a 16-bit counter. The PC specifies the lower 16 bits of the memory address of the instruction code to be executed by the CPU. PCB specifies the upper 8 bits of the address. Operations that update the content of the PC include conditional branch instructions, subroutine call instructions, interrupts, and resets. PCB FEH PC ABCDH FEABCDH Next instruction to execute Fig. 2.1.16 Program Counter Direct page register (DPR) As shown in Figure 2.1.17, the DPR specifies addr8 to addr15 of the operand for direct addressing instructions. DPR is an 8-bit register and is initialized to 01H by a reset. The DPR can be read from or written to by instructions. DPR register DTB register Direct address in instruction LSB MSB 24-bit physical address Fig. 2.1.17 Physical Address Generation Using Direct Addressing Program counter bank register (PCB) Data bank register User stack bank register System stack bank register Additional data bank register (DTB) (USB) (SSB) (ADB) The bank registers specify the memory banks for the PC space, DT space, SP space (user), SP space (system), and AD space respectively. All bank registers consist of 8 bits. A reset initializes PCB to FF H and other bank registers to 00H. The bank registers other than PCB permit reading and writing. The PCB permits reading but not writing. The PCB is written to on execution of branch instructions (JMPP, CALLP, RETP, and RETI) that operate in the total (16MB) memory space, on execution of a software interrupt instruction, and when exceptions or hardware interrupts occur. See 2.1.1 "Memory Space" for details on the operation of each register. 29 2.1 CPU General-purpose registers The general-purpose registers of the F2MC-16L F2MC-16L are located in RAM at 000180H 000180H to 00037FH 00037FH in the memory map. The register bank pointer (RP) specifies the section of memory that is currently used as the register bank. Each bank contains the following three register types. The registers are not independent. Figure 2.1.18 shows the relationship between the registers. MSB 16bit · R0 to 7: 8-bit general-purpose registers Higher LSB R7 R6 RW7 R5 R4 RW6 R3 R2 RW5 R1 R0 RW4 RL3 · RW0 to 7:16-bit general-purpose registers · RL0 to 3: 32-bit general-purpose registers RL2 RW3 RL1 RW2 RW1 Lower 000180H 000180H + RP 10H * RL0 RW0 Top address of the general-purpose registers Fig. 2.1.18 General-Purpose Registers Register bank The register bank consists of eight 16-bit registers: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. The registers can be used as general-purpose registers in various operations and as pointers in various instructions. RL0 to RL3 can also be used as linear pointers to directly access the entire memory space. Table 2.1.5 lists the function of each register. As for standard RAM, the register contents are not initialized by a reset and the registers maintain the values that they had prior to the reset. However, the register contents are indeterminate at power on. Table 2.1.5 Register Functions R0 to R7 RW0 to RW7 RL0 to RL3 30 Used as instruction operands. Note: R0 is also used as the barrel shift counter and normalize instruction counter. Used as pointers. Used as instruction operands. Note: RW0 is also used as the string instruction counter. Used as long pointers. Used as instruction operands. Chapter 2: Hardware 2.1 CPU 2.1.3 Prefix Codes Placing a prefix code in front of an instruction modifies the operation of the instruction. Three types of prefix codes are available: bank select prefixes, common register bank prefixes, and flag change inhibit prefixes. Bank select prefix The memory space used for data access is determined by the addressing mode. Placing a bank select prefix in front of an instruction selects a specific memory space for data access by the instruction, irrespective of the addressing mode. Table 2.1.6 lists the memory space selected by each bank select prefix. Table 2.1.6 Bank Select Prefix Bank Select Prefix Memory Space PCB PC space DTB Data space ADB AD space If the S flag in CCR is "0", selects the user stack space. If the S flag is "1", selects the system stack space. SPB However, note that the instructions listed in Table 2.1.7 ignore the bank select prefix. Also, for the instructions listed in Table 2.1.8, the effect of the bank select prefix is passed on to the next instruction. Table 2.1.7 Instructions that Ignore the Bank Select Prefix Instruction Type Instruction Effect of the Bank Select Prefix String instructions MOVS SCEQ FILS MOVSW SCWEQ FILSW Uses the bank register specified in the operand, whether or not a prefix is present. Stack manipulation instructions PUSHW POPW Uses USB (if the S flag = 0) or SSB (if the S flag = 1), whether or not a prefix is present. MOVX A,io I/O access instructions MOV A,io MOVW A,io MOV io,A MOV io,#imm8 MOVB A,io:bp SETB io:bp BBC io:bp,rel WBTC io:bp Interrupt return instruction RETI MOVW io,A MOVW io,#imm16 MOVB io:bp,A CLRB io:bp BBS io:bp,rel WBTS io:bp Accesses the memory space 000000H 000000H to 0000FFH 0000FFH, whether or not a prefix is present. Uses SSB, whether or not a prefix is present. Table 2.1.8 Instructions for Which the Effect of the Bank Select Prefix is Passed on to the Next Instruction Instruction Type Instruction Flag modify instructions AND CCR,#imm8 PS restore instruction POPW PS ILM set instruction OR CCR,#imm8 MOV ILM,#imm8 31 2.1 CPU When multiple prefix codes are specified When multiple conflicting prefix codes are specified, the final code specified is used. Prefix code ADB DTB PCB ADD A, 01H The PCB prefix code is used. Fig. 2.1.19 Multiple Prefix Codes Common register bank prefix (CMR) To simplify data exchange between tasks, a predetermined common register bank is required that can be accessed by a comparatively simple procedure unaffected by the value of RP at the time. Placing CMR in front of an instruction that accesses a register bank changes the accessed register bank to the common bank located at 000180H 000180H to 00018FH 00018FH (the bank selected when RP = 0), irrespective of the current value of RP. However, care is required with the instructions listed in Table 2.1.9. Table 2.1.9 Instructions Requiring Care When Using the Common Register Bank Prefix Instruction Type Instruction MOVSW SCWEQ FILSW Explanation String instructions MOVS SCEQ FILS Flag modify instructions AND CCR,#imm8 PS restore instruction POPW PS The effect of the prefix is passed on to the next instruction. ILM set instruction MOV ILM,#imm8 The effect of the prefix is passed on to the next instruction. OR CCR,#imm8 Do not use the CMR prefix with string instructions. The effect of the prefix is passed on to the next instruction. Flag change inhibit prefix Use the flag change inhibit prefix code (NCC) to inhibit unwanted changes to the flags. Placing NCC in front of an instruction prevents instruction execution from changing the flags. The prefix inhibits changes to the T, N, Z, V, and C flags. However, care is required with the instructions listed in Table 2.1.10. 32 Chapter 2: Hardware 2.1 CPU Table 2.1.10 Instructions Requiring Care When Using the Flag Change Inhibit Prefix Instruction Type String instructions Flag modify instructions Instructions MOVS SCEQ FILS Explanation MOVSW SCWEQ FILSW AND CCR,#imm8 Do not use the NCC prefix with string instructions. OR CCR,#imm8 The instruction changes CCR as usual, whether or not a prefix is present. The effect of the prefix is passed on to the next instruction. PS restore instruction POPW PS The instruction changes CCR as usual, whether or not a prefix is present^\The effect of the prefix is passed on to the next instruction. ILM set instruction MOV ILM,#imm8 The effect of the prefix is passed on to the next instruction. Interrupt instructions Interrupt return instructions INT #vct8 INT addr16 RETI Context switch instruction JCTX @A INT9 INTP addr24 The instruction changes CCR as usual, whether or not a prefix is present. The instruction changes CCR as usual, whether or not a prefix is present. Interrupt inhibiting instructions Hardware interrupt requests are not detected and interrupt requests are ignored for the ten types of instruction listed in Table 2.1.11. Table 2.1.11 Hardware Interrupt Inhibiting Instructions MOV ILM,#imm8 AND CCR,#imm8 OR CCR,#imm8 POPW PS PCB ADB NCC DTB SPB CMR Therefore, if a valid hardware interrupt request occurs during execution of one of these instructions, interrupt processing does not start until after the execution of the next instruction of a type other than those listed above. Figure 2.1.20 shows an example. Interrupt inhibiting instructions (a) (a) Normal instructions Interrupt request occurs Interrupt received Fig. 2.1.20 Interrupt Inhibiting Instructions 33 2.1 CPU Restrictions for interrupt inhibiting instructions and prefix instructions If a prefix code is placed in front of an interrupt inhibiting instruction, the effect of the prefix code is passed on to the next instruction that is not an interrupt inhibiting instruction. Figure 2.1.21 shows an example. Interrupt inhibiting instructions MOV A, FFH NCC ADD A, 01H MOV ILM, #imm8 CCR : XXX10XX XXX10XX CCR : XXX10XX XXX10XX CCR is not modified due to the NCC prefix. Fig. 2.1.21 Interrupt Inhibiting Instructions and Prefix Codes 2.1.4 Interrupts, Extended Intelligent I/O Service, and Exceptions The F2MC-16L F2MC-16L has functions that halt the currently executing processing and pass control to another defined program when an event or similar occurs. The functions can be divided into the following four types. Hardware interrupt Software interrupt Extended intelligent I/O service (EI2OS) Exception Interrupt processing triggered by an event occurring in an internal resource circuit. Interrupt processing triggered by a software event instruction. Data transfer processing triggered by an event occurring in an internal resource circuit. Interrupt processing triggered by an exception. Hardware interrupts (1) Outline The hardware interrupt function temporarily interrupts the program currently executing in the CPU in response to an interrupt request signal from an internal resource circuit. Control is passed to a user-defined interrupt handling program. To activate a hardware interrupt, the hardware compares the interrupt level of the interrupt request with the interrupt level mask register (ILM) in the PS register of the CPU and checks the value of the I flag in the PS register. The hardware interrupt activates if the conditions are valid. The CPU performs the following processing when a hardware interrupt occurs. · The A, DPR, ADB, DTB, PCB, PC, and PS registers in the CPU are saved on the system stack. · The current interrupt level is stored in ILM in the PS register. · Execution branches to the corresponding interrupt vector. 34 Chapter 2: Hardware 2.1 CPU (2) Configuration The mechanisms relating to hardware interrupts can be divided into the following three groups. · Internal resource circuits Interrupt enable bit and interrupt request bit: Controls interrupt requests from internal resources. · Interrupt controller ICR: Assigns interrupt levels and prioritizes simultaneous interrupts. · CPU I, ILM: Compares the level of the interrupt request with the current level. Stores the interrupt enable status. Microcode: Executes the interrupt processing steps. Each mechanism is represented by the content of its respective registers: internal resource control registers for internal resource circuits, the ICR for the interrupt controller, and the CCR for the CPU. When using hardware interrupts, the program must first set values to these three register types. See "Interrupt Control Register (ICR)" in the "Extended Intelligent I/O Service" section for details on the ICR. The interrupt vector table referenced during interrupt processing is located in the memory area FFFC00 FFFC00 H to FFFFFFH. The area is shared with software interrupts. Table 2.1.12 lists the allocation of interrupt numbers and interrupt vectors. Table 2.1.12 Allocation of Interrupt Numbers and Interrupt Vectors Software Interrupt Instruction Vector Address L Vector Address M Vector Address H Mode Register Interrupt Number INT 0 FFFFFCH FFFFFDH FFFFFEH Unused #0 None INT 7 FFFFE0H FFFFE1H FFFFE2H Unused #7 None INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDF #8 (Reset vector) INT 9 FFFFD8H FFFFD9H FFFFDAH Unused #9 None INT 10 FFFFD4H FFFFD5H FFFFD6H Unused #10 INT 11 FFFFD0H FFFFD1H FFFFD2H Unused #11 Hardware interrupt #0 INT 12 FFFFCCH FFFFCDH FFFFCEH Unused #12 Hardware interrupt #1 INT 13 FFFFC8H FFFFC9H FFFFCAH Unused #13 Hardware interrupt #2 INT 14 FFFFC4H FFFFC5H FFFFC6H Unused #14 Hardware interrupt #3 INT 254 FFFC04H FFFC04H FFFC05H FFFC05H FFFC06H FFFC06H Unused #254 Free INT 255 FFFC00H FFFC00H FFFC01H FFFC01H FFFC02H FFFC02H Unused #255 Hardware Interrupt 35 2.1 CPU (3) Operation Internal resources with a hardware interrupt function have an "interrupt request flag" that indicates whether an interrupt request is present and an "interrupt enable flag" that selects whether or not the resource circuit can send interrupt requests to the CPU. The interrupt request flag is set by specific events in the internal resource circuit. If the interrupt enable flag is set to "enabled", the internal resource circuit passes the interrupt request to the interrupt controller. The interrupt controller compares the interrupt level (IL) in the ICR for each simultaneously occurring interrupt request, selects the request with the highest level (the lowest IL value), and notifies the CPU. If more than one request occurs with the same level, the request with the lowest interrupt number has priority. See Section 2.2.3 "Interrupt Vector Allocation" for details on the relationship between each interrupt request and ICR. The CPU compares the received interrupt level with ILM in the PS register. If the interrupt level (IL) is less than ILM and the I flag in the PS register is "1", the CPU activates the interrupt processing microcode after completing execution of the current instruction. The interrupt processing microcode first checks that the ISE bit in the interrupt controller's ICR register is set to "0" (indicating an interrupt), then activates the main body of interrupt processing. After saving the A, DPR, ADB, DTB, PCB, PC, and PS registers (12 bytes) to the memory area specified by SSB and SSP, interrupt processing reads the 3-byte interrupt vector and loads the vector to PC and PCB, changes ILM in the PS register to the level of the received interrupt request, sets the S flag to "1", then executes branch processing. As a result, the next executed instruction is the user-defined interrupt processing program. Figure 2.1.22 shows the flow of processing from the generation of a hardware interrupt until the interrupt request is completed by the interrupt processing program. Figure 2.1.23 shows the operation flow for a hardware interrupt. F2MC-16 F2MC-16 bus PS, PC · · · · (7) PS Microcode I ILM Check IR (6) Comparator (4) (5) F2MC-16L F2MC-16L · CPU PS: I: ILM: IR: Processor status Interrupt enable flag Interrupt level mask register Instruction register (3) . Internal resource Enable FF Level comparator Interrupt level IL AND Request FF (8) (1) Internal peripheral (2) Interrupt controller RAM Fig. 2.1.22 Steps from Generation to Release of a Hardware Interrupt 36 Chapter 2: Hardware 2.1 CPU (1) Interrupt source generated in the internal resource. (2) If interrupts are enabled in the internal resource by the interrupt enable bit, the interrupt request is passed from the resource to the interrupt controller. (3) The interrupt controller receives the interrupt request, evaluates the priorities of any simultaneous interrupt requests, then passes the interrupt level of the highest priority interrupt to the CPU. (4) The CPU compares the level of the interrupt request from the interrupt controller with ILM in the processor status register. (5) If the result of comparison is that the priority is higher than for the current interrupt processing level, the CPU then checks the I flag in the processor status register. (6) If checking the I flag in step 5 indicates that interrupts are enabled, the CPU waits until the current instruction completes executing, then sets the request level in ILM. (7) The CPU saves the registers, then passes control by branching to the interrupt processing routine. (8) The interrupt request completes when the user's interrupt processing routine software clears the interrupt source generated in step 1. I: ILM: IY: IE: ISE: IL: S: I & IY & IE =1 AND ILM>IL NO Flag in CCR Interrupt level mask register in CPU Internal resource interrupt request Interrupt enable flag for the internal resource EI2 OS enable flag Interrupt request level in the internal resource Flag in the CCR YES NO Next instruction load and decode YES ISE =1 Hardware interrupt Save PS, PC, PCB, DTB, ADB, DPR, and A to the SSP stack. Then set ILM = IL. Extended intelligent I/O service processing YES INT instruction? NO Normal instruction execution NO String instruction iteration complete? Software interrupt Save PS, PC, PCB, DTB, ADB, DPR, and A to the SSP stack. Then set I = "0". S1 Load interrupt vector. Update PCB and PC. YES Update PC Fig. 2.1.23 Interrupt Operation Flow 37 2.1 CPU (4) Example procedure for using hardware interrupts Start (1) Set system stack area. (2) Initialize internal resource. (3) Set ICR in interrupt controller. (4) Start internal resource operation. Set the interrupt enable bit to "enabled". (5) Set ILM and I in the PS register. Interrupt processing program (8) Stack processing Branch to interrupt vector. Process the interrupt from the internal resource. (9) Clear the interrupt source. (10) Interrupt return instruction (RETI) (7) Hardware processing Interrupt request (6) generated. Fig. 2.1.24 Example Procedure for Using Hardware Interrupts (1) (2) (3) (4) (5) (6) (7) Set the system stack area. Initialize the internal resource that can generate interrupt requests. Set ICR in the interrupt controller. Set the internal resource to the operating state and set the interrupt enable bit to "enabled". Set the ILM and I flag in the CPU to enable the reception of interrupts. Generation of an interrupt in the internal resource triggers a hardware interrupt request. The interrupt processing hardware saves the registers and branches to the interrupt processing program. (8) The interrupt processing program performs the necessary processing for the internal resource that generated the interrupt. (9) Release the interrupt request from the internal resource circuit. (10) Execute the interrupt return instruction and return to the previous program. 38 Chapter 2: Hardware 2.1 CPU (5) Hardware interrupt requests during a write to an internal resource area Hardware interrupt requests cannot be received during a write to an internal resource area. This is to prevent misoperation of CPU interrupt processing due to an interrupt request occurring during an update of the interrupt control register in an internal resource. The internal resource area refers to the area allocated for the control and data registers of internal resources (not the I/O addressing area between 000000H 000000H and 0000FFH 0000FFH). Write instruction for an internal resource area MOV A, #08 MOV io, A Interrupt request generated here. MOV A, 2000H 2000H Does not branch to the interrupt. Interrupt processing Branches to the interrupt. Fig. 2.1.25 Hardware Interrupt Request During a Write to an Internal Resource Area (6) Interrupt inhibiting instructions Some F2MC-16L F2MC-16L instructions do not detect hardware interrupt requests. These are called interrupt inhibiting instructions. See Table 2.1.11 for details. (7) Multiple interrupts The F2MC-16L F2MC-16L CPU supports multiple interrupts. If, during the processing of an interrupt, a second interrupt with a higher priority level occurs, control passes to the second interrupt on completion of the currently executing instruction. Control returns to the original interrupt processing when the higher priority interrupt completes. If an interrupt of the same or lower priority occurs during interrupt processing, the new interrupt request is held until the current interrupt completes processing (unless the ILM or I flag has been modified by an instruction). The extended intelligent I/O service does not support overlapping operation. Any interrupt or extended intelligent I/O service request that occurs during processing of the extended intelligent I/O service is held. 39 2.1 CPU (8) Saved registers Figure 2.1.26 shows the order in which registers are saved on the stack. Register save by an interrupt Word (16-bit) MSB LSB H SSP (Value of SSP before the interrupt) AH AL DPR ADB DTB PCB PC PS L SSP (Value of SSP after the interrupt) Fig. 2.1.26 Registers Saved on the Stack (9) Cautions For some internal resources, reading the control or data registers clears any interrupt request. Clearing an interrupt source by performing a read after generation of an interrupt request but before control has passed to the interrupt processing hardware causes misoperation. Therefore, when using internal resources for which interrupt requests are cleared by register read operations, do not perform register read operations when interrupts are generated. 40 Chapter 2: Hardware 2.1 CPU Software interrupts (1) Overview The software interrupt function transfers control from the program currently executing in the CPU to a user-defined interrupt processing program on execution of a special instruction. Software interrupts are always activated by the execution of the software interrupt instruction. The CPU performs the following processing when a software interrupt occurs. · The A, DPR, ADB, DTB, PCB, PC, and PS registers in the CPU are saved on the system stack. · The I flag in the PS register is set to "0" to inhibit hardware interrupts. · Execution branches to the corresponding interrupt vector. Interrupt requests initiated by the software interrupt instruction (INT) do not have an interrupt request flag or interrupt enable flag. Executing the INT instruction always generates an interrupt request. The INT instruction does not have interrupt levels. Accordingly, the INT instruction does not modify ILM. Instead the instruction sets the I flag to "0" to hold any subsequent interrupt requests. (2) Configuration All software interrupt mechanisms are located in the CPU. The software interrupt instruction must be executed to use a software interrupt. As shown in Table 2.1.12, software and hardware interrupt vectors share the same area. For example, interrupt request number INT 11 is used by both hardware interrupt #0 and software interrupt INT #11. Therefore, hardware interrupt #0 and INT #11 call the same interrupt processing routine. (3) Operation On executing the software interrupt instruction, the CPU activates the software interrupt processing microcode. After saving the A, DPR, ADB, DTB, PCB, PC, and PS registers (12 bytes) to the memory area specified by SSB and SSP, the software interrupt processing microcode reads the 3-byte interrupt vector and loads the vector to PC and PCB, sets the I flag to "0" and the S flag to "1", then executes branch processing. As a result, the next executed instruction is the user-defined interrupt processing program. Figure 2.1.27 shows the flow of processing from the generation of a software interrupt until the interrupt request is completed by the interrupt processing program. 41 2.1 CPU F2MC-16 F2MC-16 bus (1) PS, PC · · · PS I PS: I: ILM: IR: S (2) Microcode IR Queue Processor status Interrupt enable flag Interrupt level mask register Instruction register Fetch F2MC-16L F2MC-16L · CPU Save RAM Fig. 2.1.27 Steps from Generation to Release of a Software Interrupt (1) A software interrupt instruction is executed.0 (2) The microcode for the software interrupt instruction saves the dedicated registers. (3) Interrupt processing completes on execution of the RETI instruction in the user interrupt processing routine. (4) Cautions When the program bank register (PCB) is FFH, the vector area for the CALLV instruction overlaps the table for the INT #vct8 instruction. Take note of the address overlap of the CALLV and INT #vct8 instructions when developing software. 42 Chapter 2: Hardware 2.1 CPU Extended intelligent I/O service (EI2OS) The EI2OS function automatically transfers data between I/O and memory. The function provides DMAstyle I/O data handling and replaces I/O data handling by interrupt processing programs. The function has the following advantages over interrupt processing. · No data transfer program is required. This reduces total program size. · Data transfer does not use internal registers. This increases transfer speed because register saving is not required. · The I/O can stop data transfer as required. This eliminates unnecessary data transfer. · Incrementing or no-change of the buffer address can be selected. · Incrementing or no-change of the I/O register address can be selected. On completion, EI2OS sets the completion conditions then automatically branches to an interrupt processing routine. This allows the user to determine the completion conditions. To implement EI2OS, hardware is distributed between two locations. The blocks have the following registers and descriptors. · Interrupt control register Located in the interrupt controller. Specifies the ISD address. · Extended intelligent I/O service descriptor (ISD) Located in RAM. Holds the transfer mode, I/O address, transfer count, and buffer address. Figure 2.1.28 shows an overview of the extended intelligent I/O service. Memory space by IOA I/O register I/O register Peripheral (5) Interrupt request (1) CPU (3) ISD by ICS (2) (3) Interrupt control register Interrupt controller (1) The I/O requests a transfer. by BAP (4) Buffer by DCT (2) The interrupt controller selects the descriptor. (3) Reads the transfer source and destination from the descriptor. (4) Executes transfer between I/O and memory. (5) Automatically clears the interrupt source. Fig. 2.1.28 Overview of the Extended Intelligent I/O Service Note: The area that can be specified by IOA is 000000H 000000H to 00FFFFH 00FFFFH. The area that can be specified by BAP is 000000H 000000H to FFFFFFH. The maximum transfer count that can be specified by DCT is 65536. 43 2.1 CPU Interrupt control registers (ICR00 ICR00 to 15) The interrupt control registers are located in the interrupt controller and are provided for each I/O that has an interrupt function. See 2.2.3 "Interrupt Vector Allocation" for details on interrupts and ICRs. The registers perform the following three functions. · Sets the interrupt level for the corresponding internal resource. · Selects whether the corresponding internal resource uses a standard interrupt or the extended intelligent I/O service. · Selects the extended intelligent I/O service channel. Do not access these registers using read-modify-write instructions as this can cause misoperation. Figure 2.1.29 shows the bit structure of the interrupt control registers. 7 6 5 4 3 2 1 0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 W W W W W W W W 7 6 5 4 3 2 1 0 - - S1 S0 ISE IL2 IL1 IL0 - - R R R R R R When writing to an interrupt control register (ICR) Set to 00000111B 00000111B by a reset. When reading from an interrupt control register (ICR) Set to XX000111B XX000111B by a reset. Note: ICS3 to 0 are only meaningful when EI2OS is active. Set ISE to "1" when using EI2 OS and set ISE to "0" when not using EI2OS. Any values can be set to ICS3 to 0 if EI2OS is not used. Fig. 2.1.29 Interrupt Control Registers (ICR) 44 Chapter 2: Hardware 2.1 CPU [Bits 2 to 0] IL0, IL1, IL2: Interrupt level setting bits The interrupt level setting bits specify the interrupt level of the corresponding internal resource. The bits are readable and writable. The bits are initialized to level 7 (no interrupt) by a reset. Table 2.1.13 lists the relationship between the interrupt level setting bits and each interrupt level. Table 2.1.13 Correspondence Between Interrupt Level Setting Bits and Interrupt Levels IL2 IL1 IL0 Level 0 0 0 0 (Highest interrupt level) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (Lowest interrupt level) 1 1 1 7 (No interrupt) [Bit 3] ISE: Extended intelligent I/O service enable bit The EI2OS enable bit. The processor activates EI2OS if ISE is "1" when an interrupt occurs. If the ISE bit is "0", the processor activates the interrupt sequence. The bit is readable and writable. The ISE bit changes to "0" when EI2OS completes (count completion or completion by the internal resource). If the internal resource does not have an EI2OS function, set the ISE bit to "0" by software. The ISE bit is initialized to "0" by a reset. 45 2.1 CPU [Bits 7 to 4] ICS3 to 0: Extended intelligent I/O service channel select bits The EI2OS channel select bits specify the EI2OS channel. The bits are write-only. The value set in ICS determines the address of the extended intelligent I/O service descriptor (ISD). ICS is initialized to "0000" by a reset. Table 2.1.14 lists the correspondence between ICS, the channel number, and the descriptor address. Table 2.1.14 Correspondence Between ICS, Channel Number, and Descriptor Address ICS3 ICS1 ICS0 Channel Descriptor Address 0 0 0 0 0 000100H 000100H 0 0 0 1 1 000108H 000108H 0 0 1 0 2 000110H 000110H 0 0 1 1 3 000118H 000118H 0 1 0 0 4 000120H 000120H 0 1 0 1 5 000128H 000128H 0 1 1 0 6 000130H 000130H 0 1 1 1 7 000138H 000138H 1 0 0 0 8 000140H 000140H 1 0 0 1 9 000148H 000148H 1 0 1 0 10 000150H 000150H 1 0 1 1 11 000158H 000158H 1 1 0 0 12 000160H 000160H 1 1 0 1 13 000168H 000168H 1 1 1 0 14 000170H 000170H 1 46 ICS2 1 1 1 15 000178H 000178H Chapter 2: Hardware 2.1 CPU [Bits 5, 4] S1, S0: Extended intelligent I/O service status The extended intelligent I/O service status bits can be referenced to determine the operation status and completion status of EI2OS. The bits are read-only. The bits are initialized to "00" by a reset. Table 2.1.15 lists the relationship between the S bits and EI2OS status. Table 2.1.15 S Bits and EI2OS Status EI2OS Status S1 S0 0 0 EI2OS active or inactive 0 1 Stopped due to count completion 1 0 Reserved 1 1 Stopped by request from the internal resource Extended intelligent I/O service descriptor (ISD) The extended intelligent I/O service descriptors are located in internal RAM between 000100 H to 00017FH 00017FH. ISD consist of the following items. · Various control data for data transfer · Status data · Buffer address pointer Figure 2.1.30 shows the structure of the extended intelligent I/O service descriptor. Data counter (upper 8 bits) Data counter (lower 8 bits) (IOAH) I/O address pointer (lower 8 bits) (IOAL) EI2OS status (ISCS) Buffer address pointer (upper 8 bits) (BAPH) Buffer address pointer (middle 8 bits) (BAPM) Buffer address pointer (lower 8 bits) (BAPL) H (DCTL) 3I/O address pointer (upper 8 bits) 000100H 000100H + 8 × ICS ISD top address (DCTH) L Fig. 2.1.30 Structure of the Extended Intelligent I/O Service Descriptor 47 2.1 CPU Data counter (DCT) A 16-bit register used as a counter for the number of data transferred. The counter is decremented by one before each data transfer. EI2OS completes when this counter reaches zero. Figure 2.1.31 shows the structure of the data counter. 15 14 13 12 11 10 9 8 7 6 5 DCTH 4 3 2 1 0 : DCT (undefined after a reset) DCTL Fig. 2.1.31 Data Counter Structure I/O register address pointer (IOA) A 16-bit register that indicates the lower 16 bits (A15 to A0) of the address of the I/O register for data transfer to or from the buffer. The upper address (A23 to A16) is all zeros. This allows I/O to be specified anywhere between locations 000000H 000000H and 00FFFFH 00FFFFH. Figure 2.1.32 shows the structure of IOA. 15 14 13 12 11 IOAH 10 9 8 7 6 5 4 3 IOAL 2 1 0 : IOA (undefined after a reset) Fig. 2.1.32 Structure of the I/O Register Address Pointer 48 Chapter 2: Hardware 2.1 CPU EI2OS status register (ISCS) An 8-bit register that specifies whether the buffer address pointer and I/O register address pointer are updated or fixed, the transfer data length (byte or word), and the transfer direction. Figure 2.1.33 shows the structure of ISCS. 7 6 Re. 5 4 3 2 1 0 Re. Re. IF BW BF DIR SE : ISCS (indeterminate after a reset) Re.(Reserved) Fig. 2.1.33 ISCS Structure The meaning of each bit is as follows. [Bit 4] IF: Specifies whether the I/O register address pointer is updated or fixed. 0 :Update the I/O register address pointer after data transfer. 1 :Do not update the I/O register address pointer after data transfer. Note :Only incrementing is available. [Bit 3] BW: Specifies the data transfer length 0 :Byte 1 :Word [Bit 2] BF: Specifies whether the buffer address pointer is updated or fixed. 0 :Update the buffer address pointer after data transfer. 1 :Do not update the buffer address pointer after data transfer. Note:Updating changes only the lower 16 bits of the buffer address pointer. Only incrementing is available. [Bit 1] DIR: Specifies the data transfer direction. 0 :I/O address pointer Buffer address pointer 1 :Buffer address pointer I/O address pointer [Bit 0] SE: Controls completion of the extended intelligent I/O service by request from the internal resource. 0 :Do not terminate on request from the internal resource. 1 :Terminate on request from the internal resource. 49 2.1 CPU Buffer address pointer (BAP) A 24-bit register that stores the address to use for the next EI2OS transfer. As a separate BAP is provided for each EI2OS channel, each EI2OS channel can perform data transfer to any location in the 16MB memory space. If updating is specified by the BF bit in ISCS, the lower 16 bits only of BAP are updated and BAPH does not change. Figure 2.1.34 shows the structure of BAP. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 BAPH BAPM BAPL (R/W) (R/W) 2 1 0 : BAP (undefined after a reset) (R/W) Fig. 2.1.34 Structure of the Buffer Address Pointer Figure 2.1.35 shows the operation flow of EI2OS. Figure 2.1.36 shows the procedure for using EI2OS. 50 Chapter 2: Hardware 2.1 BAP: I/OA: ISD: ISCS: DCT: ISE: S1, S0: Interrupt request generated by internal resource. ISE=1 CPU Buffer address pointer I/O address pointer EI2OS descriptor EI2OS status Data counter EI2OS enable bit EI2OS completion status NO YES Interrupt sequence ISD/ISCS read YES Completion request from resource SE=1 NO DIR=1 YES NO Data specified by IOA (Data transfer) Memory specified by BAP IF=0 NO BF=0 NO Decrement DCT. DCT=00 NO Data specified by BAP (Data transfer) Memory specified by IOA YES Update value is determined by BW. Update IOA. YES Update value is determined by BW. Update BAP. (­1) YES Set "01" to S1 and S0. Set "11" to S1 and S0. Set "00" to S1 and S0. Clear resource interrupt request. Return to CPU operation. Clear ISE to "0". Interrupt sequence Fig. 2.1.35 EI2OS Operation Flow 51 2.1 CPU Hardware processing Software processing Start Set system stack area. Set EI2OS descriptor. Initialization Initialize internal resource. Set ICR in the interrupt controller. Start internal resource operation. Set the interrupt enable bit. Set ILM and I in the PS register. S1, S0=`00' Execute user program. (Interrupt request) and (ISE=1) Data transfer (Branch to interrupt vector.) Reset the extended intelligent I/O service. (Switch channels, etc.) Determine whether to branch to interrupt on count-out or on a completion request from the resource. YES S1, S0=`01' or S1, S0=`11' Process data in buffer. RETI Fig. 2.1.36 Procedure for Using EI2OS 52 Chapter 2: Hardware NO 2.1 CPU Exception processing The F2MC-16L F2MC-16L generates exceptions in the following cases and performs exception processing. (1) Execution of an undefined instruction In principle, exception processing is the same as interrupt processing. When an exception is detected at an instruction boundary, control passes from standard processing to exception processing. In general, as exception processing occurs as a result of an unexpected operation, it is recommended that exception processing only be used for purposes such as debugging or to activate emergency recovery software. Generation of an exception by execution of an undefined instruction The F2MC-16L F2MC-16L treats all codes not defined in the instruction map as undefined instructions. Executing an undefined instruction triggers the same processing as executing the software interrupt instruction "INT 10". That is, AL, AH, DPR, DTB, ADB, PCB, PC, and PS are saved on the system stack, the I flag is set to "0" and the S flag to "1", and execution branches to the program specified by the vector for interrupt 10. The value of PC saved on the stack contains the address of the undefined instruction. For instruction codes of 2 bytes or more, the PC value on the stack contains the address of the code that was recognized as undefined. Therefore, although returning by the RETI instruction is possible, this is meaningless as it only triggers another exception. 53 2.1 CPU 2.1.5 Standby Control Register Access The device is set to the low power modes (stop mode or sleep mode) by writing to the low power mode control register. In this case, use one of the instructions listed in Table 2.1.16. Correct operation cannot be guaranteed if you change to a low power mode using an instruction other than the instructions listed in Table 2.1.16. However, any instruction can be used on the low power mode control register when controlling functions other than changing to a low power mode. Always write to an even-numbered address when performing a word-length write to the low power mode control register. Changing to a low power mode by writing to an odd-numbered address may cause misoperation. Table 2.1.16 Instructions to Use When Changing to a Low Power Mode MOV io,#imm8 MOV eam,#imm8 MOV eam,Ri MOV io,A MOV dir,A MOV addr16,A MOV eam,A MOV @RLi+disp8,A MOVP addr24,A MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,A MOVW @RLi+disp8,A MOVPW addr24,A SETB io:bp 54 MOV dir,#imm8 SETB dir:bp Chapter 2: Hardware SETB addr16:bp 2.2 Map 2.2 Map This section describes the allocation of memory space, I/O space, and interrupt numbers in the MB90610A MB90610A. 2.2.1 Memory Space for Each Mode Figure 2.2.1 shows the MB90610A MB90610A memory space. Only external ROM/external bus mode is available. External ROM/External bus FFFFFFH : Internal : External 002000H 002000H Address #1 : No access RAM 000100H 000100H 0000C0H 0000C0H Registers Peripherals 000000H 000000H Product Address #1 MB90611A MB90611A 000500H 000500H MB90V610A MB90V610A 001100H 001100H Fig. 2.2.1 Memory Space Allocation for Each MB90610A MB90610A Mode Note: When output of the upper address (A23 to A16) is disabled, the MB90610A MB90610A series can only access a maximum of 64KB. 55 2.2 Map 2.2.2 I/O Map The following shows the MB90610A MB90610A I/O map. Table 2.2.2 MB90610A MB90610A I/O Map (1) Address Register Abbreviation Access Resource Name Initial Value 000000H 000000H Free 000001H 000001H Port 1 data register PDR1 R/W* Port 1 Note 8 XXXXXXXX 000002H 000002H Port 2 data register PDR2 R/W* Port 2 Note 7 XXXXXXXX 000003H 000003H Port 3 data register PDR3 R/W* Port 3 Note 7 XXXXXXXX 000004H 000004H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 000005H 000005H Port 5 data register PDR5 R/W Port 5 -XXXXXX 000006H 000006H Port 6 data register PDR6 R/W Port 6 11111111 000007H 000007H Port 7 data register PDR7 R/W Port 7 -XXXXXXX 000008H 000008H Port 8 data register PDR8 R/W Port 8 -XXXXXXX 000009H 000009H Port 9 data register PDR9 R/W Port 9 -XXXXXX 00000AH 00000AH Port A data register PDRA R/W Port A XXXXXXX- 00000BH 00000BH to 000010H 000010H Free 000011H 000011H Port 1 direction register DDR1 R/W* Port 1 Note 8 00000000 000012H 000012H Port 2 direction register DDR2 R/W* Port 2 Note 7 00000000 000013H 000013H Port 3 direction register DDR3 R/W* Port 3 Note 7 00000000 000014H 000014H Port 4 direction register DDR4 R/W Port 4 00000000 000015H 000015H Port 5 direction register DDR5 R/W Port 5 -000000 000016H 000016H Analog input enable register ADER R/W Port 6 11111111 000017H 000017H Port 7 direction register DDR7 R/W Port 7 -0000000 000018H 000018H Port 8 direction register DDR8 R/W Port 8 -0000000 000019H 000019H Port 9 direction register DDR9 R/W Port 9 -000000 00001AH 00001AH Port A direction register DDRA R/W Port A 0000000- 00001BH 00001BH to 00001FH 00001FH Free 000020H 000020H Mode register 0 SMR0 R/W! 000021H 000021H Control register 0 SCR0 R/W! Note 3 Note 3 Note 3 00000000 00000100 UART0 (SCI) 000022H 000022H Input data register 0/Output data register 0 SIDR0/SODR0 R/W 000023H 000023H Status register 0 SSR0 R/W! 00001-00 000024H 000024H Mode register 1 SMR1 R/W! 00000000 000025H 000025H Control register 1 SCR1 R/W! 000026H 000026H Input data register 1/Output data register 1 SIDR1/SODR1 R/W 000027H 000027H Status register 1 SSR1 R/W! 56 Chapter 2: Hardware XXXXXXXX 00000100 UART1 (SCI) XXXXXXXX 00001-00 2.2 Map Table 2.2.2 MB90610A MB90610A I/O Map (2) Address Register Abbreviation Access 000028H 000028H Interrupt/DTP enable register ENIR R/W 000029H 000029H Interrupt/DTP source register EIRR R/W Interrupt level setting register ELVR Resource Name R/W 00002AH 00002AH 00002BH 00002BH 00002CH 00002CH 00002DH 00002DH 00002EH 00002EH 00002FH 00002FH Initial Value 00000000 DTP/External interrupt 00000000 00000000 00000000 AD control status register ADCS 00000000 R/W! A/D converter AD data register ADCR 00000000 XXXXXXXX R/W! Note 4 000000XX 000000XX 000030H 000030H PPG0 operation mode control register PPGC0 R/W PPG0 000000-1 000031H 000031H PPG1 operation mode control register PPGC1 R/W PPG1 000000-1 000032H 000032H to 000033H 000033H Free 000034H 000034H 000035H 000035H 000036H 000036H 000037H 000037H 000038H 000038H 000039H 000039H 00003AH 00003AH 00003BH 00003BH 00003CH 00003CH 00003DH 00003DH 00003EH 00003EH 00003FH 00003FH 000040H 000040H to 000043H 000043H PPG0 reload register Note 3 PRL0 R/W PPG0 XXXXXXXX XXXXXXXX PPG1 reload register PRL1 R/W PPG1 XXXXXXXX XXXXXXXX Control status register TMCSR0 16-bit reload timer 0 16-bit timer register/16-bit reload register TMR0/TMRLR0 Control status register TMCSR1 16-bit timer register/16-bit reload register 00000000 R/W! R/W -0000 XXXXXXXX XXXXXXXX 00000000 R/W! 16-bit reload timer 1 TMR1/TMRLR1 R/W -0000 XXXXXXXX XXXXXXXX Free Note 3 000044H 000044H Mode register 2 SMR2 R/W! 00000000 000045H 000045H Control register 2 SCR2 R/W! 00000100 000046H 000046H Input data register 2/Output data register 2 SIDR2/SODR2 R/W 000047H 000047H Status register 2 SSR2 R/W! 00001-00 000048H 000048H CS control register 0 CSCR0 R/W -0000 000049H 000049H CS control register 1 CSCR1 R/W -0000 00004AH 00004AH CS control register 2 CSCR2 R/W -0000 00004BH 00004BH CS control register 3 CSCR3 R/W 00004CH 00004CH CS control register 4 CSCR4 R/W 00004DH 00004DH CS control register 5 CSCR5 R/W -0000 00004EH 00004EH CS control register 6 CSCR6 R/W -0000 00004FH 00004FH CS control register 7 CSCR7 R/W -0000 UART2 (SCI) XXXXXXXX Chip select function -0000 -0000 57 2.2 Map Table 2.2.2 MB90610A MB90610A I/O Map (3) Address Register Abbreviation Access 000050H 000050H Free 000051H 000051H UART0 (SCI) machine clock divide-by-n control register 000052H 000052H Free 000053H 000053H UART1 (SCI) machine clock divide-by-n control register 000054H 000054H Free 000055H 000055H UART2 (SCI) machine clock divide-by-n control register 000056H 000056H to 00008FH 00008FH Free Reserved system area Note 1 00009FH 00009FH Delay interrupt generate/ release register DIRR 0000A0H 0000A0H Low power mode control register 0000A1H 0000A1H Clock selection register 0000A2H 0000A2H to 0000A4H 0000A4H Free 0000A5H 0000A5H Auto-ready function selection register ARSR 0000A6H 0000A6H External address output control register 0000A7H 0000A7H Initial Value Note 3 000090H 000090H to 00009EH 00009EH Resource Name Note 3 UART0 (SCI) -1111 UART1 (SCI) -1111 UART2 (SCI) -1111 R/W Delay interrupt generation module -0 LPMCR R/W! Low power consumption 00011000 CKSCR R/W! Low power consumption 11111100 W External pins 0011-00 HACR W External pins 00000000 Bus control signal selection register ECSR W External pins -00*0000 0000A8H 0000A8H Watchdog timer control register WDTC R/W! Watchdog timer XXXXX111 XXXXX111 0000A9H 0000A9H Timebase timer control register TBTC R/W! Timebase timer 1-00100 0000AAH 0000AAH to 0000AFH 0000AFH Free 58 Chapter 2: Hardware CDCR0 W Note 3 CDCR1 W Note 3 CDCR2 W Note 3 Note 3 2.2 Map Table 2.2.2 MB90610A MB90610A I/O Map (4) Address Register Abbreviation Access Resource Name Initial Value 0000B0H 0000B0H Interrupt control register 00 ICR00 ICR00 R/W! 00000111 0000B1H 0000B1H Interrupt control register 01 ICR01 ICR01 R/W! 00000111 0000B2H 0000B2H Interrupt control register 02 ICR02 ICR02 R/W! 00000111 0000B3H 0000B3H Interrupt control register 03 ICR03 ICR03 R/W! 00000111 0000B4H 0000B4H Interrupt control register 04 ICR04 ICR04 R/W! 00000111 0000B5H 0000B5H Interrupt control register 05 ICR05 ICR05 R/W! 00000111 0000B6H 0000B6H Interrupt control register 06 ICR06 ICR06 R/W! 00000111 0000B7H 0000B7H Interrupt control register 07 ICR07 ICR07 R/W! 00000111 0000B8H 0000B8H Interrupt control register 08 ICR08 ICR08 R/W! 0000B9H 0000B9H Interrupt control register 09 ICR09 ICR09 R/W! 0000BAH 0000BAH Interrupt control register 10 ICR10 ICR10 R/W! 00000111 0000BBH 0000BBH Interrupt control register 11 ICR11 ICR11 R/W! 00000111 0000BCH 0000BCH Interrupt control register 12 ICR12 ICR12 R/W! 00000111 0000BDH 0000BDH Interrupt control register 13 ICR13 ICR13 R/W! 00000111 0000BEH 0000BEH Interrupt control register 14 ICR14 ICR14 R/W! 00000111 0000BFH 0000BFH Interrupt control register 15 ICR15 ICR15 R/W! 00000111 0000C0H 0000C0H to 0000FFH 0000FFH External area Note 2 Interrupt controller 00000111 00000111 Note 1: Access prohibited. Note 2: This is the only external access area in the area below address 0000FFH 0000FFH. Access this address as an external I/O area. Note 3: Areas marked as "free" in the I/O map are reserved areas. These areas are accessed by internal access. No access signals are output on the external bus. Note 4: Only bit 15 can be written. The other bits are written to by the test function. Reading bits 10 to15 returns zeros. Note 5: The R/W! symbol in the access column indicates that some bits are read-only or write-only. See the resource's register list for details. Note 6: Using a read-modify-write instruction (such as the bit set instruction) to access one of the registers indicated by R/W!, R/W*, or W in the access column sets the specified bit to the desired value. However, this can cause misoperation if the other register bits include write-only bits. Therefore, do not use read-modify-write instructions to access these registers. Note 7: This register is only available when the address/data bus is in multiplex mode. Access to the register is prohibited in non-multiplex mode. Note 8: This register is only available when the external data bus is in 8-bit mode. Access to the register is prohibited in 16-bit mode. Initial values 59 2.2 Map 0: 1: *: X: -: Note: The initial value for this bit is zero. The initial value for this bit is one. The initial value for this bit is one or zero. (Determined by the level of the MD0 to 2 pins.) The initial value for this bit is indeterminate. This bit is not used. The initial value is indeterminate. The initial values listed for write-only bits are the initial values set by a reset. They are not the values returned by a read. Also, LPMCR, CKSCR, and WDTC are sometimes initialized and sometimes not initialized, depending on the reset type. The listed initial values are for when these registers are initialized. 60 Chapter 2: Hardware 2.2 Map 2.2.3 Interrupt Vector Allocation The following shows the interrupt vector allocation in the MB90610A MB90610A. Table 2.2.3 MB90610A MB90610A Interrupt Vector Allocation Interrupt I2OS Support Interrupt vector Number Interrupt Control Register Address ICR Address Reset × #08 08H FFFFDCH - - INT 9 instruction × #09 09H FFFFD8H - - Exception × #10 0AH FFFFD4H - - External interrupt #0 #11 0BH FFFFD0H ICR00 ICR00 0000B0H 0000B0H External interrupt #1 #13 0DH FFFFC8H ICR01 ICR01 0000B1H 0000B1H External interrupt #2 #15 0FH FFFFC0H ICR02 ICR02 0000B2H 0000B2H External interrupt #3 #17 11H FFFFB8H ICR03 ICR03 0000B3H 0000B3H External interrupt #4 #19 13H FFFFB0H ICR04 ICR04 0000B4H 0000B4H External interrupt #5 #21 15H FFFFA8H ICR05 ICR05 0000B5H 0000B5H External interrupt #6 #23 17H FFFFA0H UART0 transmit complete #24 18H FFFF9CH ICR06 ICR06 0000B6H 0000B6H External interrupt #7 #25 19H FFFF98H FFFF98H UART1 transmit complete #26 1AH FFFF94H FFFF94H ICR07 ICR07 0000B7H 0000B7H ICR08 ICR08 0000B8H 0000B8H ICR09 ICR09 0000B9H 0000B9H ICR10 ICR10 0000BAH 0000BAH ICR11 ICR11 0000BBH 0000BBH PPG #0 × #27 1BH FFFF90H FFFF90H PPG #1 × #28 1CH FFFF8CH 16-bit reload timer #0 #29 1DH FFFF88H FFFF88H 16-bit reload timer #1 #30 1EH FFFF84H FFFF84H A/DC measurement complete #31 1FH FFFF80H FFFF80H UART2 transmit complete #33 21H FFFF78H FFFF78H #34 22H FFFF74H FFFF74H UART2 receive complete #35 23H FFFF70H FFFF70H ICR12 ICR12 0000BCH 0000BCH UART1 receive complete #37 25H FFFF68H FFFF68H ICR13 ICR13 0000BDH 0000BDH UART0 receive complete #39 27H FFFF60H FFFF60H ICR14 ICR14 0000BEH 0000BEH #42 2AH FFFF54H FFFF54H ICR15 ICR15 0000BFH 0000BFH Timebase timer interval interrupt Delay interrupt generation module Note: × × indicates I2OS support (no stop request), indicates I2OS support (with stop request), and × indicates no I2OS support. Do not set I2OS activation in ICRXX for resources that do not support I2OS. 61 2.2 Map 2.2.4 Clock Supply Map Peripheral clock Output enable Clock input Timer output PPG:ch0 Borrow output Reload input PPG:ch1 Peripheral clock Clock input PPG0 Output enable Timer output PPG1 Peripheral clock TIN0 Event input Reload timer:ch0 Output enable Timer output TOT0 Peripheral clock TIN1 Event input Reload timer:ch1 Output enable Timer output TOT1 Peripheral clock SCK0 UAR