CM25-10130-1E MB89950 MB89953 MB89P955 QFP-64 MB89PV950 MQFP-64 MB89951 - Datasheet Archive

 

CONTROLLER MANUAL CM25-10130-1E F2MC-8L FAMILY MICROCONTROLLERS MB89950 SERIES HARDWARE MANUAL PREFACE The MB89950 series of

 

FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM25-10130-1E CM25-10130-1E F2MC-8L FAMILY MICROCONTROLLERS MB89950 MB89950 SERIES HARDWARE MANUAL PREFACE The MB89950 MB89950 series of microcontrollers are mid-range of microcontroller. They are general-purpose and high-speed products in the F2MC-8L Family series of 8-bit singlechip microcontrollers operating at low voltages. It has UART, PWM, LCD controller and etc. This manual covers the functions and operations of the MB89950 MB89950 series of microcontrollers. Refer to the F2MC-8L Family Software Manual for instructions. iii Table of Contents 1. GENERAL . 1-1 1.1 Features .1-3 1.2 Product Series .1-4 1.3 Block Diagram .1-5 1.4 Pin Assignment .1-6 1.5 Pin Description .1-8 1.6 Handling Devices . 1-12 2. HARDWARE CONFIGURATION . 2-1 2.1 CPU .2-3 2.1.1 Memory Space .2-3 2.1.2 Arrangement of 16-bit Data in Memory Space .2-5 2.1.3 Internal Registers in CPU .2-6 2.1.4 Clock Control Block .2-9 2.1.5 Interrupt Controller .2-15 2.2 Peripherals . 2-18 2.2.1 I/O Ports .2-18 2.2.2 8-bit PWM Timer (Timer 1) .2-25 2.2.3 Pulse-width Count Timer (Timer 2) .2-30 2.2.4 UART .2-37 2.2.5 8-bit Serial I/O .2-50 2.2.6 External Interrupt .2-56 2.2.7 LCD Controller/driver .2-59 2.2.8 Time-base Timer .2-69 2.2.9 Watchdog Timer Reset .2-71 3. OPERATION . 3-1 3.1 Clock Pulse Generator .3-3 3.2 Reset .3-4 3.2.1 Reset Operation .3-4 3.2.2 Reset Sources .3-5 3.3 Interrupt .3-6 3.4 Low-power Consumption Modes .3-8 3.5 Pin States for Sleep, Stop and Reset .3-9 4. INSTRUCTIONS . 4-1 4.1 Legend .4-3 4.2 Transfer Instructions .4-4 4.3 Operation Instructions .4-5 4.4 Branch Instructions .4-6 4.5 Other Instructions .4-7 4.6 F2MC-8L Family Instruction Map .4-8 5. MASK OPTIONS . 5-1 APPENDIX . App-1 Appendix A I/O Map . App-3 Appendix B Writing EPROM . App-5 iv Tables Table 1­1 Table 1­2 Table 1­3 Table 2­1 Table 2­2 Table 2­3 Table 2­4 Table 2­5 Table 2­6 Table 2­7 Table 2­8 Table 2­9 Table 3­1 Table 3­2 Table 3­3 Table 5­1 Table 5­2 Types and Functions of MB89950 MB89950 Series of Microcontrollers .1-4 Pin Description .1-8 Pin Description for External ROM .1-9 Table of Reset and Interrupt Vectors .2-4 Operating Mode of Low-power Consumption Modes . 2-11 Selection of Oscillation Stabilization Time . 2-12 Sources of Reset . 2-14 List of Port Functions . 2-18 Operation Modes of UART .2-46 Clock Division Ratio. 2-48 Input Clock of Baud Rate Generator . 2-48 Selection of Baud Rate (When Dedicated Baud Rate Generate Used) . 2-49 Interrupt Sources and Interrupt Vectors .3-7 Low-power Consumption Mode at Each Clock Mode .3-8 Pin State of MB89950 MB89950 .3-9 Mask Options .5-3 Recommended Port/Segment Mask Option Combinations .5-3 v Figures Fig. 1.1 Block Diagram (MB89953 MB89953) .1-5 Fig. 1.2 Pin Assignment of MB89953 MB89953 and MB89P955 MB89P955 (QFP-64 QFP-64, pitch: 0.65 mm) .1-6 Fig. 1.3 Pin Assignment of MB89PV950 MB89PV950 (MQFP-64 MQFP-64, pitch: 0.8 mm) .1-7 Fig. 1.4 I/O Circuits .1-10 Fig. 2.1 Memory Space of MB89950 MB89950 Series Microcontrollers .2-3 Fig. 2.2 Arrangement of 16 bit Data in Memory Space .2-5 Fig. 2.3 Arrangement of 16 bit Data during Execution of Instruction .2-5 Fig. 2.4 Structure of Processor Status .2-7 Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area .2-7 Fig. 2.6 Register Bank Configuration .2-8 Fig. 2.7 Interrupt-processing Flowchart .2-17 Fig. 2.8 Ports 0, 1 and 2 .2-20 Fig. 2.9 Port 3 .2-22 Fig. 2.10 Port 4 .2-24 Fig. 2.11 Timer Operation .2-28 Fig. 2.12 PWM Pulse Output .2-29 Fig. 2.13 Measurement of High Pulse Width .2-35 Fig. 2.14 Operation of Noise Clearing Circuit .2-36 Fig. 2.15 RDRF Flag Set Timing .2-46 Fig. 2.16 ORFE Flag Set Timing .2-47 Fig. 2.17 TDRE Flag Set Timing .2-47 Fig. 2.18 Transfer Data Format (Synchronous Transfer) .2-47 Fig. 2.19 Shift Start/Stop Timing .2-55 Fig. 2.20 Input/Output Shift Timing .2-55 Fig. 2.21 LCD Controller /Driver Block Diagram .2-59 Fig. 2.22 Example of Waveform at Pin Corresponding to the RAM Data for Display .2-64 Fig. 2.23 Example of Waveform at Pin Corresponding to the RAM Data for Display .2-65 Fig. 2.24 Example of Waveform at Pin Corresponding to the RAM Data for Display .2-66 Fig. 2.25 Connection Examples for Supply Power for Driving LCD .2-67 Fig. 2.26 Built-in Voltage Dividing resistors .2-68 Fig. 3.1 Clock Pulse Generator .3-3 Fig. 3.2 Outline of Reset Operation .3-4 Fig. 3.3 Reset Vector Structure .3-4 Fig. 3.4 Interrupt-processing Flowchart .3-6 vi 1. GENERAL 1.1 1.2 1.3 1.4 1.5 1.6 Features . 1-3 Product Series . 1-4 Block Diagram . 1-5 Pin Assignment . 1-6 Pin Description . 1-8 Handling Devices . 1-12 GENERAL The MB89950 MB89950 series of single-chip compact microcontroller using the F2MC-8L core for which can operate at high-speeds and low voltages. They contain peripheral such as timers, UART, serial interfaces, and external interrupts, including a 168-pixel LCD controller/driver; they are best suited for use in LCD panels. 1.1 Features · High-speed processing even at low voltages Minimum instruction execution time: 0.8 µs/5 MHz (VCC = 5 V) · F2MC-8L family CPU core Instruction system most suited to controller - Multiplication and division instructions - 16-bit arithmetic operation - Instruction test and branch instruction - Bit manipulation instruction, etc. · LCD controller/driver - Maximum 42 segment outputs × 4 common outputs - Built-in LCD driver split resistor · Three-channel timer unit - 8-bit PWM timer: (usable as both reload timer and PWM timer) - 8-bit pulse width count timer: (usable as both reload timer) - 20-bit time-based counter · Two serial interfaces - 8-bit synchronous serial interface (The transfer direction can be selected to communicate with various equipment.) - UART (5, 7, and 8-bit transfers possible) · External-interrupt input: 2 channels - 2 channels can be used to clear the low-power consumption modes. (An edge-detection function is provided) · Low-power consumption modes - Stop mode (Oscillation stops to minimize the current consumption.) - Sleep mode (The CPU stops to reduce current consumption to about 30% of normal.) 1­ 3 GENERAL 1.2 Product Series Table 1­1 lists the types and functions of the MB89950 MB89950 series of microcontrollers. Table 1­1 Types and Functions of MB89950 MB89950 Series of Microcontrollers Model name Classification MB89951 MB89951 MB89953 MB89953 MB89PV950 MB89PV950 One-time programmable Mass-produced product (Mask ROM product) MB89P955 MB89P955 Piggyback/Evaluation and development product ROM capacity 4K × 8 bits (internal ROM) 8K × 8 bits (internal ROM) 16K × 8 bits (Internal PROM; writable by general-purpose writers) 32K × 8 bits (External ROM) RAM capacity 128 × 8 bits 256 × 8 bits 512 × 8 bits 1024 × 8 bits CPU function Port PWM Timer Pulse-width Counter Timer Number of basic instructions:136 Instruction bit length:8 bits Instruction length:1 to 3 bytes Data bit length:1, 8, 16 bits Minimum instruction execution time:0.8 µs at 5 MHz (VCC = 5 V) Interrupt processing time:7.2 µs at 5 MHz (VCC = 5 V) I/O port (N-ch open drain): 22 (also used as segment pin)*1 I/O port (N-ch open drain): 4 (two of them are also used as LCD bias pins) I/O port (CMOS): 7 (6 used as peripheral) Total: 33 (Maximum) 8-bit reload timer operation (toggle output possible) 8-bit resolution PWM operation Operation clock (pulse-width count timer output: 0.8 µs, 12.8 µs, 51.2 µs/5 MHz) 8-bit reload timer operation 8-bit pulse width measurement (continuous measurement, High- and Low-width measurement, and one-cycle measurement) Operation clock (0.8 µs, 3.2 µs, 25.6 µs/5 MHz) Serial I/O 8-bit length, selectable from least significant bit (LSB) first or most significant bit (MSB) first, transfer clock (external, 1.6 µs, 6.4 µs, 25.6 µs/5 MHz) UART 5-, 7-, 8-bit transfers possible, internal baud-rate generator (Max. 78125 bps/5 MHz) LCD controller/driver Common output: 4 Segment output: 42 (max.) Operation mode: 1/2 bias and 1/2 duty, 1/3 bias and 1/3 duty, 1/3 bias and 1/4 duty LCD controller display RAM capacity: 42 × 4 bits LCD driver split resistor: built-in (external resistor selectable) External Interrupt Standby Mode 2 (edge selectable: one serving as pulse-width count timer input) Sleep mode, stop mode FPT-64-M09 FPT-64-M09 Package Operation Voltage *2 EPROM 2.2 V to 6.0 V MQP-64C-P01 MQP-64C-P01 2.7 V to 6.0 V not applicable *1 Mask Option. *2 Varies according to conditions such as frequency. 1­ 4 MBM27C256A-25 MBM27C256A-25 (LCC package) GENERAL 1.3 Block Diagram Internal bus X0 X1 Main oscillator circuit Time-base timer Clock control 8-bit PWM timer P41/PWM P41/PWM P40 External interrupt Reset circuit (WDT) RST P20 to P25/ SEG36 SEG36 to SEG41 SEG41 6 8-bit pulse width count timer Port 2 Noise clear P42/PWC/ P42/PWC/ INT1 Port 4 N-ch open-drain I/O port P45/SCK P45/SCK P44/SO P44/SO P43/SI P43/SI 8-bit serial P30, P31 P46/INT0 P46/INT0 Port 3 UART N-ch open-drain I/O port P33/V2 P33/V2 P32/V1 P32/V1 CMOS I/O port N-ch open-drain I/O port R A M (256 × 8 bits) 8 P00/SEG20 P00/SEG20 to P07/SEG27 P07/SEG27 F2MC-8L Port 0/1 CPU 8 P10/SEG28 P10/SEG28 to P17/SEG35 P17/SEG35 R O M (8 K × 8 bits) LCD controller driver MODA VCC, VSS SEG0 to SEG19 SEG19 4 Other pins 20 COM0 to COM3 V3 Fig. 1.1 Block Diagram (MB89953 MB89953) 1­ 5 GENERAL 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 VCC SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Top view QFP-64 QFP-64 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 P33/V2 P33/V2 P32/V1 P32/V1 P31 P30 P40 P41/PWM P41/PWM 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P00/SEG20 P00/SEG20 P01/SEG21 P01/SEG21 P02/SEG22 P02/SEG22 P03/SEG23 P03/SEG23 P04/SEG24 P04/SEG24 P05/SEG25 P05/SEG25 P06/SEG26 P06/SEG26 P07/SEG27 P07/SEG27 P10/SEG28 P10/SEG28 P11/SEG29 P11/SEG29 P12/SEG30 P12/SEG30 P13/SEG31 P13/SEG31 P14/SEG32 P14/SEG32 P15/SEG33 P15/SEG33 P16/SEG34 P16/SEG34 P17/SEG35 P17/SEG35 P42/INT1/PWC P42/INT1/PWC P43/SI P43/SI RST P44/SO P44/SO MODA X0 X1 VSS P45/SCK P45/SCK P46/INT0 P46/INT0 P25/SEG41 P25/SEG41 P24/SEG40 P24/SEG40 P23/SEG39 P23/SEG39 P22/SEG38 P22/SEG38 P21/SEG37 P21/SEG37 P20/SEG36 P20/SEG36 1.4 Fig. 1.2 Pin Assignment of MB89953 MB89953 and MB89P955 MB89P955 (QFP-64 QFP-64, pitch: 0.65 mm) 1­ 6 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 Vcc SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 GENERAL 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 84 83 82 81 80 79 78 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 77 76 75 74 73 72 71 70 69 94 95 96 65 66 67 68 85 86 87 88 89 90 91 92 93 (Top View) SEG18 SEG18 SEG19 SEG19 SEG20/P00 SEG20/P00 SEG21/P01 SEG21/P01 SEG22/P02 SEG22/P02 SEG23/P03 SEG23/P03 SEG24/P04 SEG24/P04 SEG25/P05 SEG25/P05 SEG26/P06 SEG26/P06 SEG27/P07 SEG27/P07 SEG28/P10 SEG28/P10 SEG29/P11 SEG29/P11 SEG30/P12 SEG30/P12 SEG31/P13 SEG31/P13 SEG32/P14 SEG32/P14 SEG33/P15 SEG33/P15 SEG34/P16 SEG34/P16 SEG35/P17 SEG35/P17 SEG36/P20 SEG36/P20 RST SO/P44 SO/P44 MODA X0 X1 Vss SCK/P45 SCK/P45 INT0/P46 INT0/P46 SEG41/P25 SEG41/P25 SEG40/P24 SEG40/P24 SEG39/P23 SEG39/P23 SEG38/P22 SEG38/P22 SEG37/P21 SEG37/P21 20 21 22 23 24 25 26 27 28 29 30 31 32 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 V2/P33 V2/P33 V1/P32 V1/P32 P31 P30 P40 PWM/P41 PWM/P41 INT1/PWC/P42 INT1/PWC/P42 SI/P43 SI/P43 Fig. 1.3 Pin Assignment of MB89PV950 MB89PV950 (MQFP-64 MQFP-64, pitch: 0.8 mm) Pin assignment on package top (MB89PV950 MB89PV950 only) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 65 N.C. 73 A2 81 N.C. 89 OE 66 Vpp 74 A1 82 O4 90 N.C. 67 A12 75 A0 83 O5 91 A11 68 A7 76 N.C. 84 O6 92 A9 69 A6 77 O1 85 O7 93 A8 70 A5 78 O2 86 O8 94 A13 71 A4 79 O3 87 CE 95 A14 72 A3 80 Vss 88 A10 96 Vcc N.C.: Non connection pin. Keep open. 1­ 7 GENERAL 1.5 Pin Description Table 1­2 lists the pin functions and shows the Fig. 1.4 input/output circuits. Table 1­2 Pin Description Pin No 0.65 0.8 Pin Name 22 23 X0 23 24 22 19 20 Function X1 21 Circuit A Clock oscillator pins MODA B Operation-mode select pins This pin is connected directly to VSS with pull down resistor. RST C Reset I/O pin This pin consists of an N-ch open-drain output with a pull-up resistor and hysteresis input. A Low level is put out from this pin. A "LOW" voltage on this port generates a RESET condition. 48 to 41 49 to 42 P00/SEG20 P00/SEG20 to P07/SEG27 P07/SEG27 D N-channel open-drain type general-purpose I/O ports Also serve as LCDC controller segment outputs. Switching between port output and segment output is performed by the mask option every 8 bits. 40 to 33 41 to 34 P10/SEG28 P10/SEG28 to P17/SEG35 P17/SEG35 D N-channel open-drain type general-purpose I/O ports Also serve as LCDC controller segment outputs. Switching between port output and segment output is performed by the mask option. 32 to 27 33 to 28 P20/SEG36 P20/SEG36 to P25/SEG41 P25/SEG41 D N-channel open-drain type general-purpose I/O ports Also serve as LCDC controller segment outputs. Switching between port output and segment output is performed by the mask option. 14 to 11 15 to 12 P30 to P31 F N-channel open-drain type general-purpose I/O ports 12 to 11 13 to 12 P32/V1 P32/V1 to P33/V2 P33/V2 D N-channel open-drain type general-purpose I/O ports Also serve as LCDC controller power supply. 15 16 P40 E General-purpose I/O ports A pull-up resistor option is provided. 16 17 P41/PWM P41/PWM E General-purpose I/O port Serves as PWM timer toggle output (PWM). A pull-up resistor option is provided. 17 18 P42/PWC/ P42/PWC/ INT1 E General-purpose I/O port Also serves as pulse-width count timer input (PWC) and external interrupt input (INT1). The PWC and INT1 inputs are hysteresis type. A pull-up resistor option is provided. 18 19 P43/SI P43/SI E General-purpose I/O port Also serves as serial I/O and UART data input (SI). The SI input is hysteresis type. A pull-up resistor option is provided. 20 21 P44/SO P44/SO E General-purpose I/O port Also serves as serial I/O and UART data output (SO). A pull-up resistor option is provided. 25 26 P45/SCK P45/SCK E General-purpose I/O port Also serves as serial I/O and UART clock input/output (SCK). The SCK input is hysteresis type. A pull-up resistor option is provided. 1­ 8 GENERAL Table 1­2 Pin Description (Continued) Pin No 0.65 26 0.8 27 5 to 1 6 to 1 64 to 57 64 to 55 to 49 58 56 to 50 Pin Name Circuit Function P46/INT0 P46/INT0 E General-purpose input port Also serves as external-interrupt input (INT0). The input is hysteresis type. A pull-up resistor option is provided. SEG0 to SEG19 SEG19 G For LCDC controller segment ouput 9 to 6 7 to 10 COM0 TO COM3 G For LCDC controller common output 10 11 V3 - For LCD driver power supply 56 57 Vcc - Power Pin 24 25 Vss - Power (GND) Pin Table 1­3 Pin Description for External ROM · External EPROM pins (for MB89PV950 MB89PV950) Pins No. Pin Name I/O 66 67 68 69 70 71 72 73 74 75 77 78 79 80 82 83 84 85 86 Vpp A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 Vss 04 O5 O6 O7 O8 87 CE O 88 A10 O 89 OE O 91 92 93 94 95 96 A11 A9 A8 A13 A14 Vcc Function O For High-level output O For address output I For data input O For power supply (GND) I For data input For ROM output enable The High level is output in standby mode. For address output For ROM output enable. The Low level is always output. O For address output O For address output O For EPROM power supply 1­ 9 GENERAL Table 1­3 Pin Description for External ROM (Continued) · External EPROM pins (for MB89PV950 MB89PV950) Pins No. Pin Name I/O 65 76 81 90 N.C. - Function For internal connection Keep open. Fig. 1.4 I/O Circuits Classification A Circuit Remarks · Crystal oscillator · Feedback resistor: About 1 M/ 5 V (1 to 5 MHz) X1 X0 Standby control signal B · CMOS input · Pull down resistor (N-ch) R C · Output pull-up resistor (P-ch): · About 50 M (5 V) · Hysteresis input R P-ch N-ch D · N-ch open-drain output · CMOS input N-ch · The segment output is optional. 1­ 10 GENERAL Fig. 1.4 I/O Circuits (Continued) Classification E Circuit Remarks · CMOS output · CMOS input · Hysteresis input (peripheral input) R P-ch P-ch N-ch · The pull-up resistor is optional. F · N-ch open-drain output · CMOS input N-ch G · LCDC output 1­ 11 GENERAL 1.6 Handling Devices (1) Preventing latch-up Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium to high-voltage pins or if higher than the voltage which shows on Absolute Maximum Ratings is applied between VCC and VSS. When latch-up occurs, supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. (2) Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pulldown resistor. (3) Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated, a rapid change to the IC is therefore cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied of the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less that 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and . the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. (4) Precaution When Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (option selection) and release from stop mode. (5) Recommended Screening Conditions The OTPROM product should be screened by high-temperature aging before mounting. Verify program High-temperature aging (150°C, 48H) Read Mount The programming test cannot be performed for all bits of the preprogrammed OTPROM product due to its characteristics. Consequently, 100% programming yielding cannot be ensured. 1­ 12 2. HARDWARE CONFIGURATION 2.1 CPU . . 2-3 2.2 Peripherals . 2-18 HARDWARE CONFIGURATION This chapter describes each block of the CPU hardware. 2.1 CPU CPU This section describes the memory space and register composing CPU hardware. 2.1.1 Memory Space F2MC-8L CPU has a memory space of 64 Kilobytes. All I/O, data, and program areas are located in this space. The I/O area is near the lowest address and the data area is immediately above it. The data area can be divided into register, stack, and direct-address areas according to the applications. The program area is located near the highest address, and the tables of interrupt and reset vectors and vector-call instructions are at the highest address in this area. Fig.2.1 shows the structure of the memory space for the MB89950 MB89950 series of microcontrollers. MB89951 MB89951 0000H 0000H 0080H 0080H 00C0H 00C0H 0100H 0100H 0140H 0140H 0000H 0000H I/O Reserved MB89P955 MB89P955 MB89953 MB89953 0000H 0000H I/O I/O 0080H 0080H 0080H 0080H MB89PV950 MB89PV950 0000H 0000H RAM RAM I/O 0080H 0080H RAM RAM Register 0100H 0100H 0100H 0100H 0100H 0100H Register Register 0180H 0180H 0200H 0200H Register 0200H 0200H 0280H 0280H 0480H 0480H Vacant Vacant Vacant Vacant 8000H 8000H C000H C000H ROM E000H E000H ROM F000H F000H ROM ROM Fig. 2.1 Memory Space of MB89950 MB89950 Series Microcontrollers 2­ 3 HARDWARE CONFIGURATION (1) I/O area CPU This area is where various peripherals such as control and data registers are located. The memory map for the I/O area is given in APPENDIX A. (2) RAM area This area is where the static RAM is located. Addresses from 0100H 0100H to 017FH 017FH (0100H 0100H to 013FH 013FH in MB89951 MB89951, 0100H 0100H to 01FF0H 01FF0H in MB89P955 MB89P955 and MB89PV950 MB89PV950) are also used as the general-purpose register area. One can access these registers through register-related instructions or just treat them as ordinary RAM. (3) ROM area This area is where the internal ROM is located. Addresses from FFC0H to FFFFH are also used for the table of interrupt, reset and vector-call instructions. Table 2­1 shows the correspondence between each interrupt number or reset and the table addresses to be referenced for the MB89950 MB89950 series of microcontrollers. Table 2­1 Table of Reset and Interrupt Vectors Table address Upper data Table address Lower data Upper data Lower data CALLV #0 FFC0H FFC1H Interrupt #B FFE4H FFE5H CALLV #1 FFC2H FFC3H Interrupt #A FFE6H FFE7H CALLV #2 FFC4H FFC5H Interrupt #9 FFE8H FFE9H CALLV #3 FFC6H FFC7H Interrupt #8 FFEAH FFEBH CALLV #4 FFC8H FFC9H Interrupt #7 FFECH FFEDH CALLV #5 FFCAH FFCBH Interrupt #6 FFEEH FFEFH CALLV #6 FFCCH FFCDH Interrupt #5 FFF0H FFF1H CALLV #7 FFCEH FFCFH Interrupt #4 FFF2H FFF3H Interrupt #3 FFF4H FFF5H Interrupt #2 FFF6H FFF7H Interrupt #1 FFF8H FFF9H Interrupt #0 FFFAH FFFBH Reset mode - FFFDH Reset vector FFFEH FFFFH Note: FFFCH is already reserved. When using FFFDH in the reset mode, write 00H. 2­ 4 HARDWARE CONFIGURATION 2.1.2 Arrangement of 16-bit Data in Memory Space CPU When the MB89950 MB89950 series of microcontrollers handle 16-bit data, the data written at the lower address is treated as the upper 8-bit data and that written at the next address is treated as the lower 8-bit data as shown in Fig. 2.2. Memory Memory Before execution After execution MOVW ABCDH , A ABCFH A ABCFH ABCEH 1234H 1234H A 1234H 1234H ABCDH 34H ABCEH 12H ABCDH ABCCH ABCCH Fig. 2.2 Arrangement of 16 bit Data in Memory Space This is the same when 16 bits are specified by the operand during execution of an instruction. Bits closer to the OP code are treated as the upper byte and those next to it are treated as the lower byte. This is also the same when the memory address or 16-bit immediate data is specified by the operand. [Example] MOV A, 5678H 5678H ; Extended address MOV A, #1234H 1234H ; 16-bit immediate data Assemble XXXXH XX XX XXXXH 60 56 78 ; Extended address XXXXH E4 12 34 ; 16-bit immediate data XXXXH XX Fig. 2.3 Arrangement of 16 bit Data during Execution of Instruction Data saved in the stack by an interrupt is also treated in the same manner. 2­ 5 HARDWARE CONFIGURATION CPU 2.1.3 Internal Registers in CPU The MB89950 MB89950 series of microcontrollers have dedicated registers in the CPU and general-purpose registers in memory. The types of dedicated registers are as follows. · Program counter (PC) 16-bit length register indicating the location where instructions are stored. · Accumulator (A) 16-bit length register storing results of operations temporarily. The lower one byte is used to execute 8-bit data processing instructions. · Temporary accumulator (T) 16-bit length register where the operations are performed between this register and the accumulator. The lower one byte is used to execute 8-bit data processing instructions. · Index register (IX) 16-bit length register for index modification. · Extra pointer (EP) 16-bit length register for indicating memory address. · Stack pointer (SP) 16-bit length register indicating stack area. · Processor status (PS) 16-bit length register where register pointers and condition codes are stored. 16 bits PC Program counter A Accumulator T Temporary accumulator IX Index register EP Extra pointer SP Stack pointer PS Processor status 2­ 6 HARDWARE CONFIGURATION The 16 bits of the processor status (PS) can be divided into 8 upper bits for a register bank pointer (RP) and 8 lower bits for a condition code register (CCR). (See Fig. 2.4.) CPU 15 14 PS 13 12 11 10 RP 9 8 Vacant Vacant Vacant 7 6 H 5 I 4 3 1 0 N IL1, 0 2 Z V C CCR RP Fig. 2.4 Structure of Processor Status The RP indicates the address of the current register bank. The relationship between the contents of the RP and the real addresses is as shown in Figure 2.5. RP `0' `0' `0' `0' `0' `0' `0' Source address `1' Lower bits of OP code R4 R3 R2 R1 R0 b2 b1 b0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area The CCR has bits indicating the results of operations and transfer data contents, and bits controlling the CPU operation when an interrupt occurs. - H-flag H-flag is set when a carry or a borrow out of bit 3 into bit 4 is generated as a result of operations; it is cleared in other cases. This flag is used for decimal-correction instructions. - I-flag An interrupt is enabled when this flag is 1 and is disabled when it is 0. The I-flag is 0 at reset. - IL1 and IL0 These bits indicate the level of the currently-enabled interrupt. The CPU executes interrupt processing only when an interrupt with a value smaller than the value indicated by this bit is requested. IL1 0 0 0 1 1 0 2 1 - N-flag IL0 Interrupt level 1 3 1 High and low High low = No interrupt The N-flag is set when the most significant bit is 1 as a result of operations; it is cleared when the MSB is 0. 2­ 7 HARDWARE CONFIGURATION CPU - Z-flag Z-flag is set when zero is the result of operations; it is cleared in other cases. - V-flag V-flag is set when a two's complement overflow occurs as a result of operations; it is reset when an overflow does not occur. - C-flag C-flag is set when a carry or a borrow out of bit 7 is generated as a result of operations; it is cleared in other cases. When the shift instruction is executed, the value of the C-flag is shifted out. · General-purpose register. 8-bit length register where data are stored. 8-bit general-purpose registers are provided in the register banks in the memory for storing data. Eight registers are provided per bank for and up to 16 banks can be used for MB89953 MB89953 (8 banks are provided in MB89951 MB89951, 32 banks are provided in MB89P955 MB89P955 and MB89PV950 MB89PV950). The register bank pointer (RP) indicates the currently-used bank. Note: The register banks are as follows depend on RAM area. MB89951 MB89951 MB89953 MB89953 MB89P955 MB89P955 MB89PV950 MB89PV950 0100H 0100H to 013FH 013FH 0100H 0100H to 017FH 017FH 0100H 0100H to 01FFH 01FFH 0100H 0100H to 01FFH 01FFH Address = 0100H 0100H + 8*(RP) 8 banks 16 banks 32 banks 32 banks R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area Fig. 2.6 Register Bank Configuration 2­ 8 HARDWARE CONFIGURATION 2.1.4 Clock Control Block CPU This block controls the standby operation and software reset. (1) Machine clock control block diagram (a) Machine clock control section STP SLP SPL Pin state Stop Clock oscillator CPU operation clock Clock control Peripheral operation clock HC1 From time-base timer HC3 Stop release signal Selector Option (b) Reset control section Power-on reset Watchdog timer reset External reset Software reset Internal reset signal Reset control (2) Register list 8 bits Address: 0008H 0008H STBC 2­ 9 Standby control register HARDWARE CONFIGURATION CPU (3) Description of registers The detail of each register is described below. Address: 0008H 0008H STBC (a) Standby control register (STBC) Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STP SLP SPL RST - - - - (W) Address: 0008H 0008H Bit 6 (W) (R/W) (W) (Initial value) 0001XXXXB 0001XXXXB [Bit 7] STP: Stop bit This bit is used to specify switching CPU to the stop mode. 0 No operation 1 Stop mode This bit is cleared at reset or stop cancellation. 0 is always read when this bit is read. [Bit 6] SLP: Sleep bit This bit is used to specify switching the CPU to the sleep mode. 0 No operation 1 Sleep mode This bit is cleared at reset, sleep cancellation or stop cancellation. 0 is always read when this bit is read. [Bit 5] SPL: Pin state specifying bit This bit is used to specify the external pin state in the stop mode. 0 Holds pin state and level immediately before stop mode 1 High impedance This bit is cleared at reset. [Bit 4] RST: Software reset bit This bit is used to specify the software reset. 0 Generates 4-cycle reset signal 1 No operation 1 is always read when this bit is read. 2­ 10 HARDWARE CONFIGURATION CPU (4) Description of operation (a) Low-power consumption mode This chip has three operation modes shown in the table below. The sleep mode and stop mode reduce the power consumption. The system clock can be selected out of three according to the system condition to minimize power consumption. Table 2­2 Operating Mode of Low-power Consumption Modes Oscillation mode RUN SLEEP STOP Clock pulse Oscillates Stop Each operating clock pulse (5 MHz clock) Time-base Each CPU timer peripheral 2.5 MHz 2.5 MHz 2.5 MHz Stops Stops Stops Wake-up source in each mode Various interrupt requests External interrupt · The SLEEP mode stops only the operating clock pulse of the CPU; other operations are continued. · The STOP mode stops the oscillation. Data can be held with the lowest power consumption in this mode. a. SLEEP mode · Switching to Sleep mode - Writing 1 at the SLP (bit 6) of the STBC register switches the mode to SLEEP mode. - The SLEEP mode is the mode to stop clock pulse operating the CPU; only the CPU stops and the peripherals continue to operate. - If an interrupt is requested when 1 is written at the SLP (bit 6), instruction execution continues without switching to the SLEEP mode. - In the SLEEP mode, the contents of registers and RAM immediately before entering the SLEEP mode are held. · Canceling SLEEP mode - The SLEEP mode is canceled by inputting the reset signal or requesting an interrupt. - When the reset signal is input during the SLEEP mode, the CPU is switched to the reset state and the SLEEP mode is canceled. - When an interrupt level higher than 11 is requested from a peripheral during the SLEEP mode, the SLEEP mode is canceled. - When the I flag and IL bit are enable after canceling, the CPU executes the interrupt processing like an ordinary interrupt. When they are disabled, the CPU starts processing the next instruction given before entering the SLEEP mode. 2­ 11 HARDWARE CONFIGURATION CPU b. STOP mode · Switching to STOP mode - Writing 1 at the STP (bit 7) of the STBC register switches the mode to STOP mode. - The STOP mode stops clock oscillation and the CPU and all peripherals stop. - The input/output pins and output pins in the STOP mode can be controlled by the SPL (bit 5) of the STBC register so that they are held in the state immediately before entering the STOP mode, or so that they enter in the high-impedance state. - If an interrupt is requested when 1 is written at the STP (bit 7), instruction execution continues without switching to the STOP mode. - In the STOP mode, the contents of registers and RAM immediately before entering the STOP mode are held. · Canceling STOP mode - The STOP mode is canceled either by inputting the reset signal or by requesting an interrupt. - When the reset signal is input during the STOP mode, the CPU is switched to the reset state and the STOP mode is canceled. - When an interrupt higher than level 11 is requested from the external interrupt circuit during the STOP mode, the STOP mode is canceled. - When the I flag and IL bit are enabled after canceling, the CPU executes the interrupt processing like an ordinary interrupt. When they are disabled, the CPU starts processing the next instruction given before entering the STOP mode. - The oscillation stabilization time can be selected from the two types in Table 2­3 as options. - If the STOP mode is canceled by inputting the reset signal, the CPU is switched to the oscillation stabilization state. Therefore, the reset sequence is not executed unless the oscillation stabilization time is elapsed. The oscillation stabilization time corresponds to the optionally selected oscillation stabilization time of the main clock. However, when Power-on reset unavailable is selected by the mask option, the CPU is not switched to the oscillation stabilization state even if the STOP mode is canceled by inputting the reset signal. Table 2­3 Selection of Oscillation Stabilization Time Oscillation stabilization time Oscillation stabilization time at 5 MHz Remarks About 218/fCH About 52.4 ms For crystal oscillator About 214/fCH About 3.28 ms For crystal oscillator 2­ 12 HARDWARE CONFIGURATION (b) State transition diagram CPU SLEEP Clock oscillates. (9) STOP Clock stops. (7) (5) (4) (8) RUN Clock oscillates. (3) Oscillation stabilization waiting (1) (2) Power-on (1) (2) (3) (4) (5) (7) (8) (9) When power-on reset available selected When power-on reset unavailable selected After oscillation stabilizing Set STP bit to 1. Set SLP bit to 1. External reset when power-on reset unavailable selected External reset or interrupt when power-on reset available selected External reset or interrupt 2­ 13 HARDWARE CONFIGURATION CPU (c) Reset There are four types of reset depending on the source shown in Table 2­4. Table 2­4 Sources of Reset Reset name Description External-pin reset When setting external-reset pin to Low Software reset When writing 0 at RST (bit 4) of STBC Watchdog reset When watchdog timer overflows Power-on reset When turning power on When the power-on reset or reset during the stop state is used, the oscillation stabilization time is needed after the oscillator starts operating. The time-base timer controls this stabilization time. Consequently, the operation does not start immediately even after canceling the reset. However, if Power-on reset is not selected by the mask option, no oscillation stabilization time is required in any state after external pins have been released from the reset. Note: A longer time than the optionally-specified oscillation stabilization time should be allowed for reset at power-on of Power-on reset unavailable products. In other cases, the time is based on theorist timing given in the MB89950 MB89950 SERIES DATA SHEET "AC characteristics." 2­ 14 HARDWARE CONFIGURATION 2.1.5 Interrupt Controller CPU The interrupt controller for the F2MC-8L family is located between the CPU and each peripheral. This controller receives interrupt requests from the peripherals, assigns priority to them. When the interrupt controller transfers the priority to the CPU, it also decides the priority of same-level interrupts. (1) Block diagram CPU F2MC-8L bus 2 Address decoder Test register Peripheral #1 G L Level Peripheral #2 G L Level · · · · · · · · G L Peripheral #n · · · G · · · Level deciding block Level G Same level priority deciding block · · · Interrupt vector generation block G (2) Register list Interrupt controller consists of interrupt-level registers (ILR1, 2, and 3) and interrupt-test register (ITR). 8 bits Address: 007CH 007CH ILR1 W Interrupt level register #1 Address: 007DH 007DH ILR2 W Interrupt level register #2 Address: 007EH 007EH ILR3 W Interrupt level register #3 Address: 007FH 007FH ITR - Interrupt test register 2­ 15 HARDWARE CONFIGURATION (3) Description of registers CPU The details of each register is described below. Address: 007CH 007CH (a) Interrupt level register 1 to 3 (ILRx: Interrupt Level Register x) ILR1 Bit 7 Address: 007DH 007DH Address: 007EH 007EH Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L31 L30 L21 L20 L11 L10 L01 L00 Address: 007DH 007DH L71 L70 L61 L60 L51 L50 L41 L40 LB1 LB0 LA1 LA0 L91 L90 L81 L80 (W) ILR3 Bit 5 Address: 007CH 007CH ILR2 Bit 6 (W) (W) (W) (W) (W) (W) (W) Address: 007EH 007EH Address: 007FH 007FH ITR (Initial value) 11111111B 11111111B The ILRx sets the interrupt level of each peripheral. The digits in the center of each bit correspond to the interrupt numbers. MB89820 MB89820 hardware manual [Example] L3X Interrupt number Interrupt control module Table address #0 #1 #2 #3 Interrupt requests from peripherals Upper FFFA FFF8 FFF6 FFF4 Lower FFFB FFF9 FFF7 FFF5 #11 IR0 IR1 IR2 IR3 FFE4 FFE5 IRB [Bits 7 and 6][Bits 5 and 4][Bits 3 and 2][Bits 1 and 0]Lx1, Lx0: Interrupt level setting bit Lx1 Lx0 Required interrupt level 0 X 1 1 0 2 1 1 3 (None) When an interrupt is requested from a peripheral, the interrupt controller transfers the interrupt level based on the value set at the 2 bits of the ILRx corresponding to the interrupt to the CPU. Address: 007CH 007CH ILR1 (b) Interrupt test register (ITR) Bit 7 ILR2 Address: 007EH 007EH ITR Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - * * (-) ILR3 Address: 007FH 007FH Bit 5 (-) Address: 007DH 007DH Bit 6 Address: 007FH 007FH (Initial value) XXXXXX00B XXXXXX00B The ITR is used for testing. Do not access it. 2­ 16 HARDWARE CONFIGURATION (4) Description of operation CPU The functions of interrupt controllers are described below. (a) Interrupt functions The MB89950 MB89950 series of microcontrollers have 7 inputs for interrupt requests from the peripherals. The interrupt level is set by 2-bit registers corresponding to each input. When an interrupt is requested from a peripheral, the interrupt controller receives it and transfers the contents of the corresponding level register to the CPU. The interrupt to the device is processed as follows: (1) An interrupt source is generated inside a peripheral. (2) If an interrupt is enabled after referring to the interrupt-enable bit inside the peripheral, an interrupt request is output from the peripheral to the interrupt controller. (3) After receiving this interrupt request, the interrupt controller determines the priority of simultaneously-requested interrupts and then transfers the interrupt level for the applicable interrupt to the CPU. (4) The CPU compares the interrupt level requested from the interrupt controller with the IL bit in the processor status register. (5) As a result of the comparison, if the interrupt level has priority over the current interrupt processing level, the contents of the I-flag in the same processor status register are checked. (6) As a result of the check in step (5), if the I-flag is enabled for an interrupt, the contents of the IL bit are set to the required level. As soon as the currently-executing instruction is terminated, the CPU performs the interrupt processing and transfers control to the interrupt-processing routine. (7) When an interrupt source is cleared by software in the user's interrupt processing routine, the CPU terminates the interrupt processing. Fig. 2.7 outlines the interrupt operation for the MB89950 MB89950 series of microcontrollers. Internal bus Register file IPLA PS IR (6) I IL Check Comparator (5) (4) CPU (3) Peripheral Level comparator Enable FF AND (7) Source FF (1) (2) Peripheral Interrupt controller Fig. 2.7 Interrupt-processing Flowchart 2­ 17 HARDWARE CONFIGURATION 2.2 Peripherals Peripherals 2.2.1 I/O Ports · The MB89950 MB89950 series of microcontrollers have five parallel ports (33 pins). Ports 0 and 1 serve as 8-bit I/O ports; port 2 serves 6-bit I/O port; port 3 serves as 4-bit I/O ports; port 4 serves as 7-bit I/O port. · Ports 0, 1, 2, 3 and 4 are also used as peripherals. (1) List of port functions Table 2­5 List of Port Functions Pin Input Type P00 to P07 P10 to P17 P20 to P25 CMOS P30 to P33 CMOS P40 to P45 CMOS CMOS CMOS Hysteresis Output Type N-ch open drain N-ch open drain N-ch open drain Function Parallel port 0 Segment output Parallel port 1 Segment port 1 Parallel port 2 N-ch Parallel port 3 open drain LCD voltage CMOS push-pull Parallel port 4 Timer serial/external interrupt bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P07 P06 P05 P04 P03 P02 P01 P00 SEG 27 - SEG20 SEG20 P17 P16 P15 P14 P13 P12 P11 P10 SEG 35 - SEG28 SEG28 - - P25 P24 P23 P22 P21 P20 - - - - - - - - SEG41 SEG41 - SEG36 SEG36 - - - - P33 P32 P31 P30 V2 V1 - - P46 P45 P44 P43 P42 P41 P40 INT0 SCK SO SI PWC PWM /INT1 - (2) Register list I/O port consists of the following registers. 8 bits Address: 0000H 0000H PDR0 R/W Port 0 data register Initial value = 11111111B 11111111B Address: 0002H 0002H PDR1 R/W Port 1 data register Initial value = 11111111B 11111111B Address: 0004H 0004H PDR2 R/W Port 2 data register Initial value = 11111111B 11111111B Address: 000CH 000CH PDR3 R/W Port 3 data register Initial value = 11111111B 11111111B PDR4 R/W Port 4 data register Initial value = XXXXXXXXB DDR4 W Initial value = X0000000B X0000000B Address: 000EH 000EH Address: 000FH 000FH Port 4 data direction register 2­ 18 HARDWARE CONFIGURATION Peripherals (3) Description of functions The function of each port is described below. P00 to P07: N-ch open-drain type input/output ports (also used as segment output) P10 to P17: N-ch open-drain type input/output ports (also used as segment output) P20 to P25: N-ch open-drain type input/output ports (also used as segment output) · Operation for output port The value written at the PDR is output to the pin. When the PDR is read, usually, the value of the pin is read instead of the contents of the output latch. However, when the Read Modify Write instruction is executed, the contents of the output latch are read. Therefore, the bit-processing instruction can be used even if input and output are mixed with each other. · Operation for input port When using these ports as input ports, set 1 at the PDR and turn the output transistor off. The value of the pin can always be read when the PDR is read. When the segment output is selected by the LCD controller port/segment select bit, the input data is always read as 0. · Operation for segment output When using these ports as segment outputs, the segment output must be selected by the mask option. When segment output is selected using the LCD controller port/segment select bit, these ports can be used as segment outputs. · State at reset At reset, these ports serve as port inputs. The PDR is initialized to 1 and the output transistor is turned off at all bits. · State in stop mode For segment output, the output state when the CPU enters the stop mode is held. For port output, the pins states in stop mode are controlled by SPL bit in standby control register (STBC). When SPL=0, pin states before entering stop mode are held. When SPL=1, port pins go high impedance in stop mode. 2­ 19 HARDWARE CONFIGURATION Peripherals Internal-data bus Segment output Segment output select register PDR Mask option (Note) Stop, SPL = 1 PDR read Pin PDR read (when Read Modify Write instruction executed) Output latch N-ch PDR write Stop, SPL = 1 Fig. 2.8 Ports 0, 1 and 2 Note: Selection of segment output using the mask option is available only for mass-produced products. The mask option must be consistent with LCD segment output select register (SEGR). 2­ 20 HARDWARE CONFIGURATION Peripherals P30, P31: P32, P33: N-ch open-drain output, CMOS input N-ch open-drain type input/output ports (also used as LCD controller power supply V1,V2) · Operation for output port The value written at the PDR is output to the pin. When the PDR is read, usually, the value of the pin is read instead of the contents of the output latch. However, when the Read Modify Write instruction is executed, the contents of the output latch are read. Therefore, the bit-processing instruction can be used even if input and output are mixed with each other. · Operation for input port When using these ports as input ports, set 1 at the PDR and turn the output transistor off. The value of the pin can always be read when the PDR is read. When V1/V2 is selected by PSEL bit of LCDR, the input data is always read as 0. · Operation for V1 and V2 The PSEL bit in LCDR (see page 2-60) must be cleared in order to choose P32/P33 P32/P33 as LCD controller power supply. · State at reset At reset, these ports serve as LCD controller power supply. The PDR is initialized to 1 and the output transistor is turned off at all bits. Since PSEL bit of LCDR will be reset to zero (see page 2-60), therefore P32/P33 P32/P33 will be configured to V1/V2 right after reset. · State in stop mode If P32/P33 P32/P33 is chosen as V1/V2 and stop mode is triggered, the voltage at those pins before stop mode will be held. For port output, the pins states in stop mode are controlled by SPL bit in standby control register (STBC). When SPL=0, pin states before entering stop mode are held. When SPL=1, port pins go high impedance in stop mode. 2­ 21 HARDWARE CONFIGURATION Internal-data bus Only for P32 and P33 PSEL of LCDR V1/ V2 PDR Stop PDR read Pin PDR read (when Read Modify Write instruction executed) Output latch N-ch PDR write Stop, SPL = 1 Fig. 2.9 Port 3 2­ 22 HARDWARE CONFIGURATION Peripherals P40 to P46: CMOS type I/O ports (also used as peripheral input and output) · Switching input and output This port has a data-direction register (DDR) and a port-data register (PDR) for each bit. Input and output can be set independently for each bit. The pin with the DDR set to 1 is set to output, and the pin with the DDR set to 0 is set to input. When the peripheral output bit is enabled, these ports are set to output irrespective of the DDR setting conditions. · Operation for output port (DDR = 1) The value written at the PDR is output to the pin where the DDR is set to 1. When the PDR is read, usually, the value of the pin is read instead of the contents of the output latch. However, when the Read Modify Write instruction is executed, the contents of the output latch are read irrespective of the DDR setting conditions. Therefore, the bit-processing instruction can be used even if input and output are mixed with each other. When data is written to the PDR, the written data is held in the output latch irrespective of the DDR setting conditions. · Operation for input port (DDR = 0) When used as the input port, the output impedance goes High. Therefore, when the PDR is read, the value of the pin is read. · Peripheral output operation When using as the peripheral output, setting is performed by the peripheral output enable bit (See the description of each peripheral). The peripheral output enable bit has priority in switching input and output. Even if the output from each peripheral is enabled, the read value of the port is effective, so the peripheral output value can be checked. · Peripheral input operation The pin value at a port with the peripheral input function is always input for the peripheral input irrespective of the setting of the DDR and peripheral. Set the DDR to input when using an external signal for the peripheral input. · State when reset When reset, the DDR is initialized to 0 and the output impedance goes High at all bits. When reset, the PDR is not initialized. Therefore, set the value of the PDR before setting the DDR to output. · State in stop mode With the SPL bit of the standby-control register set to 1, the output impedance goes High in stop mode irrespective of the value of the DDR. 2­ 23 HARDWARE CONFIGURATION Peripherals External interrupt enable Stop, SPL = 1 To external interrupt Stop, SPL = 1 Peripheral input Internal-data bus Pull-up resistor (option) Peripheral Peripheral output output enable PDR PDR read P-ch PDR read (when Read Modify Write instruction executed) Output latch P-ch PDR write Pin DDR N-ch DDR write Stop, SPL = 1 Fig. 2.10 Port 4 2­ 24 HARDWARE CONFIGURATION 2.2.2 8-bit PWM Timer (Timer 1) Peripherals · This timer can be used as an 8-bit timer or PWM control circuit with 8-bit resolution. · Four kinds of clock frequency can be selected. (1) Block diagram Internal-data bus P/T CNTR P/T COMR - P1 P0 TRE TIR 0E TIE Compare register Start 8-bit counter CLK IRQ2 8 CLEAR OVER FLOW 8 Timer/ PWM Selector Comparator 1/2 CPU clock pulse* 1/32 1/128 PWM generator and output control Timer-2 output (PWC timer) Output P41/PWM P41/PWM * CPU clock pulse is 1/2 oscillation. (2) Register list 8 bits CNTR Address: 0013H 0013H 2­ 25 R/W Control register COMR Address: 0012H 0012H W Compare register Output enable signal HARDWARE CONFIGURATION Peripherals (3) Description of registers (a) Control register (CNTR) Bit 7 Address: 0012H 0012H Address: 0013H 0013H COMR Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P/T Address: 0012H 0012H CNTR - P1 P0 TPE TIR OE TIE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (Initial value) 0X000000B 0X000000B [Bit 7] P/T: Timer/PWM operation mode switching bit The operation is performed as the timer when bit 7 is set to 0, and as the 0 Timer 1 PWM control circuit When switching, set channel to stop counting (TPE = 0), interrupt disabled (TIE = 0) and interrupt request flag cleared (TIR = 0). [Bits 5 and 4] P1 and P0: Clock-pulse select bits Clock pulses from the prescaler or WT0 output of timer 2 (pulse-width count timer) can be selected using P1 and P0. P1 P0 Clock cycle 0 0 Internal clock pulse 1 instruction cycle 0 1 Internal clock pulse 16 instruction cycles 1 0 Internal clock pulse 64 instruction cycles 1 1 Timer 2 cycle Note that these bits must not be rewritten when the counter is operating (TPE = 1). [Bit 3] TPE: Counting enable bit When these bits are set to 1, the timer or PWM control circuit starts operation. 0 Stops counting 1 Starts counting [Bit 2] TIR1: PWM channel interrupt request flag bit Bit 2 goes to 1 when an interrupt source occurs. To clear the generated interrupt source, write 0 at this bit. The meaning of bit to be read is as follows: 2­ 26 HARDWARE CONFIGURATION 0 Values of counter and COMR do not match. 1 Values of counter and COMR match. Note that 1 is always read when the Read Modify Write instruction is executed. Peripherals The meaning of each bit to be written is as follows: 0 Clears this bit 1 Does not change this bit nor affect other bits Note: In the PWM operation mode, neither the read nor write values of these bits have any meaning. [Bit 1] OE: Output signal control bit When bit 1 is 1, the port serves as the PWM timer output. In the timer operation mode, a signal that is reversed each time the values of the counter and the compare register match is output. In the PWM operation mode, a PWM signal is output. 0 General-purpose ports (P41) 1 Counter/PWM output pins (PWM) Even if the DDR of P41 is set for input (bit 1 of DDR4 is set to 1), when this bit is 1, it serves as the counter/PWM output pin. [Bit 0] TIE: Interrupt enable bit (Timer mode) If bit 0 is set to 1, an interrupt occurs when the values of the counter and the compare register match. 0 Disables counter interrupt output 1 Enables counter interrupt output However, in the PWM operation mode, an interrupt does not occur irrespective of the value of this bits. Address: 0012H 0012H CNTR Address: 0013H 0013H COMR (b) Compare register (COMR) This register holds the value to be compared with the counter value in the timer operation mode, and also clears the counter when the value agrees with the counter value. In the PWM operation mode, the High pulse width can be specified by this register value. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (W) (W) (W) (W) (W) (Initial value) XXXXXXXXB (W) (W) (W) Address: 0013H 0013H 2­ 27 HARDWARE CONFIGURATION Peripherals (4) Description of operation (a) Timer function Setting the P/TX bit of the CNTR to 0 gives the timer-operation mode. When the TPE bit of the CNTR is set to 1, the counter starts incrementing from 00H. When the value of the counter agrees with that of the COMR, the counter is cleared on the next count clock pulse and incrementing restarts. Therefore, the TIR bits are set and the output pin is reversed (but, when the TPE bit is 0, the output pin is fixed at Low level) in cycles of the count clock pulses when 00H is written at the COMR, or in cycles 256 times longer than those of the count clock pulses when FFH is written. If the value of the COMR is rewritten in the timer-operation mode, it becomes effective from the next cycle (when the value of the counter is 00H, the value of the COMR is transferred to the comparator latch). Count-clock pulse 00 00 00 00 00 01 FF 00 TPE P41/PWM P41/PWM TIR bit setting Value of COMR 00 FF Fig. 2.11 Timer Operation If the TIE bit of the CNTR is set to 1, an interrupt occurs when the values of the counter and COMR match. During interrupt processing, the TIR bit is used as the interrupt flag. The TIR bit is set irrespective of the value of the TIE bit. However, if the values of the counter and COMR match, the TIR bit is set to 1 even after an interrupt is disabled. Writing 0 at the TIR bit permits clearing of the interrupt source or the TIR bit. When the Read Modify Write instruction is read, the TIR bit is set so that 1 can always be read to prevent erroneous clearing. By using P0 and P1 bit in CNTR, 1 out of 4 clock sources can be selected for the counter. 2­ 28 HARDWARE CONFIGURATION (b) PWM operation Peripherals Setting the P/TX bit of the CNTR to 1 gives the PWM operation mode. The COMR specifies the duty of the output pulse. Pulses can be output with 1/256 resolution and a duty of 0% to 99.6%. When 0 (00H) is written at the COMR, the duty of the PWM output pulse is 0%; when 128 (80H) is written, the duty is 50%, and when 255 (FFH) is written, it is 99.6%. The value of COMR is transferred to the comparator latch when the value of the counter is 00H. If the value of the COMR is rewritten in the PWM operation mode, it becomes effective from the next cycle. At starting (counter = 00), output is high. When the counter matches the compare register, output goes low. · When COMR is 00H 00H ········· 00H Counter value ····· ······· FFH 00H PWM pulse output · When COMR is 80H Counter value ····· 80H ····· ····· FFH 00H ····· ····· 80H PWM pulse output comparison match · When COMR is FFH Counter value 00H ········· ········· FFH 00H Fig. 2.12 PWM Pulse Output In the PWM operation mode, the values at the TIR bit of the CNTR have no meaning. No interruption occurs even if the TIE bit are 1. The cycle of the PWM pulse can be changed by switching the count clock pulse. The count clock pulse can be selected from three clock pulses of the prescaler and the clock pulse of the internal timer by the clock pulse select bits P1 and P0 of the CNTR. 2­ 29 HARDWARE CONFIGURATION 2.2.3 Pulse-width Count Timer (Timer 2) Peripherals · This timer has timer and pulse-width measurement functions. · The timer function has two modes: reload timer and one-shot. · In the reload timer mode, the set values are counted down repeatedly. · In the one-shot mode, counting down is started from the set values and stops at the first underflow. · The pulse-width measurement function enables measurement of High, Low, or one-cycle widths of pulses input from pins. · For inputting from pins, the 5-bit noise-clearing circuit is selectable. (1) Block diagram Internal-data bus PCR2 To PWM timer NCCR IRQ3 PCR1 From time-base timer Function switching circuit Selector Timing generator Input-pulse edge detector 8-bit down counter Noise clear 1/2 1/8 RLBR 1/64 CPU clock pulse* Selector * The CPU clock pulse is an oscillation-divided pulse. 2­ 30 P42/PWC/ P42/PWC/ INT1 HARDWARE CONFIGURATION Peripherals (2) Register list 8 bits Address: 0014H 0014H PCR1 R/W Pulse-width control register 1 Address: 0015H 0015H PCR2 R/W Pulse-width control register 2 Address: 0016H 0016H RLBR R/W Reload buffer register Address: 0017H 0017H NCCR R/W Noise-clear control register (3) Description of registers Address: 0014H 0014H PCR1 (a) Pulse-width control register 1 (PCR1) Bit 7 Address: 0015H 0015H PCR2 Address: 0016H 0016H RLBR Address: 0017H 0017H NCCR Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN - IE - - UF IR BF (R/W) Address: 0014H 0014H Bit 6 (R/W) (R/W) (R/W) (R/W) (R) (Initial value) 000XX000B 000XX000B [Bit 7] EN: Count enable bit At the timer function, when 1 is written at this bit, the value of the data register is loaded to start counting down. When 0 is written, counting down stops. At the pulse-width measurement function, when 1 is written at this bit, the measurement-enable state is set. Under this condition, counting down is started when the edge of the measured pulse is detected. When 0 is written at this bit during measurement, counting down stops; the count is not transferred to the reload buffer register (RLBR). Timer function Pulse-width measurement function 0 Count disable Pulse-width measurement stop/disable 1 Count enable/start Pulse-width measurement enable/start [Bit 5] IE: Interrupt request enable bit When bit 5 is 1, an interrupt request is output when the interrupt request flags (UF, IR, and BF) are set. 0 Interrupt disabled 1 Interrupt enabled [Bit 2] UF: Underflow interrupt request bit Bit 2 indicates whether the timer underflowed. The meaning of each bit to be read is as follows: 0 No underflow 1 Underflow occurred 2­ 31 HARDWARE CONFIGURATION Peripherals 1 is always read when the Read Modify Write instruction is executed. The meaning of each bit to be written is as follows: 0 Clears this bit 1 Unchanges this bit and other bits unaffected [Bit 1] IR: Measurement-end interrupt request bit When the IE bit (bit 5) of the PCR1 is 1, an interrupt occurs at the end of pulse-width measurement. The meaning of each bit to be read is as follows: 0 Pulse-width measurement not terminated 1 Pulse-width measurement terminated 1 is always read when the Read Modify Write instruction is executed. The meaning of each bit to be written is as follows: 0 Clears this bit 1 Unchanges this bit and other bits unaffected [Bit 0] BF: Buffer-full flag When the IE bit (bit 5) of the PCR1 is 1, an interrupt occurs when any measured value is found in the RDBR. This bit is set at the end of pulsewidth measurement and cleared when data in the buffer is read. The meaning of each bit to be read is as follows: 0 1 Address: 0014H 0014H PCR1 Pulse-width measured value not found Pulse-width measured value found (b) Pulse-width control register 2 (PCR2) Bit 7 Address: 0015H 0015H PCR2 Address: 0016H 0016H RLBR Address: 0017H 0017H NCCR Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FC RM TO - C1 C0 W1 W0 (R/W) Address: 0015H 0015H Bit 6 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (Initial value) 000X0000B 000X0000B [Bit 7] FC: Function select bit Bit 7 is used to select the timer and pulse-width measurement functions. 0 Timer function 1 Pulse-width measurement function One should not change the function select bit when timer function is enabled (EN=1). 2­ 32 HARDWARE CONFIGURATION [Bit 6] RM: Timer mode select bit In the timer function, bit 6 is used to select the timer mode. Peripherals 0 Reload timer mode 1 One-shot timer mode The mode should be changed only when the operation is stopped (when the EN bit (bit 7) of the PCR1 is 0). [Bit 5] TO: Timer output bit The value of bit 5 is inverted each time the counter underflows. Bit 5 is a write bit; it must not be rewritten when the EN bit (bit 7) of the PCR1 is 1. [Bits 3 and 2] C1 and C2: Count clock pulse select bits Setting is performed as shown below using a combination of bits 3 and 2. These bits are irrelevant to the value of the FC bit (bit 7). C1 C0 Count clock pulse 0 0 Internal clock pulse 1 instruction cycle 0 1 Internal clock pulse 4 instruction cycles 1 0 Internal clock pulse 32 instruction cycles 1 1 Do not set. [Bits 1 and 0] W1 and W0: Measured pulse select bits Setting is performed as shown below using a combination of bits 1 and 0. These bits are ignored when the timer is in operation (FC = 0). W1 0 1 Low level 0 Rising-to-rising 1 Address: 0016H 0016H RLBR High level 1 Address: 0015H 0015H PCR2 0 0 Address: 0014H 0014H PCR1 W0 Measured pulse width 1 Falling-to-falling (c) Reload buffer register (RLBR) At the timer function, the RLBR is a read-and-write reload register. At pulsewidth measurement, it is a read-only data buffer register for holding the measured values. In this case, writing is impossible. The BF bit (bit 0) of the PCR1 is cleared by reading data. Bit 7 Address: 0017H 0017H NCCR Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R) (R) (R) (R) (R) (R) Address: 0016H 0016H Timer function Pulse-width measurement function 2­ 33 (R) (R) (Initial value) XXXXXXXXB HARDWARE CONFIGURATION (d) Noise-clear control register (NCCR) Peripherals Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - NCS1 NCS0 (R/W) (R/W) Address: 0017H 0017H Address: 0014H 0014H PCR1 (Initial value) -00B Address: 0015H 0015H PCR2 Address: 0016H 0016H RLBR Address: 0017H 0017H NCCR [Bits 1 and 0] NCS1 and NCS0: Sampling clock pulse select bits The sampling clock pulse of the noise-clearing circuit is selected as shown NCS1 NCS0 Clock pulse selected Clock cycle at 5MHz Noise pulse width 0 0 No noise clear - - 0 1 Oscillation clock pulse × 4 0.8 [µs] 4.0 [µs] 1 0 Oscillation clock pulse × 32 12.8 [µs] 64 [µs] 1 1 Oscillation clock pulse × 128 51.2 [µs] 256 [µs] (4) Description of operation (a) Timer function The timer function has the following two modes. a. Reload timer mode Each time the counter underflows, the value written at the RLBR is reloaded to continue counting down. In this mode, when the counter underflows, the interrupt request flag UF (bit 2) is set. An interrupt request is also output when the IE bit (bit 5) is set to 1. Each time the timer underflows, the value of the TO bit (bit 5) is inverted. b. One-shot mode Counting stops at an underflow. In this mode, when the counter underflows, the underflow interrupt request flag UF (bit 2) is set and the EN bit (bit 7) is automatically set to 0 to stop counting. In both modes, counting starts when 1 is written at the EN bit (bit 7) and stops when 0 is written. 2­ 34 HARDWARE CONFIGURATION Peripherals (b) Pulse-width measurement function a. Measurement start Writing 1 at the EN bit (bit 7) and FC bit (bit 7) causes the counter to enter the operation-enabled state. In this condition, counting starts when the edge of the measured pulse input is detected. At the pulse-width measurement function, counting down is started from FFH. b. Measurement end and measured value When measurement is terminated, the measured value is transferred to the buffer, and the measurement-end flag IR (bit 1) and buffer-full flag BF (bit 0) are set. causing the counter to re-enter the operation-enabled state. At this time, an interrupt request is output when the IE bit (bit 5) is set to 1. When the previous measured value cannot be read after continuous pulse-width measurement, it is held by continuing to set the BF flag. The new measured value is discarded. c. Long pulse When the counter underflows during measurement, the UF bit (bit 2) is set to 1 to continue counting. In this case, an interrupt request is also output when the IE bit (bit 5) is set to 1. d. Measurement stop Measurement stops when 0 is written at the EN bit (bit 7). e. Calculation of pulse width The count value when measurement is terminated is transferred as the measured value to the buffer. Therefore, the pulse width should be calculated using the following equation. Pulse width = [(256 ­ count value) + (Number of TO counts inverted × 256)] × one cycle width of count clock pulse f. Others The counter remains in the operation-enabled state even after the end of measurement, so continuous pulse-width measurement is possible. Measurement of a High pulse width is started from the changing edge of the input pulse. If the EN bit is enabled (EN = 1) when the input pulse is already High, counting is performed after the next rising edge. Input pulse EN signal Count stop Count Fig. 2.13 Measurement of High Pulse Width 2­ 35 HARDWARE CONFIGURATION Peripherals (c) Noise-clearing circuit operation Figure 2.15 shows the operation of the noise-clearing circuit. The PWC input is sampled by the clock pulse selected by the clock pulse select bits (NCS1 and NCS0) of the noise-clear control register. Integrating the sampled signal clears the noise. The maximum width of cleared noise is as follows: Nw = Sampling clock cycle × 5 When noise clearing is prohibited, the PWC input is input directly to the pulse-width count timer. PWC input Sampling clock pulse Integrated value Internal signal Fig. 2.14 Operation of Noise Clearing Circuit (5) Usage precautions (a) Do not rewrite the value of PCR2 when the EN bit is 1 (during timer operation and pulse-width measurement). (b) At mode switching (FC bit rewriting), the state of each flag does not change. Clear each flag immediately after the mode is switched. (c) Read the measured value before the next underflow. When the value is read after an underflow, the TO bit is inverted, sometimes disabling calculation of the correct measured value. (d) When the previous measured value is not read after continuous pulsewidth measurement, it is held without transferring the new value to the buffer. 2­ 36 HARDWARE CONFIGURATION 2.2.4 UART Peripherals · Full-duplex double buffers · CLK synchronous and asynchronous data transfer · 8 baud rates (for internal clock) The baud rate can also be freely selected by external clock input or input from the internal timer. · Variable data length · NRZ transfer format · Two data and clock pins can be switched for use. · The data and clock input/output polarities can be inverted. (1) Block diagram (a) Baud rate generator and serial clock generator PDS1, 0 RC2 to RC0 CS1, 0 CR SMDE 1/4 1/6 1/2n CPU clock 1/13 1/8 Serial clock 1/2 1/65 1/4 PWM timer output 1/2 P45/SCK P45/SCK UART serial clock P45/SCK P45/SCK Serial I/O clock RSEL SCKE* * At switching between port output and serial clock output, the SCKE bit of the UART is valid when the RSEL bit is 0; the SCKE bit of the serial I/O is valid when the RSEL bit is 1. 2­ 37 HARDWARE CONFIGURATION (b) Data transmitter/receiver Peripherals PEN Parity generator Data bus RD8/RP MC1, 0 P43/SI P43/SI Start Start bit detection Receiver byte count Reset Shifter Shift clock Transfer clock SIDR CR RDRF ORFE PEM, TD8/TP Parity generator Timing Transmitter byte count Shift clock Shifter P44/SO P44/SO Transmitter control Reset Transfer clock SODR MC1, 0, SBL RSEL TDRE SOE* Serial I/O data RDRF ORFE TDRE TIE RIE IRQ4 * At switching between port output and serial data output, the SOE bit of the UART is valid when the RSEL bit is 0; the SOE bit of the serial I/O is valid when the RSEL bit is 1. 2­ 38 HARDWARE CONFIGURATION (2) Register list Peripherals 8 bits R/W Serial mode control register 1 Address: 0020H 0020H SMC1 Address: 0021H 0021H SRC R/W Serial rate control register Address: 0022H 0022H SSD R/W Serial status and data register Address: 0023H 0023H SIDR R Serial input data register Address: 0023H 0023H SODR W Serial output data register Address: 0024H 0024H SMC2 R/W Serial mode control register 2 (3) Description of registers (a) Serial mode control register 1 (SMC1) Address: 0020H 0020H SMC1 This register is used to select the UART operation mode. Bit 7 Address: 0021H 0021H SRC Address: 0022H 0022H Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEN SBL MC1 MC0 SMDE - SCKE SOE (R/W) SSD Address: 0020H 0020H Bit 6 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (Initial value) 00000-00B 00000-00B Address: 0023H 0023H SIDR Address: 0023H 0023H SODR Address: 0024H 0024H SMC2 [Bit 7] PEN: Parity enable Bit 7 is used to determine whether to append a parity bit (when transmitting) or to detect it (when receiving) for serial data input/output. 0 No parity (Initial value) 1 Parity (Odd or even parity is set by TD8/TP of the SSD register.) [Bit 6] SBL: Stop bit length Bit 6 is used to determine the stop bit length of transmit data. At the receiving end, only the first bit of the stop bit is recognized; second and later bits are ignored. 0 2-bit length 1 1-bit length 2­ 39 (Initial value) HARDWARE CONFIGURATION [Bits 5 and 4] MC1 and MC0: Mode control Peripherals Bits 5 and 4 are used to select the transfer mode (data length). MC1 MC2 Mode Data Length 0 0 0 5 (4) 0 1 1 8 (7) 1 0 reserved reserved 1 1 3 9 (8) (Initial value) Values in parentheses indicate the data length with parity. [Bit 3] SMDE: 0 Synchronous transfer 1 (Initial value) Asynchronous transfer [Bit 1] SCKE: SCLK enable When 1 is written at bit 1, the UART serial clock output pin is switched to the port to output an external synchronous clock pulse. If the mode in which a synchronous clock pulse is input from the outside is set by the CS1 and CS0 bits of the SRC register, the value can also be read from the port as the input pin. Functions as general-purpose input/output port that does not output serial clock pulse 0 1 When the port is set to input (DDR = 0), it also functions as a serial clock input pin. (Initial value) Functions as UART serial clock input/output port In the external clock input mode, set this bit to 0. This bit is valid when the RSEL bit of the SMC2 is 0. [Bit 0] SOE: Serial output enable When 1 is written at bit 0, the port is switched to the UART serial data output pin to enable serial data output. 0 Functions as port that does not output serial data (Initial value) 1 Functions as UART serial data output port (SOUT) This bit is valid when the RSEL bit of the SMC2 is 0. 2­ 40 HARDWARE CONFIGURATION (b) Serial rate control register (SRC) Peripherals This register is used to control the data transfer speed (baud rate) of the UART. Bit 7 Address: 0021H 0021H Address: 0021H 0021H Address: 0022H 0022H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - CR CS1 CS0 RC2 RC1 RC0 (R/W) Address: 0020H 0020H SMC1 (R/W) (R/W) (R/W) (R/W) (R/W) SRC (Initial value) -011000B -011000B SSD Address: 0023H 0023H SIDR Address: 0023H 0023H SODR Address: 0024H 0024H SMC2 [Bit 5] CR: Clock rate Bit 5 is used to select the asynchronous transfer clock rate. However, when the CS1 and CS0 bits are 11B, the 1/8 clock rate is selected irrespective of the value of the CR bit. 0 1/16 of clock input (Initial value) 1 1/64 of clock input Note: The synchronous transfer clock rate is as follows irrespective of the value of the CR bit: Clock source PWM timer, dedicated baud rate generator . 1/2 External clock, dedicated baud rate generator . 1/1 Note that the dedicated baud rate generator may select the clock rate according to the CR value. [Bits 4 and 3] CS1 and CS0: Clock select Bits 4 and 3 are used to select the clock input of the UART port. If the external or internal clock is selected as clock input, the baud rate is a 1/16 or 1/64 clock frequency according to the value of the CR bit (initial value: 11B). For details, see (4) of Description of operation. [Bits 2 to 0] RC2 to RC0: Bits 2 to 0 are needed only when generating a serial clock pulse with the dedicated baud rate generator. The baud rate can be selected from eight kinds by these bits (initial value: 000B). For the baud rate setting, see (4) of Description of Operation. 2­ 41 HARDWARE CONFIGURATION (c) Serial status and data register (SSD) Peripherals This register is used to indicate the current status of the UART port. When the data communication length is 9 bits, the most significant data (bit 8) is included. Bit 7 Address: 0022H 0022H Address: 0021H 0021H Address: 0022H 0022H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF ORFE TDRE TIE RIE - TD8 /TP RD8 /RP (R) Address: 0020H 0020H SMC1 (R) (R) (R/W) (R/W) (R/W) (R) SRC (Initial value) 00100-1XB 00100-1XB SSD Address: 0023H 0023H SIDR Address: 0023H 0023H SODR [Bit 7] RDRF: The RDRF flag is used to indicate the data status of the serial input data register (SIDR). 0 Address: 0024H 0024H SMC2 Empty (Initial value) 1 Contains data When the SIDR register is read after reading the SSD register with the RDRF flag set to 1, the RDRF flag is cleared. When this flag is set to 1, the receiver interrupt request is output. [Bit 6] ORFE: The ORFE flag is used to indicate that an overrun or framing error has occurred. This flag is initialized to 0 at reset. 0 Normal 1 (Initial Value) Error If this flag is set, data is not transferred from the receive shift register to the SIDR register. When the SIDR register is read after reading the SSD register with the ORFE flag set to 1, the ORFE flag is cleared. When this flag is set to 1, the receiver interrupt request is output. The status of input data is specified by the RDRF and ORFE flags as follows: RDRF ORFE SIDR data status 0 0 Empty 0 1 Framing error (If new data is input under this condition, RDRF is not set.) 1 0 Normal data 1 1 Overrun (previous data remains) 2­ 42 HARDWARE CONFIGURATION [Bit 5] TDRE: Peripherals The TDRE flag is used to indicate the status of the serial output data register (SODR). 0 Contains data 1 Empty (Initial value) If SODR (Serial Output Data Register) is empty, and newly written data to SODR, SODR will be driven out of the serial output pin (P44/SO P44/SO). When the TDRE flag is set to 1, a transmitter interrupt request is output. [Bit 4] TIE: Transmitter interrupt request enable bit Bit 4 is used to enable the transmitter interrupt request. 0 Disables interrupt 1 (Initial value) Enables interrupt [Bit 3] RIE: Receiver interrupt request enable bit Bit 3 is used to enable the receiver interrupt request. 0 Disables interrupt 1 (Initial value) Enables interrupt [Bit 1] TD8/TP: When parity is not provided, bit 1 is treated as bit 8 of the SODR register. When parity is provided, this bit is used to determine whether the parity of serial output data is even or odd. 0 Odd parity 1 Even parity (Initial value) [Bit 0] RD8/RP: When parity is not provided, bit 0 is treated as bit 8 of the SIDR register. When parity is provided, this bit is used to determine whether the parity of serial input data is even or odd (Initial value: undefined). 0 Odd parity 1 Even parity 2­ 43 HARDWARE CONFIGURATION (d) Serial input data register (SIDR) Serial output data register (SODR) Peripherals Address: 0020H 0020H SMC1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (R) SIDR (R) (R) (R) (R) (R) (R) (R) Address: 0023H 0023H Address: 0021H 0021H SRC Address: 0022H 0022H SSD The SIDR register is used for input of serial data (Initial value: undefined). Address: 0023H 0023H SIDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (W) SODR (W) (W) (W) (W) (W) (W) (W) Address: 0023H 0023H Address: 0023H 0023H SODR Address: 0024H 0024H SMC2 Address: 0020H 0020H SMC1 The SODR register is used for output of serial data (Initial value: undefined). (e) Serial mode control register 2 (SMC2) Bit 7 Address: 0021H 0021H SRC Address: 0022H 0022H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - PSEN - RSEL - PDS1 PDS0 - - (R/W) - (R/W) - (R/W) (R/W) SSD Address: 0023H 0023H SIDR Address: 0023H 0023H SODR Address: 0024H 0024H SMC2 Address: 0024H 0024H (Initial value) -1-0-00B -1-0-00B [Bit 5] PSEN: Bit 5 is used to determine whether to start or stop the operation of the baud rate generator. 0 Stops operation 1 Starts operation (Initial value) [Bit 3] RSEL: Bit 3 is used to select whether either the UART or serial I/O to output data and clock. 0 UART 1 (Initial value) Serial I/O 2­ 44 HARDWARE CONFIGURATION [Bits 1 and 0] PDS1 and PDS0: Bits 1 and 0 are used to select the division of the divider at the front of the baud rate generator. PDS1 0 0 1 1 PDS0 0 1 0 1 Select 4 dividing Select 6 dividing Select 13 dividing Select 65 dividing 2­ 45 (Initial value) HARDWARE CONFIGURATION (4) Description of operation Peripherals (a) Operation modes The UART has the operation modes listed in Table 2­6; they can be switched by setting the value at the serial mode control register 1 (SMC1). Table 2­6 Operation Modes of UART Mode 0 1 3 Parity Data Length Clock Mode Stop Bit Length Provided 4 Asynchronous/synchronous 1 bit or 2 bits Not provided 5 Asynchronous/synchronous 1 bit or 2 bits Provided 7 Asynchronous/synchronous 1 bit or 2 bits Not provided 8 Asynchronous/synchronous 1 bit or 2 bits Provided 8 Asynchronous/synchronous 1 bit or 2 bits Not provided 9 Asynchronous/synchronous 1 bit or 2 bits However, the stop bit length can be specified only for the transmitter channel. The 1-bit length is always specified for the receiver channel. (b) Interrupt occurrence and flag setting conditions The UART has three flags and two interrupt sources. The three flags are ORFE, RDRF, and TDRE. The ORFE flag is an overrun/ framing error flag which is set when an error occurs at receiving. The RDRF flag indicates that the receive data is ready at the SIDR register. The TDRE flag indicates that writing to the transmit data register (SODR) is enabled. The two interrupt sources are one for receiving, and one for transmitting. At receiving, an interrupt is requested by the RDRF or ORFE flag. At transmitting, an interrupt is requested by the TDRE flag. a. Receiving in modes 0, 1, and 3 Both the RDRF (receive data register full) and ORFE (overrun/framing error) flags are set when receiving and transfer are completed and the last stop bit is detected. An interrupt request is then output to the CPU. When the RDRF flag is active, the received data is transferred to the serial data input register (SIDR). Data Stop RDRF SIN interrupt Fig. 2.15 RDRF Flag Set Timing 2­ 46 (Stop) HARDWARE CONFIGURATION Peripherals Data Data Stop Stop RDRF = 1 RDRF = 0 ORFE ORFE SIN interrupt SIN interrupt (Framing error) (Overrun error) Fig. 2.16 ORFE Flag Set Timing b. Transmission When the next data is ready to write after data written to the SODR (serial output data register) is transferred to the interrupt shift register, the TDRE (transmit data register empty) flag is set and an interrupt request is output to the CPU. SODR write TDRE Interrupt request output to CPU SOUT interrupt SOUT output S 0 1 2 3 4 5 6 7 P P S 0 1 2 3 S: Start bit 0 to 7: Data bitsP: Stop bit Fig. 2.17 TDRE Flag Set Timing (c) Transfer data format The UART can handle only NRZ (non-return-to-zero)-type data. The relationship between transmitter/receiver clocks and data is shown in the figure below. SCK SI, SO 0 1 Start LSB 0 1 1 0 0 1 0 1 1 MSB Stop Stop Stop Transmitted data is 01001101B 01001101B (mode 1) or 101001101B 101001101B (mode 3) Fig. 2.18 Transfer Data Format (Synchronous Transfer) 2­ 47 Varies with mode HARDWARE CONFIGURATION As shown in the figure, data transfer starts from the start bit (Low-level data), the data bit length specified by the LSB first is transferred, and transfer ends at the stop bit (High-level data). In asynchronous transfer, the relationship between SCK and SI is not as shown in the above figure. In addition, at asynchronous transfer, the relationship is not as shown in the above diagram even when SCK is set to input. Peripherals (d) Transfer clock selection The transfer clock can be selected from the external clock (SCK pin), PWM timer, and the dedicated baud rate generator. This selection is done by the CS0, CS1, and CR bits of the serial rate control register (SRC). The division ratios are listed in Table 2­7. Table 2­7 Clock Division Ratio CS1 CS0 Clock Input 0 0 External clock 0 1 PWM timer 1 0 Dedicated baud rate generator 1 1 CR Asynchronous 0 1/16 1 1/64 0 1/16 1 1/64 0 1/16 1 1/64 - Sychronous 1/8 1/1 1/2 1/2 1/1 When using the dedicated baud rate generator, select the input clock of the baud rate generator by PDS1 and PDS0 of the SMC2. indicates the input clocks to be used and the division, and Table 2­9 indicates the reference baud rates. Table 2­8 Input Clock of Baud Rate Generator PDS1 0 0 1 1 PDS0 0 1 0 1 2­ 48 Division 1/4 1/6 1/13 1/65 Clock CPU operation CPU operation CPU operation CPU operation HARDWARE CONFIGURATION Peripherals Table 2­9 Selection of Baud Rate (When Dedicated Baud Rate Generate Used) RC2 0 0 0 0 1 1 1 1 RC1 0 0 1 1 0 0 1 1 RC0 0 1 0 1 0 1 0 1 Division ratio 20 21 22 23 24 25 26 27 4.9152 MHz 1/4 1/64 9600 4800 2400 1200 600 300 150 75 Baud rate (bps) 5 MHz 1/4 1/8 78125 39063 19531 9766 4883 2441 1221 610 1/65 1/16 2404 1202 601 300 150 75 38 19 Remarks Clock PDS division CS,CR division (e) Selection of input/output signal The UART shares the data and clock input/output with the serial I/O. Therefore, the output signal selected by the RSEL bit is output. At switching between port output and peripheral output, the peripheral enable bit selected by the RSEL bit becomes valid. · When the RSEL bit is 0, UART is selected. · When the RSEL bit is 1, serial I/O is selected. (5) Precautions for UART · After canceling register initialization by reset, 11 shift clocks are required to initialize the internal control section. · When using the external clock, the minimum pulse width is as follows: CPU operating clock cycle × 4 2­ 49 HARDWARE CONFIGURATION 2.2.5 8-bit Serial I/O Peripherals · 8-bit serial data synchronous transfer. · LSB first or MSB first can be selected for data transfer. · The 4 shift-clock mode can be selected (three internal and one external). (1) Block diagram Internal-data bus D0 to D7 (MSB first) D7 to D0 D7 to D0 (LSB first) Transfer direction select SIOF SIOE (Shift direction) ÁÁÁÁÁÁ Serial data register (SDR) SCKE SOE CKS1 CKS0 BDS SST P43/SI P43/SI SI input Synchronizer SO output Synchronizer Serial mode register (SMR) 2 P44/SO P44/SO (Note) Overflow Output enable Output enable P45/ SCK (Note) Internal clock pulse Shift-clock pulse select Controller 3 Clear IRQ5 Shift-clock counter Note: The SO and SCK outputs serve as UART outputs. They can be used as the outputs of the serial I/O when the RSEL bit of the SMC2 in the UART is 1. (2) Register list 8 bits Address: 001CH 001CH SMR R/W Serial mode register Address: 001DH 001DH SDR R/W Serial data register 2­ 50 HARDWARE CONFIGURATION (3) Description of registers The detail of each register is described below. Peripherals Address: 001CH 001CH SMR (a) Serial-mode register (SMR) The SMR is used to control serial I/O. Address: 001DH 001DH Bit 7 Address: 001CH 001CH Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST (R/W) SDR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (Initial value) 00000000B 00000000B [Bit 7] SIOF: Serial I/O interrupt-request flag This bit is used to indicate the serial I/O transfer state. The meaning of each bit when reading is as follows: 0 Serial data transfer not terminated 1 Serial data transfer terminated Note that 1 is always read when the Read Modify Write instruction is read. If this bit is set when an interrupt is enabled (SIOE = 1), an interrupt request is output to the CPU. The meaning of each bit when writing is as follows: 0 Clears this bit 1 Unchanges this bit and other bits unaffected The end-of-transfer decision may be made by either the SST bit (bit 0) of the SMR or by this bit. [Bit 6] SIOE: Serial I/O interrupt-enable bit This bit is used to enable a serial I/O interrupt request. 0 Serial I/O interrupt-output disabled 1 Serial I/O interrupt-output enabled [Bit 5] SCKE: Shift-clock output-enable bit This bit is used to control the shift-clock I/O pins. 0 General-purpose port pin (P45) or SCK input pin 1 SCK (shift clock) output pin When using the P45/SCK P45/SCK pin as an external clock, always set the DDR4 to input (bit 5 of DDR4 = 0). This bit is valid when the RSEL bit of the SMC2 in the UART is 1. 2­ 51 HARDWARE CONFIGURATION [Bit 4] SOE: Serial-data output-enable bit This bit is used to control the output pin for serial I/O. Peripherals 0 General-purpose port pin (P44) 1 SO (serial data) output pin When using P43/SI P43/SI pin as SI pin, always set the DDR4 to input (bit 3 of DDR4 = 0). This bit is valid when the RSEL bit of the SMC2 in the UART is 1. [Bits 3 and 2] CKS1 and CKS0: Shift-clock select bits These bits are used to select the serial shift-clock modes. CKS1 CKS0 (Clock rate) Mode SCK 0 0 Internal shift-clock mode (2 instruction cycle) Output 0 1 Internal shift-clock mode (8 instruction cycle) Output 1 0 Internal shift-clock mode (32 instruction cycle) Output 1 1 External shift-clock mode (SCK) Input [Bit 1] BDS: Transfer direction select bit At serial data transfer, this bit is used to decide the transfer direction: from the least significant bit first (LSB first) or from the most significant bit first (MSB first). 0 LSB first 1 MSB first Note that when this bit is rewritten after writing data to the SDR, the data become invalid. [Bit 0] SST: Serial I/O transfer-start bit This bit is used to start serial I/O transfer. The bit is automatically cleared to 0 when transfer is terminated. 0 Stops serial I/O transfer 1 Starts serial I/O transfer Before starting transfer, ensure that transfer is stopped (SST = 0). Address: 001CH 001CH SMR Address: 001DH 001DH SDR (b) Serial-data register (SDR) This 8-bit register is used to hold serial I/O transfer data. (Note: Do not write data to this register during the serial I/O operation.) Bit 7 Bit 6 Bit 5 (R/W) (R/W) (R/W) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (R/W) (R/W) (R/W) Address: 001DH 001DH 2­ 52 (R/W) (R/W) (Initial value) XXXXXXXXB HARDWARE CONFIGURATION (4) Description of operation The operation of 8-bit serial I/O is described below. Peripherals (a) Outline This module consists of the serial-mode register (SMR) and serial-data register (SDR). At serial output, data in the SDR is output in bit serial to the serial output pin (SO) in synchronization with the falling edge of a serial shift-clock pulse generated from the internal or external clock. At serial input, data is input in bit serial from the serial input pin (SI) to the SDR at the rising edge of a serial shift-clock pulse. SDR #7 #6 #5 #4 #3 #2 #1 #0 Shift-clock pulse SO #0 #1 #2 #5 #6 #7 Shift-clock pulse CK P SDR #7 #6 S conversion #5 #4 #3 #2 0 #1 #0 SO Shift-clock pulse SI Serial output #0 #1 #2 #5 #6 #7 Shift-clock pulse CK SI SI S P conversion Serial input (b) Operation modes The serial I/O has three internal shift-clock modes and one external shiftclock mode according to the type of shift-clock, which are specified by the SMR. Mode switching or clock selection should be made with serial I/O stopped (SST bit of SMR = 0). a. Internal shift-clock mode Operation is performed by the internal clock. A shift-clock pulse with a duty of 50% is output at the SCK pin as a synchronous timing output. Data is transferred bit-by-bit at every clock pulse. b. External shift-clock mode Data is transferred bit-by-bit at every clock pulse in synchronization with the external shift-clock pulse input from