CM25-10115-2E MB89170/170A MB89P173/P175A MB89P175A MB89170 MB89170A MB89173 - Datasheet Archive

 

MICROCONTROLLER MANUAL CM25-10115-2E F2MC-8L FAMILY 8-BIT MICROCONTROLLER MB89170/170A SERIES HARDWARE MANUAL CONTENTS Chapter 1:

 

FUJITSU SEMICONDUCTOR MICROCONTROLLER MANUAL CM25-10115-2E CM25-10115-2E F2MC-8L FAMILY 8-BIT MICROCONTROLLER MB89170/170A MB89170/170A SERIES HARDWARE MANUAL CONTENTS Chapter 1: OVERVIEW ··············································································································· 1 1.1 Features ································································································································· 1 1.2 Product Series ······················································································································· 2 1.3 Differences among Products ································································································· 3 1.4 Block Diagram ······················································································································ 4 1.5 Pin Assignment ····················································································································· 5 1.6 Package Dimensions ············································································································· 7 1.7 Pin Description ······················································································································ 9 1.8 Notes on Handling the Device ···························································································· 13 Chapter 2: 2.1 HARDWARE CONFIGURATION ·········································································· 14 CPU ····································································································································· 14 2.1.1 2.1.2 Arrangement of 16-bit data in memory ······································································ 16 2.1.3 Registers ····················································································································· 17 2.1.4 Operation mode ·········································································································· 20 2.1.5 Clock controller ·········································································································· 21 2.1.6 2.2 Memory space ············································································································· 14 Interrupt controller ······································································································ 31 Peripheral Functions ··········································································································· 34 2.2.1 I/O ports ······················································································································ 34 2.2.2 8-/16-bit timer (timer 1, timer 2) ················································································ 39 2.2.3 8-bit serial I/O ············································································································· 48 2.2.4 DTMF generator ········································································································· 54 2.2.5 External interrupt circuit 1 ·························································································· 58 2.2.6 External interrupt circuit 2 (wakeup) ·········································································· 63 2.2.7 Buzzer output ·············································································································· 66 2.2.8 Watch prescaler ·········································································································· 68 2.2.9 Time-base timer ·········································································································· 70 2.2.10 Watchdog reset ··········································································································· 72 Chapter 3: OPERATION ············································································································ 74 3.1 Clock Generator ·················································································································· 74 3.2 Reset ···································································································································· 75 3.2.1 Reset operation ··········································································································· 75 3.2.2 Reset generation condition ························································································· 76 3.2.3 Notes on resets ············································································································ 76 3.3 Interrupts ····························································································································· 77 3.4 Memory Access Mode ········································································································ 78 3.5 Low-Power Consumption Modes ······················································································· 79 3.6 Pin States during Sleep Mode, Stop Mode, Watch Mode, and Reset ································· 80 Chapter 4: INSTRUCTION SET OVERVIEW ·········································································· 81 4.1 Explanation of Instruction Notation ···················································································· 81 4.2 Transfer Instructions ··········································································································· 83 4.3 Operation Instructions ········································································································· 84 4.4 Branching Instructions ········································································································ 85 4.5 Other Instructions ················································································································ 85 Chapter 5: TABLE OF MASK OPTIONS ················································································ 87 Chapter 6: MB89P173/P175A MB89P173/P175A SPECIFICATIONS ··································································· 88 6.1 Features ······························································································································· 88 6.2 Memory Space ···················································································································· 88 6.3 Writing the PROM ·············································································································· 89 6.4 Recommended Screening Conditions ················································································· 89 6.5 Write Yields ························································································································ 89 6.6 ROM Programmer Adapter ································································································· 90 6.7 OTPROM Option Settings (MB89P175A MB89P175A Only) ································································ 90 Appendix 1: I/O MAP ··················································································································· 91 Appendix 2: WRITING AN EPROM WITH A PIGGYBACK/EVALUATION CHIP ·············· 93 CONTENTS 1.1 Features Chapter 1: OVERVIEW The MB89170/170A MB89170/170A series microcontrollers were developed as general-purpose members of the F 2MC-8L family of proprietary 8-bit single-chip microcontrollers suited for applications that require ASICs (Application Specific ICs). In addition to a compact instruction set, the MB89170/170A MB89170/170A series includes a variety of peripheral functions on chip, including timers, a serial interface, a DTMF generator, and external interrupts. The MB89170/170A MB89170/170A series microcontrollers are suited for line control functions in telephone equipment, etc. *: F2MC stands for FUJITSU Flexible Microcontroller. 1.1 Features · F2MC-8L family CPU core · Maximum memory space: 64 Kbytes · Minimum instruction execution time/interrupt processing time MB89170 MB89170 Series: 1.1 µs/10 µs (when source oscillation is 3.58 MHz) MB89170A MB89170A Series: 0.6 µs/5.4 µs (when source oscillation is 7.16 MHz) · Dual clock control · I/O ports: 37 max. · 21-bit time-base counter · Clock prescaler · Watchdog timer · 8-/16-bit timer/counter: 1 channel · 8-bit serial I/O: 1 channel · DTMF generator Source oscillation frequency is selectable (MB89170A MB89170A series only) · External interrupts: 3 channels The three channels are independent and can be used to exit a low-power consumption mode (edge detection function) · External interrupts (wakeup): 8 channels The eight channels are independent and can be used to exit a low-power consumption mode (low level detection function) · Low-power consumption modes (stop mode, sleep mode, watch mode, submode) · CMOS technology 1 1.2 Product Lineup 1.2 Product Lineup Table 1.2 describes the product lineup of the MB89170/170A MB89170/170A series. Table 1.2 Product Lineup of MB89170/170A MB89170/170A Series Part number Type MB89173 MB89173 MB89P173 MB89P173 MB89174A MB89174A Mass production product (masked ROM product) 8 K × 8 bits (internal ROM) One-time PROM product (EPROM product) MB89P175A MB89P175A MB89PV170A MB89PV170A Mass production product (masked ROM product) 12 K × 8 bits (internal ROM) One-time PROM Piggyback/evalproduct (EPROM uation product product) (under development) ROM size 32 K × 8 bits 8 K × 8 bits 16 K × 8 bits (internal PROM, (internal PROM, (external ROM) can be written with can be written with general-purpose general-purpose programmer) programmer) RAM size 384 × 8 bits 512 × 8 bits 1 K × 8 bits CPU functions Number of basic instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum instruction execution time: Minimum instruction execution time: 0.6 to 9.6 µs/7.16 1.1 to 17.6 µs/3.58 MHz; 61 µs/32 kHz MHz; 61 µs/32.768 kHz Interrupt processing time: 10 to 160 µs/ Interrupt processing time: 5.4 to 86.4 µs/7.16 MHz; 3.58 MHz; 562.5 µs/32 kHz 562.5 µs/32.768 kHz Ports Output ports (N-ch open-drain): 5 Output ports (CMOS): 8 Input/output ports (CMOS): 24 (16 are shared with resources) Total: 37 Timer counter 8 bits × 2 channels or 16 bits × 1 channel, square wave output possible Operation clock can be selected from among four types: external, 2.2 µs, 35.2 µs, and 563.2 µs (when source oscillation is 3.58 MHz) Serial I/O 8-bit length LSB first/MSB first selectable Transfer clock can be selected from among four types: external, 2.2 µs, 8.8 µs, and 35.2 µs (when source oscillation is 3.58 MHz) DTMF generator CCITT all-tone output possible CCITT all-tone output possible Source oscillation frequency Source oscillation frequency (3.58 MHz) fixed (3.58 MHz/7.16 MHz) selectable External interrupts 1 3 independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge/both edges selectable Can also be used to exit watch/stop/sleep mode (edge detection possible even in watch or stop mode) External interrupts 2 8 channels (low level interrupts) (wakeup) Can also be used to exit watch/stop/sleep mode (level detection possible even in watch or stop mode) Standby mode Sleep mode, stop mode, watch mode, submode Process CMOS Operating voltage* *2.2 V to 6.0 V 2.7 V to 6.0 V 2.2 V to 6.0 V 2.7 V to 6.0 V EPROM used MBM27C256A20TV-M MBM27C256A20TV-M *: Differs according to the operation frequency, DTMF guaranteed range, and other conditions. (Refer to the data sheet.) 2 Chapter 1: OVERVIEW 1.3 Differences among Products 1.3 Differences among Products Table 1.3 Cross-reference Table for Packages and Models Package MB89173 MB89173 MB89P173 MB89P173 MB89174A MB89174A MB89P175A MB89P175A × FPT-48P-P02 FPT-48P-P02 MQP-48C-P01 MQP-48C-P01 MB89PV170A MB89PV170A × : Available ×: Not available Note: For details on the packages, refer to section 1.6, "Package Dimensions." (1) Memory space Before conducting evaluations using the piggyback product, etc., carefully verify the differences between the piggyback version and the actual product. (2) Current consumption In the case of the MB89PV170A MB89PV170A, the current consumed by the EPROM plugged into the socket on top of the IC is added to the current consumed by the IC. (3) Mask options The functions that can be selected as options and the methods for setting the options vary according to the model. Before selecting any options, first check the "Mask Option Table" in the data sheet, etc. The following points in particular should be noted: · The pull-up resistance for P40 to P44 cannot be set in the MB89P175A MB89P175A. · The options for the MB89PV170A MB89PV170A are fixed. 3 1.4 Block Diagram 1.4 Block Diagram X0 High-speed oscillator X1 Timebase timer Clock controller Watch prescaler X0A Low-speed oscillator X1A CMOS I/O ports Reset circuit RST 8-bit timer counter P20 to P27 8 / Port 3 External interrupts (wakeup) Internal bus 8 / P33/EC P33/EC CMOS I/O ports Port 0/1 P10 to P17 8-bit timer counter 8 / Port 2 P00/LI0 P00/LI0 to P07/LI7 P07/LI7 P34/TO P34/TO /INTO P30/SCK P30/SCK P32/SI P32/SI P31/SO P31/SO 8-bit serial interface P35/INT1 P35/INT1 External interrupts P36/INT2 P36/INT2 P37/BZ P37/BZ Buzzer output N-ch open drain output ports Port 4 CMOS output ports RAM 5 / P40 to P44 F2MC-8L CPU DTMF generator ROM Other pins MOD1, MOD0, VCC, VSS×2 Fig. 1.4 Overall Block Diagram 4 Chapter 1: OVERVIEW DTMF 1.5 Pin Assignment 1.5 Pin Assignment Corresponding products: MB89173/174A/P173/P175A MB89173/174A/P173/P175A 48 47 46 45 44 43 42 41 40 39 38 37 P40 P41 P42 P43 P44 VSS P30/SCK P30/SCK P31/SO P31/SO P32/SI P32/SI P33/EC P33/EC P34/TO/INT0 P34/TO/INT0 P35/INT1 P35/INT1 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 P36/INT2 P36/INT2 P37/BZ P37/BZ P00/L10 P00/L10 P01/L11 P01/L11 P02/L12 P02/L12 P03/L13 P03/L13 P04/L14 P04/L14 P05/L15 P05/L15 P06/L16 P06/L16 P07/L17 P07/L17 P10 P11 P24 P23 P22 P21 P20 P17 VSS P16 P15 P14 P13 P12 13 14 15 16 17 18 19 20 21 22 23 24 DTMF RST MOD0 MOD1 X0 X1 VCC X0A X1A P27 P26 P25 Fig. 1.5a Pin Assignment (FPT-48P-M02 FPT-48P-M02) 5 1.5 Pin Assignment Corresponding product: MB89PV170A MB89PV170A 69 70 71 72 73 74 75 76 v 60 59 58 57 56 55 54 53 77 78 79 80 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 P36/INT2 P36/INT2 P37/BZ P37/BZ P00/L10 P00/L10 P01/L11 P01/L11 P02/L12 P02/L12 P03/L13 P03/L13 P04/L14 P04/L14 P05/L15 P05/L15 P06/L16 P06/L16 P07/L17 P07/L17 P10 P11 P24 P23 P22 P21 P20 P17 VSS P16 P15 P14 P13 P12 13 14 15 16 17 18 19 20 21 22 23 24 DTMF RST MOD0 MOD1 X0 X1 VCC X0A X1A P27 P26 P25 68 67 66 65 64 63 62 61 48 47 46 45 44 43 42 41 40 39 38 37 P40 P41 P42 P43 P44 VSS P30/SCK P30/SCK P31/SO P31/SO P32/SI P32/SI P33/EC P33/EC P34/TO/INT0 P34/TO/INT0 P35/INT1 P35/INT1 (Top view) · Pin assignment on top of package (MB89PV170A MB89PV170A only) Pin no. Pin name Pin no. Pin name Pin no. Pin name 49 VPP 57 N.C. 65 O4 73 OE 50 A12 58 A2 66 O5 74 N.C. 51 A7 59 A1 67 O6 75 A11 52 A6 60 A0 68 O7 76 A9 53 A5 61 O1 69 O8 77 A8 54 A4 62 O2 70 CE 78 A13 55 A3 63 O3 71 A10 79 A14 56 N.C. 64 VSS 72 N.C. 80 VCC N.C.: Internally connected; do not use. Fig. 1.5b Pin Assignment (MQP-48C-P01 MQP-48C-P01) 6 Chapter 1: OVERVIEW Pin no. Pin name 1.6 Package Dimensions 1.6 Package Dimensions FPT-48P-M02 FPT-48P-M02 EIAJ code: *QFP048-P-1212-1 QFP048-P-1212-1 Lead pitch 48-pin Plastic QFP 0.8 mm Package width × package length Lead shape 12 × 12 mm Gull wing Sealing method Plastic mold 48-pin Plastic QFP (FPT-48P-M02 FPT-48P-M02) Dimentions in mm (inches) Fig. 1.6a Package Dimensions for FPT-48P-M02 FPT-48P-M02 7 1.6 Package Dimensions MQP-48C-P01 MQP-48C-P01 Lead pitch 0.8 mm Lead shape Straight Motherboard material 48-pin Ceramic MQFP Ceramic Socket material Plastic 48-pin Ceramic MQFP (MQP-48C-P01 MQP-48C-P01) Dimentions in mm (inches) Fig. 1.6b Package Dimensions for MQP-48C-P01 MQP-48C-P01 8 Chapter 1: OVERVIEW 1.7 Pin Description 1.7 Pin Description Tables 1.7a and 1.7b show the pin functions, and Table 1.7c shows the I/O circuit types. Table 1.7a Pin Description Pin no. QFP *1 MQFP *2 Pin name 5 6 3 4 2 X0 X1 MOD0 MOD1 RST 34 to 27 Circuit type A C D H General-purpose output-only ports. G General-purpose I/O port. This pin also serves as the serial I/O clock input/output pin. This pin is a hysteresis input. General-purpose I/O port. This pin also serves as the serial I/O data output pin. This pin is a hysteresis input. General-purpose I/O port. This pin also serves as the serial I/O data input pin. This pin is a hysteresis input. General-purpose I/O port. This pin also serves as the timer/counter external clock input pin. This pin is a hysteresis input. General-purpose I/O port. This pin also serves as the timer/counter overflow output pin and as an external interrupt input pin. This pin is a hysteresis input. General-purpose I/O ports. These pins also serve as external interrupt input pins. These pins are hysteresis inputs. General-purpose I/O port. This pin also serves as the buzzer output pin. This pin is a hysteresis input. N-ch open-drain output-only ports. 41 P31/SO P31/SO G 40 P32/SI P32/SI G 39 P33/EC P33/EC G 38 P34/TO/ P34/TO/ INT0 G P35/INT1 P35/INT1, P36/INT2 P36/INT2 G P37/BZ P37/BZ G P40 to P44 I 37, 36 35 48 to 44 Operation mode specification input pins. Connect directly to VCC or VSS. F 42 17 to 10 Crystal oscillator pin. Reset input/output pin. N-ch open-drain output with pull-up resistor and hysteresis input. This pin outputs a low signal in response to an internal source (optional function). Inputting a low signal initializes the internal circuitry. General-purpose I/O ports. These pins also serve as external interrupt inputs (wakeup). The external interrupt inputs are hysteresis inputs. General-purpose I/O ports. P00/LI0 P00/LI0 to P07/LI7 P07/LI7 P10 to P17 P20 to P27 P30/SCK P30/SCK 26 to 20, 18 Function E *1: FPT-48P-M02 FPT-48P-M02 *2: MQP-48C-P01 MQP-48C-P01 9 1.7 Pin Description Table 1.7a Pin Description (Continued) Pin no. QFP *1 MQFP *2 1 8 9 7 19, 43 Pin name DTMF X0A X1A VCC VSS Circuit type J B - - Function DTMF signal output pin. Crystal oscillator pins for low-speed clock (32.768 kHz). Power supply pin Power supply (GND) pins. Table 1.7b Pin Description for External EPROM Section (MB89PV170A MB89PV170A only) Pin no. MQFP *2 Pin name I/O 49 50 51 52 53 54 55 58 59 60 61 62 63 64 65 66 67 68 69 70 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 01 02 03 VSS 04 05 06 07 08 CE 71 73 A10 OE O O 75 76 77 78 79 80 56 57 72 74 A11 A9 A8 A13 A14 VCC N.C. *1: FPT-48P-M02 FPT-48P-M02 *2: MQP-48C-P01 MQP-48C-P01 10 Chapter 1: OVERVIEW Function O O High-level signal output pin. Address output pins. I Data input pins. O I Power supply pin (GND). Data input pins. O O Chip enable pin for ROM. This pin outputs a high signal when in standby. Address output pin. Output enable pin for ROM. This pin always outputs a low signal. Address output pins. O - EPROM power supply pin. Internally connected pins. Always leave these pins open. 1.7 Pin Description Type A Circuit Remarks For high-speed operation · Oscillating feedback resistor: approx. 1 M during 5 V operation X1 X0 Standby control signal B For low-speed operation · Oscillating feedback resistor: approx. 4.5 M during 5 V operation · Switch is left open when a single clock is optionally selected. X1A X0A Standby control signal C · Input D · Output pull-up resistor (P-ch): approx. 50 k during 5 V operation · Hysteresis input R P-ch N-ch E · CMOS output · CMOS input · Hysteresis input R P-ch P-ch N-ch Port Resource · Pull-up resistor is optional Fig. 1.7c I/O Circuit Types 11 1.7 Pin Description Type Circuit F Remarks · CMOS output · CMOS input R P-ch P-ch N-ch · Pull-up resistor is optional G · CMOS output · Hysteresis input R P-ch P-ch N-ch · Pull-up resistor is optional H · CMOS output P-ch N-ch I · N-ch open-drain output R P-ch N-ch J · Pull-up resistor is optional · DTMF analog output OPAMP Fig. 1.7c I/O Circuit Types (Continued) 12 Chapter 1: OVERVIEW 1.8 Notes on Handling the Device 1.8 Notes on Handling the Device (1) Preventing latch-up The latch-up phenomenon occurs if a voltage higher than VCC, lower than VSS, or between VCC and VSS but still in excess of the rated voltage is applied to the input or output pins of a CMOS IC, other than those rated for a medium- or high-withstand voltage. When latch-up occurs, the supply current spikes up rapidly to the point where heat damage can result; therefore, when using CMOS ICs, it is important not to exceed the maximum ratings. (2) Treatment of unused input pins The IC may not operate correctly if input pins that are not used are left open; therefore, connect pull-up or pull-down resistors to unused input pins. (3) Treatment of N.C. pins Always leave N.C. pins (internally connected pins) open. (4) Supply voltage variation Although the guaranteed operating range for the VCC supply voltage is as stipulated, rapid fluctuations that remain within the prescribed range can still cause misoperation. Make every effort to assure that the voltage supplied to the IC is as stable as possible. As a standard for stability, it is recommended that the VCC ripple fluctuation (peak to peak value) at line frequencies (50 to 60 Hz) be kept to 10% or less of the typical VCC level, and that during momentary variations, such as when the power is turned on or off, the power supply be suppressed so that the rate of transient variation is 0.1 V/ms or less. (5) Note when using an external clock Even when an external clock is used, time is allowed for oscillation stabilization in the event of a power-on reset (optional) or exit from stop mode. 13 2.1 CPU Chapter 2: HARDWARE CONFIGURATION 2.1 CPU 2.1.1 Memory space The MB89170/170A MB89170/170A series memory space consists of 64 Kbytes, and includes all I/O, data, and program areas. The I/O area is located in the lowest-order addresses, and the data area is located right above that. The data area can be partitioned for different applications into a register area, stack area, direct address area, etc. The program area is located at the other end of the memory space in the highest-order addresses; within the program area, the tables for the interrupt and reset vectors and the vector call instructions are located at the very highest addresses. The memory space configurations in the MB89170/170A MB89170/170A series are shown in Fig. 2.1.1. MB89P175A MB89P175A MB89PV170A MB89PV170A 0000H 0000H 0000H 0000H I/O 0080H 0080H 0000H 0000H I/O 0080H 0080H RAM 1 Kbytes 0100H 0100H 0200H 0200H I/O RAM 512 Kbytes Registers Registers RAM 384 Kbytes 0100H 0100H Registers 0200H 0200H Registers 0280H 0280H Not available for use 0480H 0480H 32 Kbytes of external ROM 0080H 0080H 0100H 0100H 0280H 0280H 8000H 8000H I/O RAM 512 Kbytes 0200H 0200H Not available for use 0000H 0000H 0080H 0080H 0100H 0100H MB89P173 MB89P173 MB89173 MB89173 MB89174A MB89174A BFF0H C000H C000H 0200H 0200H Not available for use Not available for use Not available for use D000H D000H E000H E000H ROM 12 Kbytes ROM 16 Kbytes FFFFH FFFFH FFFFH ROM 8 Kbytes FFFFH Fig. 2.1.1 Memory Space in the MB89170/170A MB89170/170A Series 14 Chapter 2: HARDWARE CONFIGURATION 2.1 CPU · I/O area · Space is allocated for the control registers, data registers, etc., of internal peripheral functions. · Because the I/O area is a part of the memory space, it can be accessed in the same manner as memory. It can also be accessed at high speed via direct addressing. Addresses: 0000H 0000H to 007FH 007FH · RAM area · The MB89170/170A MB89170/170A series microcontrollers include static RAM for an internal data storage area. · The internal RAM capacitance varies according to the model. · From 80H to FFH, high-speed access via direct addressing is possible. · The area from 100H to 1FFH can be used as a general-purpose register area. Addresses: 0080H 0080H to the maximum RAM address for the model in question · ROM area · The MB89170/170A MB89170/170A series microcontrollers include ROM on chip as an internal program storage area. · The internal ROM capacitance varies according to the model. · The area from FFC0H to FFFFH is used for vector call instruction, interrupt and reset vector tables. Table 2.1.1 Reset and Interrupt Vector Tables Table address Vector call instruction Upper data Lower data CALLV #0 FFC0H FFC1H CALLV #1 FFC2H CALLV #2 Table address Interrupt name Upper data Lower data Interrupt #11 FFE4H FFE5H FFC3H Interrupt #10 FFE6H FFE7H FFC4H FFC5H Interrupt #9 FFE8H FFE9H CALLV #3 FFC6H FFC7H Interrupt #8 FFEAH FFEBH CALLV #4 FFC8H FFC9H Interrupt #7 FFECH FFEDH CALLV #5 FFCAH FFCBH Interrupt #6 FFEEH FFEFH CALLV #6 FFCCH FFCDH Interrupt #5 FFF0H FFF1H CALLV #7 FFCEH FFCFH Interrupt #4 FFF2H FFF3H Interrupt #3 FFF4H FFF5H Interrupt #2 FFF6H FFF7H Interrupt #1 FFF8H FFF9H Interrupt #0 FFFAH FFFBH Reset mode -*1 FFFDH Reset vector FFFEH FFFFH *1: FFFCH is reserved. 15 2.1 CPU 2.1.2 Arrangement of 16-bit data in memory As shown in Fig. 2.1.2a, when 16-bit data is written to memory, the upper byte of the data is written in the lower address and the lower byte is written in the next higher address. The data is handled in the same manner when it is read. Memory Before execution Memory 0080H 0080H MOVW 0081H 0081H, A After execution 0081H 0081H 12H 0082H 0082H A 1234H 1234H 0080H 0080H A 1234H 1234H 0081H 0081H 34H 0082H 0082H 0083H 0083H 0083H 0083H Fig. 2.1.2a Arrangement of 16-bit Data in Memory Similarly, when a 16-bit specification is made for an operand in an instruction, the upper byte is written in the address closer to the op code, and the lower byte is written in the next higher address. This is the case even when the operand shows the memory address for 16-bit immediate data. MOV A,5678H 5678H ; Extended address MOV A,#1234H 1234H ; 16-bit immediate data After assembly XXX0H XX XX XXX2H 60 56 78 ; Extended address XXX5H E4 12 34 ; 16-bit immediate data XXX8H XX Fig. 2.1.2b Arrangement of 16-bit Data within an Instruction In the same manner, when data in a 16-bit register is saved to the stack due to an interrupt, etc., the upper bit is stored in the smaller address. 16 Chapter 2: HARDWARE CONFIGURATION 2.1 CPU 2.1.3 Registers The MB89170/170A MB89170/170A series utilizes two types of registers: dedicated registers located in the CPU and general-purpose registers located in memory. The dedicated registers are listed below: Program counter (PC) : 16 bits; indicates where instructions are stored. Accumulator (A) : 16 bits; used as a temporary storage register while performing arithmetic operations, etc. 8-bit data processing instructions use only the lower byte. Temporary accumulator (T) : 16 bits; used to perform operations in conjunction with the accumulator. 8-bit data processing instructions use only the lower byte. Index register (IX) : 16 bits; index qualification register. Extra pointer (EP) : 16 bits; points to a memory address. Stack pointer (SP) : 16 bits; points to the stack area. Program status (PS) : 16 bits; stores the register pointer and the condition codes. 16 bits Initial value PC : Program counter A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Processor status FFFDH I flag = 0; IL1, IL0 = 11; other bits: undefined In addition, the PS can be divided into the upper 8 bits, which serve as the register bank pointer (RP), and the lower 8 bits, which serve as the condition code register (CCR). (Refer to Fig. 2.1.3a.) 15 PS 14 13 12 RP 11 10 9 Not used RP 8 7 6 5 4 H I IL1,0 3 2 1 0 N Z V C CCR Fig. 2.1.3a Structure of the Processor Status Register 17 2.1 CPU The RP shows the address of the register bank currently being used; the conversion principles governing the relationship between the contents of the RP and the actual address are illustrated in Fig. 2.1.3b below. Least significant bits of op code RP "0" Generated address A15 "0" "0" "0" "0" "0" "0" "1" R4 A14 A13 A12 A11 A10 A9 A8 R3 R2 R1 R0 b2 b1 b0 A7 A6 A5 A4 A3 A2 A1 A0 Fig. 2.1.3b Conversion Principles for Actual Addresses in the General-purpose Register Area The CCR includes bits that show operation results and the contents of transfer data, and also bits that control CPU operation when an interrupt is generated. H flag : This flag is set when a carry or a borrow occurred between bits 3 and 4 in the result of an operation, and is cleared at all other times. This flag is used for decimal-corrected instructions. I flag : Interrupts are enabled when this flag is set to "1", and are disabled when this flag is set to "0". This flag is set to "0" after a reset. IL1, 0 : Indicates the interrupt level that is currently enabled. Interrupt processing is performed only if there is an interrupt request of a higher priority than that indicated by these bits. IL1 IL0 0 Interrupt level 0 Priority High 1 0 1 1 0 2 1 1 3 Low = no interrupts N flag Z flag : This flag is set when the result of an operation is "0", and is cleared in all other cases. V flag : This flag is set when the result of an operation caused a two's complement overflow, and is reset when it did not. C flag 18 : This flag is set when the most significant bit of the result of an operation is "1", and is cleared when the most significant bit is "0". : This flag is set when the result of an operation caused a carry or borrow from bit 7, and is cleared in all other cases. In the case of a shift instruction, the C flag assumes the value of the bit that was shifted out. Chapter 2: HARDWARE CONFIGURATION 2.1 CPU The general-purpose registers are described as follows: General-purpose registers: 8 bits; store data. The general-purpose registers are 8-bit registers in a register bank in memory. One bank consists of eight registers, and in the MB89170/170A MB89170/170A series a total of 32 banks can be used. The bank that is currently being used is indicated by the register bank pointer (RP). This address = 0100H 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area Fig. 2.1.3c Register Bank Configuration 19 2.1 CPU 2.1.4 Operation mode The only operation mode available for the MB89170/170A MB89170/170A series is single-chip mode. The memory map is shown below. Address Single chip 0000H 0000H Internal I/O 0080H 0080H Internal RAM *0200H 0200H Prohibited *E000H E000H Internal ROM FFFFH *In MB89173 MB89173 only. Fig. 2.1.4 Memory Map The mode that the device operates in depends ultimately on the settings of the device mode pins and the contents of the mode data read during the reset sequence. The relationship between the state and operation of the device mode pins is shown in the table below. MOD1 MOD0 Description 0 0 Read reset vectors from internal ROM 1 1 Write mode for products with internal EPROM In addition, the following functions are selected by the mode data settings. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: FFFDH 0 0 0 0 0 T2 T1 T0 Normally, specify "0" for bits 7 to 3. Mode bits T2 T1 T0 0 0 0 Others 20 Operation Selects single-chip mode Reserved; do not set. Chapter 2: HARDWARE CONFIGURATION 2.1 CPU 2.1.5 Clock controller · This block controls standby operation, the oscillation stabilization time setting, software reset signal generation, clock switching settings, etc. (1) List of registers 8 bits Address: 0007H 0007H SYCC R/W System clock control register Address: 0008H 0008H STBC R/W Standby control register (2) Block diagram (2.1) Machine clock controller SCM CS0 CS1 SCS STP SLP TMD SPL Pin state Stop Prescaler 1/2 1/4 1/8 1/32 Low-speed clock oscillator circuit Sleep Selector High-speed clock oscillator circuit Watch Clock specification Selector Clock controller Peripheral circuit operation clock WT1 Time-base clock WT0 From time-base timer From watch CPU operation clock HC1 HC2 HC3 HC4 Selector Watch prescaler clock LC (2.2) Reset controller Internal reset signal Power-on reset Watchdog reset External reset Reset controller Software reset 21 2.1 CPU (3) Description of registers (3.1) STBC (standby control register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STP SLP SPL 00010XXXB 00010XXXB (W) Address: 0008H 0008H (initial value) (W) (R/W) RST TMD (W) - - - (W) [Bit 7]STP: Stop bit This bit specifies a transition to stop mode. 0 No effect 1 Stop mode This bit is cleared by a reset or by exiting stop mode. Whenever this bit is read, it returns a "0". [Bit 6]SLP: Sleep bit This bit specifies a transition to sleep mode. 0 No effect 1 Sleep mode This bit is cleared by a reset or by exiting sleep or stop mode. Whenever this bit is read, it returns a "0". [Bit 5]SPL: Pin state specification bit This bit specifies the external pin state in stop mode. 0 Hold state and level that were in effect immediately prior to stop mode 1 High impedance This bit is cleared by a reset. [Bit 4]RST: Software reset bit This bit specifies a software reset. 0 Generate a four-cycle reset signal 1 No effect Whenever this bit is read, it returns a "1". If a software reset is generated during submode operation, the oscillation stabilization interval is allowed for before changing to main mode; therefore, the reset signal is output during the oscillation stabilization interval. [Bit 3]TMD: Watch bit This bit specifies a transition to watch mode. 0 No effect 1 Watch mode This bit can be written only during submode operation (SCS = 0). Whenever this bit is read, it returns a "0". This bit is cleared by an interrupt request or a reset. 22 Chapter 2: HARDWARE CONFIGURATION 2.1 CPU (3.2) SYCC (system clock control register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: 0007H 0007H (initial value) SCM XXXMM100B XXXMM100B - - WT1 WT0 SCS CS1 CS0 (R/W) (R/W) (R/W) (R/W) (R/W) (R) 0 Subclock (while main clock is stopped or during main clock oscillation stabilization interval) 1 Main clock [Bit 7]SCM: System clock monitor bit This bit is used to check whether the current system clock is the main clock or the subclock. [Bit 4, bit 3] WT1, WT0: Oscillation stabilization time selection bit This bit selects the main clock oscillation stabilization wait time. Oscillation stabilization time (oscillation stabilization time with 3.58 MHz source oscillation) WT1 WT0 1 1 218/Fc (approx. 73.2 ms) 1 0 216/Fc (approx. 18.3 ms) 0 1 212/Fc (approx. 1.1 ms) 0 0 3 2 /Fc (approx. 0 ms) Fc: Main clock oscillation frequency When the main mode is specified by the system clock select bit (SCS) during submode operation, operation shifts to main mode after the selected wait time elapses. The initial value of this bit is determined by the mask option. Do not alter this bit during the oscillation stabilization wait time. Also, do not change this bit while switching from low-speed operation to high-speed operation. The main clock oscillation stabilization time is generated by dividing the main clock. Because the oscillating cycle is unstable immediately after the start of oscillation, use the times indicated in the above table only as a guide. [Bit 2]SCS: System clock select bit This bit specifies the system clock mode. 0 Selects subclock (32 kHz) mode 1 Selects main clock (3.58 MHz) mode [Bit 1, Bit 0]CS1, CS0: System clock select bit When main mode is specified by the system clock select bit (SCS), the instruction cycle is as shown in the table below. After the reset condition is exited, the system clock is 64/Fc. CS1 CS0 Instruction cycle Instruction execution time during 3.58 MHz operation 0 0 64/Fc 17.9 (µs) 0 1 16/Fc 4.47 (µs) 1 0 8/Fc 2.23 (µs) 1 1 4/Fc 1.11 (µs) Fc: Main clock oscillation frequency 23 2.1 CPU (4) Description of operation (4.1) Low-power consumption mode In order to reduce power consumption, the MB89170/170A MB89170/170A series microcontrollers have three main operation modes, plus sleep mode and stop mode, as shown in the table below. Main mode also permits selection from among four system clock levels, making it possible to reduce power consumption to a minimum. Table 2.1.5a Low-Power Consumption Mode Operation Modes Clock generation Main (CS1, Operation operation CS0) mode Main Sub modes clock clock RUN Operation clocks for each section (3.58 MHz operation clock) CPU Each Clock peripheral 1.8 MHz Oscillating (1,1) Timebase 1.8 MHz 1.8 MHz Oscillating Sleep 32 kHz Wakeup source in each mode Various interrupt requests Stopped Stop Stopped Stopped Various interrupt requests 0.9 MHz Oscillating (1,0) External interrupt 1.8 MHz 0.9 MHz RUN Stopped Oscillating Sleep 32 kHz Stopped Stop Main mode Stopped Stopped 0.45 MHz Various interrupt requests 0.45 MHz Oscillating (0,1) External interrupt 1.8 MHz RUN Stopped Oscillating Sleep 32 kHz Stopped Stop Stopped Stopped 112.5 kHz Various interrupt requests 112.5 kHz Oscillating (0,0) External interrupt 1.8 MHz RUN Stopped Oscillating Sleep 32 kHz Stopped Stop Stopped Stopped Sleep 32 kHz Various interrupt requests Stopped Stopped External interrupt Stopped External interrupt Watch interrupt 32 kHz Oscillating - External interrupt 32 kHz RUN Submode Stopped Stopped Stopped Stopped Stop Watch mode - Stopped Stopped Oscillating Stopped Stopped 32 kHz · In submode, the oscillation of the main clock is stopped. · In sleep mode, only the CPU operation clock is stopped; the other clocks operate. · In watch mode, all clock pulses except for specific resources are stopped. · In stop mode, oscillation is stopped; data can be retained with minimal power consumption in this mode. 24 Chapter 2: HARDWARE CONFIGURATION 2.1 CPU (4.1.1) Watch mode · Transition to watch mode The microcontroller enters watch mode when "1" is written to the TMD bit in the STBC register. If "1" is written to the SCS bit in the SYCC register, however, the writing of "1" to the TMD bit is ignored. In watch mode, all chip functions are stopped, except for the watch prescaler, external interrupts, and the wakeup function. Whether the input/output pins and the output pins either maintain the state they were in before the chip entered watch mode or else go to high impedance can be controlled by the SPL bit in the STBC register. If an interrupt request had already been generated when a "1" is written to the TMD bit, the microcontroller does not enter watch mode, but instead continues to execute instructions. The previous register and RAM contents are maintained in watch mode. · Exiting watch mode Watch mode is exited either by the reset signal being input or by an interrupt. If a reset is input while in watch mode, the microcontroller enters the reset state and watch mode is exited. If an interrupt request with an interrupt level higher than "11" is generated by a peripheral circuit, etc., while in watch mode, watch mode is released. After recovery, just as with normal interrupt processing, if the interrupt is accepted by the I flag and the IL, then interrupt processing is executed; if not accepted, processing is resumed starting from the next instruction after the last one that was executed before the microcontroller entered watch mode. When recovery results from a reset while in watch mode, the microcontroller enters the oscillation stabilization wait state; therefore, the reset sequence is not executed until after the oscillation stabilization time elapses. In addition, the oscillation stabilization time is the main clock oscillation stabilization time selected by the WT1 and WT0 bits. However, when the mask option for no power-on reset is set, then when recovery results from a reset while in watch mode, the microcontroller does not enter the oscillation stabilization wait state. (4.1.2) Sleep mode · Transition to sleep mode The microcontroller enters sleep mode when "1" is written to the SLP bit in the STBC register. In sleep mode, all clocks used by the CPU are stopped, so that the CPU stops operating but the peripheral circuits continue to operate. If an interrupt request had already been generated when a "1" is written to the SLP bit, the microcontroller does not enter sleep mode, but instead continues to execute instructions. The previous register and RAM contents are maintained in sleep mode. · Exiting sleep mode Sleep mode is exited either by the reset signal being input or by an interrupt. If a reset is input while in sleep mode, the microcontroller enters the reset state and sleep mode is exited. If an interrupt request with an interrupt level higher than "11" is generated by a peripheral circuit, etc., while in sleep mode, sleep mode is exited. After recovery, just as with normal interrupt processing, if the interrupt is accepted by the I flag and the IL, then interrupt processing is executed; if not accepted, processing is resumed starting from the next instruction after the last one that was executed before the microcontroller entered sleep mode. 25 2.1 CPU (4.1.3) Stop mode · Transition to stop mode The microcontroller enters stop mode when "1" is written to the STP bit in the STBC register. Stop mode differs for main clock operation and subclock operation. During main clock operation: The main clock stops oscillating and the subclock continues oscillating. All chip functions are stopped, except for the watch function. However, watch interrupts are not accepted. During subclock operation: Both the main clock and the subclock stop oscillating. All chip functions are stopped. Whether the input/output pins and the output pins either maintain the state they were in before the chip entered stop mode or else go to high impedance can be controlled by the SPL bit in the STBC register. If an interrupt request had already been generated when a "1" is written to the STP bit, the microcontroller does not enter stop mode, but instead continues to execute instructions. The previous register and RAM contents are maintained in stop mode. · Exiting stop mode Stop mode is exited either by the reset signal being input or by an interrupt. If a reset is input while in stop mode, the microcontroller enters the reset state and stop mode is exited. If an interrupt request with an interrupt level higher than "11" is generated by an external interrupt circuit while in stop mode, stop mode is exited. After recovery, once the oscillation stabilization time has elapsed, then just as with normal interrupt processing, if the interrupt is accepted by the I flag and the IL, then interrupt processing is executed; if not accepted, processing is resumed starting from the next instruction after the last one that was executed before the microcontroller entered stop mode. One of four main clock oscillation stabilization times can be selected through the WT1 and WT0 bits. The subclock oscillation stabilization time is fixed at 215/FCL 215/FCL (FCL: subclock frequency). When recovery results from a reset while in stop mode, the microcontroller enters the main mode oscillation stabilization wait state; therefore, the reset sequence is not executed until after the oscillation stabilization time elapses. In addition, the oscillation stabilization time is the main clock oscillation stabilization time selected by WT1 and WT0 bits. However, when the mask option for no power-on reset is set, then when recovery results from a reset while in stop mode, the microcontroller does not enter the oscillation stabilization wait state. 26 Chapter 2: HARDWARE CONFIGURATION 2.1 CPU (4.1.4) Low-power consumption mode settings STBC register STP (Bit 7) SLP (Bit 6) TMD (Bit 3) Mode 0 0 0 Normal 0 0 1 Watch 0 1 0 Sleep 1 0 0 Stop 1 X X Prohibited Note: Do not enter stop mode, sleep mode, or watch mode when switching from subclock mode to main clock mode. When the SCS bit of the SYCC register has been overwritten from "0" to "1", enter these modes after the SCM bit of the SYCC register has changed to "1". 27 2.1 CPU (4.2) State transition diagram (24) (27) Main: sleep Main: oscillating Sub : oscillating Main: STOP Main: stopped Sub : oscillating (7) Sub: sleep Main: stopped Sub : oscillating (26) (29) (5) (16) (4) Main clock: waiting for (3) oscillation stabilization Main: RUN Main: oscillating Sub : oscillating (6) (17) (1) (2) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) 28 Product with "power-on reset" option selected Product with "no power-on reset" option selected After oscillation stabilization Set STP bit to "1". Set SLP bit to "1". Set SCS bit to "0". External reset in product with "no power-on reset" option selected External reset or interrupt in product with "poweron reset" option selected External reset or interrupt External reset in product with "no power-on reset" option selected External reset or other reset in product with "poweron reset" option selected Set SCS bit to "1". After oscillation stabilization Set STP bit to "1". Set TMD bit to "1". Set SLP bit to "1". After oscillation stabilization, or external reset in product with "no power-on reset" option selected Chapter 2: HARDWARE CONFIGURATION Sub: STOP Main: stopped Sub : stopped (21) (12) (22) (23) (13) (19) Sub: RUN Main clock: waiting for oscillation stabilization Power : ON (15) Sub : RUN (14) Main: stopped (10) Sub : oscillating (11) (18) (25) (28) (9) (8) Watch Main: stopped Sub : oscillating Sub clock: waiting for oscillation stabilization (20) (18) External reset or other reset in product with "poweron reset" option selected (19) After oscillation stabilization, or external reset in product with "no power-on reset" option selected (20) External reset in product with "power-on reset" option selected (21) External reset in product with "no power-on reset" option selected (22) Interrupt (23) External reset in product with "power-on reset" option selected (24) External reset in product with "power-on reset" option selected (25) External reset in product with "no power-on reset" option selected (26) Interrupt (27) External reset in product with "power-on reset" option selected (28) External reset in product with "no power-on reset" option selected (29) Interrupt 2.1 CPU (4.3) Reset There are four sources of resets, as shown in Table 2.1.5b. Table 2.1.5b Reset Sources Reset name Description External pin reset Set the external reset pin to low level. Software reset Write "0" to the RST bit in the STBC. Watchdog reset Watchdog timer overflow Power-on reset Turn power supply on In the case of a power-on reset or a reset during stop mode, because the oscillator is stopped, it is necessary to provide the oscillation stabilization time after the oscillator resumes operation; the stabilization time is allowed for the timebase timer or the watch prescaler. As a result, operation does not begin immediately after exit of the reset condition. However, if the "no power-on reset" mask option has been selected, no oscillation stabilization time is provided after the exit of the external pin reset, no matter what the status is. Note: When the "no power-on reset" option has been selected, keep the RST pin at low level until the oscillation stabilization time that would have been in effect if the reset option had been selected elapses after power is supplied to the microcontroller. 29 2.1 CPU (5) Single clock The microcontroller can be operated with a single clock if that mask option has been selected. Single clock operation is the same as dual clock operation, except that the microcontroller does not enter subclock mode. Accordingly, the subclock input pins X0A and X1A should be connected to GND. (5.1) State transition diagram Main: sleep Main:oscillating (7) (9) Main: STOP Main: stopped (5) (8) (4) (3) Main clock: waiting for oscillation stabilization (1) (2) Power : ON (1) (2) (3) (4) (5) (7) Product with "power-on reset" option selected Product with "no power-on reset" option selected After oscillation stabilization Set STP bit to "1". Set SLP bit to "1". External reset in product with "no power-on reset" option selected (8) External reset or interrupt in product with "poweron reset" option selected (9) External reset or interrupt 30 Chapter 2: HARDWARE CONFIGURATION Main: RUN Main:oscillating 2.1 CPU 2.1.6 Interrupt controller · The interrupt controller for the F2MC-8L family is located between the CPU and the various peripheral resources. The interrupt controller accepts interrupt requests from the peripheral resources, and sends them to the CPU in the order of their priority. The interrupt controller also determines the priority of the interrupts having the equivalent level. (1) Register list 8 bits Address: 007CH 007CH ILR1 W Interrupt level setting register #1 Address: 007DH 007DH ILR2 W Interrupt level setting register #2 Address: 007EH 007EH ILR3 W Interrupt level setting register #3 (2) Block diagram CPU Internal bus G L Level Peripheral resource #2 G L Level Peripheral resource #n G L Level G G Interrupt vector generator Peripheral resource #1 Identical level priority determination block /2 Address decoder Level determination block Test register G 31 2.1 CPU (3) Description of registers (3.1) ILRx (interrupt level setting registers) The ILRx registers set the interrupt levels for each resource. The interrupt number corresponds to the center digit of each bit name. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (initial value) Address: 007CH 007CH L31 L30 L21 L20 L11 L10 L01 L00 11111111B 11111111B Address: 007DH 007DH L71 L70 L61 L60 L51 L50 L41 L40 11111111B 11111111B Address: 007EH 007EH LB1 LB0 LA1 LA0 L91 L90 L81 L80 11111111B 11111111B (W) (W) (W) (W) (W) (W) (W) (W) [Bit 7, Bit 6] [Bit 5, Bit 4] [Bit 3, Bit 2] [Bit 1, Bit 0] Lx1, Lx0 : interrupt level setting bit Lx1 Lx0 0 Request interrupt level 0 Priority ranking High 1 0 1 1 0 2 1 1 3 Low (interrupt not accepted) The interrupt level setting registers allocate two bits for each interrupt source. The interrupt processing priority ranks (interrupt levels 1 to 3) are determined by the settings of these registers. Note that when interrupt level 3 (Lx1, Lx0 = "11") is set, that interrupt is not accepted. [Example] L3× MB89170/170A MB89170/170A specifications Interrupt control module IR0 #0 FFFA FFFB IR1 #1 FFF8 FFF9 IR2 #2 FFF6 FFF7 IR3 #3 FFF4 FFF5 #11 Interrupt request from peripheral resource Interrupt number FFE4 FFE5 IRB 32 Chapter 2: HARDWARE CONFIGURATION Table address Upper Lower 2.1 CPU (4) Description of operation (4.1) Interrupt function The MB89170/170A MB89170/170A series microcontrollers have eight inputs for interrupt requests from peripheral resources; in addition, the interrupt level can be set in 2-bit level registers corresponding to each input. If an interrupt is generated in a peripheral resource, the interrupt controller (which receives the interrupt) outputs the contents of the corresponding level register to the CPU. Interrupt processing for the device as a whole is handled as described below. (1) An interrupt source is generated within a peripheral resource. (2) If the interrupt enable bit within the peripheral resource is set so that the interrupt is enabled, the peripheral resource issues an interrupt request to the interrupt controller. (3) After receiving the interrupt request, the interrupt controller determines the order of priority among all of the interrupt requests that were received at the same time and then sends the interrupt level corresponding to the appropriate interrupt to the CPU. (4) The CPU compares the interrupt level for which there was a request from the interrupt controller with the IL bits in the processor status register. (5) Only if the results of the comparison indicate that the priority of the interrupt level of the request is higher than that of the current interrupt processing level, the CPU then checks the contents of the I flag in the processor status register. (6) Only if the results of the check of the I flag in step 5 indicate that interrupts are enabled, the CPU sets the IL bits to the level of the request, and then as soon as the instruction that is currently being executed ends, the CPU performs the interrupt processing and passes control to the interrupt processing routine. (7) When the interrupt source that was generated in step 1 is cleared by the software in the user interrupt processing routine, interrupt processing terminates. Fig. 2.1.6 shows an overview of interrupt operations in the MB89170/170A MB89170/170A series. Internal bus PS Register file IPLA IR (6) I Check IL (5) Comparator (4) MB89170 MB89170 CPU (3) Enable FF AND Source FF (7) (1) Peripheral (2) resource Level comparator Peripheral resource Interrupt controller Fig. 2.1.6 Overview of Interrupt Operations 33 C a t r2 h pe : HARD- 2.2 Peripheral Functions 2.2 Peripheral Functions 2.2.1 I/O ports · The microcontrollers in the MB89170/170A MB89170/170A series have 5 parallel ports (37 pins). Ports 0, 1, and 3 are 8-bit input/output ports, port 2 is an 8-bit output-only port, and port 4 is a 5-bit output-only port. · Ports 0 and 3 also serve as I/O pins for various resource functions. (1) Port function list Table 2.2.1 List of Functions of Each Port Pin name Input type Output type P00 to CMOS CMOS P07 (hysteresis) push-pull Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Parallel port 0 P07 P06 P05 P04 P03 P02 P01 P00 Resources LI7 LI6 LI5 LI4 LI3 LI2 LI1 LI0 P10 to P17 CMOS CMOS push-pull Parallel port 1 P17 P16 P15 P14 P13 P12 P11 P10 P20 to P27 - CMOS push-pull Parallel port 2 P27 P26 P25 P24 P23 P22 P21 P20 Parallel port 3 P37 P36 P35 P34 P33 P32 P31 P30 Resources BZ INT2 INT1 Parallel port 4 - P30 to CMOS CMOS P37 (hysteresis) push-pull P40 to P44 - N-ch open drain - - TO/ EC INT0 P44 P43 SI P42 SO SCK P41 (2) Register list 8 bits Address: 0000H 0000H Address: 0001H 0001H DDR0 Address: 0002H 0002H PDR1 Address: 0003H 0003H DDR1 Address: 0004H 0004H PDR2 R/W Port 2 data register 00000000B 00000000B Address: 000CH 000CH PDR3 R/W Port 3 data register XXXXXXXXB Address: 000DH 000DH DDR3 R/W Port 3 direction register 00000000B 00000000B Address: 000EH 000EH 34 PDR0 PDR4 R/W Port 4 data register XXX11111B XXX11111B Chapter 2: HARDWARE CONFIGRATION R/W Port 0 data register XXXXXXXXB W Port 0 direction register 00000000B 00000000B R/W Port 1 data register W Port 1 direction register XXXXXXXXB 00000000B 00000000B P40 2.2 Peripheral Functions (3) Description of functions (3.1) P00 to P07 CMOS-type input/output ports (also used for wakeup interrupt inputs) P10 to P17 CMOS-type input/output ports · Switching between input and output Each bit has a DDR (direction register) and a PDR (data register), so that each bit can be set for input or output independently. Pins for which the DDR is set to "1" are set for output, and pins for which the DDR is set to "0" are set for input. · Operation as an output port (DDR = 1) If the DDR for a pin is set to "1", the value written in the PDR is output as is. Normally, reading the PDR yields the value of the pin, not the contents of the output latch. However, because it is possible to read the contents of the output latch regardless of the state of the DDR register when executing a readmodify-write instruction, bit processing instructions can be used even when input and output are mixed together. This is due to the fact that the output latch data (for the other bits) is protected, regardless of the pin input/output direction and state. Furthermore, regardless of the DDR setting, whenever data is written to the PDR, the data that is written is retained in the output latch. · Operation as an input port (DDR = 0) The output goes to high impedance and reading the PDR yields the value of the pin. · State when reset The DDR is initialized to "0" and the output for all bits goes to high impedance. However, pins with a pull-up resistor selected as a mask option go to the pulled-up state. Because the PDR is not initialized, it is necessary to set a value in the PDR before setting the DDR for output. · State in watch and stop modes If the SPL bit in the standby control register is set to "1", the output goes to high impedance in watch mode and stop mode, regardless of the value of the DDR. However, pins with a pull-up resistor selected as a mask option go to the pulled-up state. External interrupts External interrupt enable P00 to P07 only PDR Internal data bus Stop, watch mode Pull-up resistor (optional) PDR read PDR read (during read-modify-write operation) Output latch P-ch PDR write Pin DDR N-ch DDR write Stop, watch mode (SPL = 1) Fig. 2.2.1a Port 0 and Port 1 35 2.2 Peripheral Functions (3.2) P20 to P27 CMOS-type output-only ports · Operation as an output port The pins output the values written in their PDR. Because reading the PDR always yields the contents of the output latch, the output latch data (for the other bits) is not affected even by read-modify-write instructions, such as bit processing instructions. · State when reset When a reset is executed, the pins go to high impedance; port output is enabled and the pins begin to function as output ports the moment that the vector fetch is performed. The PDRs are initialized to "0" by the reset operation, and the pins output a low signal. · State in watch and stop modes If the SPL bit in the standby control register is set to "1", the output goes to high impedance in watch mode and stop mode, regardless of the value of the PDR. Internal data bus PDR PDR read Output buffer Output latch Pin PDR write Stop, watch mode (SPL = 1) Fig. 2.2.1b Port 2 (3.3) P30 to P37 CMOS-type input/output ports (also serve as resource input/output pins) · Switching between input and output Each bit has a DDR (direction register) and a PDR (data register), so that each bit can be set for input or output independently. Pins for which the DDR is set to "1" are set for output, and pins for which the DDR is set to "0" are set for input. In addition, if the resource output enable bit is set to "enable," the pin in question is set to output, regardless of the setting of the DDR. · Operation as an output port (DDR = 1) If the DDR for a pin is set to "1", the value written in the PDR is output as is. Normally, reading the PDR yields the value of the pin, not the contents of the output latch. However, because it is possible to read the contents of the output latch, regardless of the state of the DDR register, when executing a readmodify-write instruction, bit processing instructions can be used even when input and output are mixed together. This is due to the fact that the output latch data (for the other bits) is protected regardless of the pin input/output direction and state. Furthermore, regardless of the DDR setting, whenever data is written to the PDR, the data that is written is retained in the output latch. · Operation as an input port (DDR = 0) The output goes to high impedance and reading the PDR yields the value of the pin. 36 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions · Operation as a resource output When these pins are used as resource outputs, it is necessary to set the corresponding resource output enable bit. (Refer to the descriptions concerning the individual resources.) Because the setting of the resource output enable bit has priority in regards to input/output switching, if output by a resource is enabled, then that pin is set as a resource output, even if the DDR is set to "0". Because the port can still be read even when resource output is enabled, the resource output value can be read. · Operation as a resource input When the port is also used as a resource input, the pin value is always input to the resource input, regardless of the DDR and resource settings. When external signals are used by the resource, set the DDR to "input." · State when reset The DDR and each resource output enable bit are initialized to "0" and the output for all bits goes to high impedance. However, pins with a pull-up resistor selected as a mask option go to the pulled-up state. Because the PDR is not initialized, it is necessary to set a value in the PDR before setting the DDR for output. · State in watch and stop modes If the SPL bit in the standby control register is set to "1", the output goes to high impedance in watch mode and stop mode, regardless of the value of the DDR. However, pins with a pull-up resistor selected as a mask option go to the pulled-up state. Resource input PDR Stop, watch mode Pull-up resistor (optional) Internal data bus PDR read Resource output PDR read (during read-modify-write operation) Resource output enable Output latch P-ch PDR write Pin DDR N-ch DDR write Stop, watch mode (SPL = 1) PDR read Fig. 2.2.1c Port 3 37 2.2 Peripheral Functions (3.4) P40 to P44 N-ch open-drain output-only ports · Operation as an output port The value written in the PDR is output as is. Reading the PDR always yields the contents of the output latch; the state of the pin cannot be read. · State when reset The PDR is initialized to "1" and the output transistors for all pins go to the OFF state. However, pins with a pull-up resistor selected as a mask option go to the pulled-up state. · State in watch and stop modes If the SPL bit in the standby control register is set to "1", the output goes to high impedance in watch mode and stop mode, regardless of the value of the PDR. However, pins with a pull-up resistor selected as a mask option go to the pulled-up state. Pull-up resistor (optional) Internal data bus PDR PDR read Output buffer Output latch PDR write Stop, watch mode (SPL = 1) Fig. 2.2.1d Port 4 38 Chapter 2: HARDWARE CONFIGRATION Output transistor Pin 2.2 Peripheral Functions 2.2.2 8-/16-bit timer (timer 1, timer 2) · The clock input can be selected from among three internal clocks and one external clock. · Can operate in either 8-bit 2-ch mode or 16-bit 1-ch mode. · Square wave output function provided. (1) Register list 8 bits Address: 0018H 0018H T2CR R/W Timer 2 control register Address: 0019H 0019H T1CR R/W Timer 1 control register Address: 001AH 001AH T2DR R/W Timer 2 data register Address: 001BH 001BH T1DR R/W Timer 1 data register (2) Block diagram T1STR T1STP T1CS0 T1CS1 2 / 2.23 µs 35.8 µs 572 µs P33/EC P33/EC T1OS0 T1OS1 T1IE Square wave output initialization pin control M P X Pin control / 2 R.S Q 8-bit counter TFF CO EQ Comparator data latch Internal data bus CLR LOAD Data register Data register LOAD Comparator data latch Comparator 572 µs P34/T0 P34/T0 CK Comparator 2.23 µs 35.8 µs Interrupt request IRQ3 T1IF EQ CLR M P X CK 8-bit counter 2 / T2STR T2STP T2CS0 T2CS1 T2OS01 T2OS01 T2OS1 T2IE T2IF 39 2.2 Peripheral Functions (3) Description of registers (3.1) T1CR (timer 1 control register) Bit 7 T1IF T1IE T1OS1 T1OS0 T1CS1 T1CS0 T1STP T1STR X000XXX0B X000XXX0B (R/W) Address: 0019H 0019H Bit 6 Bit 5 (R/W) (R/W) Bit 4 Bit 3 (R/W) (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (initial value) (R/W) [Bit 7]T1IF: Interrupt request flag bit (when written) 0 Clears interrupt request flag 1 No effect 0 No interrupt request 1 Interval interrupt request (when read) [Bit 6]T1IE: Interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled [Bit 5, Bit 4]T1OS1, T1OS0: Square wave output control bit T1OS1 T1OS0 0 0 Square wave output port TO serves as a general-purpose port 0 1 Hold data that sets the square wave output low 1 0 Hold data that sets the square wave output high 1 1 Set the square wave output to the value of the hold data When T1STR is "0", the square wave output is set to the setting value. [Bit 3, Bit 2]T1CS1, T1CS0: Clock source selection bit T1CS1 T1CS0 Clock cycle time When source oscillation is 3.58 MHz 0 0 2 tinst *1 2.23 [µs] 0 1 32 tinst *1 35.8 [µs] 1 0 512 tinst *1 572 [µs] 1 1 External clock - *1: tinst = instruction cycle (source oscillation divided by four) [Bit 1]T1STP: Timer stop bit 0 Continuous operation without clearing the counter 1 Temporary stop of count operation [Bit 0]T1STR: Timer startup bit 0 1 40 Operation stopped Clear counter and start operation Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions (3.2) T2CR (timer 2 control register) Bit 7 T2IF T2IE T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR X000XXX0B X000XXX0B (R/W) Address: 0018H 0018H Bit 6 Bit 5 (R/W) (R/W) Bit 4 Bit 3 (R/W) (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (initial value) (R/W) [Bit 7]T2IF: Interrupt request flag bit (when written) 0 Clears interrupt request flag 1 No effect 0 No interrupt request 1 Interval interrupt request (when read) [Bit 6]T2IE: Interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled [Bit 5, Bit 4]T2OS1, T2OS0: Unused bits T2OS1 T2OS0 0 0 Always set to "00" 0 1 Prohibited to set 1 0 Prohibited to set 1 1 Prohibited to set [Bit 3, Bit 2]T2CS1, T2CS0: Clock source selection bit T2CS1 T2CS0 Clock cycle time When source oscillation is 3.58 MHz 0 0 2 tinst *1 2.23 [µs] 0 1 32 tinst *1 35.8 [µs] 1 0 512 tinst *1 572 [µs] 1 1 16-bit mode - *1: tinst = instruction cycle (source oscillation divided by four) When used as a 8-bit timer, be sure to set these two bits to other than "11". [Bit 1]T2STP: Timer stop bit 0 Continuous operation without clearing the counter 1 Temporary stop of count operation [Bit 0]T2STR: Timer startup bit 0 Operation stopped 1 Clear counter and start operation 41 2.2 Peripheral Functions (3.3) T1DR, T2DR (timer 1 and 2 data registers) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: 001BH 001BH (initial value) XXXXXXXXB (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Address: 001AH 001AH XXXXXXXXB (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) The write data is the interval time setting value, and the read data is the counter value. (4) Description of operation (4.1) 8-bit internal clock mode 8-bit internal clock mode permits the selection of one of three internal clocks according to the setting of the clock source specification bits (T1CS1 and T1CS0 or T2CS1 and T2CS0) in the timer control register (T1CR or T2CR). The timer data register (T1DR or T2DR) serves as an interval time setting register. When starting up the timer, set the interval time in the data register, and then write "1" to the timer startup bit (T1STR or T2STR) in the timer control register. Doing so clears the counter to 00H and loads the data register value into the comparator latch. The count-up operation then begins. If the counter value matches the value set in the data register, the interval interrupt request flag (T1IF or T2IF) is set to "1". At this point the counter is cleared to 00H, the data register value is reloaded into the comparator latch, and the count-up operation continues. In addition, if the interrupt enable bit (T1IE or T2IE) is set to "1", an interrupt request is sent to the CPU. The interval time "T" is calculated as follows: T=ø × (n+1) [µs] where: n: value set in the data register ø: selected clock 42 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions Match Match Match Counter clear Set data value Comparator latch Count 0000H 0000H T1STR T1IF T1IF="0"(W) T1IF="0"(W) T1IF="0"(W) T0 terminal Fig. 2.2.2a Timing Chart for Internal Clock Mode Operation Operation mode specification Interval timer setting Timer startup T1STR="0", T1IF="0", T1IE="0" T1IF="1" Interrupt processing Main program T1IF="0"(W) Fig. 2.2.2b Timer Setting Flow Chart 43 2.2 Peripheral Functions (4.2) Initial setting of square wave output The square wave output allows any desired value to be set only when timer operation is stopped (T1STR = 0, T2STR = 0). The setting procedure is as follows: (1) Write the setting values "01,10" to the square wave output initial value setting bits (T1OS1 and T1OS0). At this point the value is held in the level latch shown in the diagram below, but is not output on the pin. (Note that the previous square wave state is output on the pin.) (2) Write "11" to the same bits. This operation initializes the square wave output to the set value. Assuming T1STR is "0", the square wave output during the write cycle will be the value that was set in step (1) above. The pin state for the square wave output as a result of steps (1) and (2) is shown below. (3) Set T1STR to "1" to start the timer. These initial value setting bits can be set by bit manipulation instructions. T1STR Level latch T1OS1 D Q QX D Q QX T1OS0 D Q QX Sets output pin high Sets output pin low D Q QX Write Fig. 2.2.2c Initial setting Pin state (P34) Port Timer Square wave output Previous square wave Á Á Á Á Á Set value (1) (2) (3) Overflow Overflow (4.3) 8-bit external clock mode In external clock mode, external clock input is selected by the clock source selection bits (T1CS1 and T1CS0) in the timer 1 control register (T1CR). The external clock input pin for the timer corresponds to P33/EC P33/EC. To start up the timer, write a "1" to the T1CR timer startup bit (T1STR) to clear the counter, after which the count-up operation starts. If the counter value matches the value set in the data register, the interval interrupt request flag (T1IF) is set to "1". At this point, if the interrupt enable bit (T1IE) is set to "1", an interrupt request is sent to the CPU. 44 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions EC Counter clear TSTR=1 Count Undefined 00 00H 01H 02H FEH FFH 00H FFH T1DR 01H FFH T1IF T1IF=0(W) Fig. 2.2.2d Timing Chart for External Clock Mode Operation (4.4) Notes on using the timer stop bit When the timer has been stopped by the timer startup bit after using the timer stop bit to pause the timer, the count value may advance by one due to the clock that is input to the timer, as shown in Fig. 2.2.2e. (The count does not advance if the input clock signal is high, but does advance if the signal is low.) Therefore, if the timer stop bit is used to pause the timer, read the counter before setting the startup bit to "0". When input clock is high When input clock is low Clock input to the timer (EC, internal clock) Count "01"H "02"H "02"H "01"H Á "01" Á Á Pause output Á "01"H Stop Pause Stop "11" "10"or "00" "01" "11" "10"or "00" Fig. 2.2.2e Operation when Using the Timer Stop Bit 45 2.2 Peripheral Functions (4.5) 16-bit mode In 16-bit mode, the settings of the bits in the timer control registers are as shown below. Bit 7 T1IE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Bit 7 Address: 0018H 0018H T1IF (R/W) Address: 0019H 0019H Bit 6 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 T2IF T2IE Don't care Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1OS1 T1OS0 T1CS1 T1CS0 T1STP T1STR Bit 1 Bit 0 T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR Set to "00" Set to "11" Don't care In 16-bit mode, set the T2CS1 and T2CS0 bits in T2CR to "11". In 16-bit mode, timer control is performed through T1CR. In addition, of the data registers, T2DR is the high-order byte and T1DR is the low-order byte. The clock source selection is made by the T1CS1 and T1CS0 bits in T1CR. To start up the timer, write a "1" to the T1STR bit in T1CR to clear the counter, after which the count-up operation starts. If the counter value matches the value set in the data register, the T1IF bit is set to "1". At this point, if the T1IE bit is set to "1", an interrupt request is sent to the CPU. Note: When reading the counter value while operating in 16-bit mode, always read the value twice in order to determine if it is valid or not before actually using the value. · For the timing chart, refer to the timing chart for 8-bit mode operation. (4.6) Timer startup and pause (1) When clearing the counter and then commencing the counting operation When the T1STR bit is "0", write "01" to the T1STP and T1STR bits, respectively. The timer is cleared and the counting operation begins at the edge when the T1STR bit changes from 0 to 1. (2) When pausing the timer and then commencing the counting operation without clearing the counter When pausing the counting operation, write "11" to the T1STP and T1STR bits. To resume the count from the paused state without clearing the counter, change the T1STP and T1STR bits from "11" to "01". The following table shows the timer states in relation to the T1STP and T1STR bits, as well as the operation of the timer when it is started up from that state (by setting the T1STP and T1STR bits to "01"). 46 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions T1STP T1STR (T2STP) (T2STR) Timer state Operation of timer when started up (bit 1, 0 = 01) from the state shown at left 0 0 Counting operation stopped Counter is cleared first and then counting operation commences 0 1 Counting operation in progress Counting operation continues 1 0 Counting operation stopped Counter is cleared first and then counting operation commences 1 1 Counting operation paused Counting operation continues without clearing the counter (4.7) Notes on usage The output (free run) of the internal prescaler is used for the timer's internal clock. When using each 8-bit timer as one channel, first set a value other than "11" in bits 2 and 3 of the T2CR. T2CR needs to be initialized even when the timer 1 alone is used in 8-bit mode. 47 2.2 Peripheral Functions 2.2.3 8-bit serial I/O · This serial I/O permits 8-bit serial data transfer through the clock synchronization method. · LSB first/MSB first can be selected for data transfer. · Four types of shift clock modes (three internal, one external) can be selected. (1) Register list 8 bits Address: 001CH 001CH SMR R/W Serial mode register Address: 001DH 001DH SDR R/W Serial data register (2) Block diagram Internal data bus D0 to D7 (MSB first) D7 to D0 (LSB first) Transfer direction selection SIOF SIOE (Shift direction) SCKE Á Á Á Á Á Á SOE SDR (Serial data register) CKS1 Overflow CKS0 BDS P32/SI P32/SI SO output synchronization circuit SI input synchronization circuit SST /2 SMR (Serial mode register) P31/SO P31/SO Output enable Output enable P30/SCK P30/SCK Internal clock Shift clock selection Controller IRQ4 / 3 clear Shift clock counter 48 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions (3) Description of registers (3.1) SMR (serial mode register) This is the serial I/O control register. Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (initial value) SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST 00000000B 00000000B (R/W) Address: 001CH 001CH Bit 6 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [Bit 7]SIOF: Serial I/O interrupt request flag This flag indicates the serial I/O transfer status. When read, this flag has the following meanings. 0 Serial data transfer has not terminated 1 Serial data transfer has terminated (is terminating) Note that during the read portion of a read-modify-write instruction, reading this flag always returns a value of "1". In addition, if interrupts are enabled (SIOE="1"), when this bit is set an interrupt request is sent to the CPU. Writing this flag has the following effects. 0 Clears this bit 1 No effect on this bit or other bits Either this bit or the SST (bit 0 of the SMR) can be used to determine when a transfer has terminated. [Bit 6]SIOE: Serial I/O interrupt enable bit This bit enables serial I/O interrupt requests. 0 Serial I/O interrupt output disabled 1 Serial I/O interrupt output enabled [Bit 5]SCKE: Shift clock output enable bit This bit controls the shift clock input/output pin. 0 General-purpose port pin (P30) or SCK input pin 1 SCK (shift clock) output pin Note that, when using the P30/SCK P30/SCK pin for an external clock, always set it for "input" (set bit 0 of DDR3 to "0"). [Bit 4]SOE: Serial data output enable bit This bit controls the external pin for serial I/O output. 0 General-purpose port pin (P31) 1 SO (serial data) output pin Note that when using the P32/SI P32/SI pin as the SI pin, always set it for "input" (set bit 2 of DDR3 to "0"). 49 2.2 Peripheral Functions [Bit 3, Bit 2]CKS1, CKS0: Shift clock mode selection bits These bits select the serial shift clock mode. Source oscillation: 3.58 MHz SCK 2 tinst *1 2.23 [µs] Output 8 tinst *1 8.94 [µs] Output 0 Internal clock 32 tinst *1 35.8 [µs] Output 1 External clock - Input CKS1 CKS0 Shift clock mode selection 0 0 Internal clock 0 1 Internal clock 1 1 *1: tinst = instruction cycle (source oscillation divided by four) [Bit 1]BDS: Transfer direction selection bit During serial data transfers, this bit selects whether to transfer the least significant bit first (LSB first) or the most significant bit first (MSB first). 0 LSB first 1 MSB first Note that if this bit is overwritten after the data has been written to the SDR, that data becomes invalid. [Bit 0]SST: Serial I/O transfer start bit This is the serial I/O transfer start bit. When the transfer terminates, this bit is automatically cleared to "0". 0 Serial I/O transfer stop 1 Serial I/O transfer start When starting a transfer, make sure first that there are no transfers in progress (i.e., that the SST bit is set to "0"). (3.2) SDR (serial data register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: 001DH 001DH (initial value) XXXXXXXXB (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) This is an 8-bit serial data register that holds the serial I/O transfer data. Do not write this register while serial I/O operations are in progress. 50 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions (4) Description of operation (4.1) Overview of operation This module consists of the serial mode register (SMR) and the serial data register (SDR). In the case of serial output, the contents of the SDR are output to the serial output pin (SO) as a series of bits in synchronization with the falling edge of the serial shift clock generated from either an internal clock or an external clock. In the case of serial input, the series of bits from the serial input pin (SI) are input to the SDR at the rising edge of the serial shift clock. SDR #7 #6 #5 #4 #3 #2 #1 #0 Shift clock SO ··· #0 #1 #2 ··· #5 #6 #7 Shift clock CK P S conversion SO SDR #7 #6 #5 #4 #3 #2 #1 #0 Shift clock SI Shift clock CK SI SI S P conversion In the case of serial output SO ··· #0 #1 #2 ··· #5 #6 #7 In the case of serial input (4.2) Operation modes The serial I/O operation modes include three internal shift clock modes and one external shift clock mode, depending on the shift clock type. The mode is set by the SMR. Mode switching and clock selection should be performed while serial I/O is in the halted state (the SST bit (bit 0) of the SMR is "0"). (4.2.1) Internal shift clock mode In this mode, serial operations are conducted according to an internal clock, and a shift clock with a duty ratio of 50% is output as the sync timing output. One data bit is transferred each clock pulse. (4.2.2) External shift clock mode One data bit is transferred each clock pulse in synchronization with the external shift clock input from the SCK pin. Even when serial I/O operations are halted, if the external shift clock is being input and serial data output is enabled, the level of the upper bit is output if MSB first is set, and the level of the lower bit is output if LSB first is set. Therefore, the external shift clock should be controlled externally so that it is maintained in the "1" state while transfer operations are halted. The transfer speed can range from DC to 1/(two instruction cycles). When one instruction cycle is 2.0 µs (when the source oscillation is 2 MHz), the transfer speed can range up to 4.0 µs (0.25 MHz). In either mode, do not write the SMR or the SDR while serial I/O operations are in progress. 51 2.2 Peripheral Functions (4.3) Interrupt function This module is able to generate interrupt requests for the CPU. An interrupt request is generated when interrupts are enabled by setting the SIOE bit of the SMR to "1" and then setting the SIOF bit (interrupt flag) of the SMR at the end of the 8-bit data transfer. However, if serial I/O transfer stop (SST is "0") and data transfer termination occur simultaneously, the SIOF bit is not set. SCK SST IRQ SO #0 #1 #2 #3 #4 #5 #6 #7 (4.4) Start/stop timing of the shift operation Transfer starts when the SST bit of the SMR is set to "1" and is halted if a "0" is written to the SST bit. In addition, the SST is cleared automatically and operation stops when the data transfer ends. (4.4.1) Internal shift clock mode (LSB first) (when transfer ends) SCK SST SIOF SO #0 #1 #2 #3 #4 #5 #6 #7 #1 #2 #3 #4 #5 #6 #7 (when transfer is interrupted) SCK SST SIOF SO #0 (4.4.2) External shift clock mode (LSB first) (when transfer ends) SCK SST SIOF SO #0 #1 #2 #3 #4 #5 #6 #7 #1 #2 #3 #4 #5 #6 #7 (when transfer is interrupted) SCK SST SIOF SO 52 #0 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions (4.5) Input/output shift timing Data is output from the serial output pin (SO) at the falling edge of the shift clock, and data is input to the serial input pin (SI) at the rising edge. (4.5.1) LSB first (when BDS is "0") SCK SI input SI #0 #1 #2 #3 #4 #5 #6 #7 #3 #4 #5 #6 #7 SO output SO #0 #1 #2 (4.5.2) MSB first (when BDS is "1") SCK SI input SI #7 #6 SO #7 #6 #5 #4 #3 #2 #1 #0 #4 #3 #2 #1 #0 SO output #5 DI7 to DI0 indicate input data, and DO7 to DO0 indicate output data. (5) Notes on use The output (free run) of the internal prescaler is used for the internal clock for 8-bit serial I/O. 53 2.2 Peripheral Functions 2.2.4 DTMF generator · Permits continuous sending of DTMF and single tone. · Permits output of all CCITT tones (0 to 9, ,#, A to D). (1) Register list 8 bits Address: 0020H 0020H DTMC R/W DTMF control register Address: 0021H 0021H DTMD R/W DTMF data register (2) Block diagram *TBTC Clock Divider COL-stage wave generator Frequency selector Voltage DTMF data adder ROW/COL decoder Frequency selector ROW-stage wave generator Count clock Dial data Control signal generator DTMF control register DTMC DTMF data register DTMD Internal bus *TBTC: Main clock source oscillation divided by two. 54 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions (3) Description of registers (3.1) DTMC (DTMF control register) MB89170 MB89170 series Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: 0020H 0020H - - - - - CDIS RDIS OUTE (initial value) XXXXX000B XXXXX000B (R/W) (R/W) (R/W) MB89170A MB89170A series Bit 7 Bit 6 Bit 5 Bit 4 Address: 0021H 0021H - - - - Bit 3 Bit 2 CSEL CDIS Bit 1 Bit 0 RDIS OUTE (initial value) XXXX0000B XXXX0000B (R/W) (R/W) (R/W) (R/W) An accurate DTMF signal cannot be output at frequencies other than these. These bits are valid only in the MB89170A MB89170A series. These bits do not exist in the 170 series. 0 Source oscillation frequency 3.58 MHz 1 Source oscillation frequency 7.16 MHz [Bit 2]CDIS: Column tone generation control bit This bit disables column tone generation. 0 Column tone generation enabled 1 Column tone generation disabled [Bit 1]RDIS: Row tone generation control bit This bit disables row tone generation. 0 Row tone generation enabled 1 Row tone generation disabled [Bit 0]OUTE: DTMF output control bit This bit controls the DTMF signal output. 0 DTMF signal output disabled 1 DTMF signal output enabled (3.2) DTMD (DTMF data register) Bit 7 Address: 0021H 0021H Bit 6 Bit 5 Bit 4 - - - - Bit 3 Bit 2 Bit 1 Bit 0 DDAT3 DDAT2 DDAT1 DDAT0 (initial value) XXXX0000B XXXX0000B (R/W) (R/W) (R/W) (R/W) [Bits 3 to 0]DDAT3 to DDAT0: Dialing data These bits set the dialing data. 55 2.2 Peripheral Functions (4) Description of operation The column and row frequencies are selected according to the value set in the dialing data register, and the row and column composite wave is output from the DTMF pin. The DTMF signal output timing is controlled by software through OUTE. (4.1) DTMF signal output The DTMF signal is output when OUTE in the DTMF control register is "1", and is not output when OUTE is "0". Tables 2.2.4a and 2.2.4b show the relationship between the value set in the dialing data register and the row and column values, and also the corresponding frequencies. (4.2) Single tone output When RDIS in the DTMF register is set to "1", a single tone consisting of the row tone only is output and the column tone output is disabled; if CDIS is set to "1", a single tone consisting of the column tone only is output and the row tone output is disabled. If both bits are set to "1", the DTMF signal is not output. Dial number 1 1 1 696.95 1 1209.31 2 2 1 696.95 2 1335.65 3 3 1 696.95 3 1476.71 4 4 2 770.13 1 1209.31 5 5 2 770.13 2 1335.65 6 6 2 770.13 3 1476.71 7 7 3 852.27 1 1209.31 8 8 3 852.27 2 1335.65 9 9 3 852.27 3 1476.71 0 A 4 940.99 2 1335.65 B 4 940.99 1 1209.31 # C 4 940.99 3 1476.71 A D 1 696.95 4 1633.01 B E 2 770.13 4 1633.01 C F 3 852.27 4 1633.01 D 56 Register value Table 2.2.4a Relationship between Dialing Data (DDAT3 to DDAT0) Settings and the Output Signal (Source oscillation is 3.579545 MHz) 0 4 940.99 4 1633.01 DTMF ROW COL Frequency (Hz) Chapter 2: HARDWARE CONFIGRATION Frequency (Hz) 2.2 Peripheral Functions Table 2.2.4b DTMF Output Frequencies Reference frequency (CCITT recommendation) DTMF output frequency (when oscillation is 3.579545 MHz) Frequency deviation ROW1 697 Hz 696.95 Hz ­ 0.01% ROW2 770 Hz 770.13 Hz + 0.02% ROW3 852 Hz 852.27 Hz + 0.03% ROW4 941 Hz 940.99 Hz ­ 0.01% COL1 1209 Hz 1209.31 Hz + 0.03% COL2 1336 Hz 1335.65 Hz ­ 0.03% COL3 1477 Hz 1476.71 Hz ­ 0.02% COL4 1633 Hz 1633.01 Hz + 0.01% 57 2.2 Peripheral Functions 2.2.5 External interrupt circuit 1 · Detects an edge on any of the three external interrupt sources INT0 to 2 and sets the appropriate flag. · Can also generate an interrupt in addition to setting the flag. · Can also be used for wakeup input. (1) Register list 8 bits Address: 0023H 0023H EIC1 R/W External interrupt control register 1 Address: 0024H 0024H EIC2 R/W External interrupt control register 2 (2) Block diagram 1 0 INT1 1 0 MUX MUX INT0 EIR1 SEL3 SEL2 EIE1 EIR0 SEL1 SEL0 EIE0 EIC1 IRQ0 IRQ1 IRQ2 EIR2 SEL5 SEL4 EIE2 EIC2 MUX INT2 0 1 58 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions (3) Description of registers (3.1) EIC1 (external interrupt control register 1) This register controls interrupts through the INT0 and INT1 pins. Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (initial value) EIR1 SEL3 SEL2 EIE1 EIR0 SEL1 SEL0 EIE0 00000000B 00000000B (R/W) Address: 0023H 0023H Bit 6 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [Bit 7]EIR1: External interrupt request flag This bit is set to "1" if the edge specified by SEL3 and SEL2 is input to the INT1 pin. If this bit is set while the EIE1 bit is "1", an interrupt request (IRQ1) is generated. The meanings of this bit when read are shown below. 0 The specified edge has not been input to the INT1 pin 1 The specified edge has been input to the INT1 pin (IRQ1 is output) Note that when read as part of a read-modify-write operation, this bit always returns a "1". Writing this bit has the following effects. 0 Clears this bit 1 No effect on this bit or other bits [Bit 6]SEL3: Edge polarity mode selection bit This bit controls the input edge polarity mode for the INT1 pin. 0 Rising edge or falling edge mode 1 Both-edge mode [Bit 5]SEL2: Edge polarity selection bit This bit controls the input edge polarity of the INT1 pin. 0 Rising edge 1 Falling edge Note: If both-edge mode is selected in bit 6, the value of this bit is ignored. [Bit 4]EIE1: Interrupt enable bit This bit enables external interrupt requests through the INT1 pin. 0 Interrupt requests disabled 1 Interrupt requests made by setting EIR1 are enabled 59 2.2 Peripheral Functions [Bit 3]EIR0: External interrupt request flag This bit is set to "1" if the edge specified by SEL0 and SEL1 is input to the INT0 pin. If this bit is set while the EIE0 bit is "1", an interrupt request (IRQ0) is generated. The meanings of this bit when read are shown below. 0 The specified edge has not been input to the INT0 pin 1 The specified edge has been input to the INT0 pin (IRQ0 is output) Note that when read as part of a read-modify-write operation, this bit always returns a "1". Writing this bit has the following effects. 0 Clears this bit 1 No effect on this bit or other bits [Bit 2]SEL1: Edge polarity mode selection bit This bit controls the input edge polarity mode for the INT0 pin. 0 Rising edge or falling edge mode 1 Both-edge mode [Bit 1]SEL0: Edge polarity selection bit This bit controls the input edge polarity of the INT0 pin. 0 Rising edge 1 Falling edge Note: If both-edge mode is selected in bit 2, the value of this bit is ignored. [Bit 0]EIE0: Interrupt enable bit This bit enables external interrupt requests through the INT0 pin. 0 1 60 Interrupt requests disabled Interrupt requests made by setting EIR0 are enabled Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions (3.2) EIC2 (external interrupt control register 2) This register controls interrupts through the INT2 pin. Bit 7 Address: 0024H 0024H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (initial value) - - - - EIR2 SEL5 SEL4 EIE2 XXXX0000B XXXX0000B (R/W) (R/W) (R/W) (R/W) [Bit 3]EIR2: External interrupt request flag This bit is set to "1" if the edge specified by SEL5 and SEL4 is input to the INT2 pin. If this bit is set while the EIE2 bit is "1", an interrupt request (IRQ2) is generated. The meanings of this bit when read are shown below. 0 The specified edge has not been input to the INT2 pin 1 The specified edge has been input to the INT2 pin (IRQ2 is output) Note that when read as part of a read-modify-write operation, this bit always returns a "1". Writing this bit has the following effects. 0 Clears this bit 1 No effect on this bit or other bits [Bit 2]SEL5: Edge polarity mode selection bit This bit controls the input edge polarity mode for the INT2 pin. 0 Rising edge or falling edge mode 1 Both-edge mode [Bit 1]SEL4: Edge polarity selection bit This bit controls the input edge polarity of the INT2 pin. 0 Rising edge 1 Falling edge Note: If both-edge mode is selected in bit 2, the value of this bit is ignored. [Bit 0]EIE2: Interrupt enable bit This bit enables external interrupt requests through the INT2 pin. 0 Interrupt requests disabled 1 Interrupt requests made by setting EIR2 are enabled 61 2.2 Peripheral Functions (4) Notes on use When enabling interrupts after the reset condition has been released, be sure to clear the external interrupt request flag bit at the same time. If the interrupt enable bit is changed from "disabled" to "enabled" (from "0" to "1") while the external interrupt request flag bit is "1", an interrupt is generated immediately. In addition, recovery from an interrupt is not possible if the interrupt enable bit is set to the "enabled" state while the external interrupt request flag bit is set to "1". Be certain to clear the external interrupt request flag bit. 62 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions 2.2.6 External interrupt circuit 2 (wakeup) · Detects a low signal on one of eight external interrupt sources and sets the appropriate flag. · Interrupt requests are generated by low input signals. · Can also be used for wakeup input. (1) Register list 8 bits Address: 0032H 0032H EIE2 R/W External interrupt 2 control register Address: 0033H 0033H EIF2 R/W External interrupt 2 flag register (2) Block diagram EIE2 7 P00/LI0 P00/LI0 EIF2 6 5 4 3 2 1 0 IF20 IRQA P01/LI1 P01/LI1 P02/LI2 P02/LI2 P03/LI3 P03/LI3 P04/LI4 P04/LI4 P05/LI5 P05/LI5 P06/LI6 P06/LI6 P07/LI7 P07/LI7 63 2.2 Peripheral Functions (3) Description of registers (3.1) EIE2 (external interrupt 2 control register) Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (initial value) IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 00000000B 00000000B (R/W) Address: 0032H 0032H Bit 6 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [Bit 7]IE27: LI7 interrupt enable bit [Bit 6]IE26: LI6 interrupt enable bit [Bit 5]IE25: LI5 interrupt enable bit [Bit 4]IE24: LI4 interrupt enable bit [Bit 3]IE23: LI3 interrupt enable bit [Bit 2]IE22: LI2 interrupt enable bit [Bit 1]IE21: LI1 interrupt enable bit [Bit 0]IE20: LI0 interrupt enable bit This register consists of the external interrupt operation enable bits for LI7 to LI0. 0 External interrupt 2 operation disabled 1 External interrupt 2 operation enabled (3.2) EIF2 (external interrupt 2 flag register) Bit 7 Address: 0033H 0033H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (initial value) - - - - - - - IF20 XXXXXXX0B (R/W) [Bit 0]IF20: Interrupt request flag bit This is the low level detection flag bit for LI7 to LI0. (when written) 0 Clears low level detection flag 1 No effect 0 No low level input 1 Low level input detected (when read) When one of the interrupt operation enable bits (IE27 to IE20) in the external interrupt 2 control register (EIE2) is set to "1", then if a low level signal is input to the corresponding port, the low level detection flag bit is set to "1" and an interrupt request is sent to the CPU. 64 Chapter 2: HARDWARE CONFIGRATION 2.2 Peripheral Functions (4) Notes on use Use the MB89PV170A MB89PV170A to evaluate the function of this resource. Unlike other resources, external interrupt circuit 2 continues to issue an interrupt until the interrupt source is cleared, even if the interrupt is disabled. Always be certai