TC835 ICL7135 TC7135 MAX7135 SI7135 TC7660 TC835CBU TC835CKW TC835CPI LH0084 - Datasheet Archive

 

Personal Computer Data Acquisition A/D Converter FEATURES GENERAL DESCRIPTION s The TC835 is a low-power, 4-1/2 digit (0.005%

 

TC835 TC835 Personal Computer Data Acquisition A/D Converter FEATURES GENERAL DESCRIPTION s The TC835 TC835 is a low-power, 4-1/2 digit (0.005% resolution), BCD analog-to-digital converter (ADC) that has been characterized for 200 kHz clock rate operation. The five conversions per second rate is nearly twice as fast as the ICL7135 ICL7135 or TC7135 TC7135. The TC835 TC835 (like the TC7135 TC7135) does not use the external diode-resistor roll-over error compensation circuits required by the ICL7135 ICL7135. The multiplexed BCD data output is perfect for interfacing to personal computers. The low-cost, greater than 14-bit high-resolution, and 100 µV sensitivity makes the TC835 TC835 exceptionally cost-effective. Microprocessor-based data acquisition systems are supported by the BUSY and STROBE outputs, along with the RUN/HOLD input of the TC835 TC835. The overrange, underrange, busy, and run/hold control functions and multiplexed BCD data outputs make the TC835 TC835 the ideal converter for µP-based scales and measurement systems and intelligent panel meters.* The TC835 TC835 interfaces with full-function LCD and LED display decoder/drivers. The UNDERRANGE and OVERRANGE outputs may be used to implement an autoranging scheme or special display functions. s s s s s s s Upgrade of Pin-Compatible TC7135 TC7135, ICL7135 ICL7135, MAX7135 MAX7135 and SI7135 SI7135 Guaranteed 200 kHz Operation Single 5V Operation With TC7660 TC7660 Multiplexed BCD Data Output UART and Microprocessor Interface Control Outputs for Auto-Ranging Input Sensitivity . 100 µV No Sample and Hold Required APPLICATIONS s s s Personal Computer Data Acquisition Scales, Panel Meters, Process Controls HP-IL Bus Instrumentation ORDERING INFORMATION Part No. Package Temperature Range TC835CBU TC835CBU TC835CKW TC835CKW TC835CPI TC835CPI 64-Pin PQFP 44-Pin PQFP 28-Pin Plastic DIP 0°C to +70°C 0°C to +70°C 0°C to +70°C NOTE: Tape and reel available for 44-pin PQFP packages. *See Application Notes 16 and 17 for microprocessor interface techniques. TYPICAL APPLICATION ADDRESS BUS CONTROL + 5V DATA BUS V+ REF CAP GAIN: 10, 20, 50, 100 +15V ­15V BUF 157 6522 -VIA- AZ POL OR INT UR D5 TC835 TC835 B8 B4 + INPUT B2 1B 2B 3B SEL 1A 2A 3A PA3 PA4 PA5 PA6 PA7 CA1 CA2 PB5 PB4 PB0 PB1 PB2 PB3 B1 D1 VR D2 ­ INPUT D3 D4 ANALOG STB COMMON R/H DGND fIN GAIN SELECTION fIN 11 8 10 LH0084 LH0084 14 ­ 1Y 2Y 3Y + PA0 PA1 PA2 16 REF VOLTAGE 15 DG529 DG529 3 9 DA DB CHANNEL 1 CHANNEL 2 CHANNEL 3 WR A1 A0 EN CHANNEL 4 DIFFERENTIAL MULTIPLEXER ­ 5V CHANNEL SELECTION © 2001 Microchip Technology Inc. DS21478A DS21478A TC835-8 TC835-8 11/5/96 Personal Computer Data Acquisition A/D Converter TC835 TC835 Package Power Dissipation (TA 70°C) 28-Pin Plastic DIP . 1.14W 44-Pin PQFP . 1.00W 64-Pin PQFP . 1.14W ABSOLUTE MAXIMUM RATINGS* (Note 1) Positive Supply Voltage . +6V Negative Supply Voltage . - 9V Analog Input Voltage (Pin 9 or 10) . V + to V ­ (Note 2) Reference Input Voltage (Pin 2) . V + to V ­ Clock Input Voltage . 0V to V + Operating Temperature Range . 0°C to +70°C Storage Temperature Range . ­ 65°C to +150°C Lead Temperature (Soldering, 10 sec) . +300°C *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS: TA = +25°C, fCLOCK = 200 kHz, V + = +5V, V ­ = ­ 5V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit ­0.0000 ±0.0000 +0.0000 - 0.5 2 Display Reading µV/°C - - 5 ppm/°C - - +0.9996 0.5 0.01 +0.9998 1 - +1.0000 - 0.5 1 Count LSB Display Reading Count - - 1 15 10 - pA µVP-P VIN = 0V VIN = +5V IOL = 1.6 mA - - - 10 0.08 0.2 100 10 0.4 µA µA V IOH = 1 mA IOH = 10 µA 2.4 4.9 4.4 4.99 5 5 V V 0 200 1200 kHz 4 ­3 - - - 5 ­5 1 0.7 8.5 6 ­8 3 3 30 V V mA mA mW Analog Display Reading With Zero Volt Input Zero Reading Temperature Coefficient Full-Scale Temperature Coefficient Nonlinearity Error Differential Linearity Error Display Reading in Ratiometric Operation ± Full-Scale Symmetry Error (Roll-Over Error) Input Leakage Current Noise TCZ TCFS NL DNL ±FSE IIN eN Notes 3 and 4 VIN = 0V Note 5 VIN = 2V Notes 5 and 6 Note 7 Note 7 VIN = VREF Note 3 ­VIN = +VIN Note 8 Note 4 Peak-to-Peak Value Not Exceeded 95% of Time Digital IIL IIH VOL VOH Input Low Current Input High Current Output Low Voltage Output High Voltage B1, B2, B4, B8, D1­D5 Busy, Polarity, Overrange, Underrange, Strobe Clock Frequency fCLK Note 10 Power Supply V+ V­ I+ I­ PD NOTES: Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation fCLK = 0 Hz fCLK = 0 Hz fCLK = 0 Hz 1. Functional operation is not implied. 7. ­ 2V VIN +2V. Error of reading from best fit straight line. 2. Limit input current to under 100 µA if input voltages exceed supply 8. |VIN| = 1.9959. d supply voltage. 9. Test circuit shown in Figure 1. 3. Full-scale voltage = 2V. 10. Specification related to clock frequency range over which the 4. VIN = 0V. TC835 TC835 correctly performs its various functions. Increased errors 5. 0°C TA +70°C. result at higher operating frequencies. 6. External reference temperature coefficient less than 0.01 ppm/°C. TC835-8 TC835-8 11/5/96 2 © 2001 Microchip Technology Inc. DS21478A DS21478A Personal Computer Data Acquisition A/D Converter TC835 TC835 BUFF OUT ­ C REF + CREF ­ INPUT 5 7 STROBE NC NC 36 35 34 33 NC 32 NC 31 RUN/HOLD 30 DGND REF CAP­ 5 29 POLARITY REF CAP+ 6 28 CLK IN TC835CKW TC835CKW ­INPUT 19 D2 7 27 BUSY +INPUT 20 D1 (LSD) 9 37 BUFF OUT 4 21 BUSY +INPUT 10 V + 11 38 AZ IN 3 22 CLOCK IN 8 41 40 39 INT OUT 2 23 POLARITY TC835CPI TC835CPI 42 NC 1 24 DIGTAL GND 6 OR 25 RUN/HOLD AZ IN UR 26 STROBE 4 V­ 3 OVERRANGE REF IN 27 ANALOG COM 2 44 43 28 UNDERRANGE REF IN ANALOG COM INT OUT NC 1 NC V­ NC PIN CONFIGURATIONS 8 26 D1 (LSD) 18 19 20 21 22 (MSB) B8 D4 D3 NC D2 D1 BUSY SUB CLK IN POL DGND RUN/HOLD STROBE NC NC NC NC NC 17 14 NC 15 16 12 13 B2 15 B4 B2 14 B4 23 NC (LSB) B1 (LSB) B1 13 NC 24 NC NC 11 NC 17 D4 16 B8 (MSD) NC (MSD) D5 12 (MSD) D5 25 D2 NC 10 NC 18 D3 V+ 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 1 48 NC NC 2 47 NC NC 3 46 NC NC 4 45 D3 NC 5 44 D4 NC 6 43 B3 OVERRANGE 7 42 B4 UNDERRANGE 8 41 B2 SUB 9 40 SUB TC835CBU TC835CBU V­ 10 39 B1 REF IN 11 38 D5 ANALOG COM 12 37 NC NC 13 36 NC NC 14 35 NC NC 15 34 NC 33 NC NC 16 V+ NC +INPUT NC NC ­INPUT BUF CAP+ SUB NC BUF CAP­ BUFFOUT NC AZ IN NC INT OUT NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NOTES: 1. NC = No internal connection. 2. Pins 9, 25, 40 and 56 are connected to the die substrate. + The potential at these pins is approximately V . No external connections should be made. © 2001 Microchip Technology Inc. DS21478A DS21478A. 3 TC835-8 TC835-8 11/5/96 Personal Computer Data Acquisition A/D Converter TC835 TC835 ­5V UNDERRANGE OVERRANGE 3 ANALOG STROBE COMMON ANALOG GND 4 RUN/HOLD INT OUT 0.47 1 µF 5 µF DIGTAL GND AZ IN 6 POLARITY BUFF OUT 100 k 7 ­ CLOCK IN CREF 100 SIGNAL 1 µF 8 + BUSY k INPUT CREF 9 ­INPUT (LSD) D1 0.1 µF 10 D2 +INPUT TC835 TC835 11 + D3 +5V V 12 D5 (MSD) D4 13 14 B1 (LSB) (MSB) B8 B2 B4 ANALOG INPUT BUFFER SW I + IN 27 ­ SW RI 26 CSZ SWIZ 24 REF IN 23 21 CLOCK INPUT 120 kHz SWZ CREF SWR CINT ­ SW + RI 25 22 RINT + COMPARATOR SWZ SW + RI INTEGRATOR SWZ ­ SW RI TO DIGITAL SECTION ANALOG COM 20 19 SW1 SW I 18 SWITCH OPEN ­ IN SWITCH CLOSED 17 16 15 Figure 3B. System Zero Phase Figure 1. Test Circuit V+ ANALOG INPUT BUFFER SW I + IN ­ SW RI CSZ COMPARATOR ­ + + BUFFER LOGIC INPUT SWZ CREF SWR CINT ­ SW + RI SWIZ REF IN RINT + SWZ SW + RI INTEGRATOR SWZ ­ SW RI ­ REF IN 28 ­ 100 k V­ ­ 2 + 1 VREF IN + SET VREF = 1V TO DIGITAL SECTION ANALOG COM SW1 SW I SWITCH OPEN ­ IN SWITCH CLOSED Figure 2. Digital Logic Input + ­ SW RI ­ SW + RI CSZ SWIZ CREF COMPARATOR REF IN CINT CSZ CREF SWR RINT ­ SWIZ SWZ ­ SWR + SWZ COMPARATOR + SW + RI + IN CINT ­ ­ SW RI RINT + + IN ANALOG INPUT BUFFER SW I + + SW + RI ­ SW RI SWZ ­ SWZ INTEGRATOR TO DIGITAL SECTION SWZ ­ SW RI INTEGRATOR TO DIGITAL SECTION ANALOG COM ANALOG COM SW I SW + RI SWZ ­ ANALOG INPUT BUFFER SW I REF IN Figure 3C. Input Signal Integration Phase SW I SW1 ­ IN SW1 SWITCH OPEN SWITCH CLOSED ­ IN Figure 3A. Analog Circuit Function Diagram TC835-8 TC835-8 11/5/96 Figure 3D. Reference Voltage Integration Cycle 4 © 2001 Microchip Technology Inc. DS21478A DS21478A Personal Computer Data Acquisition A/D Converter TC835 TC835 + IN RINT + ­ SW + RI CSZ SWIZ SWZ CREF COMPARATOR ­ + + SW + RI SWZ ­ SW RI INTEGRATOR ­ SWZ TO DIGITAL SECTION TC835 TC835 Operational Theory ANALOG COM SW1 SW I The TC835 TC835 incorporates a system zero phase and integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system errors, fewer calibration steps, and a shorter overrange recovery time result. The TC835 TC835 measurement cycle contains four phases: SWITCH OPEN ­ IN SWITCH CLOSED Figure 3E. Integrator Output Zero Phase GENERAL THEORY OF OPERATION (1) (2) (3) (4) (All Pin Designations Refer to 28-Pin DIP) Dual-Slope Conversion Principles The TC835 TC835 is a dual-slope, integrating analog-to-digital converter. An understanding of the dual-slope conversion technique will aid in following the detailed TC835 TC835 operational theory. The conventional dual-slope converter measurement cycle has two distinct phases: System zero Analog input signal integration Reference voltage integration Integrator output zero Internal analog gate status for each phase is shown in Table 1. ANALOG INPUT SIGNAL (1) Input signal integration (2) Reference voltage integration (deintegration) INTEGRATOR COMPARATOR ­ + The input signal being converted is integrated for a fixed time period. Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" and "rampdown." A simple mathematical equation relates the input signal, reference voltage, and integration time: tSI 1 V t VIN(t) dt = R RI , RC RC 0 + SWR CINT ­ ­ SW RI REF IN The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Noise spikes are integrated, or averaged, to zero during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. (See Figure 4.) ANALOG INPUT BUFFER SW I SWITCH DRIVER INTEGRATOR OUTPUT REF VOLTAGE FIXED SIGNAL INTEGRATE TIME where: VR = Reference voltage tSI = Signal integration time (fixed) tRI = Reference voltage integration time (variable). PHASE CONTROL CONTROL LOGIC POLARITY CONTROL DISPLAY CLOCK COUNTER VIN VFULL SCALE VIN 1/2 VFULL SCALE VARIABLE REFERENCE INTEGRATE TIME Figure 4. Basic Dual-Slope Converter For a constant VIN: VIN = VR [ ] tRI t SI © 2001 Microchip Technology Inc. . DS21478A DS21478A. 5 TC835-8 TC835-8 11/5/96 Personal Computer Data Acquisition A/D Converter TC835 TC835 Table 1. Internal Analog Gate Status Conversion Cycle Phase SWI + SWRI Internal Analog Gate Status ­ SWRI Input Signal Integration SWR SW1 Closed System Zero SWZ Closed SWIZ Reference Schematic Closed 3B Closed Reference Voltage Integration Integrator Output Zero 3C Closed* Closed Closed 3D Closed 3E ­ *NOTE: Assumes a positive polarity input signal. SWRI would be closed for a negative input signal. Analog Section Functional Description System Zero (Figure 3B) During this phase, errors due to buffer, integrator, and comparator offset voltages are compensated for by charging CAZ (auto-zero capacitor) with a compensating error voltage. With a zero input voltage the integrator output will remain at zero. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to ANALOG COMMON. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator, and comparator offset voltages. (In Reference to the 28-Pin Plastic Package) Differential Inputs (+INPUT, Pin 10 and ­INPUT, Pin 9) The TC835 TC835 operates with differential voltages within the input amplifier common-mode range. The input amplifier common-mode range extends from 0.5V below the positive supply to 1V above the negative supply. Within this common-mode voltage range, an 86 dB common-mode rejection ratio is typical. The integrator output also follows the common-mode voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a large positive common-mode voltage with a near full-scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common-mode voltage. For these critical applications the integrator swing can be reduced to less than the recommended 4V full-scale swing, with some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity. Analog Input Signal Integration (Figure 3C) The TC835 TC835 integrates the differential voltage between the +INPUT and ­INPUT pins. The differential voltage must be within the device common-mode range; - 1V from either supply rail, typically. The input signal polarity is determined at the end of this phase. Reference Voltage Integration (Figure 3D) The previously-charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. The digital reading displayed is: Reading = 10,000 [ ANALOG COMMON Input (Pin 3) ANALOG COMMON is used as the ­INPUT return during auto-zero and deintegrate. If ­INPUT is different from ANALOG COMMON, a common-mode voltage exists in the system. This signal is rejected by the excellent CMRR of the converter. In most applications, ­INPUT will be set at a fixed, known voltage (power supply common, for instance). In this application, ANALOG COMMON should be tied to the same point, thus removing the common-mode voltage from the converter. The reference voltage is referenced to ANALOG COMMON. ] Differential Input . VREF Integrator Output Zero (Figure 3E) This phase guarantees the integrator output is at 0V when the system zero phase is entered and that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles. TC835-8 TC835-8 11/5/96 REFERENCE Voltage Input (REF IN, Pin 2) The REF IN input must be a positive voltage with respect to ANALOG COMMON. Two reference voltage circuits are shown in Figure 5. 6 © 2001 Microchip Technology Inc. DS21478A DS21478A Personal Computer Data Acquisition A/D Converter TC835 TC835 V+ D5 POLARITY V+ D4 MSB DIGIT D3 D2 DRIVE SIGNAL 6.8V ZENER 13 B1 14 B2 DATA OUTPUT MULTIPLEXER REF IN D1 LSB 15 B4 16 B8 FROM ANALOG SECTION TC835 TC835 POLARITY FF LATCH LATCH LATCH LATCH LATCH IZ ANALOG COMMON COUNTERS ZERO CROSS DETECT CONTROL LOGIC V­ 24 DIGITAL GND V+ TC835 TC835 REF IN TC04 20 k RUN/ HOLD OVER­ RANGE 28 UNDER­ RANGE 26 21 STROBE BUSY INTEGRATOR OUTPUT SIGNAL INTE SYSTEM 10,000 ZERO 10,001 COUNTS COUNTS (FIXED) REFERENCE INTEGRATE 20,001 COUNTS (MAX) Figure 5. Using an External Reference Digital Section Functional Description ; ; ; FULL MEASUREMENT CYCLE 40,002 COUNTS ANALOG GROUND BUSY OVERRANGE WHEN APPLICABLE UNDERRANGE WHEN APPLICABLE EXPANDED SCALE BELOW The major digital subsystems within the TC835 TC835 are illustrated in Figure 6, with timing relationships shown in Figure 7. The multiplexed BCD output data can be displayed on LCD or LED display with the TC7211A TC7211A (LCD) 4-digit display driver. The digital section is best described through a discussion of the control signals and data outputs. DIGIT SCAN D5 D4 D3 D2 D1 100 COUNTS * FIRST D5 OF SYSTEM ZERO AND REFERENCE INTEGRATE ONE COUNT LONGER. STROBE RUN/HOLD Input (Pin 25) When left open, this pin assumes a logic "1" level. With a R/H = 1, the TC835 TC835 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. When R/H changes to a logic "0," the measurement cycle in progress will be completed, and data held and displayed as long as the logic "0" condition exists. A positive pulse (> 300nsec) at R/H initiates a new measurement cycle. The measurement cycle in progress when R/H initially assumed the logic "0" state must be completed before the positive pulse can be recognized as a single conversion run command. DS21478A DS21478A. 27 CLOCK IN 1.25V REF ANALOG COMMON © 2001 Microchip Technology Inc. 25 Figure 6. Digital Section Functional Diagram 6.8 k V+ 22 AUTO ZERO DIGIT SCAN FOR OVERRANGE * D5 REFERENCE INTEGRATE SIGNAL INTEGRATE * D4 D3 D2 D1 Figure 7. Timing Diagrams for Outputs 7 TC835-8 TC835-8 11/5/96 Personal Computer Data Acquisition A/D Converter TC835 TC835 The new measurement cycle begins with a 10,001count auto-zero phase. At the end of this phase the busy signal goes high. TC835 TC835 OUTPUTS BUSY STROBE Output (Pin 26) During the measurement cycle, the STROBE control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D1, D2, D3, D5, Figure 8). D5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one-half clock pulse. After the D5 digit strobe, D4 goes high for 200 clock pulses. The STROBE goes low 100 clock pulses after D4 goes high. This continues through the D1 digit drive pulse. The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. The active low STROBE pulses aid BCD data transfer to UARTs, processors and external latches. (See Application Note 16.) END OF CONVERSION * B1­B8 D5 (MSD) DATA D4 DATA D3 DATA D2 DATA D1 (LSD) DATA D5 DATA STROBE NOTE ABSENCE OF STROBE 200 COUNTS D5 D4 D3 D2 201 COUNTS 200 COUNTS 200 COUNTS 200 COUNTS 200 COUNTS 200 COUNTS D1 *DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE PULSE IS DEPENDENT ON ANALOG INPUT. BUSY Output (Pin 21) At the beginning of the signal-integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to the logic "0" state after the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY, and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto-zero cycle. Figure 8. Strobe Signal Pulses Low Five Times per Conversion The polarity bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications. DIGIT Drive Outputs (Pins 12, 17, 18, 19 and 20) Digit drive signals are positive-going signals. The scan sequence is D5 to D1. All positive pulses are 200 clock pulses wide, except D5, which is 201 clock pulses wide. All five digits are scanned continuously, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference-integrate phase. The scanning sequence is then repeated. This provides a blinking visual display indication. OVERRANGE Output (Pin 27) If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output is set to a logic "1." The overrange output register is set when BUSY goes low, and is reset at the beginning of the next reference-integration phase. BCD Data Outputs (Pins 13, 14, 15 and 16) The binary coded decimal (BCD) bits B8, B4, B2, B1, are positive-true logic signals. The data bits become active simultaneously with the digit drive signals. In an overrange condition, all data bits are at a logic "0" state. UNDERRANGE Output (Pin 28) If the output count is 9% of full scale or less (1800 counts), the underrange register bit is set at the end of BUSY. The bit is set low at the next signal-integration phase. POLARITY Output (Pin 23) A positive input is registered by a logic "1" polarity signal. The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next conversion. TC835-8 TC835-8 11/5/96 8 © 2001 Microchip Technology Inc. DS21478A DS21478A Personal Computer Data Acquisition A/D Converter TC835 TC835 APPLICATIONS INFORMATION Component Value Selection The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made. Suitable references are: The integrating resistor is determined by the full-scale input voltage and the output current of the buffer used to charge the integrator capacitor. Both the buffer amplifier and the integrator have a class A output stage, with 100 µA of quiescent current. A 20 µA drive current gives negligible linearity errors. Values of 5 µA to 40 µA give good results. The exact value of an integrating resistor for a 20 µA current is easily calculated. RINT = Part Type TC04A TC04A TC9491 TC9491 Line Frequency Rejection A signal integration period at a multiple of the 60 Hz line frequency will maximize 60 Hz "line noise" rejection. A 200 kHz clock frequency will reject 60 Hz and 400 Hz noise. This corresponds to five readings per second. Integrating Capacitor The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance buildup will not saturate the integrator swing (approximately 0.3V from either supply). For ±5V supplies and ANALOG COMMON tied to supply ground, a ±3.5V to ±4V full-scale integrator swing is adequate. A 0.10 µF to 0.47 µF is recommended. In general, the value of CINT is given by: Conversion Rate vs Clock Frequency Oscillator Frequency (kHz) (10,000) (clock period) (20 µA) Integrator output voltage swing A very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half-scale 0.9999, any deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. 50.000 53.333 66.667 80.000 83.333 100.000 125.000 133.333 166.667 200.000 250.000 Line Frequency Rejection 60 Hz 50 Hz 400 Hz · - · - - · - - - · - · - - - · · · - - - · · · · · · · · · · · · The conversion rate is easily calculated: Conversion Rate Clock Frequency (Hz) (Readings 1/sec) = 4000 Reference Voltage The analog input required to generate a full-scale output is VIN = 2 VREF. DS21478A DS21478A. 2.5 3 5 7.5 10 20 30 Oscillator Frequency (kHz) Auto-Zero and Reference Capacitors The size of the auto-zero capacitor has some influence on the noise of the system. A large capacitor reduces the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. The dielectric absorption of the reference capacitor and auto-zero capacitor are only important at power-on, or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. © 2001 Microchip Technology Inc. Conversion Rate (Conv/Sec) 100 120 200 300 400 800 1200 [10,000 × clock period] × IINT Integrator output voltage swing = TelCom Semiconductor TelCom Semiconductor Conversion Timing full-scale voltage 20 µA CINT = Manufacturer 9 TC835-8 TC835-8 11/5/96 Personal Computer Data Acquisition A/D Converter TC835 TC835 Power Supplies and Grounds For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1 MHz may be used. For a fixed clock frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted out digitally. The clock frequency may be extended above 200 kHz without this error, however, by using a low-value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. The minimum clock frequency is established by leakage on the auto-zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in the applications section. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. Power Supplies The TC835 TC835 is designed to work from ±5V supplies. For single +5V operation, a TC7660 TC7660 can provide a ­ 5V supply . Grounding Systems should use separate digital and analog ground systems to avoid loss of accuracy. Displays and Driver Circuits TelCom Semiconductor manufactures two display decoder/driver circuits to interface the TC835 TC835 to an LCD or LED display. Each drive has 28 outputs for driving four 7-segment digit displays. Device Package Description TC7211AIPL TC7211AIPL 40-Pin Epoxy 4-Digit LCD Driver/Decoder Several sources exist for LCD and LED display: Manufacturer Address Hewlett Packard Components Litronix, Inc. 640 Page Mill Rd. Palo Alto, CA 94304 19000 Homestead Rd. Cupertino, CA 94010 720 Palomar Ave. Sunnyvale, CA 94086 3415 Kanhi Kawa St. Torrance, CA 90505 AND Epson America, Inc. Display Type LED LED LCD and LED LCD Zero-Crossing Flip-Flop The flip-flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half-clock pulse have died down. False zero-crossings caused by clock pulses are not recognized. Of course, the flip-flop delays the true zero-crossing by up to one count in every instance, and if a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (deintegrate) phase. This one-count delay compensates for the delay of the zero-crossing flipflop, and allows the correct number to be latched into the display. Similarly, a one-count delay at the beginning of auto-zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate, so that true ratiometric readings result. High-Speed Operation The maximum conversion rate of most dual-slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3 µsec delay, and at a clock frequency of 200 kHz (5 µsec period), half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 at 250 µV, etc. This transition at midpoint is considered desirable by most users; however, if the clock frequency is increased appreciably above 200 kHz, the instrument will flash "1" on noise peaks even when the input is shorted. TC835-8 TC835-8 11/5/96 10 © 2001 Microchip Technology Inc. DS21478A DS21478A Personal Computer Data Acquisition A/D Converter TC835 TC835 TYPICAL APPLICATIONS DIAGRAMS +5V 4-1/2 Digit ADC With Multiplexed Common Anode LED Display 20 4 1 µF 0.33µF 5 22 100 k + ANALOG INPUT ­ 19 D2 18 D3 17 D4 10 1 µF 9 12 D5 INT OUT AZ IN POL 6 BUFF OUT 100 k 200 kHz D1 fIN 23 4.7 k b ­ CREF 7 TC835 TC835 c 7 1 µF + CREF 8 16 15 B4 14 B2 13 B1 3 ANALOG COMMON REF V ­ IN 7 9­15 5 6 D 2 C 1 B 7 A B8 7 X7 BLANK MSD ON ZERO +INPUT ­INPUT 7 RBI 16 7447 +5V V+ 1 2 6.8 k 11 ­5V 100 k TC04 Comparator Clock Circuits RC Oscillator Circuit R2 +5V R1 C 16 k 1 k fO 56 k 3 R1 R2 1 , RP = R1 + R2 2 C(0.41 RP + 0.7 R1) 30 k 16 k 390 pF +5V R2 100 k 2 R2 100 k b. f = 120 kHz, C = 420 pF, R2 = 50 k R1 = 8.93 k C2 10 pF 7 LM311 LM311 3 ­ R1 = R2 10.9 k R4 2 k 6 + a. f = 120 kHz, C = 420 pF 4 1 VOUT R3 50 k C1 0.1 µF c. f = 120 kHz, C = 220 pF, R2 = 5 k R1 = 27.3 k DS21478A DS21478A. 1 4 a. If R1 = R2 = R1, f 0.55/RC 55/RC b. If R2 >> R1, f 0.45/R1C 45/R1C c. If R2