ADM706P/R ADM708R ADM706S ADM708S ADM706T ADM708T ADM706P ADM706R/S/T - Datasheet Archive

 

FEATURES Precision Supply-Voltage Monitor +2.63 V (ADM706P/R, ADM708R) +2.93 V (ADM706S, ADM708S) +3.08 V (ADM706T, ADM708T) 100

 

a FEATURES Precision Supply-Voltage Monitor +2.63 V (ADM706P/R ADM706P/R, ADM708R ADM708R) +2.93 V (ADM706S ADM706S, ADM708S ADM708S) +3.08 V (ADM706T ADM706T, ADM708T ADM708T) 100 µA Quiescent Current 200 ms Reset Pulse Width Debounced Manual Reset Input (MR) Independent Watchdog Timer-1.6 sec Timeout (ADM706x) Reset Output Active High (ADM706P ADM706P) Active Low (ADM706R/S/T ADM706R/S/T) Both Active High and Active Low (ADM708R/S/T ADM708R/S/T) Voltage Monitor for Power-Fail or Low Battery Warning Guaranteed RESET Valid with VCC = 1 V Superior Upgrade for MAX706P/R/S/T MAX706P/R/S/T, MAX708R/S/T MAX708R/S/T APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Critical µP Monitoring Automotive Systems Battery Operated Systems Portable Instruments +3 V, Voltage Monitoring µP Supervisory Circuits ADM706P/R/S/T ADM706P/R/S/T, ADM708R/S/T ADM708R/S/T FUNCTIONAL BLOCK DIAGRAMS WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR 70µA MR RESET GENERATOR 1. Power-supply monitoring circuitry which generates a Reset output during power-up, power-down and brownout conditions. The reset output remains operational with VCC as low as 1 V. RESET, (P = RESET) VCC VREF* ADM706 ADM706 POWER FAIL INPUT (PFI) POWER FAIL OUTPUT (PFO) 1.25V *VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T) VCC RESET 70µA MR RESET GENERATOR RESET VCC VREF* The ADM706P/R/S/T ADM706P/R/S/T provide the following functions WATCHDOG OUTPUT(WDO) RESET & WATCHDOG TIMEBASE VCC GENERAL DESCRIPTION The ADM706P/R/S/T ADM706P/R/S/T and the ADM708R/S/T ADM708R/S/T microprocessor supervisory circuits are suitable for monitoring either 3 V or 3.3 V power supplies. WATCHDOG TIMER ADM708 ADM708 POWER FAIL INPUT (PFI) POWER FAIL OUTPUT (PFO) 1.25V *VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T) The ADM708R/S/T ADM708R/S/T provide the same functionality as the ADM706R/S/T ADM706R/S/T and only differ in that: 2. Independent watchdog monitoring circuitry which is activated if the watchdog input has not been toggled within 1.6 seconds. 1. A watchdog timer function is not available. 3. A 1.25 V threshold detector for power fail warning, low battery detection, or to monitor an additional power supply . All parts are available in 8-pin DIP and narrow SOIC packages. 2. An active high reset output (RESET) in addition to the active low (RESET) output is available. 4. An active low debounced manual reset input (MR). The ADM706R ADM706R, ADM706S ADM706S, ADM706T ADM706T are identical except for the reset threshold monitor levels which are 2.63 V, 2.93 V, and 3.08 V respectively. The ADM706P ADM706P is identical to the ADM706R ADM706R in that the reset threshold is 2.63 V. It differs only in that it has an active high reset output. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ADM706/708 ADM706/708 data sheet 1 © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 10/17/95, 9:05 AM ADM706P/R/S/T ADM706P/R/S/T, ADM708R/S/T ADM708R/S/T­SPECIFICATIONS (V CC = 2.70 V to 5.5 V (ADM70 ADM70_P/R), VCC = 3.00 V to 5.5 V (ADM70 ADM70_S), VCC = 3.15 V to 5.5 V (ADM70 ADM70_T), TA = TMIN to TMAX unless otherwise noted.) Parameter Min VCC Operating Voltage Range Supply Current 1.0 Reset Threshold (VRST) 2.55 2.85 3.00 160 160 RESET Output Voltage VOH VOL VOH VOL VOL Units Test Conditions/Comments 5.5 200 350 V µA µA VCC < 3.6 V VCC < 5.5 V 2.63 2.93 3.08 20 2.70 3.00 3.15 V V V mV ADM70 ADM70_P/R ADM70 ADM70_S ADM70 ADM70_T 200 200 200 280 280 ms ms ms ADM70 ADM70_P/R, VCC = 3 V ADM70 ADM70_S/T, VCC = 3.3 V VCC = 5.0 V V V V V V ADM70 ADM70_R/S/T VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA VCC = 1 V, ISINK = 100 µA V V V V ADM706P ADM706P VRST (max) < VCC < 3.6 V, ISOURCE = 215 µA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA 0.4 Reset Pulse Width Max 100 150 Reset Threshold Hysteresis Typ V V V V ADM708 ADM708_ VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA VRST (max) < VCC < 3.6 V, ISINK = 500 µA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA 2.25 sec 0.8 × VCC 0.3 VCC­1.5 V 0.4 0.3 RESET Output Voltage VOH VOL VOH VOL VCC­0.6 V 0.3 VCC­1.5 V 0.4 RESET Output Voltage VOH VOL VOH VOL 0.8 × VCC 0.3 VCC­1.5 V 1.00 1.60 V V V V µA ADM70 ADM70_P/R; VCC = 3 V. ADM70 ADM70_S/T, VCC = 3.3V VIL = 0.4 V, VIH = (VCC) × (0.8) VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V ADM706 ADM706_ VRST (max) < VCC < 3.6 V VRST (max) < VCC < 3.6 V VCC = 5.0 V VCC = 5.0 V WDI = 0 V or VCC 0.4 Watchdog Timeout Period V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA VRST (max) < VCC < 3.6 V, ISINK = 500 µA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA 250 600 µA µA MR = 0 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V ns ns VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V V V V V VRST (max) < VCC < 3.6 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V WDI Pulse Width 100 50 WDI Input Threshold VIL VIH VIL VIH WDI Input Current ns ns 0.6 0.7 × VCC 0.8 3.5 ­1.0 WDO Output Voltage VOH VOL VOH VOL 0.02 1.0 0.8 × VCC 0.3 VCC­1.5V MR Pull Up Current 25 100 70 250 MR PulseWidth 500 150 MR Input Threshold VIL VIH VIL VIH 0.7 × VCC 0.6 0.8 2.0 ­2­ ADM706/708 ADM706/708 data sheet 2 REV. 0 10/17/95, 9:05 AM ADM706P/R/S/T ADM706P/R/S/T, ADM708R/S/T ADM708R/S/T Parameter Min Typ Units Test Conditions/Comments 750 250 MR to Reset Output Delay Max ns ns VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V ADM70 ADM70_P/R; VCC = 3 V. ADM70 ADM70_S/T, VCC = 3.3 V, PFI falling PFI Input Threshold 1.2 1.25 1.3 V PFI Input Current ­25 0.01 25 nA PFO Output Voltage VOH VOL VOH VOL 0.8 × VCC V V V V 0.3 VCC­1.5 V 0.4 ORDERING GUIDE VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) Model Temperature Range Package Options ADM706PAN ADM706PAN ADM706PAR ADM706PAR ADM706RAN ADM706RAN ADM706RAR ADM706RAR ADM706SAN ADM706SAN ADM706SAR ADM706SAR ADM706TAN ADM706TAN ADM706TAR ADM706TAR ADM708RAN ADM708RAN ADM706RAR ADM706RAR ADM708SAN ADM708SAN ADM706SAR ADM706SAR ADM708TAN ADM708TAN ADM706TAR ADM706TAR ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C N-8 SO-8 N-8 SO-8 N-8 SO-8 N-8 SO-8 N-8 SO-8 N-8 SO-8 N-8 SO-8 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . . . ­0.3 V to VCC + 0.3 V Input Current VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . ­40°C to +85°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Storage Temperature Range . . . . . . . . . . . . . ­65°C to +150°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5 kV * REV. 0 ADM706/708 ADM706/708 data sheet Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability ­3­ 3 10/17/95, 9:06 AM ADM706P/R/S/T ADM706P/R/S/T, ADM708R/S/T ADM708R/S/T PIN FUNCTION DESCRIPTION Mnemonic Pin No. ADM706 ADM706 Pin No. ADM708 ADM708 MR 1 1 VCC GND PFI 2 3 4 2 3 4 PFO 5 5 WDI 6 N/A NC RESET N/A 7 (R/S/T Only) 6 7 RESET 7 (P Only) 8 WDO 8 N/A Function Manual Reset Input. When taken below 0.6 V a RESET is generated. MR can be driven from TTL, CMOS logic or from a manual reset switch as it is internally debounced. An internal 70 µA pull-up current holds the input high when floating. Power Supply Input. 0 V. Ground reference for all signals. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected to GND. Power Fail Output. PFO is the output from the Power Fail Comparator. It goes low when PFI is less than 1.25 V. Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, the watchdog output WDO goes low. The timer resets with each transition at the WDI input. Either a high-to-low or a low-to-high transition will clear the counter. The internal timer is also cleared whenever reset is asserted. The Watchdog Timer is disabled when WDI is left floating or connected to a three-state buffer. No Connect. Logic Output. RESET goes low for 200 ms when triggered. It can be triggered either by VCC being below the reset threshold or by a low signal on the manual reset (MR) input. RESET will remain low whenever VCC is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout will not trigger RESET unless WDO is connected to MR. Logic Output. RESET is an active high output suitable for systems which use active high RESET logic. It is the inverse of RESET. Logic Output. The Watchdog Output, WDO, goes low if the internal watchdog timer times out as a result of inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC goes above the reset threshold, WDO goes high immediately. PIN CONFIGURATIONS MR 1 8 WDO MR 1 8 WDO MR 1 8 RESET VCC 2 7 RESET VCC 2 7 RESET VCC 2 7 RESET GND 3 6 WDI GND 3 6 WDI GND 3 6 NC PFI 4 5 PFO PFI 4 5 PFO PFI 4 5 PFO ADM706 ADM706 P TOP VIEW (Not to Scale) ADM706 ADM706 R/S/T TOP VIEW (Not to Scale) ADM708 ADM708 R/S/T TOP VIEW (Not to Scale) NC = NO CONNECT REV. 0 ­4­ ADM706/708 ADM706/708 data sheet 4 10/17/95, 9:06 AM ADM706P/R/S/T ADM706P/R/S/T, ADM708R/S/T ADM708R/S/T Manual Reset WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER The manual reset input (MR) allows other reset sources such as a manual reset switch to generate a processor reset. The input is effectively debounced by the timeout period (200 ms typical). The MR input is TTL/CMOS compatible so it may also be driven by any logic reset output. If unused, the MR input may be tied high or left floating. WATCHDOG OUTPUT(WDO) RESET & WATCHDOG TIMEBASE VCC 70µA MR RESET GENERATOR RESET, (P = RESET) VRT VRT VCC tRS VCC VREF* RESET ADM706 ADM706 POWER FAIL INPUT (PFI) tRS POWER FAIL OUTPUT (PFO) 1.25V MR EXTERNALLY DRIVEN LOW MR *VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T) WDO Figure 1. ADM706 ADM706 Functional Block Diagram NOTE: RESET = COMPLEMENT OF RESET VCC RESET 70µA MR Figure 3. RESET, MR and WDO Timing RESET GENERATOR Watchdog Timer (ADM706 ADM706) RESET The watchdog timer circuit may be used to monitor the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the timeout period(1.6 sec), the watchdog output (WDO) is driven low. The WDO output may be connected to a nonmaskable interrupt (NMI)on the processor. Therefore, if the watchdog timer times out, an interrupt is generated. The interrupt service routine should then be used to rectify the problem. VCC VREF* ADM708 ADM708 POWER FAIL INPUT (PFI) POWER FAIL OUTPUT (PFO) 1.25V *VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T) The watchdog timer is cleared by either a high-to-low or by a low-to-high transition on WDI. Pulses as narrow as 50 ns are detected. The timer is also cleared by RESET/RESET going active. Therefore the watchdog timeout period begins after reset goes inactive. Figure 2. ADM708 ADM708 Functional Block Diagram CIRCUIT INFORMATION Power Fail Reset The reset output provides a reset (RESET or RESET) output signal to the Microprocessor whenever the VCC input is below the reset threshold. The actual reset threshold voltage is dependent on whether a P/R, S, or T suffix device is used. An internal timer holds the reset output active for 200 ms after the voltage on VCC rises above the threshold. This is intended as a power-on reset signal for the microprocessor. It allows time for both the power supply and the microprocessor to stabilize after powerup. If a power supply brownout or interruption occurs, the reset line is similarly activated and remains active for 200 ms after the supply recovers. If another interruption occurs during an active reset period, then the reset timeout period continues for an additional 200 ms. When VCC falls below the reset threshold, WDO is forced low whether or not the watchdog timer has timed out. Normally this would generate an interrupt but it is overridden by RESET/ RESET going active. The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). The WDO output can now be used as a low line output since it will only go low when VCC falls below the reset threshold. tWP tWD tWD WDI The reset output is guaranteed to remain valid with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition as the power supply starts up. WDO The ADM706P ADM706P provides an active high reset (RESET) signal; the ADM706R/S/T ADM706R/S/T provides an active low (RESET) signal; while the ADM708R/S/T ADM708R/S/T provides both RESET and RESET. RESET RESET EXTERNALLY TRIGGERED BY MR Figure 4. Watchdog Timing REV. 0 ADM706/708 ADM706/708 data sheet ­5­ 5 tWD 10/17/95, 9:07 AM tRS ADM706P/R/S/T ADM706P/R/S/T, ADM708R/S/T ADM708R/S/T 1.25 V CC ­ 1.25 V L = 1.25 + R1 ­ R2 R3 Power-Fail Comparator The power-fail comparator is an independent comparator which may be used to monitor the input power supply. The comparator's inverting input is internally connected to a 1.25 V reference voltage.The noninverting input is available at the PFI input. This input may be used to monitor the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the comparator output (PFO) goes low indicating a power failure. For early warning of power failure the comparator may be used to monitor the preregulator input simply by chosing an appropriate resistive divider network. The PFO output can be used to interrupt the processor so that a shutdown procedure is implemented before the power is lost. INPUT POWER R1 Valid RESET Below 1 V V CC The ADM70x family of products are guaranteed to provide a valid reset level with VCC as low as 1 V. Please refer to the Typical Performance Characteristics. As VCC drops below 1 V, the internal transistor will not have sufficient drive to hold it ON so the voltage on RESET will no longer be held at 0 V. A pulldown resistor as shown in Figure 7 may be connected externally to hold the line low if it is required. PFO 1.25V POWER-FAIL INPUT R1 + R2 V MID 1.25 R2 ADM70x POWER-FAIL OUTPUT PFI RESET ADM70x R2 R1 GND Figure 5. Power-Fail Comparator Figure 7. RESET Valid Below 1 V Adding Hysteresis to the Power-Fail Comparator For increased noise immunity, hysteresis may be added to the power-fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 6. When PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, resistor R3 sources current into the PFI summing junction.This results in differing trip levels for the comparator. Further noise immunity may be achieved by connecting a capacitor between PFI and GND. ADM663A ADM663A Typical Performance Characteristics VCC +3.3V INPUT POWER VCC R1 RESET PFO 1.25V TO µP NMI PFI 400ms/DIV ADM70x R2 Figure 8. ADM706/ADM708 ADM706/ADM708 RESET Output Voltage vs. Supply Voltage R3 3.3V PFO VCC 0V VH VL 0V VIN Figure 6. Adding Hysteresis to the Power-Fail Comparator RESET R2 + R3 V H = 1.25 1 + R1 R2 × R3 400ms/DIV Figure 9. RESET Output Voltage vs. Supply Voltage REV. 0 ­6­ ADM706/708 ADM706/708 data sheet 6 10/17/95, 9:09 AM ADM706P/R/S/T ADM706P/R/S/T, ADM708R/S/T ADM708R/S/T VCC = VRT TA = +25°C VCC = +5V TA = +25°C 1.3V PFI +3V +3V +1.2V RESET RESET +3V PFO 0V 0V 0V 500ns/DIV 100ns/DIV Figure 10. PFI Assertion Response Time Figure 13. RESET, RESET Deassertion TA = +25°C VCC = +5V TA = +25°C +3V VCC +2V +1.3V PFI 1.2V +3V +3V RESET PFO 0V 0V 2µs/DIV 500ns/DIV Figure 14. ADM706/ADM708 ADM706/ADM708 RESET Response Time Figure 11. PFI Deassertion Response Time APPLICATIONS A typical operating Circuit is shown in Figure 15. The unregulated dc input supply is monitored using the PFI input via the resistive divider network. Resistors R1 and R2 should be selected such that when the supply voltage drops below the desired level (e.g., 5 V) the voltage on PFI drops below the 1.25 V threshold thereby generating an interrupt to the µP. Monitoring the preregulator input gives additional time to execute an orderly shutdown procedure before power is lost. VCC = VRT TA = +25°C +3V +3V RESET RESET 0V UNREGULATED DC 0V ADM666A ADM666A IN OUT GND 100ns/DIV VCC +3.3V RESET WDI Figure 12. RESET, RESET Assertion I/O LINE ADM706 ADM706 PFI WDO MR PFO GND VCC RESET µP NMI INTERRUPT MANUAL RESET Figure 15. Typical Application Circuit REV. 0 ADM706/708 ADM706/708 data sheet ­7­ 7 10/17/95, 9:10 AM ADM706P/R/S/T ADM706P/R/S/T, ADM708R/S/T ADM708R/S/T Microprocessor activity is monitored using the WDI input. This is driven using an output line from the processor. The software routines should toggle this line at least once every 1.6 seconds. If a problem occurs and this line is not toggled, then WDO goes low and a nonmaskable interrupt is generated. This interrupt routine may be used to clear the problem. VCC WDI PFI MR C1998 C1998­18­1/95 R2 PFO MR GND Figure 17. Monitoring 3 V/3.3 V and an Additional Supply, VX µP µPs With Bidirectional RESET I/O LINE WDI µP PFI RESET ADM706 ADM706 RESET RESET ADM706 ADM706 R1 If, in the event of inactivity on the WDI line, a system reset is required, then the WDO output should be connected to the MR input as shown in Figure 16. RESET +3V/+3.3V VX In order to prevent contention for microprocessors with a bidirectional reset line, a current limiting resistor should be inserted between the ADM70x RESET output pin and the µP reset pin. This will limit the current to a safe level if there are conflicting output reset levels. A suitable resistor value is 4.7 k. If the reset output is required for other uses, then it should be buffered as shown in Figure 18. WDO GND Figure 16. RESET from WDO Monitoring Additional Supply Levels It is possible to use the power-fail comparator to monitor a second supply as shown in Figure 17. The two sensing resistors R1 and R2 are selected such that the voltage on PFI drops below 1.25 V at the minimum acceptable input supply. The PFO output may be connected to the MR input so that a RESET is generated when the supply drops out of tolerance. In this case if either supply drops out of tolerance, a RESET will be generated. BUFFERED RESET +3V/+3.3V VCC ADM70x µP RESET RESET GND GND Figure 18. Bidirectional I-O RESET OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (SO-8) 8-Lead Plastic DIP (N-8) 8 5 1 0.31 (7.87) 8 4 0.1574 (4.00) 0.1497 (3.80) 4 1 0.30 (7.62) REF 0.39 (9.91) MAX 0.035 ± 0.01 (0.89 ± 0.25) 0.165 ± 0.01 (4.19 ± 0.25) 5 0.2440 (6.20) 0.2284 (5.80) 0.1968 (5.00) 0.1890 (4.80) SEATING PLANE 0.0196 (0.50) × 45° 0.0099 (0.25) 0.0098 (0.25) 0.0040 (0.10) 0.011 ± 0.003 (4.57 ± 0.76) 0.125 (3.18) MIN 0.102 (2.59) 0.094 (2.39) 0°-8° 0.018 ± 0.003 (0.46 ± 0.08) 0.10 (2.54) TYP 0.18 ± 0.03 (4.57 ± 0.76) 0.0500 (1.27) BSC 0°- 15° 0.0192 (0.49) 0.0138 (0.35) SEATING PLANE 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.033 (0.84) NOM REV. 0 ­8­ ADM706/708 ADM706/708 data sheet 8 10/17/95, 9:11 AM PRINTED IN U.S.A. 0.25 (6.35)