MAX5181/MAX5184 MAX5184 MAX5187/MAX5190 MAX5181BEEG MAX5184BEEG MAX5184ETG - Datasheet Archive
10-Bit, 40MHz, Current/Voltage-Output DACs The devices are designed to provide a high level of signal integrity for the least
19-1579; Rev 4; 4/03 10-Bit, 40MHz, Current/Voltage-Output DACs The devices are designed to provide a high level of signal integrity for the least amount of power dissipation. They operate from a single 2.7V to 3.3V supply. Additionally, these DACs have three modes of operation: normal, low-power standby, and full shutdown, which provides the lowest possible power dissipation with a 1µA (max) shutdown current. A fast wake-up time (0.5µs) from standby mode to full DAC operation facilitates power conservation by activating the DAC only when required. The MAX5181/MAX5184 MAX5181/MAX5184 are available in 24-pin QSOP packages and are specified for the extended (-40°C to +85°C) temperature range. Additionally, the MAX5184 MAX5184 is also available in a 24-pin thin QFN with exposed paddle (EP) and is specified for the extended (-40°C to +85°C) temperature range. For lower resolution, 8-bit versions, refer to the MAX5187/MAX5190 MAX5187/MAX5190 data sheet. Applications Signal Reconstruction Arbitrary Waveform Generators (AWGs) Direct Digital Synthesis Imaging Applications Features o 2.7V to 3.3V Single-Supply Operation o Wide Spurious-Free Dynamic Range: 70dB at fOUT = 2.2MHz o Fully Differential Output o Low-Current Standby or Full Shutdown Modes o Internal 1.2V, Low-Noise Bandgap Reference o Small 24-Pin QSOP and Thin QFN Packages Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5181BEEG MAX5181BEEG -40°C to +85°C 24 QSOP MAX5184BEEG MAX5184BEEG -40°C to +85°C 24 QSOP MAX5184ETG MAX5184ETG -40°C to +85°C 24 Thin QFN-EP* *EP = Exposed paddle. Pin Configurations TOP VIEW CREF 1 24 REFO OUTP 2 23 REFR OUTN 3 22 DGND AGND 4 AVDD 5 DACEN 6 21 DVDD MAX5181 MAX5181 MAX5184 MAX5184 20 D9 19 D8 PD 7 18 D7 CS 8 17 D6 CLK 9 16 D5 REN 10 15 D4 D0 11 14 D3 D1 12 13 D2 QSOP Pin Configurations continued at end of data sheet. _ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5181/MAX5184 MAX5181/MAX5184 General Description The MAX5181 MAX5181 is a 10-bit, current-output digital-to-analog converter (DAC) designed for superior performance in signal reconstruction or arbitrary waveform generation applications requiring analog signal reconstruction with low distortion and low-power operation. The MAX5184 MAX5184 provides equal specifications, with on-chip precision resistors for voltage-output operation. The MAX5181/MAX5184 MAX5181/MAX5184 are designed for a 10pVs glitch operation to minimize unwanted spurious signal components at the output. An on-board 1.2V bandgap circuit provides a well-regulated, low-noise reference that can be disabled for external reference operation. MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD, DVDD to AGND, DGND .-0.3V to +6V Digital Inputs to DGND.-0.3V to +6V OUTP, OUTN, CREF to AGND .-0.3V to +6V VREF to AGND .-0.3V to +6V AGND to DGND.-0.3V to +0.3V AVDD to DVDD . ±3.3V Maximum Current into Any Pin.50mA Continuous Power Dissipation (TA = +70°C) 24-Pin QSOP (derate 9.50mW/°C above +70°C) .762mW 24-Pin Thin QFN (derate 20.8mW/°C above +70°C) .1667mW Operating Temperature Range MAX518 MAX518_BEEG .-40°C to +85°C MAX5184ETG MAX5184ETG .-40°C to +85°C Storage Temperature Range .-65°C to +150°C Lead Temperature (soldering, 10s) .+300°C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = 3V, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL 10 Bits +2 LSB ±0.5 1 LSB -2 +2 MAX5184 MAX5184 -8 +8 (Note 1) Full-Scale Error ±0.5 -1 MAX5181 MAX5181 Zero-Scale Error -2 Guaranteed monotonic -40 ±15 +40 LSB LSB DYNAMIC PERFORMANCE Output Settling Time To ±0.5LSB error band 25 10 Glitch Impulse Spurious-Free Dynamic Range to Nyquist fCLK = 40MHz, fOUT = 500kHz SFDR fCLK = 40MHz, fOUT = 2.2MHz, TA = +25°C ns pVs 72 57 dBc 70 fCLK = 40MHz, fOUT = 500kHz Total Harmonic Distortion to Nyquist THD MAX5184ETG MAX5184ETG -70 fCLK = 40MHz, fOUT = 2.2MHz, TA = +25°C -68 -63 fCLK = 40MHz, fOUT = 2.2MHz, TA = +25°C -68 -57 fCLK = 40MHz, fOUT = 500kHz MAX518 MAX518_BEEG 61 SNR Clock and Data Feedthrough MAX518 MAX518_BEEG fCLK = 40MHz, fOUT = 2.2MHz, TA = +25°C MAX5184ETG MAX5184ETG Signal-to-Noise Ratio to Nyquist fCLK = 40MHz, fOUT = 2.2MHz 56 59 dBc dB 59 All 0s to all 1s 50 nVs 10 Output Noise pA/Hz ANALOG OUTPUT Full-Scale Output Voltage VFS 400 Voltage Compliance of Output Output Leakage Current 2 mV -0.3 DACEN = 0, MAX5181 MAX5181 only 0.8 V -1 1 µA _ 10-Bit, 40MHz, Current/Voltage-Output DACs (AVDD = DVDD = 3V, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS Full-Scale Output Current IFS MAX5181 MAX5181 only DAC External Output Resistor load RL MIN TYP MAX UNITS 0.5 1 1.5 mA MAX5181 MAX5181 only 400 REFERENCE Output Voltage Range VREF 1.12 1.2 1.28 V Output Voltage Temperature Drift TCVREF 50 ppm/°C Reference Output Drive Capability IREFOUT 10 µA Reference Supply Rejection 0.5 mV/V 8 Current Gain (IFS / IREF) mA/mA POWER REQUIREMENTS Analog Power-Supply Voltage AVDD Analog Supply Current IAVDD Digital Power-Supply Voltage DVDD Digital Supply Current 2.7 PD = 0, DACEN = 1, digital inputs at 0 or DVDD 3.3 2.7 V 4.0 mA 3.3 1.7 V Shutdown Current IDVDD PD = 0, DACEN = 1, digital inputs at 0 or DVDD 4.2 5.0 mA ISTANDBY Standby Current PD = 0, DACEN = 0, digital inputs at 0 or DVDD 1.0 1.5 mA PD = 1, DACEN = X,digital inputs at 0 or DVDD (X = don't care) 0.5 1 µA ISHDN LOGIC INPUTS AND OUTPUTS Digital Input Voltage High VIH Digital Input Voltage Low VIL Digital Input Current IIN Digital Input Capacitance 2 V 0.8 ±1 CIN VIN = 0 or DVDD 10 V µA pF TIMING CHARACTERISTICS DAC DATA to CLK Rise Setup Time tDS 10 ns DAC CLK Rise to DATA Hold Time tDH 0 ns CS Fall to CLK Rise Time 5 ns CS Fall to CLK Fall Time 5 ns DACEN Rise Time to VOUT 0.5 µs PD Fall Time to VOUT 50 µs Clock Period tCLK 25 ns Clock High Time tCH 10 ns Clock Low Time tCL 10 ns Note 1: Excludes reference and reference resistor (MAX5184 MAX5184) tolerance. _ 3 MAX5181/MAX5184 MAX5181/MAX5184 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (AVDD = DVDD = 3V, AGND = DGND = 0, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25°C, unless otherwise noted.) 0.2 DNL (LSB) 0.3 0.2 0.1 0.1 0 -0.1 0 MAX5181/4toc03 0.3 0.4 INL (LSB) MAX5181/4toc02 0.5 3.0 ANALOG SUPPLY CURRENT (mA) 0.4 MAX5181/4toc01 0.6 ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. INPUT CODE INTEGRAL NONLINEARITY vs. INPUT CODE 2.5 2.0 MAX5184 MAX5184 1.5 MAX5181 MAX5181 -0.2 -0.1 -0.2 1.0 -0.3 0 0 128 256 384 512 640 768 896 1024 128 256 384 512 640 768 896 1024 2.5 3.0 3.5 4.0 4.5 5.0 INPUT CODE INPUT CODE DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE DIGITAL SUPPLY CURRENT vs. TEMPERATURE 2.0 MAX5184 MAX5184 1.5 MAX5181 MAX5181 MAX5184 MAX5184 6 MAX5181 MAX5181 5 4 3 1.0 -15 10 35 60 3.75 MAX5184 MAX5184 3.50 MAX5181 MAX5181 3.25 3.00 2.5 85 MAX5181/4toc06 MAX5181/4toc05 7 4.00 DIGITAL SUPPLY CURRENT (mA) 2.5 8 DIGITAL SUPPLY CURRENT (mA) MAX5181/4toc04 ANALOG SUPPLY CURRENT (mA) 3.0 -40 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 TEMPERATURE (°C) SUPPLY VOLTAGE (V) STANDBY CURRENT vs. TEMPERATURE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 590 MAX5181 MAX5181 580 MAX5181 MAX5181 570 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 0.10 MAX5181 MAX5181 0.08 MAX5184 MAX5184 0.04 550 4.0 0.12 0.06 560 3.5 MAX5181/4toc09 MAX5181/4toc08 580 0.14 SHUTDOWN CURRENT (µA) MAX5184 MAX5184 MAX5184 MAX5184 590 STANDBY CURRENT (µA) 600 570 4 600 MAX5181/4toc07 610 3.0 85 TEMPERATURE (°C) STANDBY CURRENT vs. SUPPLY VOLTAGE 2.5 5.5 SUPPLY VOLTAGE (V) ANALOG SUPPLY CURRENT vs. TEMPERATURE STANDBY CURRENT (µA) MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs -40 -15 10 35 TEMPERATURE (°C) 60 85 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) _ 5.0 5.5 10-Bit, 40MHz, Current/Voltage-Output DACs INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX5181 MAX5181 0.07 MAX5184 MAX5184 1.27 REFERENCE VOLTAGE (V) 0.09 REFERENCE VOLTAGE (V) 0.11 1.26 MAX5184 MAX5184 1.25 MAX5181 MAX5181 1.24 0.05 -40 -15 10 35 60 1.26 MAX5181 MAX5181 1.25 MAX5184 MAX5184 1.23 2.5 85 1.27 1.24 1.23 0.03 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) 5.5 -40 SUPPLY VOLTAGE (V) OUTPUT CURRENT vs. REFERENCE CURRENT DYNAMIC RESPONSE RISE TIME -15 10 35 60 85 TEMPERATURE (°C) DYNAMIC RESPONSE FALL TIME MAX5181/4toc15 MAX5181/4toc14 MAX5181/4toc13 4 OUTP 150mV/ div OUTP 150mV/ div OUTN 150mV/ div 3 OUTN 150mV/ div 2 1 0 100 200 300 400 500ns/div 500ns/div 500 REFERENCE CURRENT (µA) SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY FFT PLOT MAX5181/4toc16 0 -10 fOUT = 2.2MHz fCLK = 40MHz -20 100 MAX5181/4toc18 SETTLING TIME MAX5181/4toc17 90 -30 OUTN 100mV/ div 80 -40 -50 -60 SFDR (dBc) 0 (dBc) OUTPUT CURRENT (mA) 1.28 MAX5181/4toc11 1.28 MAX5181/4toc10 SHUTDOWN CURRENT (µA) 0.13 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX5181/4toc12 SHUTDOWN CURRENT vs. TEMPERATURE MAX5181/MAX5184 MAX5181/MAX5184 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V, AGND = DGND = 0, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25°C, unless otherwise noted.) -70 -80 OUTP 100mV/ div 12.5ns/div 70 60 -90 -100 -110 -120 50 40 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz) 10 15 20 25 30 35 40 45 50 55 60 CLOCK FREQUENCY (MHz) _ 5 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V, AGND = DGND = 0, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE PLUS DISTORTION vs. OUTPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY 76 62.4 MAX5181/4toc20 fCLK = 20MHz fCLK = 50MHz fCLK = 40MHz MAX5181/4toc19 78 62.2 62.0 72 fCLK = 10MHz SIINAD (dB) SFDR (dBc) 74 fCLK = 60MHz 61.8 61.6 61.4 70 61.2 68 61.0 fCLK = 30MHz 60.8 66 500 900 1300 1700 0 2100 500 1000 1500 2000 OUTPUT FREQUENCY (kHz) SPURIOUS-FREE DYNAMIC RANGE vs. FULL-SCALE OUTPUT CURRENT 0 MAX5181/84-22 MAX5181/84-22 74 MAX5181/4toc21 20 72 -20 70 SFDR (dBc) -40 -60 -80 68 66 -100 64 -120 62 -140 60 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz) 6 2500 OUPUT FREQUENCY (kHz) MULTITONE SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY SFDR (dBc) MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs 0.5 0.75 1.0 1.25 1.5 FULL-SCALE OUTPUT CURRENT (mA) _ 10-Bit, 40MHz, Current/Voltage-Output DACs PIN FUNCTION FUNCTION NAME QSOP THIN QFN 1 22 CREF REFO 2 23 OUTP Positive Analog Output. Current output for MAX5181 MAX5181; voltage output for MAX5184 MAX5184. 3 24 OUTN Negative Analog Output. Current output for MAX5181 MAX5181; voltage output for MAX5184 MAX5184. 4 1, EP AGND Analog Ground. Exposed paddle must be connected to AGND. 5 2 AVDD Analog Positive Supply, 2.7V to 3.3V DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND 1: Power-up DAC with PD = DGND X: Enter shutdown mode with PD = DVDD (X = don't care) 6 3 DACEN 7 4 PD Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD) 1: Enter shutdown mode 8 5 CS Active-Low Chip Select 9 6 CLK Clock Input 10 7 REN Active-Low Reference Enable. Connect to DGND to activate on-chip 1.2V reference. 11 8 D0 Data Bit D0 (LSB) 1219 916 D1D8 Data Bits D1D8 20 17 D9 21 18 DVDD Digital Supply, 2.7V to 3.3V 22 19 DGND Digital Ground 23 20 REFR Reference Input 24 21 REFO Reference Output Data Bit D9 (MSB) _ 7 MAX5181/MAX5184 MAX5181/MAX5184 Pin Description MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs Detailed Description provides a 1.2V output. Due to its limited 10µA output drive capability, REFO must be buffered with an external amplifier, if heavier loading is required. The MAX5181/MAX5184 MAX5181/MAX5184 also employ a control amplifier designed to regulate simultaneously the full-scale output current (IFS) for both outputs of the devices. The output current is calculated as follows: The MAX5181/MAX5184 MAX5181/MAX5184 are 10-bit digital-to-analog converters (DACs) capable of operating with clock speeds up to 40MHz. Each converter consists of separate input and DAC registers, followed by a current source array capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated 1.2V voltage reference and control amplifier determine the data converters' full-scale output currents/voltages. Careful reference design ensures close gain matching and excellent drift characteristics. The MAX5184 MAX5184's voltage output operation features matched 400 on-chip resistors that convert the current-array current into a voltage. IFS = 8 IREF where I REF is the reference output current (I REF = VREFO/RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier's output current on the MAX5181 MAX5181 (Figure 2). This current is mirrored into the current source array, where it is equally distributed between matched current segments and summed to valid output current readings for the DACs. The MAX5184 MAX5184 converts this output current into a differential output voltage (VOUT) with two internal, groundreferenced 400 load resistors. Using the internal 1.2V reference voltage, the MAX5184 MAX5184's integrated Internal Reference and Control Amplifier The MAX5181/MAX5184 MAX5181/MAX5184 provide an integrated 50ppm/°C, 1.2V, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to DGND, the internal reference is selected and REFO REN AVDD AGND CS DACEN PD 1.2V REF REFO CREF CURRENTSOURCE ARRAY REFR OUTP DAC SWITCHES OUTN 9.6k* OUTPUT LATCHES OUTPUT LATCHES MSB DECODE CLK 400* MSB DECODE INPUT LATCHES INPUT LATCHES MAX5181 MAX5181 MAX5184 MAX5184 DVDD *INTERNAL 400 AND 9.6k RESISTORS FOR MAX5184 MAX5184 ONLY. 400* DGND D9D0 Figure 1. Functional Diagram 8 _ 10-Bit, 40MHz, Current/Voltage-Output DACs External Reference To disable the MAX5181/MAX5184 MAX5181/MAX5184's internal reference, connect REN to DVDD. A temperature-stable, external reference may now be applied to drive the REFO pin to set the full-scale output (Figure 3). Choose a reference capable of supplying at least 150µA to drive the bias circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference such as the 1.2V, 25ppm/°C MAX6520 MAX6520 bandgap reference. Standby Mode To enter the lower-power standby mode, connect digital inputs PD and DACEN to DGND. In standby, both the reference and the control amplifier are active with the current array inactive. To exit this condition, DACEN must be pulled high with PD held at DGND. The MAX5181/MAX5184 MAX5181/MAX5184 typically require 50µs to wake up and let both outputs and the reference settle. Shutdown Mode For lowest power consumption, the MAX5181/MAX5184 MAX5181/MAX5184 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the DAC supply current is reduced to 1µA. To enter this mode, connect PD to DVDD. To return to active mode, connect PD to DGND and DACEN to DV DD. About 50µs are required for the parts to leave shutdown mode and settle to their outputs' values prior to shutdown. Table 1 lists the power-down mode selection. Timing Information Figure 4 shows a detailed timing diagram for the MAX5181/MAX5184 MAX5181/MAX5184. With each high transition of the clock, the input latch is loaded with the digital value set by bits D9 through D0. The content of the input latch is then shifted to the DAC register, and the output updates at the rising edge of the next clock. Outputs The MAX5181 MAX5181 output is designed to supply full-scale output currents of 1mA into 400 loads in parallel with a capacitive load of 5pF. The MAX5184 MAX5184 features integrated 400 resistors that restore the array current to proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a single-ended voltage. OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS DGND REN 1.2V BANDGAP REFERENCE MAX4040 MAX4040 REFO RSET CCOMP* AGND REFR RSET CURRENTSOURCE ARRAY IREF RSET* 9.6k MAX5181 MAX5181 MAX5184 MAX5184 AGND *COMPENSATION CAPACITOR (CCOMP = 100nF) IFS *9.6k REFERENCE CURRENT-SET RESISTOR INTERNAL TO MAX5184 MAX5184 ONLY. USE EXTERNAL RSET FOR MAX5181 MAX5181. Figure 2. Setting IFS with the Internal 1.2V Reference and the Control Amplifier _ 9 MAX5181/MAX5184 MAX5181/MAX5184 reference output-current resistor (RSET = 9.6k) sets IREF to 125µA and IFS to 1mA. MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs Table 1. Power-Down Mode Selection PD (POWER-DOWN SELECT) DACEN (DAC ENABLE) POWER-DOWN MODE 0 0 Standby 0 1 Wake-Up 1 X Shutdown OUTPUT STATE MAX5181 MAX5181 High-Z MAX5184 MAX5184 AGND Last state prior to standby mode MAX5181 MAX5181 High-Z MAX5184 MAX5184 AGND X = Don't care. DVDD 10µF 0.1µF DGND REN 1.2V BANDGAP REFERENCE AVDD EXTERNAL 1.2V REFERENCE REFO CURRENTSOURCE ARRAY REFR IFS MAX6520 MAX6520 AGND RSET 9.6k* AGND MAX5181 MAX5181 MAX5184 MAX5184 *9.6k REFERENCE CURRENT-SET RESISTOR INTERNAL TO MAX5184 MAX5184 ONLY. USE EXTERNAL RSET FOR MAX5181 MAX5181. Figure 3. MAX5181/MAX5184 MAX5181/MAX5184 with External Reference Applications Information Static and Dynamic Performance Definitions Integral Nonlinearity Integral nonlinearity (INL) (Figure 5a) is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function once offset and gain errors have 10 been nullified. For a DAC, the deviations are measured every single step. Differential Nonlinearity Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. _ 10-Bit, 40MHz, Current/Voltage-Output DACs tCL MAX5181/MAX5184 MAX5181/MAX5184 tCLK tCH CLK D0D9 N-1 N tDS OUT N+1 tDH N-1 N N+1 Figure 4. Timing Diagram Offset Error Offset error (Figure 5c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated by trimming. Gain Error Gain error (Figure 5d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time Settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Digital Feedthrough Digital feedthrough is the noise generated on a DAC's output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal's first four harmonics to the fundamental itself. This is expressed as: (V22 + V32 + V4 2 + V52 ) THD = 20 × log V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. Differential to Single-Ended Conversion The MAX4108 MAX4108 low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the array current output of the MAX5181 MAX5181. The differential voltage across OUTP and OUTN is converted into a single-ended voltage by designing an appropriate operational amplifier configuration (Figure 6). I/Q Reconstruction in a QAM Application The low-distortion performance of two MAX5181/ MAX5181/ MAX5184s supports analog reconstruction of in-phase (I) and quadrature (Q) carrier components typically used in quadrature amplitude modulation (QAM) architectures where two separate buses carry the I and Q data. A QAM signal is both amplitude (AM) and phase modulated, created by summing two independently modulated carriers of identical frequency but different phase (90° phase difference). In a typical QAM application (Figure 7), the modulation occurs in the digital domain, and two DACs such as the MAX5181/MAX5184 MAX5181/MAX5184 may be used to reconstruct the analog I and Q components. _ 11 7 6 ANALOG OUTPUT VALUE ANALOG OUTPUT VALUE 6 5 4 AT STEP 011 (1/2 LSB ) 3 2 AT STEP 001 (1/4 LSB ) 1 1 LSB 5 DIFFERENTIAL LINEARITY ERROR (-1/4 LSB) 4 3 1 LSB 2 DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 0 0 000 001 010 011 100 101 110 000 111 001 Figure 5a. Integral Nonlinearity IDEAL OFFSET POINT 0 000 001 OFFSET ERROR (+1 1/4 LSB) ANALOG OUTPUT VALUE IDEAL DIAGRAM 1 100 101 IDEAL FULL-SCALE OUTPUT 7 2 ACTUAL OFFSET POINT 011 Figure 5b. Differential Nonlinearity ACTUAL DIAGRAM 3 010 DIGITAL INPUT CODE DIGITAL INPUT CODE ANALOG OUTPUT VALUE MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs GAIN ERROR (-1 1/4 LSB) 6 IDEAL DIAGRAM ACTUAL FULL-SCALE OUTPUT 5 4 0 010 011 000 100 101 110 111 DIGITAL INPUT CODE DIGITAL INPUT CODE Figure 5c. Offset Error Figure 5d. Gain Error The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed components with in-phase and quadrature carrier frequencies and then sums both outputs to provide the QAM signal. For each clock cycle, a counter adds one count to the address for the waveform memory. The memory then loads the next value to the DAC, which generates an analog output voltage corresponding to that data value. A DAC output filter can either be a simple or complex lowpass filter, depending on the AWG requirements for waveform function and frequencies. The main limitations of the AWG's flexibility are DAC resolution and dynamic performance, memory length, clock frequency, and the filter characteristics. Although the MAX5181/MAX5184 MAX5181/MAX5184 offer high-frequency operation and excellent dynamics, they are suitable for relaxed requirements in resolution (10-bit AWGs). To increase an AWG's high-frequency accuracy, tempera- Using the MAX5181/MAX5184 MAX5181/MAX5184 for Arbitrary Waveform Generation Designing a traditional arbitrary waveform generator (AWG) requires five major functional blocks (Figure 8a): clock generator, counter, waveform memory, DAC for waveform reconstruction, and output filter. The waveform memory contains the sequentially stored digital replica of the desired analog waveforms. This memory shares a common clock with the DAC. 12 _ 10-Bit, 40MHz, Current/Voltage-Output DACs MAX5181/MAX5184 MAX5181/MAX5184 +3V AVDD + +3V 0.1µF 10µF + 10µF 0.1µF 0.1µF 402 DVDD AVDD CREF +5V 402 OUTP CLK OUTPUT 400* D0D9 MAX5181 MAX5181 MAX5184 MAX5184 402 -5V MAX4108 MAX4108 OUTN REFO 402 0.1µF 400* REFR RSET* DGND REN AGND *MAX5181 MAX5181 ONLY *400 RESISTORS INTERNAL TO MAX5184 MAX5184 ONLY. Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier AVDD +3V DVDD +3V I COMPONENT 10 DIGITAL SIGNAL PROCESSOR MAX5181 MAX5181 MAX5184 MAX5184 AVDD CARRIER FREQUENCY DVDD Q COMPONENT 10 BP FILTER MAX5181 MAX5181 MAX5184 MAX5184 0° 90° IF BP FILTER MAX2452 MAX2452 QUADRATURE MODULATOR Figure 7. Using the MAX5181/MAX5184 MAX5181/MAX5184 for I/Q Signal Reconstruction _ 13 MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs DVDD AVDD COUNTER ADR WAVEFORM MEMORY (RAM) LOWPASS RECONSTRUCTION FILTER DATA 10 CLOCK GENERATOR MAX5181 MAX5181 MAX5184 MAX5184 400* VARIABLE fc 9.6k* FILTERED WAVEFORM (ANALOG OUTPUT) *MAX5181 MAX5181 ONLY Figure 8a. Traditional Arbitrary Waveform Generation CLOCK GENERATOR AVDD PIR PHASE INCREMENT REGISTER A D D E R PHASE ACCUMULATOR ADR WAVEFORM MEMORY (RAM) DVDD LOWPASS RECONSTRUCTION FILTER DATA 10 MAX5181 MAX5181 MAX5184 MAX5184 ACCUMULATOR FEEDBACK LOOP FOR DATA BITS 400* 9.6k* VARIABLE fc FILTERED WAVEFORM (ANALOG OUTPUT) *MAX5181 MAX5181 ONLY Figure 8b. Direct Digital Synthesis AWG ture stability, wide-band tuning, and past phase-continuos frequency switching, the user may approach a direct digital synthesis (DDS) AWG (Figure 8b). This DDS loop supports standard waveforms that are repetitive, such as sine, square, TTL, and triangular waveforms. DDS allows for precise control of the data-stream input to the DAC. Data for one complete output waveform cycle is sequentially stored in a RAM. As the RAM addresses are changing, the DAC converts the incoming data bits into a corresponding voltage waveform. The resulting output signal frequency is proportional to the frequency rate at which the RAM addresses are changed. 14 Grounding and Power-Supply Decoupling Grounding and power-supply decoupling strongly influence the MAX5181/MAX5184 MAX5181/MAX5184's performance. Unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections, which may affect dynamic specifications like SNR or SFDR. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5181/ MAX5181/ MAX5184 MAX5184. Therefore, grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. First, a multilayer PC board with separate ground and power-supply planes is recommended. High-speed signals should be run on controlled impedance lines _ 10-Bit, 40MHz, Current/Voltage-Output DACs Pin Configurations (continued) as close to the pin as possible, and their opposite ends should be as close as possible to the ground plane. The DVDD pins should also have separate 10µF and 0.1µF capacitors adjacent to their respective pins. Try to minimize analog load capacitance for proper operation. For best performance, bypass with low-ESR 0.1µF capacitors to AVDD. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network can also improve performance. Chip Information TRANSISTOR COUNT: 9464 SUBSTRATE CONNECTED TO AGND OUTN OUTP CREF REFO REFR DGND 24 23 22 21 20 19 TOP VIEW AGND 1 18 DVDD AVDD 2 17 D9 DACEN 3 16 D8 MAX5184 MAX5184 11 12 D3 D4 D5 10 13 D2 6 9 CLK D1 D6 8 D7 14 7 15 5 D0 4 CS REN PD THIN QFN _ 15 MAX5181/MAX5184 MAX5181/MAX5184 directly above the ground plane. Since the MAX5181/ MAX5181/ MAX5184 MAX5184 have separate analog and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two. Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Both devices have two power-supply inputs: analog VDD (AVDD) and digital VDD (DVDD). Each AVDD input should be decoupled with parallel 10µF and 0.1µF ceramic-chip capacitors. These capacitors should be Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QSOP.EPS MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs 16 _ 10-Bit, 40MHz, Current/Voltage-Output DACs 24L QFN THIN.EPS PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A _ 17 MAX5181/MAX5184 MAX5181/MAX5184 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX5181/MAX5184 MAX5181/MAX5184 10-Bit, 40MHz, Current/Voltage-Output DACs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 _Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.