MAX1780 MAX1780ECM 48-PIN - Datasheet Archive

 

MAX1780 Advanced Smart Battery Pack Controller Features General Description The MAX1780 Advanced Battery Pack Controller is a

 

19-1843; Rev 0; 12/00 MAX1780 MAX1780 Advanced Smart Battery Pack Controller Features General Description The MAX1780 MAX1780 Advanced Battery Pack Controller is a smart battery pack supervisor that integrates a User programmable Microcontroller Core, CoulombCounter-based Fuel Gauge, a multi-channel Data Acquisition Unit, a high-speed SPI Interface, and a Master/Slave SMBus Interface. The 8-bit, RISC, Microcontroller core is user programmable, and provides battery pack designers with complete flexibility in developing fuel gauging and control algorithms. The Data Acquisition Unit can measure individual cell voltages to within 50mV, total battery stack voltage (up to 20.48V), and chip internal/external temperature. · · · · · User Programmable Using an External EEPROM Accurate Fuel Gauge Uses V-to-F Method o < 1µV Input Offset Voltage o No External Calibration Required Eliminates Separate Primary Protection IC o 50mV Accurate Individual Cell Voltage Measurements o Built in Protection MOSFET Gate Drivers o Over Charge & Discharge Current Protection Fully Integrated LDO (V IN = 4V to 28V) 8-bit RISC Microcontroller Core o On-board 1.5K ROM & 0.5K Program RAM o 144 Bytes Data Memory o Fast Start-up 3.5MHz Instruction Oscillator o Watch Dog Timer Hardware SMBus with Master Capability GPIO Port and High Voltage LED Drivers Typical Operating Currents < 200µA Achievable Typical Shutdown Current of 1nA The user adjustable overcurrent comparators, along with individual cell voltage measurements, allow the MAX1780 MAX1780 to eliminate a separate primary pack protection IC. The MAX1780 MAX1780 can be directly connected to 2 to 4 series Lithium Ion cells, and supplies itself through a fully integrated 3.4V low drop out linear regulator. · · · · Typical Operating Circuit Applications + SMBus Battery Packs Proprietary Battery Packs 3.4V DIS BATT CHG Data Acquisition Systems B4P SHDN IO4/TIMERA Remote Data Logging OCI B3P ODI Pin Configuration N.C. N.C. B2P CS+ D 37 38 39 40 41 42 43 44 45 48 B1P SCL 46 DETECT C 47 AGND 1 HV7 MAX1780 MAX1780 HV6 35 3 BN CS+ 36 2 34 4 SDA BATT 33 5 HV5 CS- 32 6 HV0 7 AGND OSC1 HV1 31 MAX1780ECM MAX1780ECM 30 8 26 12 MCLR 27 11 HV4 28 10 OSC2 HV3 29 9 32.768KHz HV2 25 AIN 24 23 22 21 20 19 IO0/SCLK IO1/SO BTM1 IO2/SI BTM2 AGND 48-PIN 48-PIN TQFP VCC IO3 BTEST BTM0 - 18 IO7/INT1 S 17 VDD IO5 DISPLAY CAPACITY 16 3.4V 15 VAA IO6 14 EXTCLK 13 3.4V GND AGND CS WP SCLK HOLD SI SO Ordering Information VSS PART MAX1780ECM MAX1780ECM TEMP RANGE -40 °C to +85 °C PIN/ PACKAGE 48 TQFP 1 Advanced Smart Battery Pack Controller Table Of Contents General Description . 1 Typical Operating Circuit . 1 Features . 1 Applications . 1 Pin Configuration . 1 Ordering Information . 1 Table Of Contents. 2 Table Of Figures. 6 Table Of Tables. 7 List Of Applicable Documents. 8 Architectural Overview . 9 Introduction. 9 Harvard Architecture. 9 Detailed Description Of MAX1780 MAX1780 .11 Instruction Execution.11 Phase Clocks .12 CPU Architecture .13 Program Counter (PC).13 Program Stack .13 Arithmetic Logic Unit (ALU) .14 Working Register ("W").14 Option Register (Write Only, via the "W" Register and OPTION Instruction) .15 Setupint Register (Write Only, via the "W" Register and FREE Instruction) .16 Memory Organization:.17 Page Boundaries .17 Indirect Data Addressing; INDF and FSR Registers.18 Register File Organization.19 Data RAM.19 File Select Register (FSR) Read/Write.20 Status Register (Read/Write).21 Modes Of Operation .22 Shutdown .22 Entering Shutdown .22 Recovering From Shutdown .22 Sleep.22 Entering Sleep Mode .22 Wake-Up From Sleep Mode .22 Master Clear.22 Operate (Program Execution) .22 Analog And Mixed Signal Peripheral Interface.23 MAX1780 MAX1780 Power Supply Sequencing .24 MAX1780 MAX1780 Special Purpose Port Registers.25 PORTA .25 PORTA Data Latch (Read/Write).25 PORTA TRIS Latch (Write Only) .25 PORTB .26 PORTB Data Latch (Read/Write).27 PORTB TRIS Latch (Write Only) .27 Accessing The On-board Peripherals.27 2 Advanced Smart Battery Pack Controller PORTC (IO0 ­ IO7).28 PORTC GPIO Operation .28 I/O Programming Considerations .29 PORTC Data Latch.29 PORTC TRIS Latch.29 Timers And Watchdog .30 Timer A (TMRA).30 Timer B (TMRB).30 Watchdog Timer (WDT) .31 Interrupts .32 Description .32 Peripheral Interrupt Control Registers .33 Interrupt Status Register (INTSTAT) Operation .33 Interrupt Enable Register (INTREN) Operation.34 Interrupt Control Register Descriptions.34 Analog Peripherals .35 3.5MHz Instruction Oscillator .35 32KHz Oscillator .35 Low Drop Out Linear Regulator .35 Precision Bandgap Reference.36 Mixed Signal Peripherals .37 Fuel Gauge Unit .37 General Description .37 Features.37 Automatic Cancellation Of Input Offset Voltage .38 Coulomb Counting .38 Charge And Discharge Counters .38 Current Direction Change Detection Function .39 Counter Latching Source And Arbiter.39 Direct CPU Control.39 ADC Conversion Start and Stop.40 TIMERA Overflow .40 TIMERB Overflow .40 Arbitration Logic .40 Fuel Gauge Register Descriptions.41 Data Acquisition Unit .43 General Description.43 Features.43 Analog Front End/Multiplexer (AFE).44 Input Bias Cancellation .44 AFE Register Descriptions .45 Analog-To-Digital Converter (ADC) .46 Operation .46 Dual Voltage-To-Frequency Converter.46 Digital Counter/Adder .46 Control Logic And Resolution Counter Block.46 Over-Range Status And Limit Bits .46 The OVERFLOW Bit .46 The SIGN Bit .46 The LIMIT Bit.47 Understanding ADC Error Sources.47 3 Advanced Smart Battery Pack Controller Effective ADC Resolution .48 ADC Register Descriptions .49 Temperature Sensor .51 Description .51 Operation .51 Overcurrent Protection Block .52 Description .52 DISCHARGE LOGIC.53 CHARGE LOGIC.53 Using Software To Control The Protection MOSFETs.53 Clearing Overcurrent Interrupts.53 High-Voltage Output Port .55 Description .55 Operation .56 High-Voltage Output Port Register Description.56 Digital Peripherals .57 High-Speed SPI Interface.57 Description .57 Operation .57 SPI Interface Register Descriptions .58 SMBus Interface.59 Introduction.59 Features.59 Description .59 Start Detector .60 Restart Detector.60 Stop Detector.60 ACK Detector.60 ACK/NACK Generator .61 Automatic ACK Generation After a Start or Restart Condition:.61 Conditional ACK Generation In All Other Slave or Master Mode Receive Operations: .61 SCL Holding Detector.61 Automatic SCL Hold Circuit .61 Address Comparator .61 Bus Idle Detector .61 Master Clock Generator .61 35msec Timer.62 Slave Mode Operation .62 Initialization .62 Master Mode Operation .62 Sending a START Signal.63 Sending the Slave Address and Data Direction Bit .63 Sending a STOP Signal.64 Sending a Repeated START Signal.64 SMBus Interface Register Descriptions.65 Design And Applications Information .71 Interfacing With An External Serial EEPROM.71 Chip Select (CS\) .71 Serial Clock (SCLK) .71 Serial Output (SO) .71 Serial Input (SI) .71 4 Advanced Smart Battery Pack Controller Properly Connecting Lithium Ion Cells .72 Choosing The Current Sense Resistor (RCS).72 Setting The Overcurrent Thresholds .73 Handling Battery Insertion Surge Currents .75 Handling Charger Connection Surge Currents .75 Improving Fuel Gauge Measurement Accuracy.76 Use The Correct Ground Layout .76 Filter The Current Sense Inputs.76 Connecting The SHDN Pin .77 Shutting Down The MAX1780 MAX1780 Under Software Control .77 Starting Up The MAX1780 MAX1780 After Being Shutdown.78 Implementing An SBS-IF Safety Signal.79 Circuit Layout And Grounding .79 Pin Descriptions.80 Detailed Operating Circuit .82 Absolute Maximum Ratings .83 Electrical Characteristics .83 Electrical Characteristics (continued) .84 Electrical Characteristics (continued) .85 Electrical Characteristics (continued) .86 Electrical Characteristics (continued) .87 SPI Interface Electrical Characteristics.88 SMBus Interface Electrical Characteristics .89 Electrical Characteristics (continued, TA = -40°C to +85°C).92 Electrical Characteristics (continued, TA = -40°C to +85°C).93 SPI Interface Electrical Characteristics (TA = -40°C to +85°C).94 SMBus Interface Electrical Characteristics (TA = -40°C to +85°C).95 Typical Operating Characteristics .98 Typical Operating Characteristics (continued) .99 Typical Operating Characteristics (continued) .100 Package Information .102 Appendix .103 An Overview Of Smart Batteries .103 The Smart Battery In A Notebook Power Supply System.103 What Makes Smart Batteries "Smart"? .104 Lithium Ion Cell Protection .104 Instruction Set Summary.105 Errata.107 1. ODO/OCO Section:.107 Impact:.107 Solution/Workaround:.107 2. ODI/OCI Comparators:.107 Impact:.107 Solution/Workaround:.107 3. SPI Interface:.107 Impact:.107 Solution/Workaround:.107 4. SMBus Interface:.107 Impact:.107 Solution/Workaround:.108 5 Advanced Smart Battery Pack Controller Table Of Figures Figure 1, MAX1780 MAX1780 Harvard Architecture. 9 Figure 2, MAX1780 MAX1780 Block Diagram .10 Figure 3, MAX1780 MAX1780 Instruction Pipeline .11 Figure 4, Instruction Cycle Phase Clocks .12 Figure 5, MAX1780 MAX1780 Programming Model.13 Figure 6, MAX1780 MAX1780 Program Memory Organization.17 Figure 7, DRAM Organization.19 Figure 8, MAX1780 MAX1780 On-Board Peripherals .23 Figure 9, MAX1780 MAX1780 Power Supply Sequencing .24 Figure 10, PORT B Structure (1 Bit) .26 Figure 11, PORTC GPIO Structure (1-Bit) .28 Figure 12, MAX1780 MAX1780 Timers.30 Figure 13, MAX1780 MAX1780 Interrupt Structure.32 Figure 14, Peripheral Interrupt Control Registers .33 Figure 15, Fuel Gauge Block Diagram .37 Figure 16, Data Acquisition Unit Block Diagram.44 Figure 17, Effective ADC Resolutions.48 Figure 18, Temperature Conversion Bit Weights.51 Figure 19, Overcurrent Comparator Functional Diagram .52 Figure 20, High-Voltage Output Port.55 Figure 21, High-Speed SPI Port.57 Figure 22, SMBus Interface Block Dia gram .60 Figure 23, SMBus Configuration Register .65 Figure 24, SMBus Status And Mask Registers.68 Figure 25, SMBus SLOV Register .70 Figure 26, External EEPROM Interface Schematic.71 Figure 27, Proper Series Cell Connections .72 Figure 28, Overcurrent Comparator System Diagram.75 Figure 30, Layout Recommendation For Current Sense Inputs.76 Figure 31, MAX1780 MAX1780 Software Shutdown Procedure .77 Figure 32, Shutdown Recovery Procedure .78 Figure 33, MAX1780 MAX1780 Safety Signal Circuit .79 Figure 34, MAX1780 MAX1780 Application Circuit .82 Figure 35, SPI Interface Timing .88 Figure 36, SMBus Timing Diagram .89 Figure 37, SPI Interface Timing (TA = -40°C to +85°C).94 Figure 38, SMBus Timing Diagram (TA = -40°C to +85°C) .95 Figure 39, Typical ADC Voltage Measurement Error.98 Figure 40, SHDN Input Bias Current vs. VSHDN .99 Figure 41, VAA Output Voltage vs. Load Current and Temperature.99 Figure 42, Fuel Gauge Frequency vs. Input Voltages Near Zero.100 Figure 43, Fuel Gauge Frequency vs. Input Voltage .101 Figure 44, Discharge Gain Error vs. Fuel Gauge Input Voltage .101 Figure 45, Charge Gain Error vs. Fuel Gauge Input Voltage .101 Figure 46, Simplified Notebook Computer Power Supply System .103 Figure 47, Typical Smart Battery Pack Implemented With The MAX1780 MAX1780 .104 6 Advanced Smart Battery Pack Controller Table Of Tables Table 1, Overdischarge Logic Truth Table .53 Table 2, Overcharge Logic Truth Table .53 Table 3, SMBus AC Characteristics .91 Table 4, SMBus DC Characteristics .91 Table 5, SMBus AC Characteristics (TA = -40°C to +85°C).97 Table 6, SMBus DC Characteristics (TA = -40°C to +85°C).97 7 Advanced Smart Battery Pack Controller List Of Applicable Documents "System Management Bus Specification", Revision 1.1, dated December 11, 1998. "Smart Battery Data Specification", Revision 1.1, dated December 11, 1998. "MAX1780 MAX1780 ROM Code Supplement", (Contact the Factory for availability) "MAX1780 MAX1780 Programmers Reference Manual", (Contact the Factory for availability) 8 Advanced Smart Battery Pack Controller Architectural Overview Introduction The MAX1780 MAX1780 Advanced Smart Battery Pack Controller was designed to provide Smart Battery pack designers with a flexible solution that accurately measures individual cell characteristics. I combines an 8 RISC t -bit microprocessor core, program and data memory, with an arsenal of precision analog peripherals. Together with an external serial EEPROM, the MAX1780 MAX1780 provides the most integrated solution for developing battery pack electronics in the industry. Harvard Architecture The MAX1780 MAX1780 uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. A 12-bit wide program memory bus fetches a 12-bit instruction in a single cycle. The 12-bit wide instruction opcodes make it possible to have all single word instructions. Program Address (12 bits) Program Memory Register Address (8 bits) CPU Instruction (12 bits) Data (8 bits) SpecialPurpose Registers + Data Memory + Peripherals Figure 1, MAX1780 MAX1780 Harvard Architecture The MAX1780 MAX1780 addresses 2K x 12 of internal program memory, organized as three blocks of ROM, each 512 x 12, and one program RAM block 512 x 12. Using special ROM routines (see MAX1780 MAX1780 ROM Supplement for details), the MAX1780 MAX1780 can access up to 64K x 8 of external serial EEPROM memory. This provides software designers with the ability to load program code residing in external EEPROM into program RAM under program control. This innovative capability can be used to develop self-adapting battery management and control software. Figure 2 shows a block diagram of the MAX1780 MAX1780 core microcontroller. MAX1780 MAX1780 memory is organized into program memory and data memory. Program memory pages are accessed using one or two STATUS register bits. Data memory is composed of RAM, organized as 8, 16 byte groups or pages. Collectively, all of the DRAM pages are called the Register File. The register file is divided into two functional groups: special function registers and general purpose registers. DRAM is accessed using the File Selection Register (FSR). The special function registers include the TIMERA Register, the Program Counter (PC), the Status Register, the SETUPINT Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The General Purpose registers are used for data and control information under command of the instructions. PORTB is used as a dedicated internal interface between the processor core and all the on-board peripherals. Most of the on-board peripherals function autonomously, generating interrupts to the processor core when service is required. 9 Advanced Smart Battery Pack Controller OSC1 12 9 8 32KHz OSCILLATOR LINEAR REGULATOR WATCHDOG TIMEOUT PHASE GENERATOR INTERRUPT & SLEEP LOGIC 12 PROGRAM COUNTER MCLR\ CLK INSTRUCTION OSCILLATOR RUN 8-LEVEL STACK OSC2 RESET TIMER B PROGRAM MEMORY ROM (1536x12) RAM (512x12) 8 TIMER B OVERFLOW 3 12 OPTION REGISTER FROM W REGISTER INTERNAL DATA BUS (8-bits) 8 5 8 TIMER A LOW BYTE FSR 8 TIMER A HIGH BYTE 8 8 136 x 8 STATIC RAM REGISTER FILE 7 LITERALS "W" REGISTER TIMER A OVERFLOW 8 INSTRUCTION DECODER TIMER A CONTROL IO4/TMRA 8 12 INSTRUCTION REGISTER 8 8 ARITHMATIC LOGIC UNIT 8 8 INTERNAL DATA BUS (8-bits) PORT A PORT B PORT C 8 2 I/O 8 INT2&3 2 2 DATA STATUS REGISTER ADDRESS 8 CONTROL 8 ON-BOARD PERIPHERALS Figure 2, MAX1780 MAX1780 Block Diagram 10 Advanced Smart Battery Pack Controller Detailed Description Of MAX1780 MAX1780 Instruction Execution The MAX1780 MAX1780 processor core incorporates a two-stage pipeline. The instruction fetch and execution are pipelined such that an instruction fetch takes one instruction cycle while the instruction decode and execution takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change, for example a GOTO instruction, then two cycles are required to complete the instruction, breaking the pipeline's flow. Figure 3 shows how instruction pipelining increases the processor throughput. CYCLE 1 CYCLE 2 Fetch 1 st Instruction Execute 1 st Instruction Fetch 2 nd Instruction CYCLE 3 CYCLE 4 Execute 2 nd Instruction Fetch 3 rd Instruction Execute 3 rd Instruction Fetch 4th Instruction Figure 3, MAX1780 MAX1780 Instruction Pipeline 11 Advanced Smart Battery Pack Controller Phase Clocks As shown in Figure 4, an Instruction Cycle consists of four phase clocks. The phase clocks do not overlap, and each phase transition occurs on the rising edge of the Instruction Oscillator. Phase 0 (PH0) is called the Decode Phase, where fetched instructions are decoded. Phase 1 (PH1) is known as the Data Read Phase. Any data from Data Memory required to complete the instruction will be read at this time. Phase 2 (PH2) is called the Process Phase, in which any data retrieved in PH1 is processed. The final phase, Phase 3 (PH3), is the Data Write Phase and is used to write data manipulated during PH2 back to Data Memory. (n - 1) INSTRUCTION CYCLE (n) (n + 1) INSTOSC PH0 PH1 PH2 PH3 Instruction Decode Instruction Read Data Process Data Figure 4, Instruction Cycle Phase Clocks 12 Instruction Write Data Advanced Smart Battery Pack Controller 12 Program Counter Data Bus 12 Program ROM 0 0x000 - 0x1FF 512 x 12 Program RAM 0x200 - 0x3FF 512 x 12 Program Stack 0 Program Stack 1 Program ROM 1 0x400 - 0x5FF 512 x 12 Program Stack 2 Program ROM 2 0x600 - 0x7FF 512 x 12 Program Stack 5 Program Stack 6 OPTION Register SETUPINT Register Data Registers 136 x 8 Timer A & B Ports A, B, C Program Stack 4 ADDR Program Stack 3 MUX Program Stack 7 DATA STATUS Register Instruction Bits [0.7] DATA Data Bus FSR Register Instruction Register Explicit Data MUX Instruction Decoder ALU Flags Z C DC "W" Register Figure 5, MAX1780 MAX1780 Programming Model CPU Architecture Figure 5 shows the MAX1780 MAX1780's central processing unit (CPU) architecture. As shown, instructions in program memory and variables in data memory are accessed using separate buses Program Counter (PC) As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. It should be noted that all subroutine calls are limited to the first 256 locations of any program memory page (512 words long). Program Stack The MAX1780 MAX1780 has a 12-bit wide, eight-level hardware stack. This allows program developers to create code with nested subroutine calls. When CALL instructions are executed, pushing the current value onto the stack saves the processor context. A word of caution, the MAX1780 MAX1780 program stack has only 8-levels. Programmers should not create code that has unlimited nesting of subroutine calls, or a stack overflow is possible. 13 Advanced Smart Battery Pack Controller A subroutine call is completed with a RETURN or RETLW instruction, both of which will pop the contents of the stack into the program counter. The RETLW instruction also loads the "W" Register with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. Arithmetic Logic Unit (ALU) The MAX1780 MAX1780 CPU contains an 8-bit ALU and working register. The ALU is a general-purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logic al operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the "W" (working) Register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W Register or a file register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. Working Register ("W") The "W" Register serves as an accumulator or temporary storage register for many instructions. The "W" Register is not directly accessible. Its contents must be moved to other registers that are directly accessible, in order to be read. The "W" Register is also used in every arithmetic operation. 14 Advanced Smart Battery Pack Controller Option Register (Write Only, via the "W" Register and OPTION Instruction) The Option Register is a CPU core register. It is not directly accessible and is not in the Register File address space. To change the contents of the Option Register, use the OPTION instruction, which loads the contents of the "W" Register into the Option Register. Through the Option Register the user has access to the Timer A and Timer B controls. Additionally, whether the Instruction Oscillator runs in SLEEP Mode or not may be selected. Since the contents of the Option Register cannot be read, it is suggested that programmers "shadow" its contents in a global software variable, and all changes be made to the global variable. The global variable is then moved to the "W" Register and an OPTION Instruction executed to affect changes in the Option Register. Bit 7 OSLB 0 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSLB POR STATE Bit 6 TMRAD TAS1 TAS0 MSKW PS2 PS1 PS0 1 1 1 1 1 1 1 1 The Internal Instruction Execution Oscillator Is Turned off During SLEEP Mode. INTOSC OFF in SLEEP. (See note below) The Internal Instruction Execution Oscillator Runs During SLEEP Mode. INTOSC ON in SLEEP. TMRAD 0 1 Timer A (TMRA) Enabled Timer A (TMRA) Disabled TAS1 0 0 1 1 TAS0 0 1 0 1 MSKB 0 1 TIMER B (TMRB) overflow generates an interrupt if INTOFF = 0 (cleared in STATUS Register) TIMER B (TMRB) overflow does not generate an interrupt TMRA increments count on the falling edge of IO4/TMRA pin TMRA increments count on the rising edge of IO4/TMRA pin TMRA increments count on the rising edge of the 32KHz Clock TMRA increments count on rising edge of INTOSC/4 PS2 PS1 PS0 0 0 0 TMRB period = (1/32KHz) * 256 * 2 0 0 1 TMRB period = (1/32KHz) * 256 * 4 0 1 0 TMRB period = (1/32KHz) * 256 * 8 0 1 1 TMRB period = (1/32KHz) * 256 * 16 1 0 0 TMRB period = (1/32KHz) * 256 * 32 1 0 1 TMRB period = (1/32KHz) * 256 * 64 1 1 0 TMRB period = (1/32KHz) * 256 * 128 1 1 1 *FACTORY USE ONLY (DO NOT USE) Note: The instruction oscillator will continue to run in SLEEP while an SMBus Slave progress. 15.62 ms 31.25 ms 62.50 ms 125.0 ms 250.0 ms 500.0 ms 1.0 sec transmission is in 15 Advanced Smart Battery Pack Controller Setupint Register (Write Only, via the "W" Register and FREE Instruction) The Setupint Register is a CPU core register. It is not directly accessible and is not in the Register File address space. To change the contents of the Setupint Register, use the FREE instruction with FSR bits 5 and 6 cleared to `0', which loads the contents of the "W" Register into the Setupint Register. The Setupint Register is used to set-up the triggering characteristics of the MAX1780 MAX1780's three interrupt channels. Additionally, Bit 0 is the global enable bit for addressing the on-board peripherals. Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SENSE3 SENSE2 SENSE1 EN1SN EDGE3 EDGE2 EDGE1 PADDR 1 POR STATE Bit 6 1 1 1 1 1 1 1 Interrupt 3 EDGE3 SENSE3 0 0 1 1 0 1 0 1 IF3 Flag in the PORTA Register is set to `1' when INT3 = `0'. IF3 Flag in the PORTA Register is set to `1' when INT3 = `1'. IF3 Flag in the PORTA Register is set to `1' on a Falling Edge of INT3. IF3 Flag in the PORTA Register is set to `1' on a Rising Edge of INT3. Note: The Peripheral Interrupt Controller uses INT3 for interrupts. There are total of 8 INT3 interrupt sources: POWER FAILURE, FGCHGSTAT, ADCDONE, DETECT, OCICMP, ODICMP, FGCHGOFL, FGDISOFL. Interrupt 2 EDGE2 SENSE2 0 0 1 1 0 1 0 1 IF2 Flag in the PORTA Register is set to `1' when INT2 = `0'. IF2 Flag in the PORTA Register is set to `1' when INT2 = `1'. IF2 Flag in the PORTA Register is set to `1' on a Falling Edge of INT2. IF2 Flag in the PORTA Register is set to `1' on a Rising Edge of INT2. Note: The SMBus Interface uses INT2 for interrupts. There are a total of 7 INT2 interrupt sources: START, RESTART, STOP, SCLHOLD, TOUT, MSTON, ACK. Interrupt 1 EN1SN EDGE1 SENSE1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Do not clear the EN1SN bit to `0'. Do not clear the EN1SN bit to `0'. Do not clear the EN1SN bit to `0'. Do not clear the EN1SN bit to `0'. IF1 Flag in the PORTA Register is set to `1' when the IO7/INT1 pin = `0'. IF1 Flag in the PORTA Register is set to `1' when the IO7/INT1 pin = `1'. IF1 Flag in the PORTA Register is set to `1' on an IO7/INT1 Falling Edge. IF1 Flag in the PORTA Register is set to `1' on an IO7/INT1 Rising Edge. Note: Do not clear the EN1SN bit to `0', otherwise this could result in a constant interrupt from INT1. Peripheral Address Bit PADDR D0 This bit must be set to `1' to enable access to on-board peripherals. Note: This bit defaults to `1' on Power-On -Reset. Do not change or the on-board peripherals cannot be addressed. 16 Advanced Smart Battery Pack Controller Memory Organization: The MAX1780 MAX1780 program memory is divided into four blocks 512 x 12-bits in size. Each block is further divided into 256 x 12-bits upper and lower pages. The first, third, and fourth blocks are Program ROM, which are programmed at the factory. The second memory block is Program RAM, which is loaded with user code at boot, and can be modified during operation. 0x000 PROGRAM ROM 0 LOWER PAGE 0x0FF 0x100 PROGRAM ROM 0 UPPER PAGE 0x1FF 0x200 PROGRAM RAM LOWER PAGE 0x2FF 0x300 PROGRAM RAM UPPER PAGE 0x3FF 0x400 PROGRAM ROM 1 LOWER PAGE 0x4FF 0x500 PROGRAM ROM 1 UPPER PAGE 0x5FF 0x600 PROGRAM ROM 2 LOWER PAGE 0x6FF 0x700 PROGRAM ROM 2 UPPER PAGE 0x7FF Figure 6, MAX1780 MAX1780 Program Memory Organization Page Boundaries The Page Preselect bits (PA0 ­ PA1) of the STATUS Register determine which 512 x 12 page of program memory the MAX1780 MAX1780 CPU fetches instructions from. They are mapped as: Program Memory Selection: PA2 X X X X PA1 0 0 1 1 PA0 0 1 0 1 Address Range 0x000 ­ 0x1FF 0x200 ­ 0x3FF 0x400 ­ 0x5FF 0x600 ­ 0x7FF Memory Selected ROM (512 WORDS) RAM (512 WORDS) ROM (512 WORDS) ROM (512 WORDS) Each instruction cycle causes the Program Counter to increment, which in turn, increments the address in program memory from where instructions are fetched. Program flow within a 512 x 12 page is controlled by GOTO and CALL instructions. GOTO instructions provide 9 bits of address for the Program Counter, so program control can be transferred to any memory address within a page. The CALL instruction on the other 17 Advanced Smart Battery Pack Controller hand, supplies the Program Counter with only 8 bits of address. This limits jumps by the CALL instruction to the lower half of the memory page selected by the Page Preselect Bits (PA0 ­ PA1). The Page Preselect Bits have no effect on program flow until a CALL or a GOTO instruction is executed. If the Program Counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. However, the Page Preselect bits in the STATUS register will not be updated. Therefore, the next GOTO or CALL instruction will send the program to the page specified by the Page Preselect bits (PA1:PA0). For example, a NOP at location 1FFh (page 0) increments the PC to 200h (page 1). A GOTO xxx at 200h will return the program to address 0xxh on page 0 (assuming that PA1:PA0 are clear). To prevent this, the page presele ct bits must be updated under program control. Indirect Data Addressing; INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. The FSR is an 8-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR [4:0] bits are used to select data memory addresses 0x00 to 0x1F. 18 Advanced Smart Battery Pack Controller Register File Organization Data RAM The MAX1780 MAX1780 has 144 bytes of read/writable Data Memory. It is organized as follows: 8 8 128 Special Purpose Register Files (Page Independent) General Purpose Registers (Page Independent) General Purpose Registers (Page Dependent) The FSR Register (bits 5 ­ 7) is used to select the desired data memory block. As shown in Figure 7 below, the special purpose registers and first 8 general purpose registers (0x00 ­ 0x0F) are shadowed across all eight Data RAM blocks. For this reason, the contents of these registers are accessible regardless of which memory block is selected by FSR bits 5 ­ 7. Data stored in this area is referred to as "Page Independent" memory. Selecting the appropriate FSR bits allow access to data residing in the upper 16 bytes of each block. Data stored in this area is referred to as "Page Dependent" memory. FSR [ 7:5 ] 000 0x00 INDF TIMERA (LB) 001 0x20 INDF TIMERA (HB) 010 0x40 INDF TIMERA (LB) 011 0x60 INDF 100 0x80 TIMERA (HB) INDF TIMERA (LB) 101 0xA0 INDF TIMERA (HB) 110 0xC0 INDF TIMERA (LB) 111 0xE0 INDF TIMERA (HB) PC PC PC PC PC PC PC PC STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS FSR FSR FSR FSR FSR FSR FSR FSR PORTA PORTA PORTA PORTA PORTA PORTA PORTA PORTA PORTB PORTB PORTB PORTB PORTB PORTB PORTB PORTB PORTC PORTC PORTC PORTC PORTC PORTC PORTC PORTC GPR (8 Bytes) GPR (8 Bytes) GPR (8 Bytes) GPR (8 Bytes) GPR (8 Bytes) GPR (8 Bytes) GPR (8 Bytes) GPR (8 Bytes) 0x08 0x0F 0x2F 0x4F 0x6F 0x8F 0xAF 0xCF 0xEF 0x10 0x30 0x50 0x70 0x90 0xB0 0xD0 0xF0 GPR (16 Bytes) 0x1F BLOCK 0 GPR (16 Bytes) 0x3F BLOCK 1 GPR (16 Bytes) 0x5F BLOCK 2 GPR (16 Bytes) 0x7F BLOCK 3 GPR (16 Bytes) 0x9F BLOCK 4 GPR (16 Bytes) 0xBF BLOCK 5 GPR (16 Bytes) 0xDF BLOCK 6 GPR (16 Bytes) 0xFF BLOCK 7 Figure 7, DRAM Organization 19 Advanced Smart Battery Pack Controller File Select Register (FSR) Read/Write The File Select Register selects which page of Data Memory can be accessed. Bit 7 Bit7 0 0 0 0 1 1 1 1 Bit6 0 0 1 1 0 0 1 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X POR STATE Bit 6 X X X X X X X Bit5 0 1 0 1 0 1 0 1 GPR SELECTED GPR Page/Block 0 - TIMERA Low Byte selected. GPR Page/Block 1 - TIMERA High Byte selected. GPR Page/Block 2 - TIMERA Low Byte selected. GPR Page/Block 3 - TIMERA High Byte selected. GPR Page/Block 4 - TIMERA Low Byte selected. GPR Page/Block 5 - TIMERA High Byte selected. GPR Page/Block 6 - TIMERA Low Byte selected. GPR Page/Block 7 - TIMERA High Byte selected. Bit4 0 Page Independent/Dependent Selection Page independent Data Memory (lower 16 bytes of each Page/Block) is accessed. The lower 16 bytes of Page/Block 0 are shadowed across the other 7 page/blocks regardless of the selection of FSR bits 5 ­ 7. 1 Page dependent Data Memory (upper 16 bytes of each Page/Block) is accessed. Selecting bits 5 ­ 7 of the FSR accesses a Page/Block. Selecting FSR bits 0 - 3, accesses individual bytes within a Page/Block. Selection of Register File or Data RAM Bit3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 20 Bit2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data RAM Location 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Advanced Smart Battery Pack Controller Status Register (Read/Write) The Status Register contains the arithmetic status of the ALU, TMRB overflow status, the global interrupt enable/disable bit, and the Page Preselect bits for selecting from which page of program memory program code will be fetched. The Status Register can be the destination for any instruction. If the Status Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA2 POR STATE Bit 6 PA1 PA0 TMRBF INTOFF Z DC C 0 0 0 0 1 X X X Type ROM RAM ROM ROM Length 512 WORDS 512 WORDS 512 WORDS 512 WORDS PA2 PA1 PA0 Memory Range Selected X 0 0 0x000 ­ 0x1FF X 0 1 0x200 ­ 0x3FF X 1 0 0x400 ­ 0x5FF X 1 1 0x600 ­ 0x7FF Note: PA2 is not implemented but can be used as storage. TMRBF 0 1 TIMER B overflow flag CLEARED TIMER B overflow flag SET INTOFF 0 Enable Global Interrupts 1 Disable Global Interrupts Z 0 1 Arithmetic or Logic Operation Results is NOT Zero Arithmetic or Logic Operation Results is Zero DC 0 No CARRY from Bit3 to Bit4 1 CARRY from Bit3 to Bit4 Note: Effected only by ADDWF & SUBWF Instructions C 0 1 No CARRY from Bit7 (MSB). When no CARRY generated in Addition, or when subtraction result is negative. CARRY from Bit7 (MSB). When CARRY is generated in Addition, or when subtraction result is zero or positive. 21 Advanced Smart Battery Pack Controller Modes Of Operation The MAX1780 MAX1780 has four modes of operation: 1. Shutdown ( SHDN = Low) 2. Sleep 3. Master Clear ( MCLR = Low) 4. Operate (Program Execution) Shutdown In shutdown mode, the MAX1780 MAX1780 consumes practically no current. This mode is useful for reducing the selfdischarge of battery packs in transit to customers or being stored for long periods. Entering Shutdown To enter shutdown mode, the SHDN pin should be grounded. When the voltage on the SHDN pin falls below 0.4V, the MAX1780 MAX1780 will enter a very low power (typically 1nA) consumption mode. Recovering From Shutdown To recover from shutdown mode, the SHDN pin should be connected to the BATT pin through a 3Megohm resistor. After the voltage at the SHDN pin has risen to a level greater than 2.2V, the MAX1780 MAX1780 will Power On Reset (POR) and begin to execute code. Sleep In sleep mode, instruction execution is suspended. The internal instruction oscillator may be on or off in sleep mode depending on the contents of the OSLB bit (D7) of the Option Register. The internal instruction oscillator turns on whenever sleep mode is exited regardless of the condition of the OSLB bit. Entering Sleep Mode Executing a SLEEP instruction enters sleep Mode. Wake-Up From Sleep Mode The MAX1780 MAX1780 can wake up from SLEEP through one of the following events: 1. An external reset input on the MCLR pin. 2. A Watchdog time-out. 3. An interrupt from any enabled source will wake up the MAX1780 MAX1780, regardless of the state of the INTOFF bit in the STATUS Register. Master Clear Placing a logic level LOW on the MCLR pin will cause the MAX1780 MAX1780 to reset all its internal logic circuitry. While MCLR is LOW all program execution is halted. Additionally, all GPIO pins are high-impedance, and the CHG and DIS pin drivers will rise to VBATT, opening both pack protection MOSFETs. Releasing the logic LOW on the MCLR pin, allowing it to rise to VDD, will allow the processor core to boot and begin program execution. Operate (Program Execution) Whenever instructions are executing, the MAX1780 MAX1780 is in operate mode. 22 Advanced Smart Battery Pack Controller Analog And Mixed Signal Peripheral Interface The MAX1780 MAX1780 integrates an arsenal of analog and mixed signal peripheral devices. The processor core communicates with these on-board peripherals through PORT B, as shown in Figure 8. PORT A INT3 PORT B INT 2 FROM CPU CORE ADDRESS 8 ODI DATA 8 READ WRITE REF OUT OCI ODI/OCI COMPARATORS + OSCD4 MCLR READ WRITE PFW TIMERA_OVFL ANALOG REFERENCE INT DIS ADDRESS 8 DATA CHG 8 OUT ADDRESS ADDRESS 8 8 8 8 DATA DATA READ READ WRITE INTERRUPT CONTROL REGISTER WRITE OSCD4 OSCD4 B4P MCLR PFW DATA ACQUISITION UNIT MCLR PFW B2P B1P BN DATA ADDRESS INTERRUPTS CONTROL TIMERA_OVFL INT INT0 - INT7 B3P ADDRESS 8 DATA 8 READ WRITE HIGH VOLTAGE OUTPUT HV[0.7] PORT READ WRITE CS+ FUEL GAUGE OSCD4 MCLR PFW TIMERA_OVFL CS- - INT AGND ADDRESS 8 DATA 8 ADDRESS ADDRESS 8 8 8 8 DATA DATA READ SCLK SPI WRITE SO INTERFACE READ WRITE SI OSCD4 MCLR OSCD4 MCLR PFW SMBus INTERFACE SCL C SDA D PFW TIMERA_OVFL INT Figure 8, MAX1780 MAX1780 On-Board Peripherals 23 Advanced Smart Battery Pack Controller MAX1780 MAX1780 Power Supply Sequencing The MAX1780 MAX1780 incorporates both analog and digital circuitry, which each have an optimal power supply range. The digital circuitry can begin operating with VAA voltages as low as 2.7V, whereas the analog circuitry begins to operate at 3.0V. This means that the MAX1780 MAX1780 CPU can begin executing program code before it's analog peripherals have powered up. The MAX1780 MAX1780 uses two internal control signals, POR for the digital circuitry, and PFW for the analog circuitry, to determine if the VAA supply has reached a voltage level high enough for both the digital and analog circuitry to operate. Figure 9 illustrates the MAX1780 MAX1780 power supply sequencing. 3.6 3.5 OPERATION 3.4 3.2 INTERRUPT 3.1 3.0 2.9 2.8 RA M PU P VAA (Volts) 3.3 INTERRUPT 2.7 RA MP DO W N 2.6 2.5 POR PFW Digital Supply Turns ON Analog Supply Turns ON Analog Supply Turns OFF Digital Supply Turns OFF Figure 9, MAX1780 MAX1780 Power Supply Sequencing Whenever the VAA supply rises above, or falls below 3.0V an interrupt is generated. Please refer to the Peripheral Interrupt Control Register section for a detailed description of this interrupt. Immediately after power-up, the interrupt can be used to indicate that both the digital and analog supplies have reached a reliable voltage level for operation. Any interrupts that occur after the initial power-up sequence, could be an indication that the VAA supply has either momentarily fallen below 3.0V, or is powering off. 24 Advanced Smart Battery Pack Controller MAX1780 MAX1780 Special Purpose Port Registers Each port line can be individually programmed as an input or output. This is done by using a special purpose instruction TRIS, which matches a bit pattern with the port lines. Writing a `0' to a port line's TRIS Register configures this port line as an output. Conversely, setting a port line's TRIS Register to `1' configures the port line as an input. PORTA The MAX1780 MAX1780 PORTA[3:0] signal lines are not connected to external pins. The PORTA data latch is however read/writable, so bits 0 ­ 3 can be freely used as storage. PORTA Data Latch (Read/Write) Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IF3 POR STATE Bit 6 IF2 IF1 TMRAF PORTA3 PORTA2 PORTA1 PORTA0 0 0 0 0 1 1 1 1 IF3, IF2, IF1 are the Interrupt Flags for INT3, INT2, INT1 respectively. They will be set whenever there is a respective interrupt. TMRAF flag is set when there is a TIMERA overflow. PORTA TRIS Latch (Write Only) Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MA3 POR STATE Bit 6 MA2 MA1 MTMRA X X X X 1 1 1 1 1 1 1 1 MA3, MA2, MA1, MTMRA are the interrupts of INT3, INT2, INT1, TIMERA Enable Control. Writing a `0' to an individual bit will enable the respective interrupt. 25 Advanced Smart Battery Pack Controller PORTB PORTB is a special purpose port used to communicate with the on-chip peripherals. The address for a desired peripheral is written to the PORTB TRIS Latch, and the data is either written to or read from the PORTB Data Latch using a MOVF instruction. Care should be taken to properly protect Main Loop PORTB peripheral transactions from interrupt service routines that may also use PORT to communicate to peripherals. RESET D SET PERIPHERAL ADDRESS Q TRIS PORTB CLR Q I/O CONTROL LATCH VDD "W" REGISTER P INTERNAL DATA BUS D 7 D 6 D5 D4 D3 D2 D1 D0 P PERIPHERAL DATA MOVF PORTB, 0 N PERIPHERAL READ D SET Q MOVF PORTB, 1 PERIPHERAL WRITE CLR Q N OUTPUT DATA LATCH GND Figure 10, PORT B Structure (1 Bit) 26 RD\ WR\ ON-BOARD PERIPHERAL Advanced Smart Battery Pack Controller PORTB Data Latch (Read/Write) Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 POR STATE Bit 6 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 PORTB TRIS Latch (Write Only) Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A7 POR STATE Bit 6 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 1 1 1 1 Accessing The On-board Peripherals The MAX1780 MAX1780 processor core can access on-board peripherals provided that the Setupint Register PADDR bit D0 is set to `1'. The peripheral's address is first written to the PORT B TRIS latch. If a peripheral read is desired, then a MOVF instruction is executed to latch the peripheral bus data into the "W" Register. If a peripheral write is wished, then in addition to writing the peripheral's address to the PORT B TRIS latch, the data for the peripheral must be written to the PORT B DATA latch. The following code example shows how to read data from an on-board peripheral using the PORT B internal interface. Peripheral Read MOVLW ADDRESS TRIS Port_B MOVF Port_B,0 Load the peripheral's address in W register. Latches the address. Generates Read signal and returns peripheral INPUT data to the W register. Programming code for write operations is similar, except that two extra move instructions are required to latch the data sent to the PORT B peripheral. Peripheral Write MOVLW TRIS MOVLW MOVWF MOVF ADDRESS Port_B DATA Port_B Port_B,1 Load the peripheral's address in W register. Latches the address. Load Peripheral's data in W register. Puts Data Into B For Output. Generates Write signal and sends OUTPUT data to the peripheral. 27 Advanced Smart Battery Pack Controller PORTC (IO0 ­ IO7) Port C shares duty as a general-purpose I/O (GPIO) port and SPI interface. Bits IO0, IO1, and IO2 are used exclusively in normal operation by the high-speed SPI interface. Bit IO3, under software control, is used for the SPI CS\ signal. Bit IO4, when configured as an input, can be used to increment Timer A. Bit IO7 shares use as an external input to the INT1 interrupt. Bits IO5 and IO6 are free GPIOs. "W" REGISTER D7 D6 D5 D 4 D3 D2 D1 D0 VDD D SET Q PORTC WRITE INTERNAL DATA BUS CLR Q P DATA LATCH I/O PIN D SET Q TRIS PORTC CLR N Q TRIS LATCH PORTC READ GND Figure 11, PORTC GPIO Structure (1-Bit) PORTC GPIO Operation The equivalent circuit for one of the PORTC GPIO port pins is shown in Figure 11. PORTC, IO0 - IO7 may be used for both input and output operations. For input operations PORTC is non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTC, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a PORTC I/O pin as output, the corresponding direction control bit in TRIS latch must be cleared. For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output. The TRIS latch is loaded with the contents of the "W" Register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The TRIS registers are "write-only" and are set (output drivers disabled) upon RESET. 28 Advanced Smart Battery Pack Controller Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. At power-on-reset, all port lines are tri-stated. All unused port lines should be tied to VDD. Please refer to the MAX1780 MAX1780 Electrical Characteristics and Absolute Maximum Ratings when connecting the I/O port lines to external circuitry. I/O Programming Considerations Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit-7 of PORTC will cause all eight bits of PORTC to be read into the CPU, bit-7 to be set and the PORTC value to be written to the output latches. If another bit of PORTC is used as a bidirectional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. For this reason, it is good programming practice to "shadow" the PORTC data latch. This involves maintaining a copy of the PORTC data latch contents in a data RAM location. Individual bits are set by first "OR-ing" the desired bits with the PORTC data latch copy, and then moving the latch copy to the PORTC latch. Likewise, individual port bits can be cleared by "AND-ing" the reciprocal of the desired bits with the PORTC data latch copy, followed by a move to the data latch. PORTC Data Latch Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IO7 INT1 IO6 IO5 IO4/ TMRA IO3 (CS\) IO2/ SI IO1/ SO IO0/ SCLK 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRIS7 POR STATE Bit 6 TRIS6 TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 1 1 1 1 1 1 1 1 PORTC TRIS Latch POR STATE 29 Advanced Smart Battery Pack Controller Timers And Watchdog Figure 12 below shows the organization of Timer A, Timer B, and the Watchdog Timeout circuitry. "W" REGISTER 8 8 OPTION COMMAND OPTION REGISTER D6 D5 D4 D3 TMRB OVERFLOW PRESCALER 1sec 2sec D D Q FF TIMER B (15-Bits) CLK Q Reset Q FF WATCHDOG TIMEOUT Q Reset CLRWDT Select 32KHz IO4/TMRA IO4/TMRA INTOSC/4 MUX CLK Start/Stop TMRA OVERFLOW TIMER A (16-Bits) 8 INTERNAL DATA BUS (8-Bits) Mask D2 D1 D0 FSR Bit 5 8 HB/LB 8 8 TIMER A REGISTER (HB) REGISTER SELECT 8 TIMER A REGISTER (LB) Figure 12, MAX1780 MAX1780 Timers Timer A (TMRA) TMRA is a general-purpose 16-bit ripple counter that can be configured to use one of four clock sources, IO4/TMRA pin rising edge, IO4/TMRA pin falling edge, 32KHz oscillator rising edge, or the rising edge of the instruction oscillator divided by four. Setting the TAS0 and TAS1 bits in the Option Register selects the clock source. When either the 32KHz oscillator or IO4/TMRA pin clock the timer, the timer operates asynchronously of the MAX1780 MAX1780 processor core. This means that the timer can count events even when the CPU core is in sleep mode, as it does not need the instruction oscillator to count. The user can enable Timer A by clearing the TMRAD bit in the Option Register. To disable Timer A, set the TMRAD bit in the Option Register. When TMRA overflows, the ITMRA flag in the Status Register is set and an interrupt will be generated. This flag should be cleared by the TMRA interrupt service routine. If the MAX1780 MAX1780 CPU is in SLEEP mode when a TMRA overflow occurs, it will wake-up the CPU. Timer B (TMRB) Timer B is a 15-bit ripple counter permanently attached to the 32KHz crystal oscillator. It has a 3-bit prescaler to divide the oscillator down to obtain timer periods between 15.625msec and 1sec. The prescaler can be adjusted by writing to bits PS0 through PS2 in the Option Register and executing an OPTION instruction. If the MSKB bit in the Option Register is cleared, each time the TMRB period is exceeded (overflows), an interrupt is generated and the TMRBF flag in the Status Register is set. The TMRB interrupt service routine should first, 30 Advanced Smart Battery Pack Controller execute a CLRTI instruction and then clear the TMRBF flag. If the MAX1780 MAX1780 CPU is in SLEEP mode when a TMRB overflow occurs, it will wake-up the CPU. TMRB is a logical choice for creating an accurate real-time clock that generates recurring interrupts at a desired period. Watchdog Timer (WDT) The primary function of the Watchdog Timer is to be a failsafe method for recovering from programs that are stuck in an endless loop, or may have inadvertently corrupted the stack. When a Watchdog timeout occurs, the MAX1780 MAX1780 microcontroller core is reset and the entire boot-up process is repeated. Figure 12 shows the Watchdog Timer and how i is derived from Timer B. Timer B is a free running 16-bit ripple counter, and is t clocked by the 32KHz oscillator. Timer B reaches its maximum count each second, and will overflow, setting the flip-flop connected to its output. If the flip-flop is not cle ared, by executing a CLRWDT instruction, by the time Timer B overflows again (2 seconds), the second flip-flop toggles, resulting in a reset of the MAX1780 MAX1780. The Watchdog timeout is held off or cleared by executing a CLRWDT instruction before the Watchdog's timer period has expired. Good programming practice will insure that CLRWDT instructions are properly distributed to prevent a Watchdog timeout in normal operation. A word of caution, executing the SLEEP or OPTION instructions does NOT clear the watchdog timeout. 31 Advanced Smart Battery Pack Controller Interrupts Description The MAX1780 MAX1780 CPU interrupt structure is depicted in Figure 13 below. All interrupts vector program execution to memory address 0x0200. All interrupts have the same priority. The first interrupt input (INT1) is connected to pin IO7, and may be used by external circuitry. The second interrupt input (INT2), is used exclusively by the SMBus Interface. Within the SMBus Interface, there are multiple interrupt sources. Please refer to the SMBus section of this document for details. The third interrupt input (INT3), is driven by the Peripheral Interrupt Controller. This block has mask and status registers for eight peripheral interrupt sources. Please refer to the Peripheral interrupt Controller section for details. OVFL INT1 INT2 TIMER A & B IO7 PIN SMBus Interface MAX1780 MAX1780 PROCESSOR CORE POWER FAIL FG DIRECTION ADC DONE INT3 Peripheral Interrupt Controller DETECT PIN OVERCHARGE OVERDISCHARGE FG CHG OVERFLOW FG DIS OVERFLOW Figure 13, MAX1780 MAX1780 Interrupt Structure 32 Advanced Smart Battery Pack Controller Peripheral Interrupt Control Registers The Peripheral Interrupt Control registers INTSTAT and INTREN funnel all of the on board peripheral interrupt sources to INT3 in the MAX1780 MAX1780 core. The only exceptions are the interrupts generated by the SMBus Interface, which are routed to INT2. The INTSTAT Register latches the interrupt events so that they can provide status, which can be read at any time. The INTREN Register is provided to enable or disable interrupts to INT3. Please note that even though a particular interrupt can be disabled (masked) by clearing the appropriate bit in the INTREN Register, the associated interrupt flag in the INTSTAT Register will still be set when the interrupt occurs. Figure 14 shows the INSTAT and INTREN registers, and how they interact to provide interrupt control and status. PFW FGDIR ADCDONE DETECT L A T C H PORTB PERIPHERAL BUS CLR OCINT ODINT FGCHGOVFL FGDISOVFL D7 D6 D5 D4 D3 D2 D1 D0 8 INTSTAT REGISTER Write '1' to Status bit to Clear the Interrupt D7 D6 D5 D4 D3 D2 D1 D0 8 INTREN REGISTER OR INT3 Figure 14, Peripheral Interrupt Control Registers Interrupt Status Register (INTSTAT) Operation The Interrupt Status Register latches interrupt events from 8 peripheral sources. When a peripheral interrupt occurs, the corresponding bit in the INTRSTAT Register will be set. It can be read through the PORTB Interface any number of times without affecting the state of the status flags. This is true regardless of the interrupt enable register settings. Writing a `1' to a particular bit in the interrupt status register will clear the interrupt status corresponding to that bit. 33 Advanced Smart Battery Pack Controller Interrupt Enable Register (INTREN) Operation The Interrupt Enable Register (INTREN) controls which peripheral interrupt sources will trigger Interrupt 3 (INT3) in the MAX1780 MAX1780 CPU. The register values can be read through the PORTB Interface any number of times without affecting their state. The Interrupt Enable Register bits will be cleared to `0' whenever MCLR is asserted low or a power on reset (POR) occurs. Clearing the bits in this register does not prevent the INTSTAT Register from latching peripheral interrupts that occur, this only masks them from INT3. Interrupt Control Register Descriptions INTSTAT Register (Read/Write): Bit D7 Name PFW PORTB Address = 0x0E POR 0 Function/Description Power Fail Warning. VAA Supply > 3V After POR, Or Has Fallen Below 3V During Operation. D6 FGDIR 0 Fuel Gauge Direction Change. D5 ADC 0 ADC conversion start and completion. D4 DETECT 0 A Rising Or Falling Edge On The DETECT Pin Has Occurred. D3 OCINT 0 Charge Current Limit Exceeded. D2 ODINT 0 Discharge Current Limit Exceeded. D1 FGCHGOVFL 0 Fuel Gauge Charge Counter Overflow. D0 FGDISOVFL 0 Fuel Gauge Discharge Counter Overflow. Note: The register is read to determine the interrupt status. To clear an interrupt, write a `1' to the bit that corresponds to the interrupt. INTREN Register (Read/Write): Bit D7 Name PFWMSK D6 FGDIRMSK 0 D5 ADCMSK 0 D4 DETMSK 0 D3 OCIMSK 0 D2 ODIMSK 0 D1 FGCHGMSK 0 D0 FGDISMSK 0 34 POR 0 PORTB Address = 0x0F Function/Description 0 ­ PFW Interrupt Masked. 1 ­ PFW Interrupt Enabled. 0 ­ FGDIR Interrupt Masked. 1 ­ FGDIR Interrupt Enabled. 0 ­ ADC Interrupt Masked. 1 ­ ADC Interrupt Enabled. 0 ­ DETECT Interrupt Masked. 1 ­ DETECT Interrupt Enabled. 0 ­ OCINT Interrupt Masked. 1 ­ OCINT Interrupt Enabled. 0 ­ ODINT Interrupt Masked. 1 ­ ODINT Interrupt Enabled. 0 ­ FGCHGOVFL Interrupt Masked. 1 ­ FGCHGOVFL Interrupt Enabled. 0 ­ FGDISOVFL Interrupt Masked. 1 ­ FGDISOVFL Interrupt Enabled. Advanced Smart Battery Pack Controller Analog Peripherals 3.5MHz Instruction Oscillator The MAX1780 MAX1780 contains an internal instruction execution oscillator that does not require an external crystal for operation. It is factory trimmed to 3.5MHz. In sleep mode the internal instruction oscillator can be turned off to save power. The internal oscillator is guaranteed to start up within 2 µs, minimizing interrupt latency. Any interrupt automatically exits sleep mode. The OSLB bit in the OPTION register controls whether or not the internal instruction oscillator is turned off in sleep mode. The internal instruction oscillator turns on whenever sleep mode is exited regardless of the condition of the OSLB bit. 32KHz Oscillator The 32KHz oscillator is used by several of the MAX1780 MAX1780 peripherals. It provides input clocks for TIMERA, TIMERB, the Data Acquisition Unit, and the Fuel Gauge. The oscillator requires only an external 32.768KHz watch crystal for proper operation. The 32KHz Oscillator is a Pierce-type crystal oscillator in which the output frequency is tuned by varying the total capacitance across the crystal's terminals. This capacitance is referred to as the "Load Capacitance" CL on crystal datasheets, and can vary depending on the manufacturer. Load Capacitance is calculated as follows: CL = C OSC + CPCB + C0 Where C y OSC is the MAX1780 MAX1780's on-chip load capacitance (2.5pF t pical), CPCB is PCB layout parasitic capacitance, and C0 is the shunt capacitance of the 32KHz watch crystal. For reliable oscillator start-up under worst-case conditions, insure that CL is less than 7pF. We do not recommend adding external capacitance to tune the oscillator frequency. Use caution when connecting an oscilloscope probe to OSC1, the 10pF scope probe capacitance is large enough to stop the 32KHz oscillator. Low Drop Out Linear Regulator The Low Drop Out Linear Regulator Unit regulates a 4V to 28V DC input voltage on the BATT pin, down to 3.4V. The 3.4V supplies the MAX1780 MAX1780 internal circuitry, and is available for external circuitry on the VAA output pin. Please note that for proper operation, the VAA and VDD pins must be connected as close as possible to the chip. The VAA output can supply 3.4V to external loads at up to 10mA. The Linear Regulator's current limit is typically 40mA. The VAA output should be bypassed with a 0.47µF capacitor to ground. 35 Advanced Smart Battery Pack Controller Precision Bandgap Reference The Precision Bandgap Reference provides 1.217V to the Data Acquisition Block. It is used internally and not brought out to a pin. The MAX1780 MAX1780 powers up with this reference shutdown and before attempting to make any measurements with the Data Acquisition Unit or Fuel Gauge, the user must write a `1' to bit D7 of the REFCONFIG Register. REFCONFIG Register (Write Only): Bit D7 Name REFON D6 D5 D4 D3 D2 D2 D2 RFU RFU RFU RFU RFU RFU RFU 36 POR 0 - Function/Description 0 = Reference OFF 1 = Reference ON Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 PORTB Address = 0x09 Advanced Smart Battery Pack Controller Mixed Signal Peripherals Fuel Gauge Unit General Description The Fuel Gauge measures the cumulative charge into (charging) and out of (discharging) the system battery pack and stores the information in one of two internal, independent charge and discharge counters. The unit also informs the host of changes in the direction of current flow. Communication with the Fuel Gauge is via Port B, and allows access to charge/discharge counters and internal registers. Features · True Coulomb Counting, Integrating Fuel Gauge · Separate 16-bit Charge and Discharge Counters · Counter Overflow and Current Direction Change Interrupts · 4 Counter Latching Sources · Automatic Cancellation Of Input Offset Voltage 8 8 FGCONFIG2 FGCONFIG1 Reference 8 8 Logic Control Interrupt DIS Latch Command ADC Start/Stop Timer A Overflow Timer B Overflow Synch CP A Charge Count (16-bits) CPB COMP 2.0 V 8 8 B4 8 FGCHGHIGH B3 REF/2 FGCHGLOW 8 B2 CINT B1 1.0 V Discharge Count (16-bits) RINT CS+ COMP AMP Analog Section 8 8 IBATT Chopper Stabilized 8 Peripheral Data Bus (8-bits) 2.0 V Interleaved Bidirectional Charge Pump CHG CS- FGDISHIGH 8 FGDISLOW Figure 15, Fuel Gauge Block Diagram 37 Advanced Smart Battery Pack Controller Automatic Cancellation Of Input Offset Voltage The MAX1780 MAX1780 Fuel Gauge uses a Chopper-Stabilized amplifier to couple the voltage across the current sense resistor to the Voltage-To-Frequency converter. This voltage, which can be a high as +/- 137.33mV at heavy load currents, can be only a few microvolts at light loads. Therefore, the amount of input offset voltage determines the minimum current sensitivity of the fuel gauge. The Chopper-Stabilized amplifier continually samples and corrects for its inherent offset. This cancellation occurs in conjunction with the Fuel Gauge's Coulomb counting circuitry. While the circuit is performing Fuel Gauge measurements, it is continually canceling the internal input offset voltage. The MAX1780 MAX1780 Fuel Gauge therefore, requires no software calibration. With careful attention to PCB layout, input offsets of less than 1µV can be expected. Coulomb Counting The Fuel Gauge's Coulomb counting circuit monitors the differential voltage present at the CS+ and CS- pins. In a typical application, the CS+ and CS- pins are connected across a sense resistor that is in series with the battery pack cells. This voltage is converted to a frequency proportional to the rate at which the current is flowing through the sense resistor, and the circuit counts Coulombs of charge by incrementing either the Charge Counter or the Discharge Counter accordingly. Charge And Discharge Counters Figure 15 shows the functional diagram of the Fuel Gauge's Coulomb-counter section. The Coulomb counter's output increments (but never decrements) one of two independent 16-bit counters: Charge Count for charging currents, and Discharge Count for discharging currents. By independently counting the charge and discharge currents, the Fuel Gauge can accommodate any algorithm to account for battery pack energy-conversion efficiency. The 16-bit Charge and Discharge Count latch registers are each div ided into 2 bytes: FGCHGLOW, FGCHGHIGH, FGDISLOW, and FGDISHIGH. See the Fuel Gauge Register Descriptions for details of the different registers. Charge Count and Discharge Count reset to zero whenever a power-on reset executes, or when the configuration word's FGCLRCHG FGCLRDIS bits are set. Use of the FGCLRCHG and FGCLRDIS bits to clear the fuel gauge counters is not recommended as part of a fuel gauging algorithm, as it is possible to loose counts during the clear operation. Each counter also resets any time an overflow condition occurs. When a counter overflows, it simply clears and begins counting from 0. Interrupts are generated on counter overflows unless they are masked by the FGCHGOVFL and FGDISOVFL bits in the Interrupt Controller INTREN register. Writing a one to the FGLATCHNOW bit in the Fuel Gauge's FGCONFIG2 Register latches the instantaneous counts for both the Charge and Discharge Counters without clearing the counters. The 16-bit charge count value can be obtained by reading the data in the FGCHLOW and FGCHGHIGH latch registers. Similarly, the Discharge Count can be obtained by reading the data in the FGDISLOW and FGDISHIGH registers. The gain factor is the constant of proportionality that relates the counter values stored in the Charge Count and Discharge Count registers to the amount of charge flow into or out of the battery pack. The electrical characteristics table specifies the maximum v-to-f converter frequency and the full-scale sense resistor voltage. With these two values the gain factor (FGGAIN) can be calculated as follows: Determining Fuel Gauge Gain: FG GAIN = 50 KHz 137.33 mV FGGAIN = 3.641 × 10 5 Hz V Multiplying the sense resistor value by the Gain Factor, the number of counter increments generated per Coulomb can be determined. 38 Advanced Smart Battery Pack Controller Determining Fuel Gauge Count Rate: Given: Count RCS = 0.020 RATE = RCS FGGAIN Count RATE = 7.282 × 10 3 Count C Therefore, a 20m current-sense resistor sets up a counter rate of 7.28 x 103 counts per Coulomb. A higher conversion gain (larger RCS) increases resolution at low currents, but limits the maximum measurable current. Likewise, a smaller conversion gain (smaller R ) decreases resolution at low c urrents, but increases the CS maximum measurable current. This provides a good balance between resolution and input current range for many applications. Calculating The Fuel Gauge "Bucket" Size: Given: RCS = 0.020 FGBUCKET_SIZE = 1 Count FGBUCKET_SIZE = 2.5 RATE 1 hr 1000 mA 65536 Count 3600 sec 1 A 1 Overflow mA hr Overflow The fuel gauge "bucket" size, which is the amount of energy necessary to overflow either the charge or discharge counters, is an integral factor in calculating a battery's remaining capacity. Knowing the amount of charge or discharge energy at each overflow interrupt, in milliamp-hours, makes updating the calculated battery remaining capacity as simple as adding and subtracting. In the example above, with RCS equal to 0.020, the fuel gauge charge or discharge counters will trigger an interrupt whenever 2.5 mAh of energy has flowed into or out of the battery. Current Direction Change Detection Function The Fuel Gauge's direction-change detection function informs the host whenever the current flow changes direction. The direction-change function is simple: the FGCONFIG1 Register FGCHGSTAT bit is set to 1 when the voltage potential across CS+ and CS- is positive. When the voltage from CS+ to CS- is negative (discharge) this status bit is set to 0. The FGCHGSTAT bit is READ ONLY. The INTSTAT Register, in the peripheral interrupt controller, has a dual edge triggered input for the FGCHGSTAT bit called FGDIR. FGDIR sets anytime there is a change in current flow direction on the sense resistor. This is useful for interrupting the CPU for routines in which the host must be informed immediately of a change in current-flow direction. To enable this interrupt set the FGDIR bit in the INTREN Register to a `1' (See the section on Peripheral Interrupt Controller). Counter Latching Source And Arbiter The FGMUX bits in the FGCONFIG1 Register select one of four sources for latching the Fuel Gauge's charge and discharge counter values. Direct CPU Control The fuel gauge charge and discharge counter values can be latched under direct CPU control by first setting the FGMUX bits D4 and D5 to `00' in the FGCONFIG1 Register, and then writing a `1' to the FGLATCHNOW bit D7 in the FGCONFIG2 Register. This action essentially takes a "snapshot" of the instantaneous counter values 39 Advanced Smart Battery Pack Controller and stores them in the FGDISHIGH, FGDISLOW, FGCHGHIGH, and FGCHGLOW Registers. The charge and discharge counters are not affected by the latching operation. ADC Conversion Start and Stop Setting the FGMUX bits D4 and D5 to `01' will cause the Fuel Gauge charge and discharge counter values to be latched at the beginning and end of each ADC conversion. This method of latching the Fuel Gauge counters allows the simultaneous measurement of cell voltage and current, which can be used to determine instantaneous cell impedance. TIMERA Overflow The Fuel Gauge charge and discharge counter values can be latched by each TIMERA overflow by setting the FGMUX bits D4 and D5 to `10'. TIMERA is a 16-bit programmable counter that can be clocked by several sources. This method for latching the Fuel Gauge counters is for determining the accumulated charge/discharge for an arbitrary time interval. TIMERB Overflow The Fuel Gauge charge and discharge counter values can be latched by each TIMERB overflow by setting the FGMUX bits D4 and D5 to `11'. TIMERB is clocked by the 32KHz Oscillator and is generally programmed to overflow at 1sec intervals. This latching method can then be used to capture charge and discharge counter values accumulated between the 1sec overflows. The difference between two successive counter values is the amount of charge that flows in 1sec, which is also the instantaneous current that is flowing. Arbitration Logic The charge and discharge counters increment asynchronous with respect to the MAX1780 MAX1780 CPU instruction execution. Also, each of the four counter latching sources can occur asynchronously with respect to charge and discharge counter updates. To insure that erroneous counter values are not latched, the Fuel Gauge employs specia l arbitration logic. There is no arbitration while switching modes; therefore it is prudent to only trust data that has been latched by the most recently selected mode. 40 Advanced Smart Battery Pack Controller Fuel Gauge Register Descriptions FGCONFIG1 (Read/Write) Bit D7 D6 Name FGON FGCALON POR 0 0 D5 D4 FGMUX[1:0] 00 D3 FGCHGSTAT - D2 D1 D0 RFU RFU RFU 0 0 0 PORTB Address = 0x18 Function/Description Writing a "1" turns ON the Fuel Gauge Block 0 = Track the charge flow between CS+ and CS1 = Internally connects CS+ to CS-. Note the CS+ pin is high impedance. FGMUX[1:0] chooses the source signal for latching counter data. 00 = Enables functions in FGCONFIG2 01 = Charge and discharge counts are latched at the start and completion of an ADC conversion. 10 = Charge and discharge counts are latched by each TIMERA overflow. 11 = Charge and discharge counts are latched by each TIMERB overflow. 0 = Discharge current direction. 1 = Charge current direction. (This bit is READ ONLY) Read Only Read Only Read Only FGCONFIG2 (Write Only) Bit D7 Name D6 D5 D4