MAX1181ECM MAX1181 MAX1180 MAX1182 MAX1183 MAX1184 MAX1185 8192-POINT MAX11811 - Datasheet Archive

 

Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs Applications High Resolution Imaging I/Q

 

19-2093; Rev 0; 7/01 Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs Applications High Resolution Imaging I/Q Channel Digitization Multichannel IF Undersampling Instrumentation Features o Single +3V Operation o Excellent Dynamic Performance: 59dB SNR at fIN = 20MHz 73dB SFDR at fIN = 20MHz o Low Power: 82mA (Normal Operation) 2.8mA (Sleep Mode) 1µA (Shutdown Mode) o 0.02dB Gain and 0.25° Phase Matching (typ) o Wide ±1Vp-p Differential Analog Input Voltage Range o 400MHz, -3dB Input Bandwidth o On-Chip +2.048V Precision Bandgap Reference o User-Selectable Output Format-Two's Complement or Offset Binary o 48-Pin TQFP Package with Exposed Pad for Improved Thermal Dissipation o Evaluation Kit Available Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX1181ECM MAX1181ECM -40°C to +85°C 48 TQFP-EP 37 38 39 40 41 42 43 44 45 46 47 48 REFN REFP REFIN REFOUT D9A D8A D7A D6A D5A D4A D3A D2A Pin Configuration COM 1 36 D1A VDD GND INA+ 2 35 3 34 4 33 D0A OGND OVDD INAVDD GND 5 32 6 31 INBINB+ GND 8 29 9 28 10 27 11 26 12 25 VDD CLK MAX1181 MAX1181 7 30 OVDD OGND D0B D1B D2B D3B D4B D5B 24 23 22 21 20 19 18 17 16 14 15 VDD GND T/B SLEEP PD OE D9B D8B D7B D6B Functional Diagram appears at end of data sheet. GND VDD 13 Video Application 48 TQFP-EP _ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX1181 MAX1181 General Description The MAX1181 MAX1181 is a +3V, dual 10-bit, analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, ninestage ADCs. The MAX1181 MAX1181 is optimized for low-power, high-dynamic performance applications in imaging, instrumentation, and digital communication applications. The MAX1181 MAX1181 operates from a single +2.7V to +3.6V supply, consuming only 246mW, while delivering a typical signal-to-noise ratio (SNR) of 59dB at an input frequency of 20MHz and a sampling rate of 80Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1181 MAX1181 features a 2.8mA sleep mode, as well as a 1µA power-down mode to conserve power during idle periods. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of the internal or external reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1181 MAX1181 features parallel, CMOS-compatible three-state outputs. The digital output format is set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of +1.7V to +3.6V for flexible interfacing. The MAX1181 MAX1181 is available in a 7mm 7mm, 48pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. Pin-compatible higher and lower speed versions of the MAX1181 MAX1181 are also available. Please refer to the MAX1180 MAX1180 datasheet for 105Msps, the MAX1182 MAX1182 datasheet for 65Msps, the MAX1183 MAX1183 datasheet for 40Msps, and the MAX1184 MAX1184 datasheet for 20Msps. In addition to these speed grades, this family includes a 20Msps multiplexed output version (MAX1185 MAX1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port. MAX1181 MAX1181 Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND .-0.3V to +3.6V OGND to GND.-0.3V to +0.3V INA+, INA-, INB+, INB- to GND .-0.3V to VDD REFIN, REFOUT, REFP, REFN, CLK, COM to GND .-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A­D0A, D9B­D0B to OGND .-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C).1000mW Operating Temperature Range .-40°C to +85°C Junction Temperature .+150°C Storage Temperature Range .-60°C to +150°C Lead Temperature (soldering, 10s) .+300°C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 83.333MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 10 Bits Integral Nonlinearity INL fIN = 7.47MHz ±0.6 ±2.2 Differential Nonlinearity DNL fIN = 7.47MHz, no missing codes guaranteed ±0.4 ±1.0 LSB Offset Error < ±1 ±1.7 % FS Gain Error 0 ±2 % FS LSB ANALOG INPUT Differential Input Voltage Range VDIFF Common-Mode Input Voltage Range RIN Input Capacitance k 5 CIN V 25 Switched capacitor load V VDD/2 ± 0.5 VCM Input Resistance ±1.0 Differential or single-ended inputs pF CONVERSION RATE Maximum Clock Frequency fCLK 80 Data Latency 5 DYNAMIC CHARACTERISTICS (fCLK = 83.333MHz, 4096-point FFT) fINA or B = 7.47MHz, TA = +25°C Signal-to-Noise Ratio SNR fINA or B = 20MHz, TA = +25°C fINA or B = 39.9MHz (Note 1) fINA or B = 7.47MHz, TA = +25°C Signal-to-Noise And Distortion SINAD fINA or B = 20MHz, TA = +25°C th (up to 5 harmonic) fINA or B = 39.9MHz (Note 1) fINA or B = 7.47MHz, TA = +25°C Spurious-Free Dynamic SFDR fINA or B = 20MHz, TA = +25°C Range fINA or B = 39.9MHz, (Note 1) fINA or B = 7.47MHz Third-Harmonic Distortion MHz HD3 56.5 56 56 55.3 65 64 59.5 59 59 59 58.5 58.5 75 73 71 -76 2 fINA or B = 20MHz -76 fINA or B = 39.9MHz (Note 1) -75 _ Clock Cycles dB dB dBc dBc Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = +3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 83.333MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Intermodulation Distortion (first five odd-order IMDs) IMD Total Harmonic Distortion (first five harmonics) THD CONDITIONS MIN fINA or B = 38.1546MHz at -6.5dB FS fINA or B = 41.9532MHz at -6.5dB FS (Note 2) TYP MAX -73.5 UNITS dBc fINA or B = 7.47MHz, TA = +25°C -73 -64 fINA or B = 20MHz, TA = +25°C -70 -63 fINA or B = 39.9MHz (Note 1) -70 Input at -20dB FS, differential inputs 500 MHz Input at -0.5dB FS, differential inputs 400 MHz 1 ns 2 psRMS 2 ns ±1 % ±0.25 degrees 0.2 LSBRMS REFOUT 2.048 ±3% V TCREF 60 ppm/°C 1.25 mV/mA Small-Signal Bandwidth Full-Power Bandwidth FPBW Aperture Delay tAD Aperture Jitter tAJ Overdrive Recovery Time For 1.5 x full-scale input Differential Gain Differential Phase Output Noise INA+ = INA- = INB+ = INB- = COM dBc INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN=+2.048V) REFIN Input Voltage VREFIN 2.048 V Positive Reference Output Voltage VREFP 2.012 V Negative Reference Output Voltage VREFN 0.988 V Differential Reference Output Voltage Range VREF REFIN Resistance RREFIN >50 M ISOURCE >5 mA ISINK 250 µA ISOURCE 250 µA ISINK >5 mA Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current VREF = VREFP - VREFN 0.98 1.024 1.07 V UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN and COM ) REFP, REFN Input Resistance RREFP, RREFN Measured between REFP and COM and REFN and COM 4 k _ 3 MAX1181 MAX1181 ELECTRICAL CHARACTERISTICS (continued) MAX1181 MAX1181 Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = +3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 83.333MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Differential Reference Input Voltage VREF COM Input Voltage CONDITIONS MIN TYP MAX UNITS 1.024 ± 10% V VCOM VDD/2 ± 10% V REFP Input Voltage VREFP VCOM + VREF/2 V REFN Input Voltage VREFN VCOM - VREF/2 V VREF = VREFP - VREFN DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK PD, OE, SLEEP, T/B Input High Threshold 0.8 x VDD 0.8 x OVDD VIH V CLK PD, OE, SLEEP, T/B Input Low Threshold Input Hysteresis Input Leakage Input Capacitance 0.2 x VDD 0.2 x OVDD VIL VHYST 0.1 V IIH VIH = OVDD or VDD (CLK) ±5 IIL VIL = 0 ±5 CIN V 5 µA pF DIGITAL OUTPUTS (D9A­D0A, D9B­D0B) Output Voltage Low VOL ISINK = 200µA Output Voltage High VOH ISOURCE = 200µA Three-State Leakage Current ILEAK OE = OVDD Three-State Output Capacitance COUT 0.2 OE = OVDD OVDD - 0.2 V V ±10 5 µA pF POWER REQUIREMENTS Analog Supply Voltage Range VDD Output Supply Voltage Range 2.7 OVDD 3.0 3.6 V 1.7 V Analog Supply Current IVDD 2.5 3.6 Operating, fINA or B = 20MHz at -0.5dB FS 82 97 Sleep mode 2.8 Shutdown, clock idle, PD = OE = OVDD Output Supply Current IOVDD 1 Operating, CL = 15pF , fINA or B = 20MHz at -0.5dB FS 13 Sleep mode 100 Shutdown, clock idle, PD = OE = OVDD 4 2 _ 15 mA µA mA µA 10 µA Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = +3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 83.333MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Power Dissipation MAX UNITS 246 291 mW Sleep mode PDISS TYP Operating, fINA or B = 20MHz at -0.5dB FS CONDITIONS MIN 8.4 Shutdown, clock idle, PD = OE = OVDD Power Supply Rejection 3 µW 45 Offset ±0.2 mV/V Gain PSRR ±0.1 %/V TIMING CHARACTERISTICS CLK Rise to Output Data Valid tDO Figure 3 (Note 3) 5 8 ns Output Enable Time tENABLE Figure 4 10 Output Disable Time tDISABLE Figure 4 1.5 ns 6 ±1 ns ns CLK Pulse Width High tCH Figure 3 clock period: 12ns CLK Pulse Width Low tCL Figure 3 clock period: 12ns 6 ±1 Wakeup from sleep mode (Note 4) 0.28 Wakeup from shutdown (Note 4) ns 1.5 Wake-Up Time tWAKE µs CHANNEL-TO-CHANNEL MATCHING Crosstalk fINA or B = 20MHz at -0.5dB FS -70 Gain Matching fINA or B = 20MHz at -0.5dB FS 0.02 Phase Matching fINA or B = 20MHz at -0.5dB FS dB 0.25 ±0.2 dB degrees Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS, referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB or better, if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. Typical Operating Characteristics (VDD = +3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 80.0005678MHz, CL 10pF. TA = +25°C, unless otherwise noted.) -30 -40 -50 -60 fINA = 6.0449MHz fINB = 7.5099MHz fCLK = 80.000568MHz AINB = -0.52dB FS CHB -20 AMPLITUDE (dB) AMPLITUDE (dB) -20 0 -10 -30 0 -40 -50 -60 fINA = 19.9123MHz fINB = 24.9123MHz fCLK = 80.000568MHz AINA = -0.52 dB FS CHA -10 -20 -30 MAX1181 MAX1181 toc03 fINA = 6.0449MHz fINB = 7.5099MHz fCLK = 80.000568MHz AINA = -0.46dB FS FFT PLOT CHA (8192-POINT 8192-POINT RECORD, DIFFERENTIAL INPUT) AMPLITUDE (dB) CHA MAX1181 MAX1181 toc01 0 -10 FFT PLOT CHB (8192-POINT 8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1181 MAX1181 toc02 FFT PLOT CHA (8192-POINT 8192-POINT RECORD, DIFFERENTIAL INPUT) -40 -50 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90 -100 -100 -100 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) 40 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) 40 0 5 10 15 20 25 30 35 40 ANALOG INPUT FREQUENCY (MHz) _ 5 MAX1181 MAX1181 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 80.0005678MHz, CL 10pF. TA = +25°C, unless otherwise noted.) FFT PLOT CHA (8192-POINT 8192-POINT RECORD, DIFFERENTIAL INPUT) -40 -50 -60 fINA = 40.4202MHz fINB = 47.0413MHz fCLK = 80.000568MHz AINA = -0.52dB FS -20 -30 CHA 0 -40 -50 -60 fINA = 40.4202MHz fINB = 47.0413MHz fCLK = 80.000568MHz AINB = -0.53dB FS -10 -20 AMPLITUDE (dB) -30 0 -10 AMPLITUDE (dB) AMPLITUDE (dB) -20 CHB MAX1181 MAX1181 toc05 fINA = 19.9123MHz fINB = 24.9123MHz fCLK = 80.000568MHz AINB = -0.53 dB FS MAX1181 MAX1181 toc04 0 -10 FFT PLOT CHB (8192-POINT 8192-POINT RECORD, DIFFERENTIAL INPUT) -30 MAX1181 MAX1181 toc06 FFT PLOT CHB (8192-POINT 8192-POINT RECORD, DIFFERENTIAL INPUT) CHB -40 -50 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90 -100 -100 -100 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY -40 CHA fIN2 59 -50 -60 2nd ORDER IMD -70 MAX1181 MAX1181 toc09 60 CHB SINAD (dB) -30 60 SNR (dB) -20 61 MAX1181 MAX1181 toc08 fIN1 fIN1 = 38.1545676MHz fIN2 = 41.9631884MHz fCLK = 80.0005678MHz AIN = 6.5dB FS TWO-TONE ENVELOPE = -0.52dB FS 61 MAX1181 MAX1181 toc07 0 -10 AMPLITUDE (dB) 40 ANALOG INPUT FREQUENCY (MHz) TWO-TONE IMD PLOT (8192-POINT 8192-POINT RECORD, COHERENT SAMPLING) 58 CHA 59 CHB 57 58 -80 56 -90 57 55 -100 0 5 10 15 20 25 30 35 100 10 40 100 10 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED) 83 4 2 SFDR (dB) -74 CHA CHA CHB 75 71 -77 ANALOG INPUT FREQUENCY (MHz) -2 -6 -8 63 100 10 0 -4 67 -80 6 GAIN (dB) 79 -71 MAX1181 MAX1181 toc12 6 MAX1181 MAX1181 toc11 CHB -68 87 MAX1181 MAX1181 toc10 -65 THD (dB) MAX1181 MAX1181 Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs 100 10 ANALOG INPUT FREQUENCY (MHz) 1 10 100 ANALOG INPUT FREQUENCY (MHz) _ 1000 Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED) 0 -2 -4 SINAD (dB) SNR (dB) GAIN (dB) 58 60 2 55 MAX1181 MAX1181 toc15 4 60 MAX1181 MAX1181 toc14 VIN = 100mVp-p SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 20MHz) 65 MAX1181 MAX1181 toc13 6 SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 20MHz) 50 56 54 52 -6 50 45 -8 1 10 100 -9 1000 -8 -7 -6 -5 -4 -3 -2 -1 0 -9 -8 -7 -6 -5 -4 -3 -2 ANALOG INPUT FREQUENCY (MHz) INPUT POWER (dB FS) TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 20MHz) SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 20MHz) -1 0 INPUT POWER (dB FS) INTEGRAL NONLINEARITY (BEST-STRAIGHT-LINE FIT) 76 MAX1181 MAX1181 toc18 -64 1.0 MAX1181 MAX1181 toc17 80 MAX1181 MAX1181 toc16 -60 0.8 0.6 -72 72 INL (LSB) -68 SFDR (dB) THD (dB) 0.4 68 0.2 0 -0.2 -0.4 -76 64 -80 60 -0.6 -0.8 -9 -8 -7 -6 -5 -4 -3 -2 -1 -1.0 0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 128 256 384 512 640 768 896 1024 INPUT POWER (dB FS) INPUT POWER (dB FS) DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V) OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V) GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 CHB 2 1 0 CHA MAX11811 MAX11811 toc21 3 CHB 3 OFFSET ERROR (LSB) 0.6 5 MAX1181 MAX1181 toc20 0.8 DNL (LSB) 4 MAX1181 MAX1181 toc19 1.0 1 -1 CHA -3 -1 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE -2 -40 -5 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _ 7 MAX1181 MAX1181 Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 80.0005678MHz, CL 10pF. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 80.0005678MHz, CL 10pF. TA = +25°C, unless otherwise noted.) ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY ANALOG SUPPLY CURRENT vs. TEMPERATURE 90 80 IVDD (mA) 80 OE = PD = OVDD 1.6 IVDD (µA) 90 2.0 MAX11811 MAX11811 toc23 100 MAX1181 MAX1181 toc22 100 MAX1181 MAX1181 toc24 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE IVDD (mA) 1.2 70 70 0.8 60 60 0.4 0 50 50 2.70 2.85 3.00 3.15 3.30 3.45 -40 3.60 -15 10 35 60 2.70 85 3.30 2.075 MAX1181 MAX1181 toc26 SFDR MAX1181 MAX1181 toc25 fINA = 24.9123MHz fINB = 19.9123MHz 3.15 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE 80 2.065 70 VREFOUT (V) SFDR, SNR, THD, SINAD (dB) 3.00 VDD (V) SFDR, SNR, THD, SINAD vs. CLOCK DUTY CYCLE 75 2.85 TEMPERATURE (°C) VDD (V) THD 65 SNR 2.055 2.045 60 2.035 55 SINAD 2.025 50 35 40 45 50 55 60 65 2.70 70 2.85 3.00 3.15 3.30 3.45 3.60 VDD (V) CLOCK DUTY CYCLE (%) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE OUTPUT NOISE HISTOGRAM (DC INPUT) 140000 MAX11811 MAX11811 toc27 2.10 2.08 MAX1181 MAX1181 toc28 30 129377 120000 100000 2.06 COUNTS VREFOUT (V) MAX1181 MAX1181 Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs 2.04 80000 60000 40000 2.02 20000 0 2.00 -40 -15 10 35 TEMPERATURE (°C) 8 60 85 0 965 N-2 N-1 730 N 0 N+1 N+2 DIGITAL OUTPUT NOISE _ 3.45 3.60 Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs PIN NAME 1 COM Common-Mode Voltage Input/Output. Bypass to GND with a 0.1µF capacitor. FUNCTION 2, 6, 11, 14, 15 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. 3, 7, 10, 13, 16 GND Analog Ground 4 INA+ Channel `A' Positive Analog Input. For single-ended operation, connect signal source to INA+. 5 INA- Channel `A' Negative Analog Input. For single-ended operation, connect INA- to COM. 8 INB- Channel `B' Negative Analog Input. For single-ended operation, connect INB- to COM. 9 INB+ Channel `B' Positive Analog Input. For single-ended operation, connect signal source to INB+. 12 CLK Converter Clock Input 17 T/B T/B selects the ADC digital output format. High: Two's complement. Low: Straight offset binary. 18 SLEEP 19 PD Power-Down Input. High: Power-down mode. Low: Normal operation. 20 OE Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. 21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B 22 D8B Three-State Digital Output, Bit 8, Channel B 23 D7B Three-State Digital Output, Bit 7, Channel B 24 D6B Three-State Digital Output, Bit 6, Channel B 25 D5B Three-State Digital Output, Bit 5, Channel B 26 D4B Three-State Digital Output, Bit 4, Channel B 27 D3B Three-State Digital Output, Bit 3, Channel B 28 D2B Three-State Digital Output, Bit 2, Channel B 29 D1B Three-State Digital Output, Bit 1, Channel B 30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B 31, 34 OGND Output Driver Ground 32, 33 OVDD Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with 0.1µF. 35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A 36 D1A Three-State Digital Output, Bit 1, Channel A 37 D2A Three-State Digital Output, Bit 2, Channel A 38 D3A Three-State Digital Output, Bit 3, Channel A 39 D4A Three-State Digital Output, Bit 4, Channel A Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. _ 9 MAX1181 MAX1181 Pin Description Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1181 MAX1181 Pin Description (continued) PIN NAME FUNCTION 40 D5A Three-State Digital Output, Bit 5, Channel A 41 D6A Three-State Digital Output, Bit 6, Channel A 42 D7A Three-State Digital Output, Bit 7, Channel A 43 D8A Three-State Digital Output, Bit 8, Channel A 44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A 45 REFOUT 46 REFIN Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a >1nF capacitor. 47 REFP Positive Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 48 REFN Negative Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider. Detailed Description The MAX1181 MAX1181 uses a nine-stage, fully-differential pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Counting the delay through the output latch, the clockcycle latency is five clock cycles. 1.5-bit (two-comparator) flash ADCs convert the heldinput voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held-input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. Input Track-and-Hold (T/H) Circuits Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track-andhold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a and S5b are closed. The fully-differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on 10 capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1181 MAX1181 to track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance. Analog Inputs and Reference Configurations The full-scale range of the MAX1181 MAX1181 is determined by the internally generated voltage difference between REFP (V DD /2 + V REFIN /4) and REFN (V DD /2 VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD/2) and REFN are internally buffered low-impedance outputs. The MAX1181 MAX1181 provides three modes of reference operation: · Internal reference mode · Buffered external reference mode · Unbuffered external reference mode In the internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10k) or resistor divider, if an application requires a reduced full-scale range. For stability and _ Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs T/H FLASH ADC x2 VIN VOUT T/H FLASH ADC DAC 1.5 BITS x2 VOUT DAC 1.5 BITS 2-BIT FLASH ADC STAGE 1 STAGE 8 STAGE 2 2-BIT FLASH ADC STAGE 9 STAGE 1 DIGITAL CORRECTION LOGIC T/H VINA MAX1181 MAX1181 VIN D9A­D0A STAGE 8 STAGE 9 DIGITAL CORRECTION LOGIC T/H 10 STAGE 2 VINB 10 D9B­D0B VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED) Figure 1. Pipelined Architecture­­Stage Blocks noise filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In the buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10k resistor. In the unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources. Clock Input (CLK) The MAX1181 MAX1181's CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: SNRdB = 20 log10 (1 / [2 x fIN tAJ]), where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1181 MAX1181 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. System Timing Requirements Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1181 MAX1181 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 4 also determines the relationship between the input clock parameters and the valid output data on channels A and B. Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE) All digital outputs, D0A­D9A (Channel A) and D0B­D9B (Channel B), are TTL/CMOS logic-compatible. There is a _ 11 MAX1181 MAX1181 Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b INTERNAL BIAS COM HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a INB+ OUT C2a S4c S1 OUT INBS4b MAX1181 MAX1181 C2b C1b S3b S5b S2b INTERNAL BIAS COM Figure 2. MAX1181 MAX1181 T/H Amplifiers five clock cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or two's complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two's complement output coding. The capacitive load on the digital outputs D0A­D9A and D0B­D9B should 12 be kept as low as possible (