MAX114 MAX118 MAX114CNG MAX114EAG MAX114MRG MAX114CAG MAX114C/D MAX114ENG - Datasheet Archive
+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down _Features o Single +5V Supply Operation o 4 (MAX114) or 8
19-1083; Rev 1; 8/96 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down _Features o Single +5V Supply Operation o 4 (MAX114 MAX114) or 8 (MAX118 MAX118) Analog Input Channels o Low Power: 40mW (operating mode) 5µW (power-down mode) o Total Unadjusted Error 1LSB o Fast Conversion Time: 660ns per Channel o No External Clock Required o Internal Track/Hold o 1MHz Full-Power Bandwidth o Internally Connected 8th Channel Monitors Reference Voltage (MAX118 MAX118) _Applications Ordering Information continued on last page. *Dice are specified at TA = +25°C, DC parameters only. *Contact factory for availability. Pin Configurations appear on last page. High-Speed DSP PART TEMP. RANGE PIN-PACKAGE MAX114CNG MAX114CNG 24 Narrow Plastic DIP 0°C to +70°C 0°C to +70°C -40°C to +85°C 24 SSOP Dice* 24 Narrow Plastic DIP MAX114EAG MAX114EAG MAX114MRG MAX114MRG Communications Systems 0°C to +70°C MAX114CAG MAX114CAG MAX114C/D MAX114C/D MAX114ENG MAX114ENG Remote Data Acquisition Portable Equipment _Ordering Information -40°C to +85°C -55°C to +125°C 24 SSOP 24 Narrow CERDIP* _Functional Diagram REF+ D7 D6 D5 D4 4-BIT FLASH ADC (4MSBs) *IN8 *IN7 *IN6 *IN5 IN4 IN3 IN2 MUX 4-BIT DAC IN1 REF+ 16 ADDRESS LATCH DECODE THREESTATE OUTPUT DRIVERS D3 D2 D1 D0 4-BIT FLASH ADC (4LSBs) TIMING AND CONTROL MAX114/MAX118 MAX114/MAX118 A0 * MAX118 MAX118 ONLY A1 A2 REF- RD CS PWRDN MODE WR/RDY INT _ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX114/MAX118 MAX114/MAX118 _General Description The MAX114/MAX118 MAX114/MAX118 are microprocessor-compatible, 8-bit, 4-channel and 8-channel analog-to-digital converters (ADCs). They operate from a single +5V supply and use a half-flash technique to achieve a 660ns conversion time (1Msps). A power-down (PWRDN) pin reduces current consumption typically to 1µA. The devices return from power-down mode to normal operating mode in less than 200ns, allowing large supplycurrent reductions in burst-mode applications (in burst mode, the ADC wakes up from a low-power state at specified intervals to sample the analog input signals). Both converters include a track/hold, enabling the ADC to digitize fast analog signals. Microprocessor (µP) interfaces are simplified because the ADC can appear as a memory location or I/O port without external interface logic. The data outputs use latched, three-state buffer circuitry for direct connection to an 8-bit parallel µP data bus or system input port. The MAX114/MAX118 MAX114/MAX118 input/reference configuration enables ratiometric operation. The 4-channel MAX114 MAX114 is available in a 24-pin DIP or SSOP. The 8-channel MAX118 MAX118 is available in a 28-pin DIP or SSOP. For +3V applications, refer to the MAX113/MAX117 MAX113/MAX117 data sheet. MAX114/MAX118 MAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down ABSOLUTE MAXIMUM RATINGS VDD to GND .-0.3V to +7V Digital Input Voltage to GND .-0.3V to (VDD + 0.3V) Digital Output Voltage to GND .-0.3V to (VDD + 0.3V) REF+ to GND.-0.3V to (VDD + 0.3V) REF- to GND.-0.3V to (VDD + 0.3V) IN_ to GND .-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 24-Pin Narrow Plastic DIP (derate 13.33mW/°C above +70°C).1.08W 24-Pin SSOP (derate 8.00mW/°C above +70°C).640mW 24-Pin Narrow CERDIP (derate 12.50mW/°C above +70°C).1W 28-Pin Wide Plastic DIP (derate 14.29mW/°C above +70°C).1.14W 28-Pin SSOP (derate 9.52mW/°C above +70°C).762mW 28-Pin Wide CERDIP (derate 16.67mW/°C above +70°C).1.33W Operating Temperature Ranges MAX114/MAX118C MAX114/MAX118C_ _.0°C to +70°C MAX114/MAX118E MAX114/MAX118E_ _ .-40°C to +85°C MAX114/MAX118M MAX114/MAX118M_ _ .-55°C to +125°C Storage Temperature Range .-65°C to +150°C Lead Temperature (soldering, 10sec) .+300°C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5V ±5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1 LSB ACCURACY (Note 1) Resolution N Total Unadjusted Error Differential Nonlinearity DNL 8 Bits TUE ±1 LSB Zero-Code Error No-missing-codes guaranteed ±1 LSB Full-Scale Error ±1 LSB ±1/4 LSB Channel-to-Channel Mismatch DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Input Full-Power Bandwidth MAX11 MAX11_C/E, fSAMPLE = 1MHz, fIN_ = 195.8kHz 45 MAX11 MAX11_M, fSAMPLE = 740kHz, fIN_ = 195.7kHz 45 dB MAX11 MAX11_C/E, fSAMPLE = 1MHz, fIN_ = 195.8kHz -50 MAX11 MAX11_M, fSAMPLE = 740kHz, fIN_= 195.7kHz -50 MAX11 MAX11_C/E, fSAMPLE = 1MHz, fIN_ = 195.8kHz 50 MAX11 MAX11_M, fSAMPLE = 740kHz, fIN_ = 195.7kHz 50 VIN_ = 5Vp-p Input Slew Rate, Tracking dB dB 1 3.1 MHz 15 V/µs ANALOG INPUT Input Voltage Range VIN_ Input Leakage Current IIN_ Input Capacitance VREF- CIN_ VREF+ V ±3 GND < VIN_ < VDD µA 32 pF REFERENCE INPUT Reference Resistance 4 k REF+ Input Voltage Range VREF- VDD V REF- Input Voltage Range GND VREF+ V 2 RREF 1 2 _ +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down MAX114/MAX118 MAX114/MAX118 ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V ±5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS Input High Voltage VINH Input Low Voltage VINL Input High Current IINH CS, WR, RD, PWRDN, A0, A1, A2 2.4 MODE 3.5 V CS, WR, RD, PWRDN, A0, A1, A2 0.8 MODE 1.5 CS, RD, PWRDN, A0, A1, A2 ±1 WR ±3 MODE 50 Input Low Current IINL CS, WR, RD, PWRDN, MODE, A0, A1, A2 Input Capacitance (Note 2) CIN CS, WR, RD, PWRDN, MODE, A0, A1, A2 V µA 200 ±1 5 µA 8 pF LOGIC OUTPUTS Output Low Voltage VOL ISINK = 1.6mA, INT, D0D7 0.4 RDY, ISINK = 2.6mA 0.4 Output High Voltage VOH ISOURCE = 360µA, INT, D0D7 Three-State Current ILKG D0D7, RDY, digital outputs = 0V to VDD Three-State Capacitance (Note 2) COUT D0D7, RDY 4 V V ±3 8 pF 5.25 5 µA V POWER REQUIREMENTS Supply Voltage VDD VDD Supply Current IDD MAX11 MAX11_C 8 15 MAX11 MAX11_E/M 8 20 CS = RD = VDD, PWRDN = 0V (Note 3) Power-Down VDD Current Power-Supply Rejection 4.75 CS = RD = 0V, PWRDN = VDD PSR VDD = 4.75V to 5.25V, VREF = 4.75V mA 1 10 µA ±1/16 ±1/4 LSB Note 2: Guaranteed by design. Note 3: Power-down current increases if logic inputs are not driven to GND or VDD. _ 3 MAX114/MAX118 MAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down TIMING CHARACTERISTICS (VDD = +4.75V, TA = +25°C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS TA = +25°C ALL GRADES MIN TYP CL = 20pF CL = 100pF MAX 660 685 TA = TMIN to TMAX MAX11 MAX11_C/E MAX11 MAX11_M MIN MAX MIN MAX UNITS Conversion Time (WR-RD Mode) tCWR Conversion Time (RD Mode) tCRD Power-Up Time tUP CS to RD, WR Setup Time tCSS 0 0 0 ns CS to RD, WR Hold Time tCSH 0 0 0 ns CS to RDY Delay tRDY CL = 50pF, RL = 5.1k to VDD Data-Access Time (RD Mode) tACC0 CL = 100pF (Note 5) RD to INT Delay (RD Mode) tINTH CL = 50pF Data Hold Time tRD < tINTL, (Note 5) ns 865 1125 700 875 975 ns 320 370 520 ns 70 100 ns tCRD + 50 50 85 tCRD + 65 tCRD + 75 ns 80 85 90 ns 80 ns tDH (Note 6) Minimum Acquisition Time tACQ (Note 7) WR Pulse Width tWR 0.25 Delay Between WR and RD Pulses tRD 0.25 0.35 0.45 µs 160 205 240 ns RD Pulse Width (WR-RD Mode) tREAD1 tRD < tINTL, determined by tACC1 Data-Access Time (WR-RD Mode) tACC1 60 160 70 185 10 tRD < tINTL, CL = 100pF (Note 5) 0.28 260 10 0.4 ns 10 µs 185 235 275 ns 150 185 220 ns 500 610 700 ns RD to INT Delay tRI WR to INT Delay tINTL RD Pulse Width (WR-RD Mode) tREAD2 tRD > tINTL, determined by tACC2 Data-Access Time (WR-RD Mode) tACC2 tRD > tINTL, CL = 100pF (Note 5) 90 110 130 ns WR to INT Delay CL = 50pF 380 65 75 85 ns tIHWR Pipelined mode, CL = 50pF 80 100 120 ns Data-Access Time after INT tID Pipelined mode, CL = 100pF 45 60 70 ns Multiplexer Address Hold Time tAH Note 4: Note 5: Note 6: Note 7: 4 30 35 40 Input control signals are specified with tr = tf = 5ns, 10% to 90% of 5V, and timed from a voltage level of 1.6V. See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.8V or 2.4V. See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V. Also defined as the Minimum Address-Valid to Convert-Start Time. _ ns +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY (WR-RD MODE) 1.3 1.2 VDD = +4.75V 1.1 1.0 0.9 VDD = +5.25V 0.8 8.0 MAX114/118-02 MAX114/118-02 1.4 EFFECTIVE NUMBER OF BITS 1.5 MAX114/118-01 MAX114/118-01 7.5 7.0 6.5 fSAMPLE = 1MHz VIN = 4.96Vp-p VDD = +5V 0.7 6.0 0.6 -60 -20 60 20 1k 140 100 10k AVERAGE POWER CONSUMPTION vs. SAMPLING RATE USING PWRDN 1M SIGNAL-TO-NOISE RATIO 0 MAX114/118-03 MAX114/118-03 50 40 30 20 VDD = 4.75V INPUT FREQUENCY = 195.8ksps VIN = 4.72Vp-p -20 RATIO (dB) POWER DISSIPATION (mW) 100k INPUT FREQUENCY (Hz) TEMPERATURE (°C) 10 MAX114/118-04 MAX114/118-04 tCRD (NORMALIZED TO VALUE AT VDD = +5V, +25°C) CONVERSION TIME vs. AMBIENT TEMPERATURE -40 SAMPLE FREQUENCY = 1MHz SNR = 48.2dB -60 -80 0 1k 10k 100k -100 1M 0 100 200 300 400 500 SAMPLING RATE (CONVERSIONS/SEC) FREQUENCY (kHz) TOTAL UNADJUSTED ERROR vs. POWER-UP TIME SUPPLY CURRENT vs. TEMPERATURE (EXCLUDING REFERENCE CURRENT) 4 3 2 1 MAX114/118-08 MAX114/118-08 10 SUPPLY CURRENT (mA) 5 TUE (LSB) 12 MAX114/118-06 MAX114/118-06 6 8 6 4 2 0 0 75 100 125 150 175 200 POWER-UP TIME, tUP (ns) 225 250 -60 -20 20 60 100 140 TEMPERATURE (°C) _ 5 MAX114/MAX118 MAX114/MAX118 _Typical Operating Characteristics (VDD = +5V, TA = +25°C, unless otherwise noted.) MAX114/MAX118 MAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down _Pin Description PIN NAME FUNCTION MAX114 MAX114 MAX118 MAX118 - 1 IN6 Analog Input Channel 6 - 2 IN5 Analog Input Channel 5 1 3 IN4 Analog Input Channel 4 2 4 IN3 Analog Input Channel 3 3 5 IN2 Analog Input Channel 2 4 6 IN1 Analog Input Channel 1 5 7 MODE Mode Selection Input. Internally pulled low with a 50µA current source. MODE = 0 activates read mode; MODE = 1 activates write-read mode (see Digital Interface Section). 6 D0 9, 10, 11 D1, D2, D3 10 12 RD Read Input. RD must be low to access data (see Digital Interface section). 11 13 INT Interrupt Output. INT goes low to indicate end of conversion (see Digital Interface section). 12 14 GND Ground 13 15 REF- Lower Limit of Reference Span. REF- sets the zero-code voltage. Range is GND VREF- < VREF+. 14 16 REF+ Upper Limit of Reference Span. REF+ sets the full-scale input voltage. Range is VREF< VREF+ VDD. Internally hard-wired to IN8 (Table 1). 15 17 WR/RDY 16 18 CS 17, 18, 19 19, 20, 21 D4, D5, D6 20 22 D7 Three-State Data Output (MSB) - 23 A2 Multiplexer Channel Address Input (MSB) 21 24 A1 Multiplexer Channel Address Input 22 25 A0 Multiplexer Channel Address Input (LSB) 23 26 PWRDN 24 27 VDD Positive Supply, +5V - 6 8 7, 8, 9 Three-State Data Output (LSB) 28 IN7 Analog Input Channel 7 Three-State Data Outputs Write-Control Input/Ready-Status Output (see Digital Interface section) Chip-Select Input. CS must be low for the device to recognize WR or RD inputs. Three-State Data Outputs Power-Down Input. PWRDN reduces supply current when low. _ +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down Converter Operation The MAX114/MAX118 MAX114/MAX118 use a half-flash conversion technique (see Functional Diagram) in which two 4-bit flash ADC sections achieve an 8-bit result. Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate both the analog result from the first flash conversion and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash comparators to obtain the lower four data bits (LSBs). An internal analog multiplexer enables the devices to read four (MAX114 MAX114) or eight (MAX118 MAX118) different analog voltages under microprocessor (µP) control. One of the MAX118 MAX118's analog channels, IN8, is internally hardwired and always reads VREF+ when selected. VDD DATA OUTPUTS RL = 3k DATA OUTPUTS RL = 3k CL CL Power-Down Mode In burst-mode or low sample-rate applications, the MAX114/MAX118 MAX114/MAX118 can be shut down between conversions, reducing supply current to microamp levels (see Typical Operating Characteristics). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to 1µA when powered from a single +5V supply. A logic high on PWRDN wakes up the MAX114/MAX118 MAX114/MAX118, and the selected analog input enters the track mode. The signal is fully acquired after 360ns (this includes both the power-up delay and the track/hold acquisition time), and a new conversion can be started. If the power-down feature is not required, connect PWRDN to VDD. For minimum current consumption, keep digital inputs at the supply rails in power-down mode. Refer to the Reference section for information on reducing reference current during power-down. _Digital Interface The MAX114/MAX118 MAX114/MAX118 have two basic interface modes, which are set by the MODE pin. When MODE is low, the converters are in read mode; when MODE is high, the converters are set up for write-read mode. The A0, A1, and A2 inputs control channel selection, as shown in Table 1. The address must be valid for a minimum time, tACQ, before the next conversion starts. Table 1. Truth Table for Input Channel Selection MAX114 MAX114 MAX118 MAX118 b) HIGH-Z TO VOL Figure 1. Load Circuits for Data-Access Time Test VDD 3k A0 0 1 0 1 - - - A2 0 0 0 0 1 1 1 A1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 - a) HIGH-Z TO VOH A1 0 0 1 1 - - - - 1 1 1 SELECTED CHANNEL IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 (reads VREF+ if selected) DATA OUTPUTS DATA OUTPUTS Read Mode (MODE = 0) 10pF 3k a) VOH TO HIGH-Z 10pF b) VOL TO HIGH-Z Figure 2. Load Circuits for Data-Hold Time Test In read mode, conversions and data access are controlled by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of tACQ. Initiate a conversion by driving CS and RD low. With µPs that can be forced into a wait state, hold RD low until output data appears. The µP starts the conversion, waits, and then reads data with a single read instruction. _ 7 MAX114/MAX118 MAX114/MAX118 _Detailed Description MAX114/MAX118 MAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down In read mode, WR/RDY is configured as a status output (RDY), so it can drive the ready or wait input of a µP. RDY is an open-collector output (no internal pull-up) that goes low after the falling edge of CS and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the rising edge of CS or RD. Write-Read Mode (MODE = 1) Figures 4 and 5 show the operating sequence for writeread mode. The comparator inputs track the analog input voltage for the duration of tACQ. The conversion is initiated by a falling edge of WR. When WR returns high, the result of the four-MSBs flash is latched into the output buffers and the conversion of the four-LSBs flash starts. INT goes low, indicating conversion end, and the lower four data bits are latched into the output buffers. The data is then accessible after RD goes low (see Timing Characteristics). A minimum acquisition time (tACQ) is required from INT going low to the start of another conversion (WR going low). Options for reading data from the converter include using internal delay, reading before delay, and pipelined operation (discussed in the following sections). Using Internal Delay The µP waits for the INT output to go low before reading the data (Figure 4). INT goes low after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With CS low, data outputs D0D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD. Figure 5 shows an external method of controlling the conversion time. The internally generated delay (tINTL) varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conversion time. RD is brought low after the rising edge of WR, but before INT goes low. This completes the conversion and enables the output buffers that contain the conversion result (D0D7). INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: tWR + tRD + tACC1 = 660ns. CS tCSH tCSS tWR WR tACQ ADDRESS VALID (N) A0A2 ADDRESS VALID (N + 1) tREAD2 tINTL tCSS tACC2 tACQ ADDRESS VALID (N) tAH tACQ ADDRESS VALID (N + 1) tAH WITH EXTERNAL PULL-UP tINTH INT tCRD tDH VALID DATA (N) D0D7 tACCO Figure 3. Read Mode Timing (MODE = 0) 8 tDH Figure 4. Write-Read Mode Timing (tRD > tINTL) (MODE = 1) A0A2 tRDY VALID DATA (N) D0D7 tWR tCSS RDY tINTH tRD INT WR tCSH A0A2 tCSH tCSS RD CS RD tACQ tAH CS tUP PWRDN Fastest Conversion: Reading Before Delay tCSH tRD tACQ tINTL tAH tACQ ADDRESS VALID (N) ADDRESS VALID (N + 1) tCSS RD tCSH tREAD1 tRI INT VALID DATA (N) D0D7 tCWR tACC1 tINTH tDH Figure 5. Write-Read Mode Timing (tRD < tINTL) (MODE = 1) _ +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down CS tCSS Figures 7a, 7b, and 7c show typical reference connections. The voltages at REF+ and REF- set the ADC's analog input range (see Figure 10). The voltage at REFdefines the input that produces an output code of all zeros, and the voltage at REF+ defines the input that produces an output code of all ones. The internal resistance from REF+ to REF- can be as low as 1k, and current will flow through it even when the MAX114/MAX118 MAX114/MAX118 are shut down. Figure 7d shows how an N-channel MOSFET can be connected to REF- VIN+ RD, WR tACQ A0A2 tACQ tAH ADDRESS VALID (N) ADDRESS VALID (N + 1) tIHWR INT tINTL tID D0D7 NEW DATA (N) OLD DATA (N - 1) Figure 6. Pipelined Mode Timing (WR = RD) (MODE = 1) IN_ VIN+ IN_ VIN- tCSH tWR _Analog Considerations Reference GND GND +5V MAX114 MAX114 VDD MAX118 MAX118 +5V 4.7µF MAX114/MAX118 MAX114/MAX118 Pipelined Operation Besides the two standard write-read-mode options, pipelined operation can be achieved by connecting WR to RD (Figure 6). With CS low, driving WR and RD low initiates a conversion and concurrently reads the result of the previous conversion. 4.7µF VDD MAX114 MAX114 MAX118 MAX118 0.1µF REF+ +2.5V 0.1µF REF+ REF- VIN- REFR* 0.1µF 0.1µF * CURRENT PATH MUST STILL EXIST FROM VIN- TO GND Figure 7a. Power Supply as Reference Figure 7c. Input Not Referenced to GND +5V VIN+ VIN- GND MAX874 MAX874 0.1µF MX584 MX584 C1 0.1µF REF+ C1 3.3µF VDD MAX114 MAX114 MAX118 MAX118 REF+ +5V 4.7µF VDD 0.1µF IN_ MAX114 MAX114 MAX118 MAX118 REFN-FET* REF- 0.1µF PWRDN PWRDN * IRML2402 IRML2402 Figure 7b. External Reference, 4.096V Full Scale Figure 7d. An N-channel MOSFET switches off the reference load during power-down _ 9 MAX114/MAX118 MAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down to break this current path during power-down. The FET should have an on-resistance of less than 2 with a 5V gate drive. When REF- is switched, as in Figure 7d, a new conversion can be initiated after waiting a period of time equal to the power-up delay (tUP) plus the Nchannel FET's turn-on time. Although REF+ is frequently connected to VDD, the circuit of Figure 7d uses a low-current, low-dropout, 4.096V voltage reference: the MAX874 MAX874. Since the MAX874 MAX874 cannot continuously furnish enough current for the reference resistance, this circuit is intended for applications where the MAX114/MAX118 MAX114/MAX118 are normally in standby and are turned on in order to make measurements at intervals greater than 65µs. C1 (the capacitor connected to REF+) is slowly charged by the MAX874 MAX874 during the standby period, and furnishes the reference current during the short measurement period. C1's 3.3µF value ensures a voltage drop of less than 1/2LSB when performing four to eight successive conversions. Larger capacitors reduce the error still further. Use ceramic or tantalum capacitors for C1. Initial Power-Up When power is first applied, perform a conversion to initialize the MAX114/MAX118 MAX114/MAX118. Disregard the output data. Bypassing Use a 4.7µF electrolytic in parallel with a 0.1µF ceramic capacitor to bypass VDD to GND. Minimize capacitor lead lengths. Bypass the reference inputs with 0.1µF capacitors, as shown in Figures 7a, 7b, and 7c. MUX MAX114 MAX114 MAX118 MAX118 Track/Hold The track/hold enters hold mode when a conversion starts (RD low or WR low). INT goes low at the end of the conversion, at which point the track/hold enters track mode. The next conversion can start after the minimum acquisition time, tACQ. RIN VIN_ VIN 2k RON VIN2 RIN . . . Figure 8. Equivalent Input Circuit 10 Analog Inputs Figure 8 shows the equivalent circuit of the MAX114/ MAX114/ MAX118 MAX118 input. When a conversion starts and WR is low, V IN_ is connected to sixteen 0.6pF capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. In addition, about 22pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge. The typical 32pF input capacitance allows source resistance as high as 800 without setup problems. For larger resistances, the acquisition time (tACQ) must be increased. Internal protection diodes, which clamp the analog input to VDD and GND, allow the channel input pins to swing from GND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than GND by 50mV. If the analog input exceeds 50mV beyond the supplies, limit the input current to no more than 2mA, as excessive current will degrade the conversion accuracy of the on channel. 22pF 10pF T/H MAX114 MAX114 MAX118 MAX118 Figure 9. RC Network Equivalent Input Model _ +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down Conversion Rate OUTPUT CODE FULL-SCALE TRANSITION 11111111 11111110 11111101 The maximum sampling rate (fMAX) for the MAX114/ MAX114/ MAX118 MAX118 is achieved in write-read mode (tRD < tINTL), and is calculated as follows: 1 fMAX = t WR + t RD + tRI + t ACQ fMAX = 1 250ns + 250ns + 150ns + 160ns 1LSB = VREF+ - VREF256 VREF256 00000011 00000010 00000001 fMAX = 1.23MHz where tWR = the write pulse width, t RD = the delay between write and read pulses, tRI = RD to INT delay, and tACQ = minimum acquisition time. Signal-to-Noise Ratio and Effective Number of Bits Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to all other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 195.8kHz sinusoid at a 1MHz rate. This FFT plot of the output shows the output level in various spectral bands. The effective resolution (or "effective number of bits") the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SINAD 1.76) / 6.02 (see Typical Operating Characteristics). VREF+ 00000000 VREF- 1 2 FS 3 INPUT VOLTAGE (LSBs) FS - 1LSB Figure 10. Transfer Function band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + .VN THD = 20log V1 where V1 is the fundamental RMS amplitude, and V2 through VN are the amplitudes of the 2nd through Nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC's noise floor. See the Signal-toNoise Ratio graph in Typical Operating Characteristics. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency _ 11 MAX114/MAX118 MAX114/MAX118 Transfer Function Figure 10 shows the MAX114/MAX118 MAX114/MAX118's nominal transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary with 1LSB = (VREF+ - VREF-) / 256. MAX114/MAX118 MAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down _Ordering Information (continued) PART TEMP. RANGE _Chip Information PIN-PACKAGE MAX118CPI MAX118CPI 0°C to +70°C 28 Wide Plastic DIP MAX118CAI MAX118CAI MAX118C/D MAX118C/D MAX118EPI MAX118EPI 0°C to +70°C 0°C to +70°C -40°C to +85°C MAX118EAI MAX118EAI MAX118MJI MAX118MJI -40°C to +85°C -55°C to +125°C TRANSISTOR COUNT: 2011 28 SSOP Dice* 28 Wide Plastic DIP 28 SSOP 28 Wide CERDIP* *Dice are specified at TA = +25°C, DC parameters only. *Contact factory for availability. _Pin Configurations TOP VIEW IN6 1 IN4 1 24 VDD IN3 2 23 PWRDN IN2 3 22 A0 IN1 4 21 A1 MAX114 MAX114 28 IN7 IN5 2 27 VDD IN4 3 26 PWRDN IN3 4 25 A0 IN2 5 MAX118 MAX118 24 A1 20 D7 IN1 6 D0 6 19 D6 MODE 7 D1 7 18 D5 D0 8 21 D6 D2 8 17 D4 D1 9 20 D5 MODE 5 23 A2 22 D7 D3 9 16 CS D2 10 19 D4 RD 10 15 WR/RDY D3 11 18 CS INT 11 14 REF+ RD 12 17 WR/RDY GND 12 13 REF- INT 13 16 REF+ GND 14 15 REF- DIP/SSOP DIP/SSOP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 _Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.