MAX038 MAX038CPP MAX038CWP MAX038C/D MAX038C MAX038-08 MAX038-09 MAX038-16B - Datasheet Archive
KIT ATION EVALU BLE AVAILA High-Frequency Waveform Generator The MAX038 is a high-frequency, precision function generator
19-0266; Rev 7; 8/07 KIT ATION EVALU BLE AVAILA High-Frequency Waveform Generator The MAX038 MAX038 is a high-frequency, precision function generator producing accurate, high-frequency triangle, sawtooth, sine, square, and pulse waveforms with a minimum of external components. The output frequency can be controlled over a frequency range of 0.1Hz to 20MHz by an internal 2.5V bandgap voltage reference and an external resistor and capacitor. The duty cycle can be varied over a wide range by applying a ±2.3V control signal, facilitating pulse-width modulation and the generation of sawtooth waveforms. Frequency modulation and frequency sweeping are achieved in the same way. The duty cycle and frequency controls are independent. Sine, square, or triangle waveforms can be selected at the output by setting the appropriate code at two TTL-compatible select pins. The output signal for all waveforms is a 2VP-P signal that is symmetrical around ground. The low-impedance output can drive up to ±20mA. The TTL-compatible SYNC output from the internal oscillator maintains a 50% duty cycle-regardless of the duty cycle of the other waveforms-to synchronize other devices in the system. The internal oscillator can be synchronized to an external TTL clock connected to PDI. Features 0.1Hz to 20MHz Operating Frequency Range Triangle, Sawtooth, Sine, Square, and Pulse Waveforms Independent Frequency and Duty-Cycle Adjustments 350 to 1 Frequency Sweep Range 15% to 85% Variable Duty Cycle Low-Impedance Output Buffer: 0.1 Low 200ppm/°C Temperature Drift Ordering Information PART TEMP RANGE MAX038CPP MAX038CPP PIN-PACKAGE 0°C to +70°C 20 Plastic DIP MAX038CWP MAX038CWP 0°C to +70°C 20 SO MAX038C/D MAX038C/D* 0°C to +70°C Dice * Contact factory prior to design. Applications Pin Configuration Precision Function Generators Voltage-Controlled Oscillators Frequency Modulators Pulse-Width Modulators Phase-Locked Loops Frequency Synthesizer FSK Generator-Sine and Square Waves TOP VIEW REF 1 20 V- GND 2 19 OUT A0 3 18 GND A1 4 MAX038 MAX038 COSC 5 17 V+ 16 DV+ GND 6 15 DGND DADJ 7 14 SYNC FADJ 8 13 GND 9 12 PDO IIN 10 11 PDI GND DIP/SO _ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX038 MAX038 General Description MAX038 MAX038 High-Frequency Waveform Generator ABSOLUTE MAXIMUM RATINGS V+ to GND .-0.3V to +6V DV+ to DGND.-0.3V to +6V V- to GND .+0.3V to -6V Pin Voltages IIN, FADJ, DADJ, PDO .(V- - 0.3V) to (V+ + 0.3V) COSC .+0.3V to V A0, A1, PDI, SYNC, REF.-0.3V to V+ GND to DGND .±0.3V Maximum Current into Any Pin .±50mA OUT, REF Short-Circuit Duration to GND, V+, V- .30s Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 11.11mW/°C above +70°C) .889mW SO (derate 10.00mW/°C above +70°C) .800mW CERDIP (derate 11.11mW/°C above +70°C) .889mW Operating Temperature Ranges MAX038C MAX038C_ _ .0°C to +70°C Maximum Junction Temperature . .+150°C Storage Temperature Range .-65°C to +150°C Lead Temperature (soldering, 10s) .+300°C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, GND = D GND = 0V, V+ = DV+ = 5V, V- = -5V, V DADJ = V FADJ = V PDI = V PDO = 0V, C F = 100pF, RIN = 25k RL = 1k, CL = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX CF 15pF, IIN = 500µA 20.0 40.0 VFADJ = 0V 2.50 750 VFADJ = -3V 1.25 375 UNITS FREQUENCY CHARACTERISTICS Maximum Operating Frequency Frequency Programming Current IIN Offset Voltage Frequency Temperature Coefficient Frequency Power-Supply Rejection Fo IIN VIN ±1.0 MHz ±2.0 Fo/°C VFADJ = 0V 600 Fo/°C VFADJ = -3V 200 (Fo/Fo) V+ V- = -5V, V+ = 4.75V to 5.25V ±0.4 V+ = 5V, V- = -4.75V to -5.25V ±0.2 mV ±2.00 (Fo/Fo) V- µA ±1.00 ppm/°C %/V OUTPUT AMPLIFIER (applies to all waveforms) Output Peak-to-Peak Symmetry VOUT ±4 Output Resistance ROUT 0.1 Output Short-Circuit Current IOUT Short circuit to GND mV 0.2 40 mA SQUARE-WAVE OUTPUT (RL = 100) Amplitude VOUT 1.9 2.0 Rise Time tR 10% to 90% 12 Fall Time tF 90% to 10% 12 Duty Cycle dc VDADJ = 0V, dc = tON/t x 100% 2.1 VP-P ns ns 47 50 53 % 1.9 2.0 2.1 VP-P TRIANGLE-WAVE OUTPUT (RL = 100) Amplitude VOUT Nonlinearity Duty Cycle FO = 100kHz, 5% to 95% dc VDADJ = 0V (Note 1) 0.5 % 47 50 53 % 1.9 2.0 2.1 VP-P SINE-WAVE OUTPUT (RL = 100) VOUT Total Harmonic Distortion 2 THD CF = 1000pF, FO = 100kHz 2.0 _ % High-Frequency Waveform Generator (Circuit of Figure 1, GND = D GND = 0V, V+ = DV+ = 5V, V- = -5V, V DADJ = V FADJ = V PDI = V PDO = 0V, C F = 100pF, RIN = 25k RL = 1k, CL = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL SYNC OUTPUT Output Low Voltage VOL Output High Voltage VOH Rise Time tR Fall Time tF Duty Cycle dcSYNC DUTY-CYCLE ADJUSTMENT (DADJ) DADJ Input Current IDADJ DADJ Voltage Range VDADJ Duty-Cycle Adjustment Range dc DADJ Nonlinearity dc/VFADJ Change in Output Frequency Fo/VDADJ with DADJ Maximum DADJ Modulating FDC Frequency FREQUENCY ADJUSTMENT (FADJ) FADJ Input Current IFADJ FADJ Voltage Range VFADJ Frequency Sweep Range Fo FM Nonlinearity with FADJ Fo/VFADJ Change in Duty Cycle with FADJ dc/VFADJ Maximum FADJ Modulating FF Frequency VOLTAGE REFERENCE Output Voltage Temperature Coefficient Load Regulation VREF Input High Voltage ISINK = 3.2mA ISOURCE = 400µA 10% to 90%, RL = 3k, CL = 15pF 90% to 10%, RL = 3k, CL = 15pF MIN MAX UNITS 0.3 3.5 10 10 50 0.4 V V ns ns % 250 ±2.3 320 2.8 190 -2.3V VDADJ +2.3V -2V VDADJ +2V TYP 2 85 4 µA V % % ±2.5 ±8 % 15 -2V VDADJ +2V 2 190 -2.4V VFADJ +2.4V -2V VFADJ +2V -2V VFADJ +2V 250 ±2.4 ±70 ±0.2 ±2 VREF/V+ MHz 320 2 IREF = 0 2.48 2.50 VREF/°C VREF/IREF Line Regulation LOGIC INPUTS (A0, A1, PDI) Input Low Voltage CONDITIONS MHz 2.52 20 0mA IREF 4mA (source) 1 -100µA IREF 0µA (sink) 1 4.75V V+ 5.25V (Note 2) V ppm/°C 2 4 1 µA V % % % mV/mA mV/V 0.8 VIL VIH 2 V 2.4 V Input Current (A0, A1) IIL, IIH VA0, VA1 = VIL, VIH ±5 µA Input Current (PDI) POWER SUPPLY Positive Supply Voltage IIL, IIH VPDI = VIL, VIH ±25 µA V+ 4.75 5.25 V DV+ 4.75 5.25 V Negative Supply Voltage V -4.75 -5.25 V Positive Supply Current I+ 35 45 mA IDV+ 1 2 mA I 45 55 mA SYNC Supply Voltage SYNC Supply Current Negative Supply Current Note 1: Guaranteed by duty-cycle test on square wave. Note 2: VREF is independent of V-. _ 3 MAX038 MAX038 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k/, CL = 20pF, TA = +25°C, unless otherwise noted.) NORMALIZED OUTPUT FREQUENCY OUTPUT FREQUENCY vs. FADJ VOLTAGE vs. IIN CURRENT MAX038-08 MAX038-08 10M 1M 3.3nF 100k FOUT NORMALIZED 330pF OUTPUT FREQUENCY (Hz) 1.6 100pF 1.4 1.2 1.0 0.8 0.6 33nF 0.4 100nF 10k I IN = 100 A, COSC = 1000pF 1.8 33pF MAX038-09 MAX038-09 2.0 100M 0.2 0 -3 1k -2 0 -1 1F 2 1 3 V FADJ (V) 3.3 F DUTY CYCLE vs. DADJ VOLTAGE 10 F 100 90 47 F 100 F 1 0.1 1 10 100 1000 80 DUTY CYCLE (%) 10 MAX038-16B MAX038-16B 100 IIN CURRENT ( A) 70 60 50 40 30 20 10 I IN = 200 A 0 -3 -2 0 -1 1 2 3 DADJ (V) I IN = 25 A I IN = 50 A 1.00 0.95 I IN = 100 A I IN = 250 A 0.90 I IN = 500 A I IN = 500 A 1.5 DUTY-CYCLE LINEARITY ERROR (%) I IN = 10 A 1.05 2.0 MAX038-17 MAX038-17 1.10 DUTY-CYCLE LINEARITY vs. DADJ VOLTAGE 1.0 0.5 I IN = 250 A 0 I IN = 100 A -0.5 -1.0 -1.5 I IN = 50 A I IN = 25 A I IN = 10 A -2.0 -2.5 0.85 -2.0 DADJ (V) 4 MAX038-18 MAX038-18 NORMALIZED OUTPUT FREQUENCY vs. DADJ VOLTAGE NORMALIZED OUTPUT FREQUENCY MAX038 MAX038 High-Frequency Waveform Generator -1.0 0 1.0 1.5 DADJ (V) _ 2.5 High-Frequency Waveform Generator SINE WAVE THD vs. FREQUENCY SINE-WAVE OUTPUT (50Hz) MAX038 MAX038 toc01 7 6 THD (%) 5 4 3 2 1 0 100 1k 10k 100k 1M FREQUENCY (Hz) SINE-WAVE OUTPUT (20MHz) IIN = 400A CF = 20pF TRIANGLE-WAVE OUTPUT (20MHz) IIN = 400A CF = 20pF 10M TOP: OUTPUT 50Hz = Fo BOTTOM: SYNC IIN = 50A CF = 1F TRIANGLE-WAVE OUTPUT (50Hz) TOP: OUTPUT 50Hz = F o BOTTOM: SYNC IIN = 50A C F = 1F SQUARE-WAVE OUTPUT (50Hz) TOP: OUTPUT 50Hz = Fo BOTTOM: SYNC IIN = 50A CF = 1F _ 5 MAX038 MAX038 Typical Operating Characteristics (continued) (Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k/, CL = 20pF, TA = +25°C, unless otherwise noted.) MAX038 MAX038 High-Frequency Waveform Generator Typical Operating Characteristics (continued) (Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k/, CL = 20pF, TA = +25°C, unless otherwise noted.) SQUARE-WAVE OUTPUT (20MHz) FREQUENCY MODULATION USING FADJ 0.5V 0V -0.5V IIN = 400A CF = 20pF TOP: OUTPUT BOTTOM: FADJ FREQUENCY MODULATION USING IIN FREQUENCY MODULATION USING IIN TOP: OUTPUT BOTTOM: IIN TOP: OUTPUT BOTTOM: IIN PULSE-WIDTH MODULATION USING DADJ +1V 0V -1V +2V 0V -2V TOP: SQUARE-WAVE OUT, 2VP-P BOTTOM: VDADJ, -2V to +2.3V 6 _ High-Frequency Waveform Generator OUTPUT SPECTRUM, SINE WAVE (Fo = 11.5MHz) 0 -20 -20 ATTENUATION (dB) ATTENUATION (dB) RIN = 51k (VIN = 2.5V), CF = 0.01F, VDADJ = 50mV, VFADJ = 0V -10 MAX038 MAX038 12B RIN = 15k (VIN = 2.5V), CF = 20pF, VDADJ = 40mV, VFADJ = -3V MAX038-12A MAX038-12A 0 -10 OUTPUT SPECTRUM, SINE WAVE (Fo = 5.9kHz) -30 -40 -50 -60 -70 -30 -40 -50 -60 -70 -80 -80 -90 -90 -100 -100 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) FREQUENCY (kHz) Pin Description PIN NAME 1 REF 2.50V bandgap voltage reference output 2, 6, 9, 11, 18 GND Ground* 3 A0 Waveform selection input; TTL/CMOS compatible 4 A1 Waveform selection input; TTL/CMOS compatible 5 COSC 7 DADJ Duty-cycle adjust input 8 FADJ Frequency adjust input 10 IIN 12 PDO Phase detector output. Connect to GND if phase detector is not used. 13 PDI Phase detector reference clock input. Connect to GND if phase detector is not used. 14 SYNC 15 DGND 16 DV+ 17 V+ 19 OUT 20 V- FUNCTION External capacitor connection Current input for frequency control TTL/CMOS-compatible output, referenced between DGND and DV+. Permits the internal oscillator to be synchronized with an external signal. Leave open if unused. Digital ground Digital +5V supply input. Can be left open if SYNC is not used. +5V supply input Sine, square, or triangle output -5V supply input *The five GND pins are not internally connected. Connect all five GND pins to a quiet ground close to the device. A ground plane is recommended (see Layout Considerations). _ 7 MAX038 MAX038 Typical Operating Characteristics (continued) (Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k/, CL = 20pF, TA = +25°C, unless otherwise noted.) MAX038 MAX038 High-Frequency Waveform Generator 3 5 6 TRIANGLE COSC GND OSCILLATOR CF OSC A OSC B 4 A0 A1 SINE SINE SHAPER OUT TRIANGLE 19 MUX SQUARE 8 7 10 FADJ DADJ OSCILLATOR CURRENT GENERATOR RL CL COMPARATOR IIN MAX038 MAX038 RF RD RIN -250A -250A SYNC 1 * +5V -5V REF 17 20 PDI PHASE DETECTOR 13 GND DGND DV+ 16 15 * = SIGNAL DIRECTION, NOT POLARITY * 12 2.5V VOLTAGE REFERENCE V+ V- 2, 9, 11, 18 14 PDO COMPARATOR +5V = BYPASS CAPACITORS ARE 1F CERAMIC OR 1F ELECTROLYTIC IN PARALLEL WITH 1nF CERAMIC. Figure 1. Block Diagram and Basic Operating Circuit Detailed Description The MAX038 MAX038 is a high-frequency function generator that produces low-distortion sine, triangle, sawtooth, or square (pulse) waveforms at frequencies from less than 1Hz to 20MHz or more, using a minimum of external components. Frequency and duty cycle can be independently controlled by programming the current, voltage, or resistance. The desired output waveform is selected under logic control by setting the appropriate code at the A0 and A1 inputs. A SYNC output and phase detector are included to simplify designs requiring tracking to an external signal source. The MAX038 MAX038 operates with ±5V ±5% power supplies. The basic oscillator is a relaxation type that operates by alternately charging and discharging a capacitor, CF, 8 with constant currents, simultaneously producing a triangle wave and a square wave (Figure 1). The charging and discharging currents are controlled by the current flowing into IIN, and are modulated by the voltages applied to FADJ and DADJ. The current into IIN can be varied from 2µA to 750µA, producing more than two decades of frequency for any value of CF. Applying ±2.4V to FADJ changes the nominal frequency (with VFADJ = 0V) by ±70%; this procedure can be used for fine control. Duty cycle (the percentage of time that the output waveform is positive) can be controlled from 10% to 90% by applying ±2.3V to DADJ. This voltage changes the CF charging and discharging current ratio while maintaining nearly constant frequency. _ High-Frequency Waveform Generator The triangle wave is also sent to a comparator that produces a high-speed square-wave SYNC waveform that can be used to synchronize other oscillators. The SYNC circuit has separate power-supply leads and can be disabled. Two other phase-quadrature square waves are generated in the basic oscillator and sent to one side of an "exclusive-OR" phase detector. The other side of the phase-detector input (PDI) can be connected to an external oscillator. The phase-detector output (PDO) is a current source that can be connected directly to FADJ to synchronize the MAX038 MAX038 with the external oscillator. Waveform Selection The MAX038 MAX038 can produce either sine, square, or triangle waveforms. The TTL/CMOS-logic address pins (A0 and A1) set the waveform, as shown below: A0 A1 WAVEFORM X 1 Sine wave 0 0 Square wave 1 0 Triangle wave X = Don't care. Waveform switching can be done at any time, without regard to the phase of the output. Switching occurs within 0.3µs, but there may be a small transient in the output waveform that lasts 0.5µs. Waveform Timing Output Frequency The output frequency is determined by the current injected into the IIN pin, the COSC capacitance (to ground), and the voltage on the FADJ pin. When VFADJ = 0V, the fundamental output frequency (Fo) is given by the formula: Fo (MHz) = IIN (µA) ÷ CF (pF)  The period (to) is:  to (µs) = CF (pF) ÷ IIN (µA) where: IIN = current injected into IIN (between 2µA and 750µA) CF = capacitance connected to COSC and GND (20pF to >100µF). For example: 0.5MHz = 100µA ÷ 200pF and 2µs = 200pF ÷ 100µA Optimum performance is achieved with IIN between 10µA and 400µA, although linearity is good with IIN between 2µA and 750µA. Current levels outside of this range are not recommended. For fixed-frequency operation, set IIN to approximately 100µA and select a suitable capacitor value. This current produces the lowest temperature coefficient, and produces the lowest frequency shift when varying the duty cycle. The capacitance can range from 20pF to more than 100µF, but stray circuit capacitance must be minimized by using short traces. Surround the COSC pin and the trace leading to it with a ground plane to minimize coupling of extraneous signals to this node. Oscillation above 20MHz is possible, but waveform distortion increases under these conditions. The low frequency limit is set by the leakage of the COSC capacitor and by the required accuracy of the output frequency. Lowest frequency operation with good accuracy is usually achieved with 10µF or greater non-polarized capacitors. An internal closed-loop amplifier forces IIN to virtual ground, with an input offset voltage less than ±2mV. IIN may be driven with either a current source (IIN), or a voltage (VIN) in series with a resistor (RIN). (A resistor between REF and IIN provides a convenient method of generating IIN: IIN = VREF/RIN.) When using a voltage in series with a resistor, the formula for the oscillator frequency is: Fo (MHz) = VIN ÷ [RIN x CF (pF)]  and: to (µs) = CF(pF) x RIN ÷ VIN  _ 9 MAX038 MAX038 A stable 2.5V reference voltage, REF, allows simple determination of IIN, FADJ, or DADJ with fixed resistors, and permits adjustable operation when potentiometers are connected from each of these inputs to REF. FADJ and/or DADJ can be grounded, producing the nominal frequency with a 50% duty cycle. The output frequency is inversely proportional to capacitor CF. CF values can be selected to produce frequencies above 20MHz. A sine-shaping circuit converts the oscillator triangle wave into a low-distortion sine wave with constant amplitude. The triangle, square, and sine waves are input to a multiplexer. Two address lines, A0 and A1, control which of the three waveforms is selected. The output amplifier produces a constant 2VP-P amplitude (±1V), regardless of wave shape or frequency. MAX038 MAX038 High-Frequency Waveform Generator When the MAX038 MAX038's frequency is controlled by a voltage source (VIN) in series with a fixed resistor (RIN), the output frequency is a direct function of VIN as shown in the above equations. Varying VIN modulates the oscillator frequency. For example, using a 10k resistor for RIN and sweeping VIN from 20mV to 7.5V produces large frequency deviations (up to 375:1). Select RIN so that IIN stays within the 2µA to 750µA range. The bandwidth of the IIN control amplifier, which limits the modulating signal's highest frequency, is typically 2MHz. IIN can be used as a summing point to add or subtract currents from several sources. This allows the output frequency to be a function of the sum of several variables. As VIN approaches 0V, the IIN error increases due to the offset voltage of IIN. Output frequency will be offset 1% from its final value for 10 seconds after power-up. FADJ Input The output frequency can be modulated by FADJ, which is intended principally for fine frequency control, usually inside phase-locked loops. Once the funda-mental, or center frequency (Fo) is set by IIN, it may be changed further by setting FADJ to a voltage other than 0V. This voltage can vary from -2.4V to +2.4V, causing the output frequency to vary from 1.7 to 0.30 times the value when FADJ is 0V (F o ±70%). Voltages beyond ±2.4V can cause instability or cause the frequency change to reverse slope. The voltage on FADJ required to cause the output to deviate from Fo by Dx (expressed in %) is given by the formula: VFADJ = -0.0343 x Dx  where VFADJ, the voltage on FADJ, is between -2.4V and +2.4V. Note: While IIN is directly proportional to the fundamental, or center frequency (Fo), VFADJ is linearly related to % deviation from Fo. VFADJ goes to either side of 0V, corresponding to plus and minus deviation. The voltage on FADJ for any frequency is given by the formula: VFADJ = (Fo - Fx) ÷ (0.2915 x Fo)  where: Fx = output frequency Fo = frequency when VFADJ = 0V. Likewise, for period calculations: VFADJ = 3.43 x (tx- to) ÷ tx where: tx = output period to = period when VFADJ = 0V. 10  Conversely, if VFADJ is known, the frequency is given by: Fx = Fo x (1 - [0.2915 x VFADJ]) and the period (tx) is: tx = to ÷ (1 - [0.2915 x VFADJ])   Programming FADJ FADJ has a 250µA constant current sink to V- that must be furnished by the voltage source. The source is usually an op-amp output, and the temperature coefficient of the current sink becomes unimportant. For manual adjustment of the deviation, a variable resistor can be used to set VFADJ, but then the 250µA current sink's temperature coefficient becomes significant. Since external resistors cannot match the internal temperature-coefficient curve, using external resistors to program V FADJ is intended only for manual operation, when the operator can correct for any errors. This restriction does not apply when VFADJ is a true voltage source. A variable resistor, RF, connected between REF (+2.5V) and FADJ provides a convenient means of manually setting the frequency deviation. The resistance value (RF) is: RF = (VREF - VFADJ) ÷ 250µA  VREF and VFADJ are signed numbers, so use correct algebraic convention. For example, if VFADJ is -2.0V (+58.3% deviation), the formula becomes: RF = (+2.5V - (-2.0V) ÷ 250µA = (4.5V) ÷ 250µA = 18k Disabling FADJ The FADJ circuit adds a small temperature coefficient to the output frequency. For critical open-loop applications, it can be turned off by connecting FADJ to GND (not REF) through a 12k resistor (R1 in Figure 2). The 250µA current sink at FADJ causes -3V to be developed across this resistor, producing two results. First, the FADJ circuit remains in its linear region, but disconnects itself from the main oscillator, improving temperature stability. Second, the oscillator frequency doubles. If FADJ is turned off in this manner, be sure to correct equations 1-4 and 6-9 above, and 12 and 14 below by doubling Fo or halving to. Although this method doubles the normal output frequency, it does not double the upper frequency limit. Do not operate FADJ open circuit or with voltages more negative than -3.5V. Doing so may cause transistor saturation inside the IC, leading to unwanted changes in frequency and duty cycle. _ High-Frequency Waveform Generator 20 FREQUENCY 1 C1 1F C3 1nF 10 8 DADJ IIN MAX038 MAX038 OUT DV+ DGND SYNC CF 3 19 C2 1F PDI COSC PDO 16 13 12 R3 +2.5V 100k MAX038 MAX038 R2 50 SINE-WAVE OUTPUT R7 100k R5 100k N.C. 15 14 R4 100k REF FADJ R1 12k 5 2.5V 4 V+ A1 AO 7 RIN 20k REF 17 V- MAX038 MAX038 PRECISION DUTY-CYCLE ADJUSTMENT CIRCUIT 5V +5V R6 5k N.C. Fo = 2 x 2.5V RIN x CF DADJ GND GND GND GND GND 6 2 9 11 18 ADJUST R6 FOR MINIMUM SINE-WAVE DISTORTION Figure 2. Operating Circuit with Sine-Wave Output and 50% Duty Cycle; SYNC and FADJ Disabled With FADJ disabled, the output frequency can still be changed by modulating IIN. Swept Frequency Operation The output frequency can be swept by applying a varying signal to IIN or FADJ. IIN has a wider range, slightly slower response, lower temperature coefficient, and requires a single polarity current source. FADJ may be used when the swept range is less than ±70% of the center frequency, and it is suitable for phase-locked loops and other low-deviation, high-accuracy closedloop controls. It uses a sweeping voltage symmetrical about ground. Connecting a resistive network between REF, the voltage source, and FADJ or IIN is a convenient means of offsetting the sweep voltage. Duty Cycle The voltage on DADJ controls the waveform duty cycle (defined as the percentage of time that the output waveform is positive). Normally, VDADJ = 0V, and the duty cycle is 50% (Figure 2). Varying this voltage from +2.3V to -2.3V causes the output duty cycle to vary from 15% to 85%, about -15% per volt. Voltages beyond ±2.3V can shift the output frequency and/or cause instability. DADJ can be used to reduce the sine-wave distortion. The unadjusted duty cycle (VDADJ = 0V) is 50% ±2%; any deviation from exactly 50% causes even order harmonics to be generated. By applying a small adjustable voltage (typically less than ±100mV) to VDADJ, exact symmetry can be attained and the distortion can be minimized (see Figure 2). The voltage on DADJ needed to produce a specific duty cycle is given by the formula: VDADJ = (50% - dc) x 0.0575  or: VDADJ = (0.5 - [tON ÷ to]) x 5.75  where: VDADJ = DADJ voltage (observe the polarity) dc = duty cycle (in %) tON = ON (positive) time to = waveform period. Conversely, if VDADJ is known, the duty cycle and ON time are given by: dc = 50% - (VDADJ x 17.4) tON = to x (0.5 - [VDADJ x 0.174])   _ 11 MAX038 MAX038 High-Frequency Waveform Generator Programming DADJ DADJ is similar to FADJ; it has a 250µA constant current sink to V- that must be furnished by the voltage source. The source is usually an op-amp output, and the temperature coefficient of the current sink becomes unimportant. For manual adjustment of the duty cycle, a variable resistor can be used to set VDADJ, but then the 250µA current sink's temperature coefficient becomes significant. Since external resistors cannot match the internal temperature-coefficient curve, using external resistors to program VDADJ is intended only for manual operation, when the operator can correct for any errors. This restriction does not apply when VDADJ is a true voltage source. A variable resistor, RD, connected between REF (+2.5V) and DADJ provides a convenient means of manually setting the duty cycle. The resistance value (RD) is: RD = (VREF - VDADJ) ÷ 250µA  Note that both VREF and VDADJ are signed values, so observe correct algebraic convention. For example, if VDADJ is -1.5V (23% duty cycle), the formula becomes: RD = (+2.5V - (-1.5V) ÷ 250µA = (4.0V) ÷ 250µA = 16k Varying the duty cycle in the range 15% to 85% has minimal effect on the output frequency-typically less than 2% when 25µA < IIN < 250µA. The DADJ circuit is wideband, and can be modulated at up to 2MHz (see photos, Typical Operating Characteristics). Output The output amplitude is fixed at 2VP-P, symmetrical around ground, for all output waveforms. OUT has an output resistance of under 0.1, and can drive ±20mA with up to a 50pF load. Isolate higher output capacitance from OUT with a resistor (typically 50) or buffer amplifier. Reference Voltage REF is a stable 2.50V bandgap voltage reference capable of sourcing 4mA or sinking 100µA. It is principally used to furnish a stable current to IIN or to bias DADJ and FADJ. It can also be used for other applications external to the MAX038 MAX038. Bypass REF with 100nF to minimize noise. Selecting Resistors and Capacitors The MAX038 MAX038 produces a stable output frequency over time and temperature, but the capacitor and resistors that determine frequency can degrade performance if they are not carefully chosen. Resistors should be metal film, 1% or better. Capacitors should be chosen 12 for low temperature coefficient over the whole temperature range. NPO ceramics are usually satisfactory. The voltage on COSC is a triangle wave that varies between 0V and -1V. Polarized capacitors are generally not recommended (because of their outrageous temperature dependence and leakage currents), but if they are used, the negative terminal should be connected to COSC and the positive terminal to GND. Large-value capacitors, necessary for very low frequencies, should be chosen with care, since potentially large leakage currents and high dielectric absorption can interfere with the orderly charge and discharge of CF. If possible, for a given frequency, use lower IIN currents to reduce the size of the capacitor. SYNC Output SYNC is a TTL/CMOS-compatible output that can be used to synchronize external circuits. The SYNC output is a square wave whose rising edge coincides with the output rising sine or triangle wave as it crosses through 0V. When the square wave is selected, the rising edge of SYNC occurs in the middle of the positive half of the output square wave, effectively 90° ahead of the output. The SYNC duty cycle is fixed at 50% and is indepen-dent of the DADJ control. Because SYNC is a very-high-speed TTL output, the high-speed transient currents in DGND and DV+ can radiate energy into the output circuit, causing a narrow spike in the output waveform. (This spike is difficult to see with oscilloscopes having less than 100MHz bandwidth). The inductance and capacitance of IC sockets tend to amplify this effect, so sockets are not recommended when SYNC is on. SYNC is powered from separate ground and supply pins (DGND and DV+), and it can be turned off by making DV+ open circuit. If synchronization of external circuits is not used, turning off SYNC by DV+ opening eliminates the spike. Phase Detectors Internal Phase Detector The MAX038 MAX038 contains a TTL/CMOS phase detector that can be used in a phase-locked loop (PLL) to synchronize its output to an external signal (Figure 3). The external source is connected to the phase-detector input (PDI) and the phase-detector output is taken from PDO. PDO is the output of an exclusive-OR gate, and produces a rectangular current waveform at the MAX038 MAX038 output frequency, even with PDI grounded. PDO is normally connected to FADJ and a resistor, RPD, and a capacitor CPD, to GND. RPD sets the gain of the phase detector, while the capacitor attenuates high-frequency components and forms a pole in the phase-locked loop filter. _ High-Frequency Waveform Generator CENTER FREQUENCY RD 14 1 16 17 SYNC DV+ V+ VA1 7 10 8 3 4 DADJ IIN FADJ MAX038 MAX038 OUT 19 CPD CF PDI COSC PDO ROUT 50 RF OUTPUT RPD 5 The phase error (deviation from phase quadrature) depends on the open-loop gain of the PLL and the initial frequency deviation of the oscillator from the external signal source. The oscillator conversion gain (Ko) is:  KO = o ÷ VFADJ which, from equation  is: KO = 0.2915 x o (radians/sec)  20 A0 REF charge CPD, so the rate at which VFADJ changes (the loop bandwidth) is inversely proportional to CPD. C1 1F C2 1F 13 12 GND GND GND GND GND DGND 2 6 9 11 18 15 EXTERNAL OSC INPUT Figure 3. Phase-Locked Loop Using Internal Phase Detector PDO is a rectangular current-pulse train, alternating between 0µA and 500µA. It has a 50% duty cycle when the MAX038 MAX038 output and PDI are in phase-quadrature (90° out of phase). The duty cycle approaches 100% as the phase difference approaches 180° and conversely, approaches 0% as the phase difference approaches 0°. The gain of the phase detector (KD) can be expressed as: KD = 0.318 x RPD (volts/radian)  where RPD = phase-detector gain-setting resistor. When the loop is in lock, the input signals to the phase detector are in approximate phase quadrature, the duty cycle is 50%, and the average current at PDO is 250µA (the current sink of FADJ). This current is divided between FADJ and RPD; 250µA always goes into FADJ and any difference current is developed across RPD, creating VFADJ (both polarities). For example, as the phase difference increases, PDO duty cycle increases, the average current increases, and the voltage on RPD (and V FADJ ) becomes more positive. This in turn decreases the oscillator frequency, reducing the phase difference, thus maintaining phase lock. The higher RPD is, the greater VFADJ is for a given phase difference; in other words, the greater the loop gain, the less the capture range. The current from PDO must also The loop gain of the PLL system (KV) is: KV= KD x KO  where: KD = detector gain KO = oscillator gain. With a loop filter having a response F(s), the open-loop transfer function, T(s), is:  T(s) = KD x KO x F(s) ÷ s Using linear feedback analysis techniques, the closedloop transfer characteristic, H(s), can be related to the open-loop transfer function as follows: H(s) = T(s) ÷ [1+ T(s)]  The transient performance and the frequency response of the PLL depends on the choice of the filter characteristic, F(s). When the MAX038 MAX038 internal phase detector is not used, PDI and PDO should be connected to GND. External Phase Detectors External phase detectors may be used instead of the internal phase detector. The external phase detector shown in Figure 4 duplicates the action of the MAX038 MAX038's internal phase detector, but the optional ÷N circuit can be placed between the SYNC output and the phase detector in applications requiring synchronizing to an exact multiple of the external oscillator. The resistor network consisting of R4, R5, and R6 sets the sync range, while capacitor C4 sets the capture range. Note that this type of phase detector (with or without the ÷N circuit) locks onto harmonics of the external oscillator as well as the fundamental. With no external oscillator input, this circuit can be unpredictable, depending on the state of the external input DC level. Figure 4 shows a frequency phase detector that locks onto only the fundamental of the external oscillator. With no external oscillator input, the output of the frequency phase detector is a positive DC voltage, and the oscillations are at the lowest frequency as set by R4, R5, and R6. _ 13 MAX038 MAX038 +5V -5V MAX038 MAX038 High-Frequency Waveform Generator -5V +5V C1 1F C2 1 F +N 14 CENTER FREQUENCY 1 16 17 20 SYNC DV+ V+ VA0 REF A1 R2 3 4 CW 7 R3 PHASE DETECTOR 10 R4 8 R5 OFFSET EXTERNAL OSC INPUT MAX038 MAX038 DADJ IIN OUT -5V RF OUTPUT FADJ R6 GAIN 5 R1 50 19 PDI COSC PDO 13 12 GND GND GND GND GND DGND 2 6 9 11 18 15 C4 CAPTURE Figure 4. Phase-Locked Loop Using External Phase Detector +5V -5V C1 1 F C2 1F +N 14 CENTER FREQUENCY 1 16 17 SYNC DV+ V+ 20 VA0 REF R2 A1 3 4 CW 7 R3 10 R4 EXTERNAL OSC INPUT 8 R5 OFFSET DADJ IIN -5V C4 CAPTURE FREQUENCY OUT 19 PDI COSC PDO 13 12 GND GND GND GND GND DGND 2 6 9 11 18 15 Figure 5. Phase-Locked Loop Using External Frequency Phase Detector 14 R1 50 RF OUTPUT FADJ R6 GAIN 5 MAX038 MAX038 _ 35pF 28 LD FIN PD1OUT VDD VSS RA0 N10 N11 OSCOUT OSCIN PDV PDR RA2 RA1 1 PDR PDV 0.1F 3.3M 3 2 7 4 6 0.1F MAX427 MAX427 0.1F 33k BIT7 3.3M VDD 8.192MHz 1kHz 2kHz 4kHz 8kHz 16kHz FV BIT8 BIT6 N8 MC145151 MC145151 N9 T/R N12 N13 BIT9 BIT5 N0 BIT10 BIT10 BIT4 N1 BIT11 BIT11 BIT3 N N6 BIT2 33k BIT12 BIT12 N7 14 VREF 20pF 512kHz 1.024MHz 2.048MHz 4.096MHz 8.192MHz MX7541 MX7541 N3 N2 BIT1 N4 N5 GND 15 32kHz 64kHz 128kHz 256kHz RFB OUT2 10 9 OUT1 _ 18 1 0.1F 7.5k 10k 0.1F MAX412 MAX412 1 2.5V +2.5V 3.33k 0.1F 2 0V TO 2.5V 3 2N3904 2N3904 8 35 pF 4 7 10 1 1N914 1N914 OUT V- V+ DV+ DADJ IIN GND1 GND1 PDO PDI SYNC GND1 FADJ DGND COSC MAX038 MAX038 A0 A1 GND GND1 VREF 2A to 750A 2N3906 2N3906 WAVEFORM SELECT MAX412 MAX412 2.7M 5 6 1k 11 20 0.1 F 100 50.0 56pF 110pF -5V SYNC OUTPUT SIGNAL OUTPUT 56pF 50 FREQUENCY SYNTHESIZER 1kHz RESOLUTION; 8kHz TO 16.383MHz 0.1F 0.1F 50, 50MHz LOWPASS FILTER 220nH 220nH +5V MAX038 MAX038 1k High-Frequency Waveform Generator Figure 6. Crystal-Controlled, Digitally Programmed Frequency Synthesizer-8kHz to 16MHz with 1kHz Resolution 15 MAX038 MAX038 High-Frequency Waveform Generator Layout Considerations Realizing the full performance of the MAX038 MAX038 requires careful attention to power-supply bypassing and board layout. Use a low-impedance ground plane, and connect all five GND pins directly to it. Bypass V+ and Vdirectly to the ground plane with 1µF ceramic capacitors or 1µF tantalum capacitors in parallel with 1nF ceramics. Keep capacitor leads short (especially with the 1nF ceramics) to minimize series inductance. If SYNC is used, DV+ must be connected to V+, DGND must be connected to the ground plane, and a second 1nF ceramic should be connected as close as possible between DV+ and DGND (pins 16 and 15). It is not necessary to use a separate supply or run separate traces to DV+. If SYNC is disabled, leave DV+ open. Do not open DGND. Minimize the trace area around COSC (and the ground plane area under COSC) to reduce parasitic capacitance, and surround this trace with ground to prevent coupling with other signals. Take similar precautions with DADJ, FADJ, and IIN. Place CF so its connection to the ground plane is close to pin 6 (GND). Applications Information Frequency Synthesizer Figure 6 shows a frequency synthesizer that produces accurate and stable sine, square, or triangle waves with a frequency range of 8kHz to 16.383MHz in 1kHz increments. A Motorola MC145151 MC145151 provides the crystal-controlled oscillator, the ÷N circuit, and a high-speed phase detector. The manual switches set the output frequency; opening any switch increases the output frequency. Each switch controls both the ÷N output and an MX7541 MX7541 12-bit DAC, whose output is converted to a current by using both halves of the MAX412 MAX412 op amp. This current goes to the MAX038 MAX038 IIN pin, setting its coarse frequency over a very wide range. Fine frequency control (and phase lock) is achieved from the MC145151 MC145151 phase detector through the differential amplifier and lowpass filter, U5. The phase detec- tor compares the ÷N output with the MAX038 MAX038 SYNC output and sends differential phase information to U5. U5's single-ended output is summed with an offset into the FADJ input. (Using the DAC and the IIN pin for coarse frequency control allows the FADJ pin to have very fine control with reasonably fast response to switch changes.) A 50MHz, 50 lowpass filter in the output allows passage of 16MHz square waves and triangle waves with reasonable fidelity, while stopping high-frequency noise generated by the ÷N circuit. Chip Topography GND REF V- OUT AO GND V+ A1 DV+ DGND COSC 0.118" (2.997mm) SYNC GND DADJ PDI FADJ GND IIN GND 0.106" (2.692mm) PDO TRANSISTOR COUNT: 855 SUBSTRATE CONNECTED TO GND Package Information For the latest package outline information, go to www.maxim-ic.com/packages. Revision History Pages changed at Rev 7: 13, 16 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 _Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc.