DA9142 MAS9142 GSM900 DCS1800 PF08103B TSSOP16 LDC15D BAT62 MO-153 EIA-481 - Datasheet Archive

 

4 January, 2002 MAS9142 Power Amplifier Controller (PAC) and 2.8 V, 50 mA LDO Voltage Regulator · Temperature Compensation

 

DA9142 DA9142.002 4 January, 2002 MAS9142 MAS9142 Power Amplifier Controller (PAC) and 2.8 V, 50 mA LDO Voltage Regulator · Temperature Compensation of Sensor Signal · Bias Current Source for Detector Diodes · Applicable for a Wide Range of Power Amplifiers · Low Noise LDO Regulator Included DESCRIPTION MAS9142 MAS9142 is designed for use in both the GSM900 GSM900 and DCS1800 DCS1800 systems and particularly with Hitachi PF08103B PF08103B power amplifier module. Other PA modules can be used with the MAS9142 MAS9142, but external compensation elements may be required to maintain the stability of the PA control loop. MAS9142 MAS9142 incorporates the power detector biasing components, RC-filtering for power ramping signal, operational amplifier with AC feedback and a low FEATURES · · · · · · · Two functional blocks: Power Amplifier Controller and LDO Voltage Regulator Low current consumption Temperature compensated biasing for external RF power detection Schottky diodes Both PAC loop and LDO voltage regulator have temperature-controlled power-down feature LDO voltage regulator with short circuit current protection Excellent ripple rejection in regulator Various operating modes provide greater flexibility dropout (LDO) voltage regulator. The regulator has the output voltage of 2.8 V and the maximum load current of 50 mA for generating supply voltage for VCO/Modulator in the radio channel of a mobile phone. The regulator's output is short-circuit protected. Both the PA control loop and LDO voltage regulator have common thermal (over-temperature) protection with 10 °C hysteresis. APPLICATION · · · · Dual- and Triple-Band Cellular Phones PCMCIA GSM/DCS data communications GSM based controller for vehicles Other RF power controlling applications NOT AVAILABLE IN THE USA AND CANADA 1 (11) DA9142 DA9142.002 4 January, 2002 BLOCK DIAGRAM OAMINUS 1 DTEMP 2 DRECT 3 PSENSE 4 VSS1 5 RAMP 6 CBYPASS 7 VRCTRL 16 OAOUT 8 FB 15 14 OA Power Down Control VDD1 TXEN 13 Diode bias + adder VAPC 12 VROUT 10 VOLTAGE ENREF VDD2 9 REF GEN 11 VSS2 REGULATOR MAS9142 MAS9142 PIN CONFIGURATION 9142A YYWW OAMINUS DTEMP DRECT PSENSE VSS1 RAMP CBYPASS VRCTRL OAOUT VDD1 TXEN VAPC VROUT ENREF VDD2 VSS2 Top Marking Definitions: YYWW = Year Week PIN DESCRIPTION Pin name Pin No Type Function OAMINUS DTEMP DRECT PSENSE VSS1 RAMP CBYPASS VRCTRL (note 1) VSS2 VDD2 ENREF (note 1) VROUT VAPC TXEN (note 1) VDD1 OAOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I I I I G I I I G P I O O I P O OA Inverting Input (for Optional External Feedback Components) Schottky Diode for Temperature Compensation RF Rectifier Schottky Diode Power Measurement Input (from Directional Coupler) Ground for Power Amplifier Controller GSM Power Ramping Signal Input Voltage Regulator Reference Voltage Bypass Capacitor Voltage Regulator Enable Ground for Voltage Regulator Supply for Voltage Regulator Voltage Reference Enable ('warm-up') Voltage Regulator Output Automatic Power Control Output Voltage (to PA) Transmit Enable Supply for Power Amplifier Controller OA Output (for Optional External Feedback Components) NOTE 1:Digital control pads with pull-down resistor, Active-High, CMOS-compatible voltage levels. G = Ground, I = Input, O = Output, P = Power 2 (11) DA9142 DA9142.002 4 January, 2002 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min 6.5 V 6.5 V ­6 6.5 V ­55 Voltage Range for All Pins Unit ­0.3 VDD Max ­0.3 Supply Voltage Conditions +125 Voltage Range for Pins 2, 3 and 4 Storage Temperature TS ESD Rating Human Body Model, HBM Operating Ambient Temperature 1 TOP ­40 +95 Note 1) o C kV o C NOTE: Except PSENSE (4), DRECT (3) and DTEMP (2) pins RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions Min Typ Max Unit 3.6 5.3 V mA Supply Voltage VDD 3.0 Supply Current IDD 0.5 2.0 Operating Temperature TA ­30 +85 o C ELECTRICAL CHARACTERISTICS For typical values TA = 27oC, for min/max values TA = -30oC to +85oC,CIN = 330 nF, CL = 1 µF, CBYP = 100 nF unless otherwise noted Common Characteristics u Thermal Protection Parameter Symbol Threshold High Conditions Threshold Low TL Typ Max 145 TH Min Unit 155 165 o o C 135 145 155 C Typ Max Unit VDD V 0.3 7.8 µA The hysteresis of 10°C prevents the device from turning on too soon after thermal shut-down. u Digital Control Pin Parameters Parameter Input Voltage HIGH-state LOW-state Input Current, in HIGH state Symbol Conditions Min VIN VIN (H) VIN (L) IIN,H For Pin 8 (VRCTRL), pin 11 (ENREF) and pin 14 (TXEN) For Pin 8 (VRCTRL), pin 11 (ENREF) and pin 14 (TXEN) 0 2.0 3.8 4.5 3 (11) DA9142 DA9142.002 4 January, 2002 u Current Parameters Parameter Quiescent Supply Currents Symbol Conditions IDD Min Total power down Typ 0.01 Max Unit 5 µA (note 1) PAC on 0.9 1.8 mA References `warm-up' 190 300 µA LDO Regulator on 320 450 µA Whole chip on 1.1 2.0 mA Max Unit 285 700 mW mW NOTE 1: Test limit. High value is used for speeding up production testing. u Power Dissipation Parameter Power Dissipation Power Dissipation Symbol Conditions Pd Pd Min Typ VCC = 6.0 V, TA = 85 °C VCC = 6.0 V, TA = 25 °C Maximum power dissipation is calculated from Pd=(Tj ­TA )/RTJA , where RTJA is thermal resistance of TSSOP16 TSSOP16 package, RTJA = 144 °C /W and Tj is maximum allowed junction temperature, Tj = 125 °C. Regulator Parameter Symbol Conditions Min Regulator Output Current IOUT IMAX 75 Ground Pin Current IVSS2 Regulator Output Voltage Regulator Dropout Voltage Load Regulation Line Regulation VOUT VDROP VOUT IOUT VOUT PSRR Output Noise Voltage Rise Time (V OUT from 10% to 90%) Delay Time (From VRCTRL 50% to VOUT 50%) Overshoot Settling Time (from VOUT 90% to max ±0.1% fluctuation) VRMS tr td No load for typical value, IOUT = 50mA, T = 85 °C VDD = 3.6 V, IOUT = 0 mA IOUT = 50 mA VDD = 3.6 V, IOUT from 0 to 50 mA IOUT = 50 mA, VDD from 6.0 V to 3.6 V f = 1 kHz f = 10 kHz f = 100 kHz 100 Hz < f < 100 kHz, CBYPASS = 100 nF CL = 1 µF, IOUT = 50 mA CL = 1 µF, ENREF is ON at least for 10 ms CL = 1 µF, ENREF is ON at least for 10 ms CL = 1 µF CL = 1 µF 150 Max Unit 50 0 Output Current Limit Typ mA 340 mA µA 320 2.75 2.80 0.14 2.85 0.17 0.5 0.25 1.2 68 54 37 37 V V mV mA mV dB µVrms 14 26 µs 15 35 µs 0.5 8 70 % µs 4 (11) DA9142 DA9142.002 4 January, 2002 u External Capacitors Parameter Symbol Output Capacitor for Regulator Effective Series Resistance Bypass Capacitor Conditions Min CL ESR CBYPASS Typ Unit 1 100 1 0.05 Max 3 µF nF Power Amplifier Controller Parameter Maximum Output Current (sink and source) Output Voltage Range RF input power range RAMP lowpass filter corner frequency Bias current for external Schottky diodes PSRR Symbol Conditions Min Typ Max Unit 3 5 mA IOUT VOUT PIN IOUT = 3 mA At DRECT pin 0 ­14 VDD -0.4 V 20 V dBm f­3dB 2nd order RC filter 40 160 kHz IDRECT, IDTEMP Independent of VDD 21.5 43.6 µA 28 f = 1 kHz f = 10 kHz 56 41 dB u Parameters of Operational Amplifier Parameter Symbol Input Offset Voltage AVOL Min IOUT from 0 to 3 mA Typ Max Unit 0.2 VOS DC gain Conditions 1.2 mV 100 dB 3.5 MHz Unity Gain Bandwidth FT Phase margin m Unity-Gain buffer configuration 55 65 80 deg Gain margin Am Unity-Gain buffer configuration 13 15 26 dB Small-signal Slew Rate SRS V­ = 0.13 V, V+ = 0.0.135 V step 0.2 V/µs Large-signal Slew Rate SRL V­ = 0.13 V, V+ = 0.3 V step 1.5 V/µs 5 (11) DA9142 DA9142.002 4 January, 2002 FUNCTION DESCRIPTION Measured Pout vs. Vramp of MAS9142 MAS9142 35 0.4 Mean 30 0.35 Stdev 0.3 25 0.25 20 0.2 15 0.15 10 0.1 5 0.05 0 VRCTRL 0 0 0 0 1 1 1 1 ENREF 0 0 1 1 0 0 1 1 TXEN 0 1 0 1 0 1 0 1 Mode Total power-down PAC on References 'warm-up' PAC on Voltage regulator on Whole chip on Voltage regulator on Whole chip on The ENREF control pin is included to provide flexibility: it can be used to switch on the voltage reference block in a sufficient amount of time before the regulator or PA controller. When not used, the two other signals will turn the internal reference generator on using a logical 'OR' operation. The startup time of the reference generator is approximately 10 ms due to the large time constant generated by the external capacitor connected to CBYPASS pin and an on-chip resistor. Power Amplifier Controller (PAC) The PAC is an operational amplifier based controller for adjusting the output power of a radio frequency power amplifier. It takes a voltage input at the RAMP pin and adjusts the output power of the power amplifier to a known value. This power value depends on the external rectification diodes, the directional coupler and the power amplifier control curve. The measurement results MAS9142 MAS9142 PA controller, a power amplifier, an LDC15D LDC15D with coupling attenuation of diode pair BAT62 BAT62 in a are obtained using Hitachi PF08103B PF08103B RF type directional coupler 14 dB and a Schottky feedback loop. The standard deviation, dB PAC and LDOVR use common thermal protection and reference voltage generator blocks. There are three power-down pins on MAS9142 MAS9142: TXEN for PA controller, VRCTRL for the voltage regulator and ENREF for the reference generator and thermal protection block. All power-down pins are pull-down type and use standard CMOS control voltage levels and positive logic. The operating modes of MAS9142 MAS9142 are listed in the table below: measurement results are shown in Figure 1. It can be seen that a ±3 corridor is approximately 1 dB even at very low power levels. The measurements were carried out at room temperature with a supply voltage of 3.6 V and RF input frequency of 900 MHz. Pout, dBm MAS9142 MAS9142 contains two functionally distinct parts ­ the radio frequency power amplifier controller (PAC) and low-dropout voltage regulator (LDOVR). Both blocks have separate power lines, which must be connected together on the system printed circuit board. 0 0.2 0.3 0.4 0.5 0.6 0.7 VRAMP, V 0.8 0.9 1 Figure 1. MAS9142 MAS9142 measurement results To achieve a better power supply rejection ratio for the PAC, the rectification diode biasing is made using a on-chip 2.8 V voltage reference generator and biasing resistors. The bias current can vary from sample to sample, but is constant in the whole operating temperature and supply voltage range with accuracy of ±2%. MAS9142 MAS9142 also guarantees that the radio power is ramped up and down properly, generating only few spurious frequency components. For that reason, the control signal that comes from a D/A converter to the PAC is first low-pass filtered inside MAS9142 MAS9142 chip. There are also other RC time constants on the chip, which help in assuring the stability of the PA control loop. An optional stabilising capacitor can be connected between the OAMINUS and OAOUT pins of MAS9142 MAS9142. In the measurement setup described above, the additional compensation capacitor was not used. Low-Dropout Voltage Regulator (LDOVR) The LDOVR is a high performance, low dropout voltage regulator including short circuit current and thermal protection. The circuit also contains necessary reference voltage and current generators, so minimum number of external components are required. 6 (11) DA9142 DA9142.002 4 January, 2002 APPLICATION INFORMATION Battery voltage (V ) BAT Antenna C FB (Note 4) C VD1 100 nF 1 2 3 Power ramping signal C RF 10 pF 4 5 6 7 8 C BYP 100 nF OAMINUS DTEMP DRECT PSENSE VSS1 RAMP CBYPASS VRCTRL OAOUT MAS9142 MAS9142 BAT62 BAT62 VDD1 TXEN VAPC VROUT ENREF VDD2 VSS2 16 C BST 100 µF 15 14 C VD2 68 pF 13 0­2.2V, max. 3 mA 12 C APC 100 pF C REG 2.8V, 1 µF 50 mA 11 10 9 Directional coupler (­14 dB) Power Amplifier R M 50 C VD3 330 nF Transmit signal VRCTRL ENREF TXEN Digital signals from System Controller Figure 2. Application diagram of MAS9142 MAS9142 The application circuit diagram is shown in Figure 2. 1. The VSS1 (ground for PAC, pin 5) and VSS2 (ground for regulator, pin 9) must be connected together. 2. The VDD1 (pin 15) and VDD2 (pin 10) must be connected together. 3. There are no external biasing components needed for the RF rectifier, they are on the chip. 4. Loop time constant adjusting capacitor CFB between the OAMINUS (pin 1) and OAOUT (pin 16) is optional and its recommended value is between 100 pF and 300 pF. This capacitor is not necessary when using Hitachi PF08103B PF08103B power amplifier and Murata LDC15D LDC15D type directional coupler. 7 (11) DA9142 DA9142.002 4 January, 2002 PACKAGE (TSSOP16 TSSOP16) OUTLINES C E D Seating Plane B F G H A O Pin 1 B Detail A B L I I1 K P Section B-B J1 M J Dimension Detail A N Min Max A 6.40 BSC B 4.30 4.50 C 4.90 5.10 D 0.05 0.15 E 1.10 F 0.19 0.30 G 0.65 BSC H 0.18 0.28 I 0.09 0.20 I1 0.09 0.16 J 0.19 0.30 J1 0.19 0.25 K 0° 8° L 0.24 0.26 M 0.50 0.75 (The length of a terminal for soldering to a substrate) N 1.00 REF O 12° P 12° Dimensions do not include mold flash, protrusions, or gate burrs. All dimensions are in accordance with JEDEC standard MO-153 MO-153. Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm 8 (11) DA9142 DA9142.002 4 January, 2002 SOLDERING INFORMATION Resistance to Soldering Heat Maximum Reflow Temperature Maximum Number of Reflow Cycles Seating Plane Co-planarity Lead Finish According to RSH test IEC 68-2-58/20 2*220°C 235°C 2 max 0.08 mm Solder plate 7.62 - 25.4 µm, material Sn 85% Pb 15% EMBOSSED TAPE SPECIFICATIONS Tape Feed Direction P0 D0 P2 A E1 F1 W D1 A A0 P Tape Feed Direction T Section A - A B0 S1 K0 Pin 1 Designator Dimension Min Max Unit A0 B0 D0 D1 E1 F1 K0 P P0 P2 S1 T W 6.50 5.20 6.70 5.40 mm mm mm mm mm mm mm mm mm mm mm mm mm 1.50 +0.10 / -0.00 1.50 1.65 7.20 1.20 11.90 1.85 7.30 1.40 12.10 4.0 1.95 2.05 0.6 0.25 0.35 11.70 12.30 All dimensions are in accordance with EIA-481 EIA-481 Standard. 9 (11) DA9142 DA9142.002 4 January, 2002 REEL SPECIFICATIONS W2 A D C Tape Slot for Tape Start N B W1 2000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader Weight Leader Components Min Unit 330 14.4 mm mm mm mm mm mm 18.4 1.5 12.80 20.2 50 12.4 Max mm 13.50 160 390, of which minimum 160mm of empty carrier tape sealed with cover tape mm mm 1500 g 10 (11) DA9142 DA9142.002 4 January, 2002 ORDERING INFORMATION Product Code Product Package Comments MAS9142AUA1-T MAS9142AUA1-T PAC & 2.8 V LDO Regulator TSSOP16 TSSOP16 Tape & Reel LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O.Box 51 FIN-02771 FIN-02771 Espoo, FINLAND www.mas-oy.com Tel. (09) 80521 Tel. Int. +358 9 80521 Telefax +358 9 8053213 Email: info@mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 11 (11)