MACH436/MACHLV436-7/10/12/15 MACH435 PAL33V16 MACH436 M4-128N MACH4-128N - Datasheet Archive

 

COM'L: -7/10/12/15 IND: -10/12/14/18 MACH436/MACHLV436-7/10/12/15 High-Density EE CMOS Programmable Logic V A N T I S The

 

PRELIMINARY COM'L: -7/10/12/15 IND: -10/12/14/18 MACH436/MACHLV436-7/10/12/15 MACH436/MACHLV436-7/10/12/15 High-Density EE CMOS Programmable Logic V A N T I S The Programmable Logic Company From AMD DISTINCTIVE CHARACTERISTICS s 84-pins in PLCC s 5-V and 3.3-V options - JEDEC compatible for both 5-V and 3.3-V versions s Fully pinout, function, and JEDEC programming data file compatible with MACH435 MACH435 s Enhanced features - Bus-FriendlyTM inputs and I/Os - PAL® Block programmable power-down mode for further power savings - Individual output slew rate control - Both 5-V and 3.3-V supply operation versions are safe for mixed supply voltage system designs s 128 macrocells s 7.5 ns tPD s 133 MHz fCNT s 70 Inputs s 64 Outputs s 192 flip-flops - 128 Macrocell flip-flops - 64 Input flip-flops s Up to 20 product terms per function, with XOR s Flexible clocking - Four global clock pins with selectable edges - Asynchronous mode available for each macrocell s 8 "PAL33V16 PAL33V16" blocks s Input and output switch matrices for high routability and pinout retention s Fixed, predictable, deterministic delays s Zero-hold-time input register option s Peripheral Component Interconnect (PCI) compliant (-7,-10, -12 speed grades) PLEASE NOTE: The MACH436 MACH436 reflects an old nomenclature for the MACH® 4 Family. This device is currently dualmarked with the M4-128N M4-128N ordering part number. The dual-mark scheme will facilitate design and manufacturing flows until we have completely phased in the new M4-128N M4-128N nomenclature. Please use the MACH4-128N MACH4-128N data sheet (PID#21423A) as a reference. GENERAL DESCRIPTION The MACH436/MACHLV436 MACH436/MACHLV436 is a member of Vantis' high-performance EE CMOS MACH 4 family. This device has approximately 12 times the macrocell capability of the popular PALCE22V10 PALCE22V10, with significant density and functional features that the PALCE22V10 PALCE22V10 does not provide. The MACH436/MACHLV436 MACH436/MACHLV436 consists of 8 PAL blocks interconnected by a programmable central switch matrix. The central switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix. The input switch matrix provides input signals with alternative paths into the central switch matrix; the output switch matrix provides flexibility in assigning macrocells to I/O pins. The MACH436/MACHLV436 MACH436/MACHLV436 has macrocells that can be configured as synchronous or asynchronous. This allows designers to implement both synchronous and asynchronous logic together on the same device. The two types of design can be mixed in any proportion, since the selection on each macrocell affects only that macrocell. Up to 20 product terms per function can be assigned. It is possible to allocate some product terms away from a macrocell without losing the use of that macrocell for logic generation. This document contains information on a product under development at Vantis. The information is intended to help you evaluate this product. Vantis reserves the right to change or discontinue work on this proposed product without notice. Publication# 21442 Rev: A Amendment/0 Issue Date: April 1997 V A N T I S P R E L I M I N A R Y The MACH436/MACHLV436 MACH436/MACHLV436 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type, T-type, J-K, or S-R to help reduce the number of product terms used. The flip-flop can also be configured as a latch. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell through the output switch matrix. The output switch matrix makes it possible to make significant design changes while minimizing the risk of pinout changes. The MACH436/MACHLV436 MACH436/MACHLV436, an enhanced version of the MACH435 MACH435, is fully pinout, function and JEDEC programming data file compatible with the MACH435 MACH435. The enhanced features include: low power consumption; each PAL block has a programmable power-down mode for further power saving of up to 50%; each I/O has an individually programmable output slew-rate control bit; all inputs and I/Os feature the Bus-Friendly circuitry which weakly holds the voltage at the input to a logic low or high level depending on the last driven logic level. Both 5-V and 3.3-V supply operation versions are safe for mixed supply voltage system designs. The 3.3-V sup- 2 ply operation device power consumption is significantly reduced due to the lower required supply voltage, both versions 5-V and 3.3-V supply operation devices provide the same high performance. MACH designs can be implemented using Vantis' MACHXL®, and industry-standard universal design software tools. Vantis and MINC have developed a strategic partnership that ensures timely universal software support for the MACH devices. MINC develops back-end PLD software for nearly every major industry-standard PLD and board-level design tools. This back-end software fits a design into a device and creates a JEDEC programming data file. Schematic capture, boolean, state machine, VHDL, and Verilog HDL design entry and simulation are features of the front-end tool. MINC produces the back-end for PC tools such as MicroSim's Design Center, Synario Design Automation's Synario, and others. MINC also supplies the back-end for workstation tools from Cadence, Mentor Graphics, Synopsys, and Viewlogic. The Vantis-MINC partnership provides timely, accurate, and quality support for MACH devices in almost every design environment. Please see Vantis' Universal Tools brochure for more information. MACH436/MACHLV436 MACH436/MACHLV436 4 OE CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 MACH436/MACHLV436 MACH436/MACHLV436 OE 4 4 8 8 I/O Cells 8 Output Switch Matrix I/O48 I/O48­I/O55 I/O55 Clock Generator Block G I/O56 I/O56­I/O63 I/O63 8 I/O Cells 8 16 Block H 16 4 4 8 Block F I/O40 I/O40­I/O47 I/O47 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 33 24 16 16 4 4 4 4 4 8 8 OE Output Switch Matrix 16 Input Switch Matrix 16 Macrocells 4 OE 8 OE 4 16 24 24 Input Switch Matrix 16 Input Switch Matrix 16 OE Macrocells 4 66 X 90 AND Logic Array and Logic Allocator 33 16 16 4 Block D Block E I/O32 I/O32­I/O39 I/O39 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 33 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 I/O Cells 8 I/O24 I/O24­I/031 I/031 16 16 24 24 16 16 Input Switch Matrix 4 24 Central Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 OE 16 66 X 90 AND Logic Array and Logic Allocator Input Switch Matrix 24 4 4 8 OE 33 16 16 Input Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 4 I/O Cells 8 Input Switch Matrix 24 4 4 8 8 Block C I/O16 I/O16­I/O23 I/O23 Input Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 16 16 Clock Generator 4 Clock Generator Macrocells 16 Output Switch Matrix 4 I/O Cells 8 Clock Generator 4 8 8 I/O Cells 8 Block B I/O8­I/O15 I/O15 Clock Generator 4 4 4 Block A I/O0­I/O7 2 P R E L I M I N A R Y V A N T I S BLOCK DIAGRAM I2, I5 Clock Generator Clock Generator Clock Generator 21442-1 3 P R E L I M I N A R Y V A N T I S I/O34 I/O34 I/O35 I/O35 I/O36 I/O36 I/O37 I/O37 I/O38 I/O38 I/O39 I/O39 GND 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 12 13 73 72 14 71 15 70 16 17 69 68 18 67 19 66 20 21 65 64 22 63 23 62 24 61 25 60 26 27 59 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O24 I/O24 I/O25 I/O25 I/O26 I/O26 I/O27 I/O27 I/O28 I/O28 I/O29 I/O29 I/O30 I/O30 I/O31 I/O31 I2 VCC GND VCC I/O32 I/O32 I/O33 I/O33 I/O8 I/O9 I/O10 I/O10 I/O11 I/O11 I/O12 I/O12 I/O13 I/O13 I/O14 I/O14 I/O15 I/O15 CLK0/I0 VCC GND CLK1/I1 I/O16 I/O16 I/O17 I/O17 I/O18 I/O18 I/O19 I/O19 I/O20 I/O20 I/O21 I/O21 I/O22 I/O22 I/O23 I/O23 GND VCC I5 I/O63 I/O63 I/O62 I/O62 I/O61 I/O61 I/O60 I/O60 I/O59 I/O59 I/O58 I/O58 I/O57 I/O57 I/O56 I/O56 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND CONNECTION DIAGRAM Top View Note: Pin-compatible with MACH130 MACH130, MACH131 MACH131, MACH230 MACH230, MACH231 MACH231, and MACH435 MACH435. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage 4 MACH436/MACHLV436 MACH436/MACHLV436 GND I/O55 I/O55 I/O54 I/O54 I/O53 I/O53 I/O52 I/O52 I/O51 I/O51 I/O50 I/O50 I/O49 I/O49 I/O48 I/O48 CLK3/I4 GND VCC CLK2/I3 I/O47 I/O47 I/O46 I/O46 I/O45 I/O45 I/O44 I/O44 I/O43 I/O43 I/O42 I/O42 I/O41 I/O41 I/O40 I/O40 P R E L I M I N A R Y V A N T I S ORDERING INFORMATION Commercial Products Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 436 -7 J C FAMILY TYPE MACH = Macro Array CMOS High-Speed (5-V Vcc) OPTIONAL PROCESSING Blank = Standard Processing DEVICE NUMBER 436 = 128 Macrocells, Non-ISP OPERATING CONDITIONS C = Commercial (0°C to +70°C) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrier (PL 084) Valid Combinations Valid Combinations MACH436-7 MACH436-7 The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH436-10 MACH436-10 JC MACH436-12 MACH436-12 MACH436-15 MACH436-15 MACH436-7/10/12/15 MACH436-7/10/12/15 (5-V Com'l) 5 P R E L I M I N A R Y V A N T I S ORDERING INFORMATION Commercial Products Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACHLV 436 -10 J C FAMILY TYPE MACHLV= Macro Array CMOS High-Speed Low Voltage (3.3-V Vcc) OPTIONAL PROCESSING Blank = Standard Processing DEVICE NUMBER 436 = 128 Macrocells, Non-ISP OPERATING CONDITIONS C = Commercial (0°C to +70°C) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrier (PL 084) Valid Combinations Valid Combinations MACHLV436-7 MACHLV436-7 MACHLV436-10 MACHLV436-10 JC The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACHLV436-12 MACHLV436-12 MACHLV436-15 MACHLV436-15 6 MACHLV436-7/10/12/15 MACHLV436-7/10/12/15 (3.3-V Com'l) P R E L I M I N A R Y V A N T I S ORDERING INFORMATION Industrial Products Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 436 -10 J I FAMILY TYPE MACH = Macro Array CMOS High-Speed (5-V Vcc) OPTIONAL PROCESSING Blank = Standard Processing DEVICE NUMBER 436 = 128 Macrocells, Non-ISP OPERATING CONDITIONS I = Industrial (-40°C to +85°C) SPEED -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14 ns tPD -18 = 18 ns tPD PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrier (PL 084) Valid Combinations Valid Combinations MACH436-10 MACH436-10 The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH436-12 MACH436-12 JI MACH436-14 MACH436-14 MACH436-18 MACH436-18 MACH436-10/12/14/18 MACH436-10/12/14/18 (5-V Ind) 7 P R E L I M I N A R Y V A N T I S ORDERING INFORMATION Industrial Products Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACHLV 436 -10 J I FAMILY TYPE MACHLV= Macro Array CMOS High-Speed (3.3-V Vcc) OPTIONAL PROCESSING Blank = Standard Processing DEVICE NUMBER 436 = 128 Macrocells, Non-ISP OPERATING CONDITIONS I = Industrial (-40°C to +85°C) SPEED -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14 ns tPD -18 = 18 ns tPD PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrier (PL 084) Valid Combinations Valid Combinations MACHLV436-10 MACHLV436-10 The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACHLV436-12 MACHLV436-12 JI MACHLV436-14 MACHLV436-14 MACHLV436-18 MACHLV436-18 8 MACHLV436-10/12/14/18 MACHLV436-10/12/14/18 (3.3-V Ind) P R E L I M I N A R Y V A N T I S FUNCTIONAL DESCRIPTION The Product-Term Array The MACH436/MACHLV436 MACH436/MACHLV436 consists of eight PAL blocks connected by a central switch matrix. There are 64 I/O pins and 6 dedicated input pins feeding the central switch matrix. These signals are distributed to the eight PAL blocks for efficient design implementation. There are 4 global clock pins that can also be used as dedicated inputs. The MACH436/MACHLV436 MACH436/MACHLV436 product-term array consists of 80 product terms for logic use, eight product terms for output enable use, and two product terms for global PAL block initialization. Each macrocell has a nominal allocation of 5 product terms for logic, a l t h o u g h t h e l o g i c a l l o c a t o r a l l ow s fo r l o g i c redistribution. Each I/O pin has its own individual output enable term. The initialization product terms provide asynchronous reset or preset to synchronousmode macrocells in the PAL block. All inputs and I/O pins have bus-friendly latches. While it is always good design practice to tie unused pins high, the latches provide design security and stability in the event that unused pins are left disconnected. The PAL Blocks Each PAL block in the MACH436/MACHLV436 MACH436/MACHLV436 (Figure 1) contains a clock generator, a 90-productterm logic array, a logic allocator, 16 macrocells, an output switch matrix, 8 I/O cells, and an input switch matrix. The central switch matrix feeds each PAL block with 33 inputs. This makes the PAL block look effectively like an independent "PAL33V16 PAL33V16" with 8 to 16 buried macrocells. In addition to the logic product terms, individual output enable product terms and two PAL block initialization product terms are provided. Each I/O pin can be individually enabled. All flip-flops that are in the synchronous mode within a PAL block are initialized together by either of the PAL block initialization product terms. The Central Switch Matrix and Input Switch Matrix The MACH436/MACHLV436 MACH436/MACHLV436 central switch matrix is fed by the input switch matrices in each PAL block. Each PAL block provides 16 internal feedback signals, 8 registered input signals, and 8 I/O pin signals to the input switch matrix. Of these 32 signals, 24 decoded signals are provided to the central switch matrix by the input switch matrix. The central switch matrix distributes these signals back to the PAL blocks in a very efficient manner that provides for high performance. The design software automatically configures the input and central switch matrices when fitting a design into the device. The Logic Allocator The logic allocator in the MACH436/MACHLV436 MACH436/MACHLV436 takes the 80 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 20 product terms in synchronous mode, or 18 product terms in asynchronous mode. When product terms are routed away from a macrocell, all 5 product terms may be redirected, which precludes the use of the macrocell for logic generation. It is possible to redirect only 4 product terms, leaving one for simple function generation. The design software automatically configures the logic allocator when fitting the design into the device. The logic allocator also provides an exclusive-OR gate. This gate allows generation of combinatorial exclusiveOR logic, such as comparison or addition. It allows registered exclusive-OR functions, such as CRC generation, to be implemented more efficiently. Emulating all flip-flop types with a D-type flip-flop is also made possible. Register type emulation is automatically handled by the design software. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. The Clock Generator Each PAL block has a clock generator that can generate four clock signals for use throughout the PAL block. These four signals are available to all macrocells and I/O cells in the PAL block, whether in synchronous or asynchronous mode. The clock generator chooses the four signals from the eight possible signals given by the true and complement versions of the four global clock pin signals. MACH436/MACHLV436 MACH436/MACHLV436 9 P R E L I M I N A R Y V A N T I S Table 1. Macrocell Logic Allocation Available Clusters M0 C0, C1, C2 M1 C0, C1, C2, C3 M2 C1, C2, C3, C4 M3 C2, C3, C4, C5 M4 C3, C4, C5, C6 M5 C4, C5, C6, C7 M6 C5, C6, C7, C8 M7 C6, C7, C8, C9 The flip-flop clock depends on the mode selected for the macrocell. In synchronous mode, any of the PAL block clocks generated by the Clock Generator can be used. In asynchronous mode, the additional choice of either edge of an individual product-term clock is available. M8 C7, C8, C9, C10 M9 C8, C9, C10, C11 M10 C9, C10, C11, C12 M11 C10, C11, C12, C13 M12 C11, C12, C13, C14 M13 C12, C13, C14, C15 M14 C13, C14, C15 M15 C14, C15 The MACH436/MACHLV436 MACH436/MACHLV436 has 16 macrocells, half of which can drive I/O pins; this selection is made by the output switch matrix. Each macrocell can drive one of four I/O cells. The allowed combinations are shown in Table 2. Please refer to Figure 1 for macrocell and I/O pin numbers. Macrocell Output Switch Matrix Combinations Routable to I/O Pins M0,M1 I/O5,I/O6,I/O7,I/O0 M2,M3 I/O6,I/O7,I/O0,I/O1 M4, M5 I/O7,I/O0,I/O1,I/O2 M6,M7 I/O1,I/O2,I/O3,I/O4 M10,M11 I/O3,I/O4,I/O5,I/O6 M14,M15 I/O4,I/O5,I/O6,I/O7 I/O Pin Available Macrocells I/O0 M0,M1,M2,M3,M4,M5,M6,M7 I/O1 M2,M3,M4,M5,M6,M7,M8,M9 I/O2 M4,M5,M6,M7,M8,M9,M10,M11 I/O3 M8,M9,M10,M11,M12,M13,M14,M15 I/O5 M10,M11,M12,M13,M14,M15,M0,M1 I/O6 M12,M13,M14,M15,M0,M1,M2,M3 I/O7 This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges. M6,M7,M8,M9,M10,M11,M12,M13 I/O4 10 Zero-Hold-Time Input Register When programmed, the ZHT fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased, the setup time to the input storage element is minimized. I/O2,I/O3,I/O4,I/O5 M12, M13 The I/O cell in the MACH436/MACHLV436 MACH436/MACHLV436 consists of a three-state buffer and an input flip-flop. The I/O cell is driven by one of the macrocells, as selected by the output switch matrix. Each I/O cell can take its input from one of eight macrocells. The three-state buffer is controlled by an individual product term. The input flipflop can be configured as a register or latch. Both the direct I/O signal and the registered/latched signal are available to the input switch matrix, and can be used simultaneously if desired. The MACH436/MACHLV436 MACH436/MACHLV436 device has a zero-hold time (ZHT) fuse. This fuse controls the time delay associated with loading data into all I/O cell registers and latches in the MACH436/MACHLV436 MACH436/MACHLV436 device. I/O0,I/O1,I/O2,I/O3 M8, M9 Initialization can be handled as part of a bank of macrocells via the PAL block initialization terms if in synchronous mode, or individually if in asynchronous mode. In synchronous mode, one of the PAL block product terms is available each for preset and reset. The swap function determines which product term drives which function. This allows initialization polarity compatibility with the MACH 1 and 2 series. In asynchronous mode, one product term can be used either to drive reset or preset. The I/O Cell The Macrocell and Output Switch Matrix Table 2. The macrocells can be configured as registered, latched, or combinatorial. In combination with the logic allocator, the registered configuration can be any of the standard flip-flop types. The macrocell provides internal feedback whether configured with or without the flip-flop, and whether or not the macrocell drives an I/O cell. M14,M15,M0,M1,M2,M3,M4,M5 MACH436/MACHLV436 MACH436/MACHLV436 P R E L I M I N A R Y Power-Down Mode E a c h i n d i v i d u a l PA L bl o ck i n t h e M AC H 4 3 6 / MACHLV436 MACHLV436 features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slightly slower than those in the non-low-power PAL block. This feature allows speed critical signal paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode. Bus-Friendly Inputs and I/Os The MACH436/MACHLV436 MACH436/MACHLV436 inputs and I/Os feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state and pulls the voltage away from the input threshold voltage. At power-up, the Bus-Friendly latches are reset to a logic level "1." For an illustration of this configuration, please refer to the Input/Output Equivalent Schematics section. Programmable Slew Rate Each MACH436/MACHLV436 MACH436/MACHLV436 I/O has an individually programmable output slew-rate control bit. Each output can be individually configured for the highest speed transition or for the lowest noise transition. In systems V A N T I S properly designed for high-speed applications, the fast slew-rate output option can be used to achieve the highest speed. However, the slower slew rate is more effective than the fast slew rate in keeping noise generation and ground bounce to the minimum level. PCI Compliance The MACH436/MACHLV436 MACH436/MACHLV436 devices with speed grades -10 and -12 are compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The predictable timing of the MACH436/MACHLV436 MACH436/MACHLV436 ensures compliance with the PCI timing specifications independent of the logic design fitting. Safe for Mixed Supply Voltage Designs The MACH436/MACHLV436 MACH436/MACHLV436 is safe for mixed supply voltage system designs. The 5-V supply operation version device outputs will not drive above 3.3 V. Thus, it can safely drive any 3.3-V supply operation device. The 3.3-V supply operation version device inputs are 5-V tolerant. MACH436/MACHLV436 MACH436/MACHLV436 11 CLK0/I0 CLK1/I1 16 CLK2/I3 CLK3/I4 P R E L I M I N A R Y V A N T I S Clock Generator 4 Macrocell M0 M1 Macrocell M1 C2 M2 Macrocell M2 C3 M3 Macrocell M3 C4 M4 Macrocell M4 C5 M5 Macrocell M5 C6 M6 Macrocell M6 M7 Macrocell M7 M8 Macrocell M8 C9 M9 Macrocell M9 C10 M10 Macrocell M10 C11 M11 Macrocell C12 M12 Macrocell M12 C13 M13 Macrocell M13 C14 M14 Macrocell M14 C15 M15 Macrocell M15 C7 C8 O0 I/O Cell I/O0 O1 I/O Cell I/O1 O2 I/O Cell I/O2 O3 Output Switch Matrix Logic Allocator M0 C1 Central Switch Matrix C0 I/O Cell I/O3 O4 I/O Cell I/O4 O5 I/O Cell I/O5 O6 I/O Cell I/O6 O7 I/O Cell I/O7 M11 17 16 24 Input Switch Matrix 16 21442-2 Figure 1. 12 MACH436/MACHLV436 MACH436/MACHLV436 PAL Block MACH436/MACHLV436 MACH436/MACHLV436 P R E L I M I N A R Y V A N T I S ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . ­65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . ­55°C to +100°C Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C Supply Voltage with Respect to Ground . . . . . . . . . . . ­0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . .­0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = 0°C to +70°C). . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = ­3.2 mA, VCC = Min VIN = VIH or VIL VOL Output LOW Voltage Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) VIL Input LOW Voltage Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) Unit V 0.5 2.4 Max 3.3 Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) IIH Typ IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) VIH Min V 2.0 V 0.8 V 10 µA ­10 µA IOZH Off-State Output Leakage Current VOUT = 5.25 V, VCC = Max HIGH VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current VOUT = 0 V, VCC = Max LOW VIN = VIH or VIL (Note 3) ­10 µA ISC Output Short-Circuit Current ­160 mA ICC Supply Current VOUT = 0.5 V, VCC = Max (Note 4) ­30 All PAL Blocks low-power VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 5.0 V, f = 1 MHz, TA = 25°C (Note 5) 70 mA All PAL Blocks full-power VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 5.0 V, f = 1 MHz, TA = 25°C (Note 5) 120 mA Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. MACH436-7/10/12/15 MACH436-7/10/12/15 (5-V Com'l) 13 P R E L I M I N A R Y V A N T I S CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit 6 pF 8 pF VCC = 5.0 V, TA = 25°C, f = 1 MHz Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) -7 Parameter Symbol Parameter Description Min tPD Input, I/O, or Feedback to Combinatorial Output tSA Setup Time from Input, I/O, or Feedback to Product Term Clock tHA Register Data Hold Time Using Product Term Clock tCOA tWLA 7.5 3 12 3 15 ns 8 ns T-type 4.5 5 6 9 ns 3.5 4 5 8 ns 4 9.5 4 12 4 14 4 18 ns LOW 4 5 8 9 ns HIGH 4 5 8 9 ns D-type 74.0 62.5 52.6 38.5 MHz Maximum T-type Frequency Using D-type Internal Feedback (fCNTA) Product T-type Term Clock (Note 2) No Feedback 1/(tWLA + tWHA) (Note 3) 71.4 58.8 50.0 37 MHz 90.9 71.4 58.8 47.6 MHz 83.3 66.7 55.6 45.4 MHz 125 100 62.5 55.6 MHz D-type 5.5 6 7 10 ns T-type 6.5 7 8 11 ns 0 0 0 ns 1/(tSA + tCOA) Register Data Hold Time Using Global Clock 0 Global Clock to Output 2 5.5 2 6.5 2 8 2 10 ns LOW 3 5 6 6 ns HIGH 3 5 6 6 ns D-type 90 80 66.7 50 MHz T-type 83.3 74.1 62.5 47.6 MHz D-type 133 100 83.3 66.6 MHz T-type 117 90.9 76.9 62.5 MHz 166.7 100 83.3 88.3 MHz 4 4 5 8 ns Global Clock Width tWHS tSLA 10 5 Setup Time from Input, I/O, or Feedback to Global Clock fMAXS 3 4 tHS 14 Max Min Max Min Max Min Max Unit 3.5 tSS tWLS -15 Product Term, Clock Width External Feedback tCOS -12 D-type Product Term Clock to Output tWHA fMAXA 3 -10 Maximum Frequency Using Global Clock (Note 2) External Feedback 1/(tSS + tCOS) Internal Feedback (fCNTS) No Feedback (Note 3) 1/(tWLS + tWHS) Setup Time from Input, I/O, or Feedback to Product Term Clock MACH436-7/10/12/15 MACH436-7/10/12/15 (5-V Com'l) P R E L I M I N A R Y V A N T I S SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) -7 Parameter Symbol Parameter Description Min -10 -12 -15 Max Min Max Min Max Min Max Unit tHLA Latch Data Hold Time Using Product Term Clock 4 4 tGOA Product Term Gate to Output tGWA Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 4 5 6 9 ns tSLS Setup Time from Input, I/O, or Feedback to Global Gate 6 7 8 10 ns tHLS Latch Data Hold Time Using Global Gate 0 0 0 0 ns tGOS Gate to Output 6 tGWS Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 5 tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 11 5 13 16 7.5 5 14 8 19 10 6 15.5 ns 11 6 18 ns ns ns 20 ns D-type tWICL 8 9 15 T-type 8 9 10 16 LOW 4.5 5 6 6 ns HIGH 4.5 5 6 6 ns 110 100 83.3 83.3 MHz Input Register Clock Width tWICH fMAXIR 7 Maximum Input Register Frequency 1/(tWICL + tWICH) tIGO Input Latch Gate to Combinatorial Output 12 14 16 20 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 14 16 18 22 ns tIGSA Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate 4 4 4 14 ns tIGSS Input Latch Gate to Output Latch Setup Using Global Output Latch Gate 9 9 9 16 ns tWIGL Input Latch Gate Width LOW 5 5 6 6 ns tAR Asynchronous Reset to Registered or Latched Output 12 14 16 20 ns tARW Asynchronous Reset Width (Note 2) 10 10 12 15 ns tARR Asynchronous Reset Recovery Time (Note 2) 8 8 10 15 ns tAP Asynchronous Preset to Registered or Latched Output 12 14 16 20 ns tAPW Asynchronous Preset Width (Note 2) 10 10 12 15 ns tAPR Asynchronous Preset Recovery Time (Note 2) 8 8 8 15 ns tEA Input, I/O, or Feedback to Output Enable 2 9.5 2 10 2 12 2 15 ns tER Input, I/O, or Feedback to Output Disable 2 9.5 2 10 2 12 2 15 ns 17 ns Input Register with Standard-Hold-Time Option tPDL tSIR Input Register Setup Time 2 2 2 2 ns tHIR 15 Input, I/O, or Feedback to Output Through Transparent Input Latch Input Register Hold Time 3 3 3 4 ns 10 MACH436-7/10/12/15 MACH436-7/10/12/15 (5-V Com'l) 12 14 P R E L I M I N A R Y V A N T I S SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) Parameter Symbol -7 Parameter Description Min -10 -12 -15 Max Min Max Min Max Min Max Unit tSIL Input Latch Setup Time 2 2 2 2 ns tHIL Input Latch Hold Time 3 3 3 4 ns tSLLA Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate 4 4 4 4 ns tSLLS Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate 7 8 9 12 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 12 14 16 19 ns 16 18 20 23 ns Input Register with Zero-Hold-Time Option tPDLI Input, I/O, or Feedback to Output Through Transparent Input Latch tSIRI Input Register Setup Time 6 6 6 6 ns tHIRI Input Register Hold Time 0 0 0 0 ns tSILI Input Latch Setup Time 6 6 6 6 ns tHILI Input Latch Hold Time 0 0 0 0 ns tSLLAI Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate 11 13 16 16 ns tSLLSI Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate 12 15 18 18 ns tPDLLI Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 18 20 22 25 ns tLP Power-down mode delay adder. For macrocells in a power-down mode PAL block, this parameter must be added to: tPD, tCOA, tSS, tGOA, tSLS, tICO, tICS, tIGO, tIGOL, tIGSS, tAR, tARR, tAP, tAPR, tEA, tER, tPDL, tSLLS, tPDLL 2.5 2.5 2.5 2.5 ns tSLW Slow slew rate delay adder. For an output configured with slow slew rate option, this parameter must be added to: tPD, tCOA, tCOS, tGOA, tGOS, tICO, tIGO, tIGOL, tAP, tAR, tPDL, tPDLL 2.5 2.5 2.5 2.5 ns Power-Down Mode and Slow Slew Rate Option Notes: 1. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 16 MACH436-7/10/12/15 MACH436-7/10/12/15 (5-V Com'l) P R E L I M I N A R Y V A N T I S ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . ­65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . ­55°C to +100°C Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C Supply Voltage with Respect to Ground . . . . . . . . . . . ­0.5 V to +4.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +3.0 V to +3.6 V DC Input Voltage . . . . . . . . . . . . . . . . . ­0.5 V to 6.0 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = 0°C to +70°C). . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min VIN = VIH or VIL IOH = ­100 µA VOL Output LOW Voltage VCC = Min VIN = VIH or VIL (Note 1) Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs IIH Input HIGH Leakage Current IIL Input LOW Leakage Current Typ IOL = 100 µA VIH Min Max Unit VCC ­ 0.2 V 0.2 V 2.0 5.5 V ­0.3 0.8 V VIN = 3.6 V, VCC = Max (Note 2) 5 µA VIN = 0 V, VCC = Max (Note 2) ­5 µA IOZH Off-State Output Leakage Current VOUT = 3.6 V, VCC = Max HIGH VIN = VIH or VIL (Note 2) 5 µA IOZL Off-State Output Leakage Current VOUT = 0 V, VCC = Max LOW VIN = VIH or VIL (Note 2) ­5 µA ISC Output Short-Circuit Current ­160 mA ICC Supply Current VOUT = 0.5 V, VCC = Max (Note 3) ­15 All PAL Blocks low-power VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 3.3 V, f = 1 MHz, TA = 25°C (Note 4) 70 mA All PAL Blocks full-power VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 3.3 V, f = 1 MHz, TA = 25°C (Note 4) 120 mA Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. MACHLV436-7/10/12/15 MACHLV436-7/10/12/15 (3.3-V Com'l) 17 P R E L I M I N A R Y V A N T I S CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit 6 pF 8 pF VCC = 3.3 V, TA = 25°C, f = 1 MHz Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) -7 Parameter Symbol Parameter Description Min tPD Input, I/O, or Feedback to Combinatorial Output tSA Setup Time from Input, I/O, or Feedback to Product Term Clock tHA Register Data Hold Time Using Product Term Clock tCOA tWLA 7.5 3 12 3 15 ns ns T-type 4.5 5 6 9 ns 3.5 4 5 8 ns 4 4 LOW 4 5 8 9 ns HIGH 4 5 8 9 ns D-type 74.0 62.5 52.6 38.5 MHz T-type 71.4 58.8 50.0 37 MHz D-type 90.9 71.4 58.8 47.6 MHz T-type 83.3 66.7 55.6 45.4 MHz 125 100 62.5 55.6 MHz D-type 5.5 6 7 10 ns T-type 6.5 7 8 11 ns 0 0 0 ns 12 4 14 4 18 ns Product Term, Clock Width Maximum Frequency Using Product Term Clock (Note 2) External Feedback 1/(tSA + tCOA) Internal Feedback (fCNTA) No Feedback (Note 3) 1/(tWLA + tWHA) 0 Global Clock to Output 2 5.5 2 6.5 2 8 2 10 ns LOW 3 5 6 6 ns HIGH 3 5 6 6 ns D-type 90 80 66.7 50 MHz 83.3 74.1 62.5 47.6 MHz 133 100 83.3 66.6 MHz 117 90.9 76.9 62.5 MHz 100 83.3 88.3 MHz 4 5 8 ns Global Clock Width tWHS External Feedback tSLA 3 8 Register Data Hold Time Using Global Clock fMAXS 10 5 tHS 18 Max Min Max Min Max Min Max Unit 4 Setup Time from Input, I/O, or Feedback to Global Clock tWLS -15 3.5 tSS tCOS -12 D-type Product Term Clock to Output tWHA fMAXA 3 -10 1/(tSS + tCOS) T-type Maximum Frequency D-type Internal Feedback (fCNTS) Using T-type Global Clock (Note 2) No Feedback 1/(tWLS + tWHS) (Note 3) Setup Time from Input, I/O, or Feedback to Product Term Clock 166.7 4 MACHLV436-7/10/12/15 MACHLV436-7/10/12/15 (3.3-V Com'l) P R E L I M I N A R Y V A N T I S SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) -7 Parameter Symbol Parameter Description Min -10 -12 -15 Max Min Max Min Max Min Max Unit tHLA Latch Data Hold Time Using Product Term Clock tGOA Product Term Gate to Output tGWA Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 4 5 6 9 ns tSLS Setup Time from Input, I/O, or Feedback to Global Gate 6 7 8 10 ns tHLS Latch Data Hold Time Using Global Gate 0 0 0 0 ns tGOS Gate to Output 6 tGWS Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 5 tICO Input Register Clock to Combinatorial Output 14 tICS Input Register Clock to Output Register Setup tWICL 4 11 5 13 16 7.5 5 8 19 10 6 15.5 ns 11 6 18 ns ns ns 20 ns D-type 7 8 9 15 T-type 8 9 10 16 LOW 4.5 5 6 6 ns HIGH 4.5 5 6 6 ns 110 100 83.3 83.3 MHz Input Register Clock Width tWICH fMAXIR 4 Maximum Input Register Frequency 1/(tWICL + tWICH) tIGO Input Latch Gate to Combinatorial Output 12 14 16 20 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 14 16 18 22 ns tIGSA Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate 4 4 4 14 ns tIGSS Input Latch Gate to Output Latch Setup Using Global Output Latch Gate 9 9 9 16 ns tWIGL Input Latch Gate Width LOW 5 5 6 6 ns tAR Asynchronous Reset to Registered or Latched Output 12 14 16 20 ns tARW Asynchronous Reset Width (Note 2) 10 10 12 15 ns tARR Asynchronous Reset Recovery Time (Note 2) 8 8 10 15 ns tAP Asynchronous Preset to Registered or Latched Output 12 14 16 20 ns tAPW Asynchronous Preset Width (Note 2) 10 10 12 15 ns tAPR Asynchronous Preset Recovery Time (Note 2) 8 8 8 15 ns tEA Input, I/O, or Feedback to Output Enable 2 9.5 2 10 2 12 2 15 ns tER Input, I/O, or Feedback to Output Disable 2 9.5 2 10 2 12 2 15 ns 17 ns Input Register with Standard-Hold-Time Option tPDL tSIR Input Register Setup Time 2 2 2 2 ns tHIR 19 Input, I/O, or Feedback to Output Through Transparent Input Latch Input Register Hold Time 3 3 3 4 ns 10 MACHLV436-7/10/12/15 MACHLV436-7/10/12/15 (3.3-V Com'l) 12 14 P R E L I M I N A R Y V A N T I S SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) Parameter Symbol -7 Parameter Description Min -10 -12 -15 Max Min Max Min Max Min Max Unit tSIL Input Latch Setup Time 2 2 2 2 ns tHIL Input Latch Hold Time 3 3 3 4 ns tSLLA Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate 4 4 4 4 ns tSLLS Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate 7 8 9 12 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 12 14 16 19 ns 18 20 23 ns Input Register with Zero-Hold-Time Option tPDLI Input, I/O, or Feedback to Output Through Transparent Input Latch tSIRI Input Register Setup Time 6 6 6 6 ns tHIRI Input Register Hold Time 0 0 0 0 ns tSILI Input Latch Setup Time 6 6 6 6 ns tHILI Input Latch Hold Time 0 0 0 0 ns 16 tSLLAI Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate 11 13 16 16 ns tSLLSI Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate 12 15 18 18 ns tPDLLI Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 18 20 22 25 ns tLP Power-down mode delay adder. For macrocells in a power-down mode PAL block, this parameter must be added to: tPD, tCOA, tSS, tGOA, tSLS, tICO, tICS, tIGO, tIGOL, tIGSS, tAR, tARR, tAP, tAPR, tEA, tER, tPDL, tSLLS, tPDLL 2.5 2.5 2.5 2.5 ns tSLW Slow slew rate delay adder. For an output configured with slow slew rate option, this parameter must be added to: tPD, tCOA, tCOS, tGOA, tGOS, tICO, tIGO, tIGOL, tAP, tAR, tPDL, tPDLL 2.5 2.5 2.5 2.5 ns Power-Down Mode and Slow Slew Rate Option Notes: 1. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 20 MACHLV436-7/10/12/15 MACHLV436-7/10/12/15 (3.3-V Com'l) P R E L I M I N A R Y V A N T I S ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . ­65°C to +150°C Industrial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . ­55°C to +100°C Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . -40°C to +85°C Supply Voltage with Respect to Ground . . . . . . . . . . . ­0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.50 V to +5.5 V DC Input Voltage . . . . . . . . . . . .­0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = ­40°C to +85°C). . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = ­3.2 mA, VCC = Min VIN = VIH or VIL VOL Output LOW Voltage Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) VIL Input LOW Voltage Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) Unit V 0.5 2.4 Max 3.3 Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) IIH Typ IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) VIH Min V 2.0 V 0.8 V 10 µA ­10 µA IOZH Off-State Output Leakage Current VOUT = 5.25 V, VCC = Max HIGH VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current VOUT = 0 V, VCC = Max LOW VIN = VIH or VIL (Note 3) ­10 µA ISC Output Short-Circuit Current ­160 mA ICC Supply Current VOUT = 0.5 V, VCC = Max (Note 4) ­30 All PAL Blocks low-power VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 5.0 V, f = 1 MHz, TA = 25°C (Note 5) 70 mA All PAL Blocks full-power VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 5.0 V, f = 1 MHz, TA = 25°C (Note 5) 120 mA Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. MACH436-10/12/14/18 MACH436-10/12/14/18 (5-V Ind) 21 P R E L I M I N A R Y V A N T I S CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit 6 pF 8 pF VCC = 5.0 V, TA = 25°C, f = 1 MHz Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 1) -10 Parameter Symbol Parameter Description tPD Setup Time from Input, I/O, or Feedback to Product Term Clock tHA tCOA tWLA -14 -18 Min Max Min Max Min Max Min Max Unit Input, I/O, or Feedback to Combinatorial Output tSA -12 3 10 3 12 3 14 3 18 ns D-type 4 5 8 10 ns T-type 5 6 9 11 ns Register Data Hold Time Using Product Term Clock 4 5 8 10 ns Product Term Clock to Output 4 12 4 14 4 18 4 20 ns LOW 5 8 9 10 ns HIGH 5 8 9 10 ns D-type 62.5 52.6 38.5 33.3 MHz Maximum T-type Frequency Using D-type Internal Feedback (fCNTA) Product T-type Term Clock (Note 2) No Feedback 1/(tWLA + tWHA) (Note 3) 58.8 50.0 37 32.2 MHz 71.4 58.8 47.6 35.7 MHz 66.7 55.6 45.4 34.4 MHz 100 62.5 55.6 50.0 MHz D-type 6 7 10 12 ns T-type 7 8 11 13 ns 0 0 0 ns Product Term, Clock Width tWHA External Feedback 1/(tSA + tCOA) fMAXA tSS Setup Time from Input, I/O, or Feedback to Global Clock tHS Register Data Hold Time Using Global Clock 0 Global Clock to Output 2 tCOS tWLS 6.5 2 8 2 10 2 12 ns LOW 6 6 7 ns HIGH 5 6 6 7 ns D-type 80 66.7 50 41.7 MHz T-type 74.1 62.5 47.6 40.0 MHz D-type tWHS fMAXS 5 100 83.3 66.6 58.8 MHz T-type 90.9 76.9 62.5 55.5 MHz 100 83.3 88.3 71.4 MHz Global Clock Width Maximum Frequency Using Global Clock (Note 2) External Feedback 1/(tSS + tCOS) Internal Feedback (fCNTS) No Feedback (Note 3) 1/(tWLS + tWHS) tSLA 4 5 8 10 ns tHLA 22 Setup Time from Input, I/O, or Feedback to Product Term Clock Latch Data Hold Time Using Product Term Clock 4 5 8 10 ns MACH436-10/12/14/18 MACH436-10/12/14/18 (5-V Ind) P R E L I M I N A R Y V A N T I S SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 1) -10 Parameter Symbol Parameter Description -12 -14 -18 Min Max Min Max Min Max Min Max Unit tGOA Product Term Gate to Output 13 16 tGWA Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 5 6 9 11 ns tSLS Setup Time from Input, I/O, or Feedback to Global Gate 7 8 10 12 ns tHLS Latch Data Hold Time Using Global Gate 0 0 0 0 ns tGOS Gate to Output tGWS Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 7.5 5 19 10 6 15.5 22 11 6 18 12 7 20 ns ns ns 22 ns D-type tWICL 9 15 17 T-type 9 10 16 18 LOW 5 6 6 7 ns HIGH 5 6 6 7 ns 100 83.3 83.3 71.4 MHz Input Register Clock Width tWICH fMAXIR 8 Maximum Input Register Frequency 1/(tWICL + tWICH) tIGO Input Latch Gate to Combinatorial Output 14 16 20 22 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 16 18 22 24 ns tIGSA Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate 4 4 14 16 ns tIGSS Input Latch Gate to Output Latch Setup Using Global Output Latch Gate 9 9 16 18 ns tWIGL Input Latch Gate Width LOW 5 6 6 7 ns tAR Asynchronous Reset to Registered or Latched Output 14 16 20 22 ns tARW Asynchronous Reset Width (Note 2) 10 12 15 17 ns tARR Asynchronous Reset Recovery Time (Note 2) 8 10 15 17 ns tAP Asynchronous Preset to Registered or Latched Output 14 16 20 22 ns tAPW Asynchronous Preset Width (Note 2) 10 12 15 17 ns tAPR Asynchronous Preset Recovery Time (Note 2) 8 8 15 17 ns tEA Input, I/O, or Feedback to Output Enable 2 10 2 12 2 15 2 17 ns tER Input, I/O, or Feedback to Output Disable 2 10 2 12 2 15 2 17 ns 20 ns Input Register with Standard-Hold-Time Option tPDL tSIR Input Register Setup Time 2 2 2 2 ns tHIR Input Register Hold Time 3 3 4 4 ns tSIL 23 Input, I/O, or Feedback to Output Through Transparent Input Latch Input Latch Setup Time 2 2 2 2 ns 12 MACH436-10/12/14/18 MACH436-10/12/14/18 (5-V Ind) 14 17 P R E L I M I N A R Y V A N T I S SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 1) Parameter Symbol tHIL -10 Parameter Description -12 -14 -18 Min Max Min Max Min Max Min Max Unit Input Latch Hold Time 3 3 4 4 ns tSLLA Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate 4 4 4 4 ns tSLLS Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate 8 9 12 15 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 14 16 19 22 ns 18 20 23 26 ns Input Register with Zero-Hold-Time Option tPDLI Input, I/O, or Feedback to Output Through Transparent Input Latch tSIRI Input Register Setup Time 6 6 6 6 ns tHIRI Input Register Hold Time 0 0 0 0 ns tSILI Input Latch Setup Time 6 6 6 6 ns tHILI Input Latch Hold Time 0 0 0 0 ns tSLLAI Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate 13 16 16 16 ns tSLLSI Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate 15 18 18 18 ns tPDLLI Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 20 22 25 27 ns tLP Power-down mode delay adder. For macrocells in a power-down mode PAL block, this parameter must be added to: tPD, tCOA, tSS, tGOA, tSLS, tICO, tICS, tIGO, tIGOL, tIGSS, tAR, tARR, tAP, tAPR, tEA, tER, tPDL, tSLLS, tPDLL 2.5 2.5 2.5 2.5 ns tSLW Slow slew rate delay adder. For an output configured with slow slew rate option, this parameter must be added to: tPD, tCOA, tCOS, tGOA, tGOS, tICO, tIGO, tIGOL, tAP, tAR, tPDL, tPDLL 2.5 2.5 2.5 2.5 ns Power-Down Mode and Slow Slew Rate Option Notes: 1. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 24 MACH436-10/12/14/18 MACH436-10/12/14/18 (5-V Ind) P R E L I M I N A R Y V A N T I S ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . ­65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . ­55°C to +100°C Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . .­40°C to +85°C Supply Voltage with Respect to Ground . . . . . . . . . . . ­0.5 V to +4.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +3.0 V to +3.6 V DC Input Voltage . . . . . . . . . . . . . . . . . ­0.5 V to 6.0 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = ­40°C to +85°C). . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min VIN = VIH or VIL IOH = ­100 µA VOL Output LOW Voltage VCC = Min VIN = VIH or VIL (Note 1) Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs IIH Input HIGH Leakage Current IIL Input LOW Leakage Current Typ IOL = 100 µA VIH Min Max Unit VCC ­ 0.2 V 0.2 V 2.0 5.5 V ­0.3 0.8 V VIN = 3.6 V, VCC = Max (Note 2) 5 µA VIN = 0 V, VCC = Max (Note 2) ­5 µA IOZH Off-State Output Leakage Current VOUT = 3.6 V, VCC = Max HIGH VIN = VIH or VIL (Note 2) 5 µA IOZL Off-State Output Leakage Current VOUT = 0 V, VCC = Max LOW VIN = VIH or VIL (Note 2) ­5 µA ISC Output Short-Circuit Current ­160 mA ICC Supply Current VOUT = 0.5 V, VCC = Max (Note 3) ­15 All PAL Blocks low-power VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 3.3 V, f = 1 MHz, TA = 25°C (Note 4) 70 mA All PAL Blocks full-power VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 3.3 V, f = 1 MHz, TA = 25°C (Note 4) 120 mA Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. MACHLV436-10/12/14/18 MACHLV436-10/12/14/18 (3.3-V Ind) 25 P R E L I M I N A R Y V A N T I S CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit 6 pF 8 pF VCC = 3.3 V, TA = 25°C, f = 1 MHz Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 1) -10 Parameter Symbol Parameter Description tPD Setup Time from Input, I/O, or Feedback to Product Term Clock tHA tCOA tWLA 3 3 14 3 18 ns 10 ns T-type 5 6 9 11 ns Register Data Hold Time Using Product Term Clock 4 5 8 10 ns Product Term Clock to Output 4 12 4 14 4 18 4 20 ns LOW 5 8 9 10 ns HIGH 5 8 9 10 ns D-type 62.5 52.6 38.5 33.3 MHz Maximum T-type Frequency Using D-type Internal Feedback (fCNTA) Product T-type Term Clock (Note 2) No Feedback 1/(tWLA + tWHA) (Note 3) 58.8 50.0 37 32.2 MHz 71.4 58.8 47.6 35.7 MHz 66.7 55.6 45.4 34.4 MHz 100 62.5 55.6 50.0 MHz D-type 6 7 10 12 ns T-type 7 8 11 13 ns 0 0 0 ns Product Term, Clock Width 1/(tSA + tCOA) tHS Register Data Hold Time Using Global Clock 0 Global Clock to Output 2 6.5 2 8 2 10 2 12 ns LOW 5 6 6 7 ns HIGH 5 6 6 7 ns D-type 80 66.7 50 41.7 MHz T-type 74.1 62.5 47.6 40.0 MHz D-type 100 83.3 66.6 58.8 MHz T-type 90.9 76.9 62.5 55.5 MHz 100 83.3 88.3 71.4 MHz 5 8 10 ns 5 8 10 ns Global Clock Width tWHS fMAXS 3 8 Setup Time from Input, I/O, or Feedback to Global Clock tWLS 12 5 tSS Maximum Frequency Using Global Clock (Note 2) External Feedback 1/(tSS + tCOS) Internal Feedback (fCNTS) No Feedback (Note 3) 1/(tWLS + tWHS) tSLA Setup Time from Input, I/O, or Feedback to Product Term Clock 4 tHLA 26 10 Unit 4 External Feedback tCOS -18 D-type tWHA fMAXA -14 Min Max Min Max Min Max Min Max Input, I/O, or Feedback to Combinatorial Output tSA -12 Latch Data Hold Time Using Product Term Clock 4 MACHLV436-10/12/14/18 MACHLV436-10/12/14/18 (3.3-V Ind) P R E L I M I N A R Y V A N T I S SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 1) -10 Parameter Symbol Parameter Description -12 -14 -18 Min Max Min Max Min Max Min Max 13 16 tGOA Product Term Gate to Output tGWA Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 5 6 9 11 ns tSLS Setup Time from Input, I/O, or Feedback to Global Gate 7 8 10 12 ns tHLS Latch Data Hold Time Using Global Gate 0 0 0 0 ns tGOS Gate to Output tGWS Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 7.5 19 10 5 6 15.5 22 Unit 11 6 18 12 7 20 ns ns ns 22 ns D-type tWICL 9 15 17 T-type 9 10 16 18 LOW 5 6 6 7 ns HIGH 5 6 6 7 ns 100 83.3 83.3 71.4 MHz Input Register Clock Width tWICH fMAXIR 8 Maximum Input Register Frequency 1/(tWICL + tWICH) tIGO Input Latch Gate to Combinatorial Output 14 16 20 22 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 16 18 22 24 ns tIGSA Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate 4 4 14 16 ns tIGSS Input Latch Gate to Output Latch Setup Using Global Output Latch Gate 9 9 16 18 ns tWIGL Input Latch Gate Width LOW 5 6 6 7 ns tAR Asynchronous Reset to Registered or Latched Output 14 16 20 22 ns tARW Asynchronous Reset Width (Note 2) 10 12 15 17 ns tARR Asynchronous Reset Recovery Time (Note 2) 8 10 15 17 ns tAP Asynchronous Preset to Registered or Latched Output 14 16 20 22 ns tAPW Asynchronous Preset Width (Note 2) 10 12 15 17 ns tAPR Asynchronous Preset Recovery Time (Note 2) 8 8 15 17 ns tEA Input, I/O, or Feedback to Output Enable 2 10 2 12 2 15 2 17 ns tER Input, I/O, or Feedback to Output Disable 2 10 2 12 2 15 2 17 ns 20 ns Input Register with Standard-Hold-Time Option tPDL tSIR Input Register Setup Time 2 2 2 2 ns tHIR Input Register Hold Time 3 3 4 4 ns tSIL 27 Input, I/O, or Feedback to Output Through Transparent Input Latch Input Latch Setup Time 2 2 2 2 ns 12 MACHLV436-10/12/14/18 MACHLV436-10/12/14/18 (3.3-V Ind) 14 17 P R E L I M I N A R Y V A N T I S SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 1) Parameter Symbol tHIL -10 Parameter Description -12 -14 -18 Min Max Min Max Min Max Min Max Unit Input Latch Hold Time 3 3 4 4 ns tSLLA Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate 4 4 4 4 ns tSLLS Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate 8 9 12 15 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 14 16 19 22 ns 18 20 23 26 ns Input Register with Zero-Hold-Time Option tPDLI Input, I/O, or Feedback to Output Through Transparent Input Latch tSIRI Input Register Setup Time 6 6 6 6 ns tHIRI Input Register Hold Time 0 0 0 0 ns tSILI Input Latch Setup Time 6 6 6 6 ns tHILI Input Latch Hold Time 0 0 0 0 ns tSLLAI Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Gate 13 16 16 16 ns tSLLSI Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Gate 15 18 18 18 ns tPDLLI Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 20 22 25 27 ns tLP Power-down mode delay adder. For macrocells in a power-down mode PAL block, this parameter must be added to: tPD, tCOA, tSS, tGOA, tSLS, tICO, tICS, tIGO, tIGOL, tIGSS, tAR, tARR, tAP, tAPR, tEA, tER, tPDL, tSLLS, tPDLL 2.5 2.5 2.5 2.5 ns tSLW Slow slew rate delay adder. For an output configured with slow slew rate option, this parameter must be added to: tPD, tCOA, tCOS, tGOA, tGOS, tICO, tIGO, tIGOL, tAP, tAR, tPDL, tPDLL 2.5 2.5 2.5 2.5 ns Power-Down Mode and Slow Slew Rate Option Notes: 1. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 28 MACHLV436-10/12/14/18 MACHLV436-10/12/14/18 (3.3-V Ind) P R E L I M I N A R Y V A N T I S TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Typ Parameter Symbol Parameter Description PLCC Unit jc Thermal impedance, junction to case 5 °C/W ja Thermal impedance, junction to ambient 20 °C/W 200 lfpm air 17 °C/W 400 lfpm air 14 °C/W 600 lfpm air 12 °C/W 800 lfpm air 10 °C/W jma Thermal impedance, junction to ambient with air flow Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. MACH436/MACHLV436 MACH436/MACHLV436 29 P R E L I M I N A R Y V A N T I S SWITCHING WAVEFORMS Input, I/O, or Feedback VT tPD Combinatorial Output VT 21442A-3 Combinatorial Output Input, I/O, or Feedback Input, I/O, or Feedback VT tS VT tH tSL Gate VT Clock tHL tCO VT tPDL Registered Output VT tGO Latched Out VT 21442A-4 21442A-5 Registered Output Latched Output tWH Gate Clock VT tGWS tWL 21442A-6 21442A-7 Clock Width Gate Width Registered Input Registered Input VT tSIR Input Register Clock tHIR Input Register Clock VT tICO Combinatorial Output VT VT Output Register Clock VT tICS VT 21442A-8 Registered Input 21442A-9 Input Register to Output Register Setup Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns­4 ns typical. 30 MACH436/MACHLV436 MACH436/MACHLV436 P R E L I M I N A R Y V A N T I S SWITCHING WAVEFORMS Latched In VT tSIL tHIL VT Gate tIGO Combinatorial Output VT 21442A-10 Latched Input tPDLL Latched In VT Latched Out Input Latch Gate VT tIGOL tSLL tIGS VT Output Latch Gate 21442A-11 Latched Input and Output Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns­4 ns typical. MACH436/MACHLV436 MACH436/MACHLV436 31 P R E L I M I N A R Y V A N T I S SWITCHING WAVEFORMS tWICH Clock Input Latch Gate VT tWICL VT tWIGL 21442A-12 21442A-13 Input Register Clock Width Input Latch Gate Width tARW tAPW Input, I/O, or Feedback Input, I/O, or Feedback VT VT tAP tAR Registered Output Registered Output VT VT tARR tAPR VT Clock VT Clock 21442A-14 21442A-15 Asynchronous Reset Asynchronous Preset Input, I/O, or Feedback VT tER Outputs tEA VOH ­ 0.5 V VOL + 0.5 V VT 21442A-16 Output Disable/Enable Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns­4 ns typical. 32 MACH436/MACHLV436 MACH436/MACHLV436 P R E L I M I N A R Y V A N T I S KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance "Off" State KS000010-PAL KS000010-PAL SWITCHING TEST CIRCUIT VCC S1 R1 Output Test Point R2 CL 21442A-17 Commercial Specification tPD, tCO tEA tER S1 CL R1 R2 300 (1.6 K) 390 (1.6 K) Measured Output Value Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 35 pF (30 pF) 5 pF 1.5 V H Z: VOH ­ 0.5 V L Z: VOL + 0.5 V Values in parentheses are for 3.3-V devices. * Switching several outputs simultaneously should be avoided for accurate measurement. MACH436/MACHLV436 MACH436/MACHLV436 33 P R E L I M I N A R Y V A N T I S FMAX PARAMETERS The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called "fCNT." The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + t WICH ). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except f MAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. CLK CLK (SECOND CHIP) LOGIC tS REGISTER LOGIC REGISTER tCO tS fMAX External; 1/(tS + tCO) fMAX Internal (fCNT) CLK LOGIC CLK REGISTER REGISTER tS tSIR fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL) LOGIC tHIR fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH) 21442A-18 34 MACH436/MACHLV436 MACH436/MACHLV436 P R E L I M I N A R Y V A N T I S INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC 100 k VCC 1 k ESD Protection Input VCC VCC 100 k 1 k Preload Circuitry Feedback Input I/O MACH436/MACHLV436 MACH436/MACHLV436 21442A-19 35 P R E L I M I N A R Y V A N T I S POWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up Parameter Symbol reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Descriptions tPR Unit 10 Power-Up Reset Time tS Max µs Input or Feedback Setup Time tWL See Switching Characteristics Clock Width LOW VCC Power 4V tPR Registered Output tS Clock tWL 21442A-20 Power-Up Reset Waveform 36 MACH436/MACHLV436 MACH436/MACHLV436 P R E L I M I N A R Y V A N T I S DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the Vantis FusionPLD Catalog. MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Vantis Corporation P.O. Box 3755 920 DeGuigne Drive Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHXL Software Vantis Corporation P.O. Box 3755 920 DeGuigne Drive Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com Vantis-ABEL Software Vantis-Synario Software Cadence Design Systems 555 River Oaks Pkwy San Jose, CA 95134 (408) 943-1234 PLD Designer Verilog XL, LeapFrog Synario® Design Automation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 ABELTM SynarioTM Software ISDATA GmbH Daimlerstr. 51 D-76185 D-76185 Karlsruhe, Germany (721) 75 10 87 LOG/iC2 LOG/iC Classic Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (503) 690-6900 Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 SmartModel® Library PLDSynthesisTM II Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator MicroSim Corp. 20 Fairbanks Irvine, CA 92718 (714) 770-3022 MicroSim DesignLab PLogic, PLSyn MINC Incorporated 6755 Earl Drive, Suite 200 Colorado Springs, CO 80918 (800) 755-FPGA 755-FPGA or (719) 590-1155 PLDesigner-XLTM Software SUSIE-CAD 10000 Nevada Highway, Suite 201 Boulder City, NV 89005 (702) 293-2271 SUSIETM Simulator Synopsys 700 E. Middlefield Rd. Mountain View, CA 94040 Design Compiler (Requires MINC PLDesigner-XLTM) VSS Simulator MACH436/MACHLV436 MACH436/MACHLV436 37 P R E L I M I N A R Y V A N T I S MANUFACTURER Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 Viewlogic Systems, Inc. 293 Boston Post Road West Marlboro, MA 01752 (800) 442-4660 or (508) 480-0881 MANUFACTURER Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 891-1995 SOFTWARE DEVELOPMENT SYSTEMS MultiSIM Interactive Simulator LASAR ViewPLD PureSpeed Simulator, ViewSim Simulator, VCS Simulator TEST GENERATION SYSTEM ATGENTM Test Generation Software iNt GmbH Busenstrasse 6 D-8033 D-8033 Martinsried, Munich, Germany (87) 857-6667 PLDCheck 90 Vantis is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by Vantis of these products. 38 MACH436/MACHLV436 MACH436/MACHLV436 P R E L I M I N A R Y V A N T I S APPROVED PROGRAMMERS (subject to change) For more information on the products listed below, please consult the Vantis FusionPLD Catalog. MANUFACTURER PROGRAMMER CONFIGURATION Advin Systems, Inc. 1050-L 1050-L East Duane Ave. Sunnyvale, CA 940 86 (408) 243-7000 BP Microsystems 1000 N. Post Oak Rd., Suite 225 Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 Pilot-U84 BP1200 BP1200 UniSiteTM SMS GmbH Im Grund 15 88239 Wangen Germany (49) 7522-97280 ALL-07 ALL-07 Sprint Expert Stag House Silver Court Watchmead, Welwyn Garden City Herfordshire UK AL7 1LT 707-332148 System General 1603A South Main Street Milpitas, CA 95035 (408) 263-6667 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Road, Shin Diau Taipei, Taiwan 2-917-3005 BP1400 BP1400 Model 2900 Hi-Lo Systems 4F, No. 2, Sec. 5, Ming Shoh E. Road Taipei, Taiwan 2-764-0215 or Tribal Microsystems / Hi-Lo Systems 44388 South Grimmer Blvd. Fremont, CA 94538 (510) 623-8859 MVP BP2100 BP2100 BP2200 BP2200 Model 3900 AutoSite FLEX-700 FLEX-700 Sprint Optima Multisite Stag Quazar Stag Eclipse Turpro-1 MACH436/MACHLV436 MACH436/MACHLV436 Turpro-1/FX Turpro-1/TX 39 P R E L I M I N A R Y V A N T I S APPROVED ON-BOARD PROGRAMMERS MANUFACTURER PROGRAMMER CONFIGURATION Corelis, Inc. 12607 Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 JTAG PROG Vantis Corporation P.O. Box 3755 920 DeGuigne Drive Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHPRO 40 MACH436/MACHLV436 MACH436/MACHLV436 P R E L I M I N A R Y V A N T I S PHYSICAL DIMENSIONS PL 084 84-Pin Plastic Leaded Chip Carrier (measured in inches) 1.185 1.195 .042 .056 1.150 1.156 .062 .083 1.090 1.130 1.000 REF Pin 1 I.D. 1.185 1.195 1.150 1.156 .013 .021 .026 .032 .007 .013 .050 REF TOP VIEW .090 .130 .165 .180 SEATING PLANE SIDE VIEW 16-038-SQ 16-038-SQ PL 084 DF79 8-1-95 ae Trademarks Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof, and Bus-Friendly and Vantis are trademarks, and MACH, MACHXL, and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. MACH436/MACHLV436 MACH436/MACHLV436 41