NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| MAB 05 015 | Powerbox | DC-DC Converter, (9 to 36) V to (-5 / 5) V |
2 pages, |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: VOLTAGE VDC OUTPUT VOLTAGE VDC OUTPUT CURRENT mA INPUT CURRENT NO LOAD mA MAB 05 003 MAB 05 006 MAB 05 009 MAB 05 012 9-36 9-36 9-36 9-36 3.3 5 12 15 600 600 250 200 15 15 15 15 127 165 165 165 MAB 05 015 MAB 05 018 MAB 05 021 9-36 9-36 9-36 ±5 ±12 ±15 300 125 100 25 25 25 179 160 160 MAB 05 024 MAB 05 027 MAB 05 030 MAB 05 , 80 78 78 MAB 05 036 MAB 05 039 MAB 05 042 18-72 18-72 18-72 ±5 ±12 ±15 300 125 ... | Original |
2 pages, |
MAB 05 027 MAB 05 006 datasheet abstract |
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| Abstract: MAB 06 003 MAB 06 006 MAB 06 009 MAB 06 012 MAB 06 015 MAB 06 018 MAB 06 021 4.5-6 4.5-6 , , 36-72V. 500VDC 500VDC (3kV available). PI-type 3W. Line: Load: ±0.5%. Single: ±0.5 %. 10% min load is , 15 15 15 15 25 25 25 650 850 800 800 800 800 800 MAB 06 024 MAB 06 027 MAB 06 030 MAB 06 033 MAB 06 036 MAB 06 039 MAB 06 042 9-18 9-18 9-18 9-18 9-18 9-18 9-18 3.3 5 , 340 320 320 340 320 320 MAB 06 045 MAB 06 048 MAB 06 051 MAB 06 054 MAB 06 057 MAB 06 060 ... | Original |
2 pages, |
MAB 06 048 datasheet abstract |
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| Abstract: I L80?5±.0I0 -all^^tft 1.475 (37.47 +.008 -.006 0.20) -0.15) 7 6 3 2 1 1 44441 1 NOTES; 1. , ; RAS KBP 3: I REVISED PER UCR2001-0709 UCR2001-0709 SOMMER 01/05/29 REVISED PER UCR 1999-0340 LENZ 98/11/24 REVISED PER ECN" U7I442 U7I442 97/05/21 KBP REVISED PER ECR »U709I5 U709I5 MARANTO 97/02/06 REVISED PER ECR "U70564 U70564 MARANTO 97/01/15 REVISED PRE ECN" U70029 U70029 96/07/12 KSM REMOVE "X1 PER ECN* U60363 U60363 95/09/18 MAB X-RELEASE ECR U5 0548 95/01/09 REVISE ONLY ON CAD SYSTEM 6-CIR RECEPTACLE HOUSING . 125/(3.18) X .020/(0.5 I) SABRE ... | OCR Scan |
1 pages, |
datasheet abstract |
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| Abstract: GM432BST89R GM432BST89R 1% MAB SOT-89 1,000 Units / Tape & Reel GM432CT92B GM432CT92B 2 0.5% GM432AT92RL GM432AT92RL , , R1 = 10KW, R2 = TA = full range -1.0 mV/V (2) 0.15 0.5 mA 0.1 0.4 mA , VKA = 6V, Vref = 0V (3) VKA = 16V, Vref = 0V (3) 0.5 0.15 W NOTES: (1) See test circuit , , these versatile darlings are ideal volt- 0.5%, 1% or 2% reference voltage tolerance Adjustable , Package Shipping MAA A TO-92 1,000 Units/ ESD Bag 0.5% MAA A TO-92 2,000 ... | Original |
12 pages, |
TLV431 7805 SOT-89 1 in 7805 to92 GM432 GM432AST23R GM432AST25R SC431L 432G 7805 sot-89 7805 sot-23 MAA 7805 GM432 abstract |
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| Abstract: 0.135 VKA = 6V, Vref = 0V (3) VKA = 16V, Vref = 0V (3) 0.5 0.150 0.150 mA 0.05 0.15 , Low-voltage operation, down to 1.24V cision shunt regulators with specified thermal stability over 0.5 , Shipping GM432AT92B GM432AT92B 0.5% MAA A TO-92 1,000 Units/ ESD Bag GM432AT92RL GM432AT92RL 0.5% MAA A TO-92 2,000 Units/ Ammo Pack(Tape) GM432AST23R GM432AST23R 0.5% MAA SOT-23 3,000 Units/Tape &Reel GM432AST25R GM432AST25R 0.5% MAA SOT-25 3,000 Units/Tape &Reel GM432AS8R GM432AS8R 0.5 ... | Original |
13 pages, |
triac MAC 97 08 7805 sot-25 7805 to92 GM432AST23R GM432AST25R KA 7805 MAB marking SC431L TLV431 432G GM432 7805 SOT-89 1 in 7805 sot-89 7805 SOT-23 GM432 abstract |
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| Abstract: 1.0 dBm 1.9:1 1.9:1 + 0.5 dBm ^ DC Current (Max.) 20 mA 22 mA 24 mA y "Measured in a 50-ohm system , Peak Power (3 usee Max.) .0.5 Watt , x 0.15 DEEP THREADED INSERT -0.250 (6.35) 0.320-(8.12) DIMENSIONS ARE IN INCHES (MILLIMETERS , LINEAR S-PARAMETERS Ucc-15 Icc* 20.42 mA FREQ. SII S2I SI 2 S22 MHZ MA6 AN6 MAB ANS MAB A NB MAB ANS 1 .50 -Ë7.0 21 . .03 114.3 .005 129 .57 -62.6 2 .28 -65.5 33. .65 58.2 .007 69 .30 -65.6 3 ... | OCR Scan |
2 pages, |
AC573 2225-K 2225-K abstract |
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| Abstract: 11 Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) . . . , : Bit Number: 7 T4 6 5 4 3 2 1 0 T3 T2 T1 MAB HDT PDC/ VPS , Bit Allocation for the Header Time Mode (MAB = 0) 2.4 I2C Bus Header Time Mode Byte 1 , I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) 2.4 I2C Bus Header , of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) 2.4 ... | Original |
42 pages, |
Q67106-H5163 Q67100-H5164 NB b6 smd transistor Micronas i2c GPS05094 5650X 5650/X 6251-563-1PD 5650/X abstract |
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| Abstract: 11 Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) . . . , : Bit Number: 7 T4 6 5 4 3 2 1 0 T3 T2 T1 MAB HDT PDC/ VPS , Bit Allocation for the Header Time Mode (MAB = 0) 2.4 I2C Bus Header Time Mode Byte 1 , I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) 2.4 I2C Bus Header , of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) 2.4 ... | Original |
42 pages, |
Q67106-H5163 Q67100-H5164 NB b6 smd transistor GPS05094 diode smd marking BUF 5650X 5650/X 6251-563-1PD 5650/X abstract |
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| Abstract: Bit Allocation for the Header Time Mode (MAB=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . , T4 5 T2 T1 MAB HDT PDC/ VPS FOR1/ FOR2 Default: All bits are set to 0 on , 2.4 Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB=0) I2C , 2.4 Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB , (MAB=0) (cont'd) I2C Bus Header Time Mode Byte 9 bit 7 6 5 4 3 2 1 0 byte 30 bit ... | Original |
41 pages, |
Q67106-H5163 NB b6 smd transistor GPS05094 BDSP 7 bit hamming code 5650X Q67100-H5164 5650/X 5650/X abstract |
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| Abstract: MAB 4-2 4.1.1 RXB1 4 RB0 RB0 RB0 RB0 RXBnCTRL MAB MAB , RFXnSIDL.EXIDE MAB MAB RXBnCTRL.RXM 01 10 RFXnSIDL.EXIDERXBnCTRL.RXM RXBnCTRL.RXM / CANINTF.RXnIF 1 MCU MCU MCP2515 MCP2515 RXBnCTRL.RXM 11 MAB CAN CANINTE.RXnIE 1 INT , RXB0 RXB1 MAB MCU DS21801D DS21801D_CN 23 MCP2515 MCP2515 4.3 4.4.1 RXCAN CAN , 1 0 0 = 0 1 0 1 = 1 MAB RXB0 RXF0 RXF2 RXF0 ... | Original |
84 pages, |
RXB1 MCP2515 ID10 mcp2510 mcp2515 MCP2515 integrated controller MCP2515 dspic MCP2515 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| 20 1P VLIM1 33 20 1V * CAB4 42 20 0.1P CAB5 41 20 0.1P CAB6 17 20 0.1P MAB1 17 43 41 18 MOSFETN RAB5 43 44 10K DAB3 44 105 DA RAB7 105 43 8K CAB1 43 41 2.5P EAB3 44 41 32 20 10 MAB2 17 45 22 20 1 CC 23 21 10P *DOMINANT POLE AT 22.5KHZ EG 20 18 10 18 0.5 * DVL1 22 59 DA *VOLTAGE LIMITING DVL2 60 22 DA ELIM2 59 61 10 18 0.5 ELIM1 63 60 10 18 0.5 ECOMP2 62 20 65 66 1 ECOMP IMPEDENCE ROUT2 71 75 0.15 LOUT 75 76 23.87N *1.5 OHMS AT 10MHz RLOAD 76 20 10MEG 10MEG 10MEG 10MEG www.datasheetarchive.com/files/maxim/modeling-simulation/spice/operational-amplifiers/macro/max4024.fam |
Maxim | 04/10/2012 | 5.79 Kb | FAM | max4024.fam |
| 20 1P VLIM1 33 20 1V * CAB4 42 20 0.1P CAB5 41 20 0.1P CAB6 17 20 0.1P MAB1 17 43 41 18 MOSFETN RAB5 43 44 10K DAB3 44 105 DA RAB7 105 43 8K CAB1 43 41 2.5P EAB3 44 41 32 20 10 MAB2 17 45 22 20 1 CC 23 21 10P *DOMINANT POLE AT 22.5KHZ EG 20 18 10 18 0.5 * DVL1 22 59 DA *VOLTAGE LIMITING DVL2 60 22 DA ELIM2 59 61 10 18 0.5 ELIM1 63 60 10 18 0.5 ECOMP2 62 20 65 66 1 ECOMP IMPEDENCE ROUT2 71 75 0.15 LOUT 75 76 23.87N *1.5 OHMS AT 10MHz RLOAD 76 20 10MEG 10MEG 10MEG 10MEG www.datasheetarchive.com/files/maxim/modeling-simulation/spice/operational-amplifiers/orcad/max4024.lib |
Maxim | 01/04/2004 | 5.63 Kb | LIB | max4024.lib |
| CSA2.45MG 30 30 1M - MOTOROLA MC68HC05C4 CSA2.45MG TOSHIBA TMPZ84C015AF CSA2.45MG040 45MG040 45MG040 45MG040 100 100 - - NEC u .45MG040 45MG040 45MG040 45MG040 100 100 - 680 MOTOROLA XC68HC05C4FN1 CSA2.45MG040 45MG040 45MG040 45MG040 100 100 1M 680 MOTOROLA XC68HC05C5PI CSA2.45MG040 45MG040 45MG040 45MG040 100 100 1M 470 MOTOROLA XC68HC05C9FN1 CSA2.45MG040 45MG040 45MG040 45MG040 100 100 1M 680 www.datasheetarchive.com/files/murata/products/data/a07x/c81g06c1.txt |
Murata | 17/09/1996 | 18.89 Kb | TXT | c81g06c1.txt |
| - - 1M - MOTOROLA MC68HC05C4 CST2.45MGW 45MGW 45MGW 45MGW - - 1M CST2.45MGW 45MGW 45MGW 45MGW - - - - MOTOROLA XC68HC05C4FN1 CST2.45MGW040 45MGW040 45MGW040 45MGW040 - - 1M 680 MOTOROLA XC68HC05C5PI CST2.45MGW040 45MGW040 45MGW040 45MGW040 - - 1M 470 MOTOROLA XC68HC05C9FN1 CST2.45MGW040 45MGW040 45MGW040 45MGW040 - - 1M 680 MOTOROLA XC68HC05E CST2.45MGW040 45MGW040 45MGW040 45MGW040 - - 1M 680 MOTOROLA XC68HC05P8PI www.datasheetarchive.com/files/murata/products/data/a07x/c81g06p1.txt |
Murata | 17/09/1996 | 24.95 Kb | TXT | c81g06p1.txt |
| GND2 10MEG 10MEG 10MEG 10MEG R2 VDD2 56 10MEG 10MEG 10MEG 10MEG EVCVS1 VM IGND VALUE = {0.5*V(IAVDD,IGND)} EAVDD _0 EVCVS1 VM IGND VALUE = {0.5*(V(IAVDD,IGND)} EGND IGND 0 GND1 0 1 .ENDS .SUBCKT } *I2 40 0 {I0} *E3 1 2 40 0 1 *.PARAM CA={38.7746*0.9} *.PARAM BA={206.5114M 5114M 5114M 5114M*0.5} .PARAM CA={38 = {(C0 + MC*V(VDD2,GND2)*TANH(B0 + MB*V(VDD2,GND2)*(V(INP,INN) + A0/B0 + MA/B0*V(VDD2,GND2) + D0 KAPPA = 1.0 .PARAM THETA = 0.23 .PARAM ETA = 3 *.PARAM KPN = 5.0E-05 *.PARAM KPP = 2.0E-05 .PARAM www.datasheetarchive.com/download/41034043-923217ZC/amc1200_tina-ti_spice_model.zip (AMC1200.lib) |
Texas Instruments | 11/08/2011 | 11.81 Kb | ZIP | amc1200_tina-ti_spice_model.zip |
| ST | PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY (3.3V) Datasheet PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY (3.3V) STE10/100A STE10/100A STE10/100A STE10/100A Document Format Size Document Number Date Update Pages Portable Document Format 6773 01/09/2000 66 Raw Text Format 1/66 STE10/100A STE10/100A STE10/100A STE10/100A September 2000 This is preliminary information on a new product now in development. Details are subject to www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6773.htm |
STMicroelectronics | 20/10/2000 | 111.92 Kb | HTM | 6773.htm |
| ST | PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY (3.3V) Datasheet PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY (3.3V) STE10/STE100A STE10/STE100A STE10/STE100A STE10/STE100A Document Format Size Document Number Date Update Pages Portable Document Format 6773 08/01/2001 66 Raw Text Format 1/66 STE10/100A STE10/100A STE10/100A STE10/100A January 2001 This is preliminary information on a new pro www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6773-v1.htm |
STMicroelectronics | 09/01/2001 | 108.62 Kb | HTM | 6773-v1.htm |
| ST | PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY STE10/100 STE10/100 STE10/100 STE10/100 PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY Document Number: 6641 Date Update: 18/05/99 Pages: 69 The document is available in the following formats: Portable Document Format and Raw Text Format 1/69 STE10/100 STE10/100 STE10/100 STE10/100 May 1999 This is preliminary information on a new product now in development. Details are subject to change without notice. 1.0 DESCRIPTION The STE10/100 STE10/100 STE10/100 STE10/100 is a high performance PCI www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6641.htm |
STMicroelectronics | 14/06/1999 | 112.55 Kb | HTM | 6641.htm |
| "Serial Channel 0 Clock Control Register" BFLD S0CLC.0-15 S0CLC,rw 0 0 SFR 0x " BFLD BUSCON0.3-0 MCTC,rw 0 0 BIT BUSCON0.4 RWDC0,rw 0 0 BIT BUSCON0.5 .14 CSREN0,rw 0 0 BIT BUSCON0.15 CSWEN0,rw 0 0 SFR 0xFF14 BUSCON1,0x0000 undef 0 BIT PECC0.15 PT,rw 0 0 SFR 0xFEC2 PECC1,0x0000 undef "PEC Channel www.datasheetarchive.com/files/infineon/mc_data/dave/products/c165utah.dip!/c165utah/data/c165utah.regs |
Infineon | 23/08/2002 | 7427.8 Kb | DIP | c165utah.dip |
| * * $Revision: 1.3 $ * $Date: 1998/05/06 23:27:16 $ * $Modtime $ * $Author: bblack $ * $Workfile #define OFFS_SD1RRCAL 0x015e // SmartDMA1 Receive Ring Count / Address Low Register #define OFFS_SD1TRAH 0x015c // SmartDMA1 Transmit Ring Address High Register #define OFFS_SD1TRCAL 0x015a // SmartDMA1 Transmit Ring www.datasheetarchive.com/download/70183754-7840ZC/usb.zip (am186cc.h) |
AMD | 11/08/1998 | 116.87 Kb | ZIP | usb.zip |