M88E3080 100BASE-TX 10BASE-T 100BASE-FX 100BASE-TX/FX MV-S100147-00 - Datasheet Archive

 

Integrated 8 Port 10/100 Fast Ethernet Transceiver Preliminary Information 1. FEATURES OVERVIEW · Eight independent IEEE

 

M88E3080 M88E3080 Integrated 8 Port 10/100 Fast Ethernet Transceiver Preliminary Information 1. FEATURES OVERVIEW · Eight independent IEEE 802.3 compliant 100BASE-TX 100BASE-TX and 10BASE-T 10BASE-T ports · IEEE 802.3 100BASE-FX 100BASE-FX compliant support for fiber-optics · IEEE 802.3u Auto-Negotiation support for automatic speed and duplex selection · Reduced MII (RMII) or Serial MII (SMII) for reduced pin count · FEFI support when Auto-Negotiation disabled · Baseline wander correction · 100BASE-TX 100BASE-TX performance over 150 meters · Flexible serial and direct drive LED support · Standard MII Management interface for register access · Programmable interrupt to minimize polling The M88E3080 M88E3080 is an eight port physical layer device for Ethernet 100BASE-TX/FX 100BASE-TX/FX and 10BASE-T 10BASE-T applications. It contains all the active circuitry to interface eight controllers that supports either the Reduced Media Independent Interface (RMII) or the Serial Media Independent Interface (SMII) to 100BASE-TX 100BASE-TX and 10BASE-T 10BASE-T media. A pseudo-ECL (PECL) interface is also available on a per port basis to support 100BASE-FX 100BASE-FX applications. The M88E3080 M88E3080 uses advanced mixed signal processing (MSP) and power management techniques for low power dissipation and high port count integration. It is manufactured in an all CMOS process. · IEEE 1149.1 Standard Test Access Port and Boundary Scan Compatible 125 MHz DPLL Receiver FEFD Rx PCS PMA Receive State Machine Digital Adaptive Equalizer RX[n]+ RX[n]- AGC Gain Control 6.5-bit ADC S/H Baseline Wander Canceller FIR Filter Line Quality Monitor SerialParallel Symbol Alignment Manchester -NRZ SerialParallel SFD Alignment 5B/ 4B SYNC (TX_EN[0]) SMII RX DFE SEL_RMII FIFO PECL Receiver SDET[n] SDET[n]- Descrambler NRZI -NRZ 10Mb/s Receiver FEFG RXD[0][n] RXD[1][n] CRS_DV[n] RX_ER[n] RMII RX Transmit State Machine SEL_FXTX[n] Transmitter PreDriver TX[n]+ NRZNRZI Scrambler ParallelSerial 4B/ 5B SMII TX TP Driver DAC TX[n]- Digital FIR NRZManchester TXD[0][n] TXD[1][n] TX_EN[n] RMII TX Tx PCS PMA LED DIST LED[n] [2:0] AutoNegotiation Port LED Port Registers TX_DUPLEX FX_DUPLEX DIS_FEFI Port 0 Port 1 . . Port 6 Port 7 RSET + RSET VREF CONTROL HSDAC HSDAC + TSTPT Regulator/ References RESET CLKREF Clock/Oscillator Global Registers LED PHYADR[1:0] MDC MDIO INT Management Interface JTAG TRST TDI TMS TCK TDO LEDENA LEDCLK LEDSER Global Figure 1: M88E3080 M88E3080 Functional Block Diagram Copyright © 1999 MARVELL Semiconductor, Inc. MARVELL COMPANY CONFIDENTIAL. Do Not Duplicate Without Permission. Document Classification: Proprietary Document Number: MV-S100147-00 MV-S100147-00 Revision: D Sept. 27, 1999 Page 1 of 2 M88E3080 M88E3080 Integrated 8 Port 10/100 Fast Ethernet Transceiver 2. FUNCTIONAL DESCRIPTION The M88E3080 M88E3080 is an 8 port physical layer device with IEEE 802.3 compliant interfaces for 100BASE-TX 100BASE-TX and 10BASE-T 10BASE-T. Upon power-up and de-assertion of reset, the ports are individually configured to operate in either 100BASE-TX/10BASE-T 100BASE-TX/10BASE-T or 100BASE-FX 100BASE-FX. Auto-Negotiation can be selectively enabled and disabled at hardware reset. Auto-Negotiation can subsequently be enabled via software. If the 100BASE-FX 100BASE-FX mode is selected then AutoNegotiation is permanently disabled for the port and the link operates in 100Mb/s. If Auto-Negotiation is enabled then the M88E3080 M88E3080 will negotiate with its link partner to determine the speed and duplex with which to operate on. If the link partner is unable to auto-negotiate the link, the M88E3080 M88E3080 will go into the parallel detect mode to determine the speed of the link partner. The M88E3080 M88E3080 interfaces to eight 10/100 Media Access Controllers (MAC) via the RMII or SMII. All ports operate in the same mode and the M88E3080 M88E3080 is dependent on a continuous 50MHz (RMII) or 125MHz (SMII) clock from an external source. Registers are accessible via the MII management interface. An interrupt pin is programmable to generate interrupts based on changes in status. A serial LED interface provides various status bits that can be shifted into external shift registers and displayed. Direct drive LED support is also available with each port capable of supporting 3 different LED statuses. Copyright © 1999 MARVELL Semiconductor, Inc. MARVELL COMPANY CONFIDENTIAL. Do Not Duplicate Without Permission. Document Classification: Proprietary Document Number: MV-S100147-00 MV-S100147-00 Revision: D Sept. 27, 1999 Page 2 of 2