M87C251SB A5091-01 A5092-01 A5093-01 A10/P2 A11/P2 A12/P2 A13/P2 A14/P2 - Datasheet Archive

 

M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Military s Real-time and Programmed Wait State Bus Operation s User-selectable

 

PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Military s Real-time and Programmed Wait State Bus Operation s User-selectable Configurations: - External Wait States (0-3 wait states) s Binary-code Compatible with MCS® 51 - Address Range & Memory Mapping s Pin Compatible with 44-pin PLCC and 40pin PDIP MCS 51 Sockets - Page Mode s 32 Programmable I/O Lines s Register-based MCS® 251 Architecture - 40-byte Register File - Registers Accessible as Bytes, Words, or Double Words s Enriched MCS 51 Instruction Set - 16-bit and 32-bit Arithmetic and Logic Instructions - Compare and Conditional Jump Instructions s Seven Maskable Interrupt Sources with Four Programmable Priority Levels s Three Flexible 16-bit Timer/counters s Hardware Watchdog Timer s Programmable Counter Array - High-speed Output - Compare/Capture Operation - Pulse Width Modulator - Expanded Set of Move Instructions - Watchdog Timer s Linear Addressing s 256-Kbyte Expanded External Code/Data Memory Space s Programmable Serial I/O Port - Framing Error Detection s 16-Kbyte On-chip EPROM - Automatic Address Recognition s 16-bit Internal Code Fetch s High-performance CHMOS Technology s 64-Kbyte Extended Stack Space s Static Standby to 16-MHz Operation s 1-Kbyte On-chip Data RAM s Complete System Development Support - Compatible with Existing Tools s 8-bit, 2-clock External Code Fetch in Page Mode s Fast MCS 251 Instruction Pipeline s Available in Two Product Grades - QML Certified SE3 (­40°C to +110°C) - QML Certified SE1 (­55°C to +125°C) - New MCS 251 Tools Available: Compiler, Assembler, Debugger, ICE s Available in 44-pin LCC and 40-pin Side-brazed DIP Packages A member of the Intel family of 8-bit MCS 251 microcontrollers, the M87C251SB M87C251SB is binary-code compatible with MCS 51 microcontrollers and pin compatible with 44-pin PLCC MCS 51 microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and efficient C-language support. The M87C251SB M87C251SB has 1 Kbyte of on-chip RAM and 16 Kbytes of on-chip EPROM. A variety of features can be selected by new user-programmable configurations. COPYRIGHT © INTEL CORPORATION, 1996 July 1996 Order Number: 271354-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-764 or call 1-800-548-4725 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER I/O Ports and Peripheral Signals System Bus and I/O Ports P0.7:0 P2.7:0 Port 0 Drivers Port 2 Drivers P1.7:0 Code EPROM 16 Kbytes Data RAM 1 Kbyte P3.7:0 Port 1 Drivers Port 3 Drivers Memory Data (16) Watchdog Timer Memory Address (16) Code Bus (16) Code Address (24) Interrupt Handler Data Bus (8) SRC1 (8) SRC2 (8) Data Address (24) Instruction Sequencer IB Bus (8) Peripheral Interface Bus Interface Timer/ Counters PCA Serial I/O ALU Data Memory Interface Register File Clock & Reset Peripherals DST (16) MCS® 251 Microcontroller Core Clock & Reset M87C251SB M87C251SB Microcontroller A5091-01 A5091-01 Figure 1. M87C251SB M87C251SB Block Diagram PRODUCT PREVIEW 3 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER PINOUT 6 5 4 3 2 1 44 43 42 41 40 P1.4 / CEX1 P1.3 / CEX0 P1.2 / ECI P1.1 / T2EX P1.0 / T2 VSS1 VCC AD0 / P0.0 AD1 / P0.1 AD2 / P0.2 AD3 / P0.3 1.0 7 8 9 10 11 12 13 14 15 16 17 M87C251SB M87C251SB View of component as mounted on PC board 39 38 37 36 35 34 33 32 31 30 29 AD4 / P0.4 AD5 / P0.5 AD6 / P0.6 AD7 / P0.7 EA# / VPP VSS2 ALE / PROG# PSEN# A15 / P2.7 A14 / P2.6 A13 / P2.5 P3.6 / WR# P3.7 / RD# / A16 XTAL2 XTAL1 VSS VSS2 A8 / P2.0 A9 / P2.1 A10 / P2.2 A11 / P2.3 A12 / P2.4 18 19 20 21 22 23 24 25 26 27 28 P1.5 / CEX2 P1.6 / CEX3 / WAIT# P1.7 / CEX4 / A17 / WCLK RST P3.0 / RXD VCC2 P3.1 / TXD P3.2 / INT0# P3.3 / INT1# P3.4 / T0 P3.5 / T1 A5092-01 A5092-01 Figure 2. M87C251SB M87C251SB 44-pin LCC Package 4 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER P1.0 / T2 1 40 VCC P1.1 / T2EX 2 39 AD0 / P0.0 P1.2 / ECI 3 38 AD1 / P0.1 P1.3 / CEX0 4 37 AD2 / P0.2 P1.4 / CEX1 5 36 AD3 / P0.3 P1.5 / CEX2 6 35 AD4 / P0.4 P1.6 / CEX3 / WAIT# 7 34 AD5 / P0.5 P1.7 / CEX4 / A17 / WCLK 8 33 AD6 / P0.6 RST 9 32 P3.0 / RXD 10 31 AD7 / P0.7 EA# / VPP M87C251SB M87C251SB P3.1 / TXD 11 30 ALE / PROG# P3.2 / INT0# 12 29 PSEN# P3.3 / INT1# 13 28 A15 / P2.7 P3.4 / T0 14 27 A14 / P2.6 P3.5 / T1 15 26 A13 / P2.5 P3.6 / WR# 16 25 A12 / P2.4 P3.7 / RD# / A16 17 24 A11 / P2.3 XTAL2 18 23 A10 / P2.2 XTAL1 VSS 19 22 A9 / P2.1 20 21 A8 / P2.0 View of component as mounted on PC board A5093-01 A5093-01 Figure 3. M87C251SB M87C251SB 40-pin Ceramic DIP Package PRODUCT PREVIEW 5 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 1. M87C251SB M87C251SB Pin Assignment LCC DIP LCC DIP Name VSS1 1 2 Name 1 23 P1.0/T2 24 21 VSS2 A8/P2.0 3 2 P1.1/T2EX 25 22 A9/P2.1 4 3 P1.2/ECI 26 23 A10/P2 A10/P2.2 5 4 P1.3/CEX0 27 24 A11/P2 A11/P2.3 6 5 P1.4/CEX1 28 25 A12/P2 A12/P2.4 7 6 P1.5/CEX2 29 26 A13/P2 A13/P2.5 8 7 P1.6/CEX3/WAIT# 30 27 A14/P2 A14/P2.6 9 8 P1.7/CEX4/A17/WCLK 7/CEX4/A17/WCLK 31 28 A15/P2 A15/P2.7 10 9 RST 32 29 PSEN# 11 10 P3.0/RXD 33 30 VCC2 34 12 ALE/PROG# VSS2 13 11 P3.1/TXD 35 31 EA#/VPP 14 12 P3.2/INT0# 36 32 AD7/P0.7 15 13 P3.3/INT1# 37 33 AD6/P0.6 16 14 P3.4/T0 38 34 AD5/P0.5 17 15 P3.5/T1 39 35 AD4/P0.4 18 16 P3.6/WR# 40 36 AD3/P0.3 19 17 P3.7/RD#/A16 41 37 AD2/P0.2 20 18 XTAL2 42 38 AD1/P0.1 21 6 19 XTAL1 43 39 AD0/P0.0 22 20 VSS 44 40 VCC PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 2. M87C251SB M87C251SB LCC/DIP Pin Assignments Arranged by Functional Category Address & Data Name LCC Input/Output DIP Name LCC DIP AD0/P0.0 43 39 P1.0/T2 2 1 AD1/P0.1 42 38 P1.1/T2EX 3 2 AD2/P0.2 41 37 P1.2/ECI 4 3 AD3/P0.3 40 36 P1.3/CEX0 5 4 AD4/P0.4 39 35 P1.4/CEX1 6 5 AD5/P0.5 38 34 P1.5/CEX2 7 6 AD6/P0.6 37 33 P1.6/CEX3/WAIT# 8 7 AD7/P0.7 36 32 P1.7/CEX4/A17/WCLK 7/CEX4/A17/WCLK 9 8 A8/P2.0 24 21 P3.0/RXD 11 10 A9/P2.1 25 22 P3.1/TXD 13 11 A10/P2 A10/P2.2 26 23 P3.4/T0 16 14 A11/P2 A11/P2.3 27 24 P3.5/T1 17 15 A12/P2 A12/P2.4 28 25 A13/P2 A13/P2.5 29 26 A14/P2 A14/P2.6 30 27 LCC DIP A15/P2 A15/P2.7 31 28 VCC 44 40 P3.7/RD#/A16 19 17 VCC2 12 P1.7/CEX4/A17/WCLK 7/CEX4/A17/WCLK 9 8 VSS 22 Power & Ground Name VSS1 Processor Control Name 1 VSS2 20 23, 34 EA#/VPP 35 31 LCC DIP P3.2/INT0# 14 12 Bus Control & Status P3.3/INT1# 15 13 Name EA#/VPP 35 31 P3.6/WR# 18 16 RST 10 9 P3.7/RD#/A16 19 17 XTAL1 21 18 ALE/PROG# 33 30 XTAL2 20 19 PSEN# 32 29 PRODUCT PREVIEW LCC DIP 7 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 2.0 SIGNALS Table 3. Signal Descriptions Signal Name 18th Address Bit (A17). Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0 (see the 8XC251SA/SB/SP/SQ 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual). See also RD# and PSEN#. P1.7/CEX4/ WCLK O A16 Description O A17 A15:8 Alternate Function Type Address Line 16. See RD#. RD# O Address Lines. Upper address lines for the external bus. P2.7:0 AD7:0 I/O Address/Data Lines. Multiplexed lower address lines and data lines for external memory. P0.7:0 ALE O Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus. PROG# CEX4:0 I/O Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode. P1.6:3 P1.7/A17/ 7/A17/ WAIT# EA# I External Access. Directs program memory accesses to on-chip or off- VPP chip code memory. For EA# = 0, all program memory accesses are offchip. For EA# = 1, an access is to on-chip EPROM if the address is within the range of the on-chip EPROM; otherwise the access is offchip. The value of EA# is latched at reset. For devices without on-chip EPROM, EA# must be strapped to ground. ECI I PCA External Clock Input. External clock input to the 16-bit PCA timer. P1.2 INT1:0# I External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#. P3.3:2 PROG# I Programming Pulse. The programming pulse is applied to this pin for programming the on-chip EPROM. ALE P0.7:0 I/O Port 0. This is an 8-bit, open-drain, bidirectional I/O port. AD7:0 P1.0 P1.1 P1.2 P1.7:3 I/O Port 1. This is an 8-bit, bidirectional I/O port with internal pullups. T2 T2EX ECI CEX3:0 CEX4/A17/ CEX4/A17/ WAIT#/ WCLK P2.7:0 I/O Port 2. This is an 8-bit, bidirectional I/O port with internal pullups. A15:8 8 The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin LCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 3. Signal Descriptions (Continued) Signal Name Type Description Alternate Function P3.0 P3.1 P3.3:2 P3.5:4 P3.6 P3.7 I/O Port 3. This is an 8-bit, bidirectional I/O port with internal pullups. RXD TXD INT1:0# T1:0 WR# RD#/A16 PSEN# O Program Store Enable. Read signal output. This output is asserted for a memory address range that depends on bits RD0 and RD1 in configuration byte UCONFIG0 (see the RD# signal description and 8XC251SA/SB/SP/SQ 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual). - RD# O Read or 17th Address Bit (A16). Read signal output to external data memory or 17th external address bit (A16), depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. (See the PSEN# signal description and 8XC251SA/SB/SP/SQ 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual). P3.7/A16 7/A16 RST I Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and VCC. Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation. - RXD I/O Receive Serial Data. RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3. P3.0 T1:0 I Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. P3.5:4 I/O Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is the external clock input. For the clock-out mode, it is the timer 2 clock output. P1.0 T2EX I Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. In the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. P1.1 TXD O Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3. P3.1 VCC PWR Supply Voltage. Connect this pin to the +5V supply voltage. - VCC2 PWR Secondary Supply Voltage 2. This supply voltage connection is provided to reduce power supply noise. Connection of this pin to the +5V supply voltage is recommended. However, when using the 8XC251SB 8XC251SB as a pin-for-pin replacement for the 8XC51FX 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) - T2 The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin LCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). PRODUCT PREVIEW 9 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 3. Signal Descriptions (Continued) Signal Name Type VPP I VSS Alternate Function Description Programming Supply Voltage. The programming supply voltage is applied to this pin for programming the on-chip EPROM. EA# GND Circuit Ground. Connect this pin to ground. - VSS1 GND Secondary Ground. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the M87C251SB M87C251SB as a pin-forpin replacement for the 8XC51BH 8XC51BH, VSS1 can be unconnected without loss of compatibility. (Not available on DIP) - VSS2 GND Secondary Ground 2. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SB 8XC251SB as a pin-for-pin replacement for the 8XC51FX 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) - WAIT# I Real-time Wait State Input. The real-time WAIT# input is enabled by writing a logical `1' to the WCON.0 (RTWE) bit at S:A7H. During bus cycles, the external memory system can signal `system ready' to the microcontroller in real time by controlling the WAIT# input signal on the port 1.6 input. P1.6/CEX3 WCLK O Wait Clock Output. The real-time WCLK output is driven at port 1.7 (WCLK) by writing a logical `1' to the WCON.1 (RTWCE) bit at S:A7H. When enabled, the WCLK output produces a square wave signal with a period of one-half the oscillator frequency. P1.7/CEX4/ A17 WR# O Write. Write signal output to external memory. P3.6 XTAL1 I Input to the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. - XTAL2 O Output of the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. - The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin LCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). 10 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 4. Memory Signal Selections (RD1:0) RD1:0 P1.7/CEX/ A17/WCLK A17/WCLK P3.7/RD#/A16 PSEN# WR# Features 0 0 A17 A16 Asserted for all addresses Asserted for writes to all memory locations 256-Kbyte external memory 0 1 P1.7/CEX4/ WCLK A16 Asserted for all addresses Asserted for writes to all memory locations 128-Kbyte external memory 1 0 P1.7/CEX4/ WCLK P3.7 only Asserted for all addresses Asserted for writes to all memory locations 64-Kbyte external memory. One additional port pin. 1 1 P1.7/CEX4/ WCLK RD# asserted for addresses 7F:FFFFH Asserted for 80:0000H 0000H Asserted only for writes to MCS 51 microcontroller data memory locations. 64-Kbyte external memory. Compatible with MCS 51 microcontrollers. PRODUCT PREVIEW 11 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 3.0 ADDRESS MAP Table 5. M87C251SB M87C251SB Address Map Internal Address) Description Notes FF:FFFFH FF:4000H 4000H External Memory except the top eight bytes (FF:FFF8H­FF:FFFFH), which are reserved for the configuration array. 1, 3, 10 FF:3FFFH FF:0000H 0000H External memory or on-chip nonvolatile memory (16 Kbytes) 3, 4, 5 FE:FFFFH FE:0000H 0000H External Memory 3 FD:FFFFH 02:0000H 0000H Reserved 6 01:FFFFH 01:0000H 0000H External Memory 3 00:FFFFH 00:E000H E000H External memory or with configuration bit EMAP# = 0, addresses in this range access on-chip code memory in region FF:. 5, 7 00:DFFFH 00:0420H 0420H External Memory 7 00:041FH 041FH 00:0080H 0080H On-chip RAM (928 bytes, 00:0080H 0080H­00:041FH 041FH) 7 00:007FH 007FH 00:0020H 0020H On-chip RAM (96 bytes, 00:0020­00:07FH) 8 00:001FH 001FH 00:0000H 0000H Storage for R0­R7 of Register File 2, 9 NOTES: 1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration). 2. The special function registers (SFRs) and the register file have separate internal address spaces. 3. Data in this area is accessible by indirect addressing only. 4. Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information See EA#. See also UCONFIG1:0 bit definitions in the 8XC251SA/SB/SP/SQ 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual. 5. The 16-Kbyte EPROM devices allow internal locations FF:2000H 2000H­FF:3FFFH to map into region 00:. In this case, if EA# = 1, a data read to 00:E000H E000H­00:FFFFH is redirected to internal EPROM (see bit 1 in UCONFIG0). 6. This reserved area returns indeterminate values. 7. Data is accessible by direct and indirect addressing. 8. Data is accessible by direct, indirect, and bit addressing. 9. Data is accessible by direct, indirect, and register addressing. 10. Eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information. 12 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ­SE1 . ­55°C to +125°C ­SE3 . ­40°C to +110°C Storage Temperature . ­65°C to +150°C Voltage on EA#/VPP Pin to VSS . 0 V to +13.0 V Voltage on Any Other Pin to VSS . ­0.5 V to +6.5 V IOL per I/O Pin . 15 mA Power Dissipation . 1.5 W NOTE Maximum power dissipation is based on package heat-transfer limitations, not device power consumption. NOTICE: This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. OPERATING CONDITIONS TCSE1, Operating Temperature (SE1) . ­55°C to +125°C TCSE3, Operating Temperature (SE1) . ­40°C to +110°C VCC (Digital Supply Voltage) . 4.5 V to 5.5 V VSS . 0 V PRODUCT PREVIEW 13 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.1 D.C. Characteristics Parameter values apply to all devices unless otherwise indicated. Table 6. DC Characteristics at VCC = 4.5 ­ 5.5 V Symbol Parameter Max Units VIL Input Low Voltage (except EA#) -0.5 Min 0.2VCC ­ 0.1 V VIL1 Input Low Voltage (EA#) 0 0.2VCC ­ 0.3 V VIH Input High Voltage (except XTAL1, RST) 0.2VCC + 0.9 VCC + 0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7VCC VCC + 0.5 V VOL Output Low Voltage (Port 1, 2, 3) 0.3 0.45 1.0 V IOL = 100 µA IOL = 1.6 mA IOL = 3.5 mA (Note 1, Note 2) VOL1 Output Low Voltage (Port 0, ALE, PSEN#) 0.3 0.45 1.0 V IOL = 200 µA IOL = 3.2 mA IOL = 7.0 mA (Note 1, Note 2) VOH Output High Voltage (Port 1, 2, 3, ALE, PSEN#) V IOH = -10 µA IOH = -30 µA IOH = -60 µA (Note 3) VCC ­ 0.3 VCC ­ 0.7 VCC ­ 1.5 Typical Test Conditions NOTES: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: port 0 26 mA ports 1­3 15 mA Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. 3. 4. 14 Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed. PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 6. DC Characteristics at VCC = 4.5 ­ 5.5 V (Continued) Symbol Parameter Min Typical VOH1 Output High Voltage (Port 0 in External Address) VCC ­ 0.3 VCC ­ 0.7 VCC ­ 1.5 V IOH = -200 µA IOH = -3.2 mA IOH = -7.0 mA VOH2 Output High Voltage (Port 2 in External Address during Page Mode) VCC ­ 0.3 VCC ­ 0.7 VCC ­ 1.5 V IOH = -200 µA IOH = -3.2 mA IOH = -7.0 mA IIL Logical 0 Input Current (Port 1, 2, 3) -50 µA VIN = 0.45 V ILI Input Leakage Current (Port 0) +/-10 µA 0.45 < VIN < VCC ITL Logical 1-to-0 Transition Current (Port 1, 2, 3) -750 µA VIN = 2.0 V RRST RST Pulldown Resistor 225 k CIO Pin Capacitance 10 (Note 4) pF IPD Powerdown Current 10 (Note 4) µA IDL Idle Mode Current 10 (Note 4) 25 mA FOSC = 16 MHz ICC Operating Current 45 (Note 4) 85 mA FOSC = 16 MHz 40 Max Units Test Conditions FOSC = 16 MHz TA = 25 °C NOTES: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: port 0 26 mA ports 1­3 15 mA Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. 3. 4. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed. PRODUCT PREVIEW 15 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER VCC VCC IPD VCC P0 RST EA# M87C251SB M87C251SB (NC) XTAL2 XTAL1 VSS All other 8XC251SA/SB/SP/SQ 8XC251SA/SB/SP/SQ pins are unconnected. A5094-01 A5094-01 Figure 4. IPD Test Condition, Powerdown Mode, VCC = 2.0 ­ 5.5V 16 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 70 60 ) ICC (mA) 50 de o em x ma 40 (mA A) e (m iv Act typ od ve m i Act 30 20 10 e (mA) max Idle mod typ Idle mode (mA) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Frequency at XTAL (MHz) A4400-01 A4400-01 Figure 5. ICC vs. Frequency (Mhz) 4.2 Definition of AC Symbols Table 7. AC Timing Symbol Definitions Signals Conditions A Address D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD#/PSEN# Z Floating W WR# PRODUCT PREVIEW H High 17 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.3 A.C. Characteristics Test Conditions: Capacitive load on all pins = 50 pF. Table 8 lists AC timing parameters for the M87C251SB M87C251SB with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and/or by extending ALE. In the table, Notes 3 and 5 mark parameters affected by an ALE wait state, and Notes 4 and 5 mark parameters affected by a PSEN#/RD#/WR# wait state. Figures 7­9 show the bus cycles with the timing parameters. Table 8. AC Characteristics Symbol Parameter @ Max Fosc (1) Min Max Fosc Variable Min Max 16 FOSC XTAL1 Frequency N/A N/A 0 TOSC 1/FOSC N/A N/A 62.5 Units MHz ns M87C251SB-16 M87C251SB-16 TLHLL ALE Pulse Width M87C251SB-16 M87C251SB-16 52.5 (1+2M) TOSC ­ 10 ns (3) TAVLL Address Valid to ALE Low M87C251SB-16 M87C251SB-16 37.5 (1+2M) TOSC ­ 25 ns (3) TLLAX Address Hold after ALE Low M87C251SB-16 M87C251SB-16 15 15 ns TRLRH (2) RD# or PSEN# Pulse Width M87C251SB-16 M87C251SB-16 105 2(1+N) TOSC ­ 20 ns (4) TWLWH WR# Pulse Width M87C251SB-16 M87C251SB-16 105 2(1+N) TOSC ­ 20 ns (4) TLLRL (2) ALE Low to RD# or PSEN# Low M87C251SB-16 M87C251SB-16 37.5 TOSC ­ 25 ns TLHAX ALE High to Address Hold M87C251SB-16 M87C251SB-16 62.5 (1+2M)TOSC ns (3) TRLDV (2) RD#/PSEN# Low to valid Data/Instruction In M87C251SB-16 M87C251SB-16 TRHDX (2) Data/Instruction Hold Time. Occurs after RD#/PSEN# are exerted to VOH. TRLAZ (2) RD#/PSEN# Low to Address Float TRHDZ1 Instruction Float after RD#/PSEN# High M87C251SB-16 M87C251SB-16 2(1+N) Tosc ­ 60 65 0 ns 0 Typ.= 0 (5) 2 Typ=2 5 (5) 18 Typ. = 0 (5) 2 Typ.=25 (5) 18 ns NOTES: 1. 16 MHz. 2. Specifications for PSEN# are identical to those for RD#. 3. In the formula, M=Number of wait states (0 or 1) for ALE. 4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#. 5. "Typical" specifications are untested and not guaranteed. 18 ns (4) PRODUCT PREVIEW ns M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 8. AC Characteristics (Continued) Symbol Parameter @ Max Fosc (1) Min Max Fosc Variable Min Max Units TRHDZ2 Data Float after RD#/PSEN# High M87C251SB-16 M87C251SB-16 TRHLH1 RD#/PSEN# High to ALE High (Instruction) M87C251SB-16 M87C251SB-16 10 10 ns TRHLH2 RD#/PSEN# High to ALE High (Data) M87C251SB-16 M87C251SB-16 115 2Tosc ­ 10 ns TWHLH WR# High to ALE High M87C251SB-16 M87C251SB-16 130 2Tosc + 5 ns TAVDV1 Address (P0) Valid to Valid Data/Instruction In M87C251SB-16 M87C251SB-16 160 4(1+M/2) TOSC ­ 90 ns (3) TAVDV2 Address (P2) Valid to Valid Data/Instruction In M87C251SB-16 M87C251SB-16 185 4(1+M/2) TOSC ­ 65 ns (3) TAVDV3 Address (P0) Valid to Valid Instruction In M87C251SB-16 M87C251SB-16 75 2TOSC ­ 50 TAVRL (2) Address Valid to RD#/PSEN# Low M87C251SB-16 M87C251SB-16 80 2(1+M) TOSC ­ 45 ns (3) TAVWL1 Address (P0) Valid to WR# Low M87C251SB-16 M87C251SB-16 85 2(1+M) TOSC ­ 40 ns (3) TAVWL2 Address (P2) Valid to WR# Low M87C251SB-16 M87C251SB-16 105 2(1+M) TOSC ­ 20 ns (3) TWHQX Data Hold after WR# High M87C251SB-16 M87C251SB-16 42.5 TOSC ­ 20 TQVWH Data Valid to WR# High M87C251SB-16 M87C251SB-16 97 2(1+N) Tosc ­ 28 TWHAX WR# High to Address Hold M87C251SB-16 M87C251SB-16 115 2TOSC ­ 10 115 2Tosc ­ 10 ns ns ns ns (4) ns NOTES: 1. 16 MHz. 2. Specifications for PSEN# are identical to those for RD#. 3. In the formula, M=Number of wait states (0 or 1) for ALE. 4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#. 5. "Typical" specifications are untested and not guaranteed. PRODUCT PREVIEW 19 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.3.1 EXTERNAL BUS CYCLES, NONPAGE MODE TOSC XTAL1 ALE TLHLL TRLRH TRHLH1 TLLRL RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P0 TLLAX A7:0 TAVRL TRHDZ1 TRHDX D7:0 Instruction In TAVDV1 TAVDV2 P2/A16/A17 P2/A16/A17 A15:8/A16/A17 8/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4211-03 A4211-03 Figure 6. External Bus Cycle: Code Fetch (Nonpage Mode) 20 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL TRLRH TLLRL TRHLH2 RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P0 TAVRL TRHDZ2 TLLAX A7:0 TRHDX D7:0 Data In TAVDV1 TAVDV2 P2/A16/A17 P2/A16/A17 A15:8/A16/A17 8/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4210-03 A4210-03 Figure 7. External Bus Cycle: Data Read (Nonpage Mode) PRODUCT PREVIEW 21 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL TWLWH TWHLH WR# TLHAX TAVLL TLLAX P0 TQVWH TWHQX A7:0 D7:0 Data Out TAVWL1 TAVWL2 P2/A16/A17 P2/A16/A17 TWHAX A15:8/A16/A17 8/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4179-01 A4179-01 Figure 8. External Bus Cycle: Data Write (Nonpage Mode) 22 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.3.2 EXTERNAL BUS CYCLES, PAGE MODE TOSC XTAL1 ALE TLHLL TLLRL RD#/PSEN# TRLDV TRLAZ TRHDZ1 TLHAX TAVLL P2 TRHDX TLLAX A15:8 TAVRL D7:0 TAVDV1 TAVDV2 P0/A16/A17 P0/A16/A17 D7:0 Instruction In Instruction In A7:0/A16/A17 0/A16/A17 Page Miss TAVDV3 A7:0/A16/A17 0/A16/A17 Page Hit The value of this parameter depends on wait states. See the table of AC characteristics. A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2TOSC); a page miss requires two states (4TOSC). During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle. A4213-02 A4213-02 Figure 9. External Bus Cycle: Code Fetch (Page Mode) PRODUCT PREVIEW 23 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL TLLRL TRLRH TRHLH2 RD#/PSEN# TRLDV TRLAZ TLHAX TRHDZ2 TAVLL P2 TLLAX A15:8 TAVRL TRHDX D7:0 Data In TAVDV1 TAVDV2 P0/A16/A17 P0/A16/A17 A7:0/A16/A17 0/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4212-03 A4212-03 Figure 10. External Bus Cycle: Data Read (Page Mode) 24 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL TWLWH TWHLH WR# TLHAX TAVLL TLLAX P2 TQVWH TWHQX A15:8 D7:0 Data Out TAVWL1 TAVWL2 P0/A16/A17 P0/A16/A17 TWHAX A7:0/A16/A17 0/A16/A17 The value of this parameter depends on wait states. See the table of AC characteristics. A4182-01 A4182-01 Figure 11. External Bus Cycle: Data Write (Page Mode) PRODUCT PREVIEW 25 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.3.3 DEFINITION OF REAL-TIME WAIT SYMBOLS Table 9. Real-time Wait Timing Symbol Definitions Signals Conditions A L Low Data X Hold C WCLK V Setup Y WAIT# W WR# R 4.3.4 Address D RD#/PSEN# EXTERNAL BUS CYCLES, REAL-TIME WAIT STATES State 1 State 2 State 3 State 1 (next cycle) WCLK TCLYX min TCLYX max ALE TCLYV RD#/PSEN# RD#/PSEN# stretched TRLYX max TRLYX min TRLYV WAIT# P0 P2 A0-A7 D0-D7 stretched A8-A15 A8-A15 stretched A0-A7 A8-A15 A8-A15 A5000-01 A5000-01 Figure 12. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode) 26 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER State 1 State 2 State 3 State 4 WCLK TCLYX min TCLYX max ALE TCLYV WR# WR# stretched TWLYX max TWLYX min TWLYV WAIT# P0 D0-D7 A0-A7 P2 stretched A8-A15 A8-A15 stretched A5002-01 A5002-01 Figure 13. External Bus Cycle: Data Write (Nonpage Mode) State 1 State 2 State 3 State 1 (next cycle) WCLK TCLYX min TCLYX max ALE TCLYV RD#/PSEN# RD#/PSEN# stretched TRLYX max TRLYX min TRLYV WAIT# P2 A8-A15 A8-A15 P0 D0-D7 stretched A0-A7 A8-A15 A8-A15 stretched A0-A7 A5001-01 A5001-01 Figure 14. External Bus Cycle: Code Fetch/Data Read (Page Mode) PRODUCT PREVIEW 27 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER State 1 State 2 State 3 State 4 WCLK TCLYX min TCLYX max ALE TCLYV WR# WR# stretched TWLYX max TWLYX min TWLYV WAIT# P2 A8-A15 A8-A15 D0-D7 P0 stretched A0-A7 stretched A5003-01 A5003-01 Figure 15. External Bus Cycle: Data Write (Page Mode) Table 10. Real-time Wait AC Timing Symbol Min Max Units TCLYV Wait Clock Low to Wait Set-up 0 TOSC ­ 20 ns TCLYX Wait Hold after Wait Clock Low (2W)TOSC + 5 (1+2W)TOSC ­ 20 ns TRLYV PSEN#/RD# Low to Wait Set-up 0 TOSC ­ 20 ns TRLYX Wait Hold after PSEN#/RD# Low (2W)TOSC + 5 (1+2W)TOSC ­ 20 ns TWLYV WR# Low to Wait Set-up 0 TOSC ­ 20 ns TWLYX Wait Hold after WR# Low (2W)TOSC + 5 (1+2W)TOSC ­ 20 ns 28 Parameter PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.4 AC Characteristics - Serial Port, Shift Register Mode Table 11. Serial Port Timing - Shift Register Mode Symbol Parameter Min Max Units TXLXL Serial Port Clock Cycle Time 12TOSC 12TOSC ns TQVSH Output Data Setup to Clock Rising Edge 10TOSC 10TOSC ­ 133 ns 2TOSC ­ 117 ns 0 ns TXHQX Output Data hold after Clock Rising Edge TXHDX Input Data Hold after Clock Rising Edge TXHDV Clock Rising Edge to Input Data Valid 10TOSC 10TOSC ­ 133 ns TXLXL TXD TXHQX Set TI TQVXH RXD (Out) 0 1 2 Valid 7 6 5 TAV TXHDV RXD (In) 4 3 Set RI TXHDX Valid Valid Valid Valid Valid Valid Valid TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit. A2592-02 A2592-02 Figure 16. Serial Port Waveform - Shift Register Mode 4.5 External Clock Drive Table 12. External Clock Drive Symbol Parameter Min 1/TCLCL Oscillator Frequency (FOSC) TCHCX High Time Max Units 20 16 MHz 20 ns TCLCX Low Time TCLCH Rise Time 10 ns TCHCL Fall Time 10 ns PRODUCT PREVIEW ns 29 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER TCLCH VCC ­ 0.5 TCHCX 0.7 VCC TCLCX 0.45 V 0.2 VCC ­ 0.1 TCHCL TCLCL A4119-01 A4119-01 Figure 17. External Clock Drive Waveforms Outputs Inputs VCC ­ 0.5 0.2 VCC + 0.9 VIH MIN 0.45 V 0.2 VCC ­ 0.1 VOL MAX AC inputs during testing are driven at VCC ­ 0.5V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made at a min of VIH for a logic 1 and VOL for a logic 0. A4118-01 A4118-01 Figure 18. AC Testing Input, Output Waveforms VLOAD + 0.1 V VOH ­ 0.1 V Timing Reference Points VLOAD VOL + 0.1 V VLOAD ­ 0.1 V For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = ± 20 mA. A4117-01 A4117-01 Figure 19. Float Waveforms 30 PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.0 THERMAL CHARACTERISTICS All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. Table 13. Thermal Characteristics JA JC 44-pin LCC 30°C/W 10°C/W 40-pin Ceramic DIP 31°C/W 10°C/W Package Type 6.0 NONVOLATILE MEMORY PROGRAMMING AND VERIFICATION CHARACTERISTICS 6.1 Definition of Nonvolatile Memory Symbols Table 14. Nonvolatile Memory Timing Symbol Definitions Signals Conditions A Address D Data In L Low Q Data Out V Valid S Supply X No Longer Valid G PROG# Z Floating E Enable PRODUCT PREVIEW H High 31 M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.2 Programming and Verification Timing for Nonvolatile Memory Programming Cycle Verification Cycle Address (16 Bits) Address P1, P3 TAVQV P2 Data In (8 Bits) TDVGL Data Out TGHDX TAVGL TGHAX TGHGL PROG# TGLGH 1 2 3 4 5 TGHSL TSHGL EA#/VPP 12.75V 5V TELQV TEHQZ TEHSH P0 Mode (8 Bits) Mode A4128-01 A4128-01 Figure 20. Timing for Programming and Verification of Nonvolatile Memory Table 15. Nonvolatile Memory Programming and Verification Characteristics at TA = 21 ­ 27 °C, VCC = 5 V, and VSS = 0 V Symbol Definition Min Max Units 12.5 13.5 D.C. Volts 75 mA 4.0 6.0 MHz VPP Programming Supply Voltage IPP Programming Supply Current FOSC Oscillator Frequency TAVGL Address Setup to PROG# Low 48TOSC 48TOSC TGHAX Address Hold after PROG# 48TOSC 48TOSC TDVGL Data Setup to PROG# Low 48TOSC 48TOSC TGHDX Data Hold after PROG# 48TOSC 48TOSC TEHSH ENABLE High to VPP 48TOSC 48TOSC TSHGL VPP Setup to PROG# Low TGHSL VPP Hold after PROG# 10 TGLGH PROG# Width 90 32 µs 10 µs 110 µs PRODUCT PREVIEW M87C251SB M87C251SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 15. Nonvolatile Memory Programming and Verification Characteristics at TA = 21 ­ 27 °C, VCC = 5 V, and VSS = 0 V (Continued) Symbol Definition Min TAVQV Address to Data Valid TELQV ENABLE Low to Data Valid TEHQZ Data Float after ENABLE 0 TGHGL PROG# High to PROG# Low 10 7.0 Max Units 48TOSC 48TOSC 48TOSC 48TOSC 48TOSC 48TOSC µs ERRATA The M87C251SB M87C251SB may contain design defects or errors known as errata. Characterized errata that may cause the M87C251SB M87C251SB's behavior to deviate from published specifications are documented in a specification update. Specification updates can be obtained from your local Intel sales office or from the World Wide Web (www.intel.com). 8.0 REVISION HISTORY Table 16. Revision History Rev. Description 001 002 33 Original version. The following changes were made in the -002 datasheet. 1. Real-time wait state operation was added. 2. Reserved memory locations were defined and the memory map renamed to "Address Map." 3. An "ICC vs. Frequency" graph was added. 4. Signature byte information has been deleted. See the 8XC251SA/SB/SP/SQ 8XC251SA/SB/SP/SQ Embedded Microcontroller User's Manual. 5. The PLCC offering has been eliminated. 6. The IPD maximum specification has been deleted. PRODUCT PREVIEW