M7700-62-9912 M7700-36-9803 16-BIT P7-12 P8-39 P17-22 P8-43 FFFE16 P8-45 P11-21 - Datasheet Archive

 

MESC TECHNICAL NEWS A No. M7700-62-9912 Corrections and Supplementary Explanation for "7721 Group User's Manual" (REV.

 

GRADE MESC TECHNICAL NEWS A No. M7700-62-9912 M7700-62-9912 Corrections and Supplementary Explanation for "7721 Group User's Manual" (REV. B) This news includes a few corrections and supplementary explanation for "7721 Group User's Manual". And also, this news includes the information previously announced by the MESC TECHNICAL NEWS (No. M7700-36-9803 M7700-36-9803, Corrections and Supplementary Explanation for "7721 Group User's Manual" REV. A). 5 represents the new information. The information about the product expansion, electrical characteristics, and development support tools will not be announced by the MESC TECHNICAL NEWS, even if the above information is updated. So, for the product expansion, electrical characteristics, and development support tools, please refer to the latest version of the following documents in our web site: · Product Expansion Mitsubishi Microcomputers General Catalogg · Electrical Characteristics Datasheets · Development Support Tools Datasheets Microcomputers Development Support Tools Catalogg Microcomputers Development Support Tools Accessory Guide Please Visit Our Web Site. · Mitsubishi MCU Technical Information (http://www.infomicom.mesc.co.jp/indexe.htm) · Mitsubishi Microcomputer Development Support Tools (http://www.tool-spt.mesc.co.jp/index_e.htm) g The printed version is also released. Note: For products not included in the above web site, refer to "1996 MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE-CHIP 16-BIT 16-BIT MICROCOMPUTERS Vol. 1 to 2." (1/ 1) M7700-62-9912 M7700-62-9912 1, Dec., 1999 Corrections and Supplementary Explanation for "7721 Group User's Manual" (REV. B) No. 1 Page Correction Error P2-7 (2) Bit 1: Zero Flag Note: This flag is invalid in the decimal mode addition (the ADC instruction). Note: This flag is invalid in the decimal mode addition (the ADC instruction) and subtraction (the SBC instruction). 5 P5-6 Last 3 lines in order of priority ··· MSB becomes "0." For interrupts not to be accepted, ··· in order of priority ··· MSB becomes "0." (When the level sense of an INTi interrupt is used, an interrupt request is not retained. Therefore, if the level at the INTi pin is invalid when the watchdog timer's MSB becomes "0," the interrupt request is not accepted.) For interrupts not to be accepted, ··· 5 P7-12 P7-12 Fig. 7.6.1 (1) Interrupt priotiry detection time select bits b7 b6 b5 b4 b3 b2 b1 b0 Processor mode 0 register 0 (Address 5E16) Processor mode bits (1) Interrupt priotiry detection time select bits b7 b6 b5 b4 b3 b2 b1 b0 Processor mode 0 0 register 0 (Address 5E16) Must be fixed to "0." Clock 1 output select bit 5 P8-39 P8-39 Fig. 8.6.1, Functions Bit P17-22 P17-22 TAjOUT pin is expressed as follows: 5 P8-43 P8-43 Last 2 lines 5 n16 ­ 1 fi Functions Bit 15 to 0 These bits can be set to "000016" to "FFFE16 FFFE16." Assuming that the set value = n, the " H" level width of the PWM pulse output from the (PWM pulse period = Stack bank select bit n fi ) 15 to 0 These bits can be set to "000016" to "FFFE16 FFFE16." Assuming that the set value = n, the " H" level width of the PWM pulse output from the TAjOUT pin is expressed as follows: (PWM pulse period = the TAjOUT pin outputs "L" level which has the same width as "H" level width of the PWM pulse, which was set. ··· ) the TAjOUT pin outputs "L" level for a period of (1/fi) ! (m+1) ! (n+1). ··· P8-45 P8-45 Fig. 8.6.6 Count source Count source TAjIN pin's input signal TAjIN pin's input signal 8-bit prescaller's underflow signal 8-bit prescaller's underflow signal PWM pulse output from TAjOUT pin PWM pulse output from TAjOUT pin Timer Aj interrupt request bit Timer Aj interrupt request bit (1/3) 216 ­ 1 fi n fi M7700-62-9912 M7700-62-9912 1, Dec., 1999 Corrections and Supplementary Explanation for "7721 Group User's Manual" (REV. B) No. 2 Page Error Correction ··· after 1 cycle of the transfer clock has passed. ··· 5 P11-21 P11-21 Line 4, P11-27 P11-27 Lines 3 and 4, P11-38 P11-38 Lines 3 and 4 P13-20 P13-20 Table 13.3.3 Burst transfer mode Level Sense · "H"-level input to the DMAREQi pin · Change of the TC pin's input level from "H" to "L" (when the TC pin is valid) ·A write of "0" to the DMAi request bit · A write of "0" to the DMAi enable bit Cycle-steal transfer mode · Start of 1-unit transfer · Change of the TC pin's input level from "H" to "L" during DMA transfer (when the TC pin is valid) · A write of "0" to the DMAi request bit · A write of "0" to the DMAi enable bit ··· after a maximum of 1 cycle of the transfer clock has passed. ··· Burst transfer mode Level Sense · "H"-level input to the DMAREQi pin (Delete) Cycle-steal transfer mode · Start of 1-unit transfer · Change of the TC pin's input level from "H" to "L" during DMA transfer (when the TC pin is valid) · A write of "0" to the DMAi request bit (Delete) Note: (Delete) Note: While the DMAi enable bit is "0,". Supplement: Regardless of the DMAi enable bit's contents, DMAi request bit is set to "1" when a DMA request is generated P13-27 P13-27 Table 13.3.5 DMAi request bit DMAi request bit When edge sense is selected in the burst 0 transfer mode: o When level sense is selected in the burst transfer mode: not changed In the cycle-steal transfer mode: 0 5 P13-28 P13-28 13.3.6 (1) (1) Restarting the same DMA ··· beginning At normal and forced termination, the latches of SARi, DARi, and TCRi maintain their values written before the transfer start. (Refer to "Figure 13.3.4-a.") ··· the following procedures: q In single or repeat transfer mode Set the DMAi enable bit to "1." ··· (Refer to "Figure 13.3.4-b.") q In array chain ··· mode Re-set the values ··· Set the DMAi ··· P13-48 P13-48 Line 23 P13-51 P13-51 Fig. 13.4.11 ··· pin's input level = "L," the DMAi request bit is cleared to "0"; when this pin's input level = "L," the DMAi request bit is set to "1." (1) Restarting the same DMA ··· beginning q In single or repeat transfer mode At normal and forced termination, the latches of SARi, DARi, and TCRi maintain their values written before the transfer start. (Refer to "Figure 13.3.4-a.") ··· the following procedures: Set the DMAi enable bit to "1." ··· (Refer to "Figure 13.3.4-b.") q In array chain ··· mode As values other than the initial values of SARi and TCRi have been set in their latches (refer to "Table 13.2.5"), it is necessary to re-set them. Re-set the values ··· Set the DMAi ··· ··· pin's input level = "L," the DMAi request bit is set to "1"; when this pin's input level = "H," the DMAi request bit is cleared to "0." DMAi enable bit DMAi enable bit (2/3) M7700-62-9912 M7700-62-9912 1, Dec., 1999 Corrections and Supplementary Explanation for "7721 Group User's Manual" (REV. B) No. 3 Error Page P13-57 P13-57 Fig. 13.5.3, P13-64 P13-64 Fig. 13.6.3, P13-73 P13-73 Fig. 13.7.4, P13-85 P13-85 Fig. 13.8.4 b7 b0 Correction DMA0 control register (Address 1FCE16 1FCE16) DMA1 control register (Address 1FDE16 1FDE16) DMA2 control register (Address 1FEE16 1FEE16) DMA3 control register (Address 1FFE16 1FFE16) b7 DMA request source select bits 1000: Tim er B0 0000: Do not select. 0001: External source (DMAREQi) 1001: Tim er B1 1010: Tim er B2 0010: Software DMA source 1011: UART0 receive 0011: Timer A0 1100: UART0 transm it 0100: Timer A1 1101: UART1 receive 1110: UART1 transm it 0101: Timer A2 1111: A-D conversion 0110: Timer A3 0111: Timer A4 DMA request source select bits 1000: Tim er B0 0000: Do not select. 1001: Tim er B1 0001: External source (DMAREQi) 1010: Tim er B2 1011: UART0 receive 0010: Software DMA source 1100: UART0 transm it 0011: Timer A0 1101: UART1 receive 0100: Timer A1 1110: UART1 transm it 0101: Timer A2 1111: A-D conversion 0110: Timer A3 0111: Timer A4 Edge sense/level sense select bit (Note) 0: Edge sense 1: Level sense Edge sense/level sense select bit (Note) 0: Edge sense 1: Level sense DM AACKi validity bit 0: Invalid 1: Valid DM AACKi validity bit 0: Invalid 1: Valid Note: When a source other than the external source (DMAREQi) is selected or when the cyclesteal transfer mode is selected, set this bit to "0" Note: When an external source (DMAREQi) is selected or when the cycle-steal transfer mode is selected, set this bit to "0" (Continue to the corresponding figure on the next page.) P13-94 P13-94 Fig.13.8.12, P13-95 P13-95 Fig.13.8.13, P13-96 P13-96 Fig.13.8.14 5 P14-8 P14-8 14.4.1 (3) Line 4 5 P14-9 P14-9 Fig. 14.4.1 (C) At refresh (Continue to the corresponding figure on the next page.) E E R/W R/W R/W is undefined. R/W, BHE, and BLE are undefined. (c) At refresh (c) At refresh · · · · R/W, BHE, BLE Undefined R/W P16-6 P16-6 Fig.16.1.3 DMA0 control register (Address 1FCE16 1FCE16) DMA1 control register (Address 1FDE16 1FDE16) DMA2 control register (Address 1FEE16 1FEE16) DMA3 control register (Address 1FFE16 1FFE16) b0 CAS Undefined CAS t CLZ DRAM data output 5 P17-64 P17-64 5. Setup for I/O ports t CLZ t CAC t CAC Data q Read the data of ··· are equal. q Since the output data may reverse because of noise, rewrite data ··· periodically. q Rewrite data ··· periodically. DRAM data output Data q Read the data of ··· are equal. q Since the output data may reverse because of noise, rewrite (Note) data ··· periodically. q Rewrite (Note) data ··· periodically. Note: Be sure to use the LDM or STA instruction for the above rewriting. (3/3)