M48Z08 M48Z08Y M48Z18 M48Z18/Z08Y PCDIP28 SOH28 M48Z08/18/08Y DS1225 - Datasheet Archive

 

M48Z08Y, M48Z18 5V, 64 Kbit (8Kb x 8) ZEROPOWER® SRAM FEATURES SUMMARY s INTEGRATED, ULTRA LOW POWER SRAM and POWER-FAIL

 

M48Z08 M48Z08 M48Z08Y M48Z08Y, M48Z18 M48Z18 5V, 64 Kbit (8Kb x 8) ZEROPOWER® SRAM FEATURES SUMMARY s INTEGRATED, ULTRA LOW POWER SRAM and POWER-FAIL CONTROL CIRCUIT s UNLIMITED WRITE CYCLES s READ CYCLE TIME EQUALS WRITE CYCLE TIME s AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION Figure 1. 28-pin CAPHAT, DIP Package s s WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): ­ M48Z08 M48Z08: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V ­ M48Z18/Z08Y M48Z18/Z08Y: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V SELF-CONTAINED BATTERY IN THE CAPHATTM DIP PACKAGE s PACKAGING INCLUDES A 28 LEAD SOIC and SNAPHAT® TOP (to be Ordered Separately) s 1 PCDIP28 PCDIP28 (PC) Battery/Crystal CAPHAT Figure 2. 28-pin SOIC Package SNAPHAT (SH) Battery SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY s 28 PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 8K x 8 SRAMs 28 1 SOH28 SOH28 (MH) May 2002 1/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 3.) . . . . . . . Signal Names (Table 1.) . . . . . . . . DIP Connections (Figure 4.) . . . . . SOIC Connections (Figure 5.) . . . . Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 .3 .4 .4 .4 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Testing Load Circuit (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Enable Controlled, WRITE Mode AC Waveform (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable Controlled, WRITE Mode AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Down/Up Trip Points DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Crystal Accuracy Across Temperature (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SNAPHAT Battery Table (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y SUMMARY DESCRIPTION The M48Z08/18/08Y M48Z08/18/08Y ZEROPOWER ® RAM is a 8K x 8 non-volatile static RAM which is pin and functional compatible with the DS1225 DS1225. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z08/18/08Y M48Z08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28-pin, 600mil DIP CAPHATTM houses the M48Z08/18/08Y M48Z08/18/08Y silicon with a long life lithium button cell in a single package. Figure 3. Logic Diagram The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is "M4Z28-BR00SH M4Z28-BR00SH" or M4Z32-BR00SH M4Z32-BR00SH (see Table 12, page 14). Table 1. Signal Names VCC W E Chip Enable G Output Enable W WRITE Enable VCC Supply Voltage VSS Ground NC A0-A12 A0-A12 Data Inputs / Outputs E 8 Address Inputs DQ0-DQ7 13 A0-A12 A0-A12 Not Connected Internally DQ0-DQ7 M48Z08 M48Z08 M48Z18 M48Z18 M48Z08Y M48Z08Y G VSS AI01022 AI01022 3/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Figure 4. DIP Connections NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 5. SOIC Connections 28 1 27 2 26 3 25 4 24 5 23 6 7 M48Z08 M48Z08 22 M48Z18 M48Z18 21 8 20 9 19 10 18 11 17 12 13 16 14 15 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 1 28 27 2 26 3 25 4 24 5 23 6 7 M48Z08Y M48Z08Y 22 21 8 20 9 19 10 18 11 17 12 16 13 15 14 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS AI01183 AI01183 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI01023B AI01023B Figure 6. Block Diagram A0-A12 A0-A12 LITHIUM CELL POWER VOLTAGE SENSE AND SWITCHING CIRCUITRY 8K x 8 SRAM ARRAY DQ0-DQ7 E VPFD W G VCC 4/20 VSS AI01394 AI01394 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol TA TSTG TSLD(1,2) Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Value Unit 0 to 70 °C ­40 to 85 °C 260 °C VIO Input or Output Voltages ­0.3 to 7 V VCC Supply Voltage ­0.3 to 7 V IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). 2. For SO package: Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120 seconds). CAUTION: Negative undershoots below ­0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 5/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M48Z08 M48Z08 M48Z18/Z08Y M48Z18/Z08Y Unit 4.75 to 5.5 4.5 to 5.5 V 0 to 70 0 to 70 °C Load Capacitance (CL) 100 100 pF Input Rise and Fall Times 5 5 ns 0 to 3 0 to 3 V 1.5 1.5 V Supply Voltage (VCC) Ambient Operating Temperature (TA) Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 7. AC Testing Load Circuit 5V 1.8k DEVICE UNDER TEST OUT 1k CL = 100pF or 30pF CL includes JIG capacitance AI01398 AI01398 Table 4. Capacitance Parameter(1,2) Symbol CIN CIO(3) Min Max Unit Input Capacitance 10 pF Input / Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs deselected. 6/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Table 5. DC Characteristics Symbol ILI ILO(2) Test Condition(1) Parameter Unit ±1 µA 0V VOUT VCC ±1 µA Outputs open 80 mA E = VIH 3 mA E = VCC ­ 0.2V Output Leakage Current Max 0V VIN VCC Input Leakage Current Min 3 mA ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS VIL(3) Input Low Voltage ­0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = ­1mA 2.4 V Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected. 3. Negative spikes of ­1V allowed for up to 10ns once per Cycle. OPERATION MODES The M48Z08/18/08Y M48Z08/18/08Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns. Table 6. Operating Modes Mode VCC WRITE READ READ W DQ0-DQ7 Power X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL 4.75 to 5.5V or 4.5 to 5.5V G VIH Deselect E VIH VIH High Z Active Deselect VSO to VPFD(min)(1) X X X High Z CMOS Standby Deselect VSO(1) X X X High Z Battery Back-up Mode Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10, page 12 for details. 7/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y READ Mode The M48Z08/18/08Y M48Z08/18/08Y is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripplethrough access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next address access. Figure 8. READ Mode AC Waveforms tAVAV VALID A0-A12 A0-A12 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI01385 AI01385 Note: WRITE Enable (W) = High. Table 7. READ Mode AC Characteristics Symbol Parameter(1) M48Z08/M48Z18/Z08Y M48Z08/M48Z18/Z08Y Unit Min Max tAVAV READ Cycle Time 100 ns tAVQV Address Valid to Output Valid 100 ns tELQV Chip Enable Low to Output Valid 100 ns tGLQV Output Enable Low to Output Valid 50 ns tELQX(2) Chip Enable Low to Output Transition 10 ns tGLQX(2) Output Enable Low to Output Transition 5 ns tEHQZ(2) Chip Enable High to Output Hi-Z 50 ns tGHQZ(2) Output Enable High to Output Hi-Z 40 ns tAXQX Address Transition to Output Transition 5 Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 30pF. 8/20 ns M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y WRITE Mode The M48Z08/18/08Y M48Z08/18/08Y is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 9. WRITE Enable Controlled, WRITE Mode AC Waveform tAVAV VALID A0-A12 A0-A12 tAVWH tWHAX tAVEL E tWLWH tAVWL W tWHQX tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI01386 AI01386 Figure 10. Chip Enable Controlled, WRITE Mode AC Waveforms tAVAV A0-A12 A0-A12 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI01387B AI01387B 9/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Table 8. WRITE Mode AC Characteristics Symbol Parameter(1) tAVAV WRITE Cycle Time tAVWL M48Z08/M48Z18/Z08Y M48Z08/M48Z18/Z08Y Unit Min Max 100 ns Address Valid to WRITE Enable Low 0 ns tAVEL Address Valid to Chip Enable 1 Low 0 ns tWLWH WRITE Enable Pulse Width 80 ns tELEH Chip Enable Low to Chip Enable 1 High 80 ns tWHAX WRITE Enable High to Address Transition 10 ns tEHAX Chip Enable High to Address Transition 10 ns tDVWH Input Valid to WRITE Enable High 50 ns tDVEH Input Valid to Chip Enable 1 High 30 ns tWHDX WRITE Enable High to Input Transition 5 ns tEHDX Chip Enable High to Input Transition 5 ns tWLQZ(2,3) WRITE Enable Low to Output Hi-Z 50 ns tAVWH Address Valid to WRITE Enable High 80 ns tAVEH Address Valid to Chip Enable High 80 ns WRITE Enable High to Output Transition 10 ns tWHQX(2,3) Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 30pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 10/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Data Retention Mode With valid VCC applied, the M48Z08/18/08Y M48Z08/18/08Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care." Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z08/18/08Y M48Z08/18/08Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z08/18/08Y M48Z08/18/08Y for an accumulated period of at least 11 years when VCC is less than VSO. Note: Requires use of M4Z32-BR00SH M4Z32-BR00SH SNAPHAT® top when using the SOH28 SOH28 package. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus tREC (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent write cycles prior to system stabilization. Normal RAM operation can resume tREC after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012 AN1012. Figure 11. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tF tPD INPUTS tDR tR tFB RECOGNIZED tRB DON'T CARE tREC NOTE RECOGNIZED HIGH-Z OUTPUTS VALID (PER CONTROL INPUT) VALID (PER CONTROL INPUT) AI00606 AI00606 Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running. 11/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Table 9. Power Down/Up AC Characteristics Symbol Parameter(1) tPD E or W at VIH before Power Down tF(2) tFB(3) Min Max Unit 0 µs VPFD (max) to VPFD (min) VCC Fall Time 300 µs VPFD (min) to VSS VCC Fall Time 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 0 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs E or W at VIH before Power Up 2 ms tREC Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 10. Power Down/Up Trip Points DC Characteristics Parameter(1,2) Typ Max Unit 4.5 4.6 4.75 V M48Z18/Z08Y M48Z18/Z08Y VPFD Min M48Z08 M48Z08 Symbol 4.2 4.3 4.5 V Power-fail Deselect Voltage VSO Battery Back-up Switchover Voltage tDR Expected Data Retention Time 3.0 11(3) Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 3. Requires use of M4Z32-BR00SH M4Z32-BR00SH SNAPHAT® top when using the SOH28 SOH28 package. 12/20 V YEARS M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Figure 12. Crystal Accuracy Across Temperature ppm 20 0 -20 -40 F = -0.038 ppm (T - T )2 ± 10% 0 F C2 -60 T0 = 25 °C -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 °C 70 AI02124 AI02124 VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure 13) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 1N5817 is recommended for through hole and MBRS120T3 MBRS120T3 is recommended for surface mount. Figure 13. Supply Voltage Protection VCC VCC 0.1µF DEVICE VSS AI02169 AI02169 13/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y PART NUMBERING Table 11. Ordering Information Scheme Example: M48Z 08 ­100 MH 1 TR Device Type M48Z Supply Voltage and Write Protect Voltage 08(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 18/08Y 18/08Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Speed ­100 = 100ns ­10 = 100ns (M48Z08Y M48Z08Y) Package PC = PCDIP28 PCDIP28 MH(2) = SOH28 SOH28 Temperature Range 1 = 0 to 70°C Shipping Method blank = Tubes TR = Tape & Reel Note: 1. The M48Z08/18 M48Z08/18 part is offered with the PCDIP28 PCDIP28 (e.g., CAPHATTM) package only. 2. The SOIC package (SOH28 SOH28) requires the battery/crystal package (SNAPHAT®) which is ordered separately under the part number "M4ZXX-BRxxSH" in plastic tube or "M4ZXX-BRxxSHTR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery/crystal package "M4ZXX-BRxxSH" in conductive foam as it will drain the lithium buttoncell battery. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest you. Table 12. SNAPHAT Battery Table Part Number Description Package M4Z28-BR00SH M4Z28-BR00SH SH M4Z32-BR00SH M4Z32-BR00SH 14/20 Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT SH M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y PACKAGE MECHANICAL INFORMATION Figure 14. PCDIP28 PCDIP28 ­ 28-pin Plastic DIP, battery CAPHAT, Package Outline A2 A1 B1 B A L C e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 13. PCDIP28 PCDIP28 ­ 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data mm inches Symb Typ Min Max A 8.89 A1 Typ Min Max 9.65 0.350 0.380 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 28 28 15/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Figure 15. SOH28 SOH28 ­ 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline A2 A C B eB e CP D N E H A1 L 1 SOH-A Note: Drawing is not to scale. Table 14. SOH28 SOH28 ­ 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 ­ ­ ­ ­ eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 0° 8° 0° 8° N 28 e CP 16/20 1.27 0.050 28 0.10 0.004 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Figure 16. SH ­ 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline A1 eA A2 A A3 B L eB D E SH Note: Drawing is not to scale. Table 15. SH ­ 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 17/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Figure 17. SH ­ 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline A1 eA A2 A A3 B L eB D E SH Note: Drawing is not to scale. Table 16. SH ­ 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 18/20 0.46 2.03 2.29 0.080 0.090 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y REVISION HISTORY Table 17. Document Revision History Date March 1999 Revision Details First issue 07/19/01 2-socket SOH and 2-pin SH packages removed; reformatted; temperature information added to tables (Table 4, 5, 7, 8, 9, 10) 12/19/01 Remove all references to "clock" 12/21/01 Changes to text to reflect addition of M48Z08Y M48Z08Y option 05/20/02 Modify reflow time and temperature footnotes (Table 2) 19/20 M48Z08 M48Z08, M48Z18 M48Z18, M48Z08Y M48Z08Y Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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