M470L3224BT0 256MB DDR266A DDR266B DDR200 DDR200/266 M470L3224BT0-C A10/AP - Datasheet Archive

 

200pin DDR SDRAM SODIMM 256MB DDR SDRAM MODULE (32Mx64 based on 16Mx16 DDR SDRAM) 200pin SODIMM 64-bit Non-ECC/Parity Revision

 

M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM 256MB 256MB DDR SDRAM MODULE (32Mx64 based on 16Mx16 DDR SDRAM) 200pin SODIMM 64-bit Non-ECC/Parity Revision 0.3 Dec. 2001 Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM Revision History Revision 0.0 (Apr. 2001) 1. First release. Revision 0.1 (June. 2001) 1. Changed module current speificaton 2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm). 3. Changed AC parameter table. Revision 0.2 (Aug. 2001) 1. Corrected the Functional Block Diagram Before -> CKE0 : SDRAMs D0 ~D7 After -> CKE0 : SDRAMs D0 ~D3 CKE1 : SDRAMs D4 ~D7 Revision 0.3 (Dec. 2001) - Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 47. - Revised "Absolute maximum rating" table in page 38. . Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V . Changed "power dissipation" value from 1.0W to 1.5W. - Revised AC parameter table From DDR266A DDR266A To DDR266B DDR266B DDR200 DDR200 DDR266A DDR266A DDR266B DDR266B DDR200 DDR200 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tHZ tACmin -400ps tACmax -400ps tACmin -400ps tACmax -400ps tACmin -400ps tACmax -400ps -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 tLZ tACmin -400ps tACmax -400ps tACmin -400ps tACmax -400ps tACmin -400ps tACmax -400ps -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 tWPST (tCK) 0.25 0.25 0.25 0.4 0.6 0.4 0.6 0.4 0.6 tPDEX 10ns 10ns 10ns 7.5ns 7.5ns 10ns - Deleted typical current in IDD spec. table - Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 DDR200/266 AC specification - Deleted Exit self refresh to write command(tXSW) in DDR200/266 DDR200/266 AC specification - Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266 DDR200/266 - Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266 DDR200/266 - Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266 DDR200/266 - Rename tREF(Refresh interval time) to tREFI at DDR200/266 DDR200/266 - Changed tWR value from 2tCK to 15ns. -Rename tCDLR(Write data out to Read command) t0 tWTR - Added tDAL(tWR+tRP) Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM 32Mx64 200pin DDR SDRAM SODIMM based on 16Mx16 GENERAL DESCRIPTION FEATURE The Samsung M470L3224BT0 M470L3224BT0 is 32M bit x 64 Double Data · Performance range Part No. Rate SDRAM high density memory modules based on first gen Max Freq. Interface of 256Mb DDR SDRAM respectively. M470L3224BT0-C M470L3224BT0-C(L)A2 133MHz(7.5ns@CL=2) The Samsung M470L3224BT0 M470L3224BT0 consists of eight CMOS 16M x M470L3224BT0-C M470L3224BT0-C(L)B0 133MHz(7.5ns@CL=2.5) 16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP- M470L3224BT0-C M470L3224BT0-C(L)A0 100MHz(10ns@CL=2) II(400mil) packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M470L3224BT0 M470L3224BT0 is Dual In-line Memory Modules and intended for mounting into 200pin edge connector sockets. Synchronous design allows precise cycle control with the use SSTL_2 · Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V · Double-data-rate architecture; two data transfers per clock cycle · Bidirectional data strobe(DQS) · Differential clock inputs(CK and CK ) · DLL aligns DQ and DQS transition with CK transition of system clock. Data I/O transactions are possible on both · Programmable Read latency 2, 2.5 (clock) · Programmable Burst length (2, 4, 8) edges of DQS. Range of operating frequencies, programmable · Programmable Burst type (sequential & interleave) latencies and burst lengths allow the same device to be useful · Edge aligned data output, center aligned data input · Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) for a variety of high bandwidth, high performance memory sys- · Serial presence detect with EEPROM · PCB :Height 1250 (mil), double sided component tem applications. PIN DESCRIPTION PIN CONFIGURATIONS (Front side/back side) Pin Front 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS Key DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 41 43 45 47 49 51 53 55 57 59 61 63 65 Pin Front Pin Front 67 DQ27 135 DQ34 69 VDD 137 VSS 71 CB0 139 DQ35 73 CB1 141 DQ40 75 VSS 143 VDD 77 DQS8 145 DQ41 79 CB2 147 DQS5 81 VDD 149 VSS 83 CB3 151 DQ42 85 DU 153 DQ43 87 VSS 155 VDD 89 CK2 157 VDD 91 /CK2 159 VSS 93 VDD 161 VSS 95 CKE1 163 DQ48 97 DU(A13) 165 DQ49 99 A12 167 VDD 101 A9 169 DQS6 103 VSS 171 DQ50 105 A7 173 VSS 107 A5 175 DQ51 109 A3 177 DQ56 111 A1 179 VDD 113 VDD 181 DQ57 115 A10/AP A10/AP 183 DQS7 117 BA0 185 VSS 119 /WE 187 DQ58 121 /S0 189 DQ59 123 DU 191 VDD 125 VSS 193 SDA 127 DQ32 195 SCL 129 DQ33 197 VDDSPD 131 VDD 199 VDDID 133 DQS4 Pin Back Pin Back Pin Back 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS Key DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/(RESET) VSS VSS VDD VDD CKE0 DU(BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /S1 DU VSS DQ36 DQ37 VDD DM4 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU Pin Name Function BA0 ~ BA1 Bank Select Address DQ0 ~ DQ63 Data input/output DQS0 ~ DQS7 Data Strobe input/output CK0~ CK2, CK0 ~ CK2 Clock input CKE0 Clock enable input CS0 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DM0 ~ DM7 Data - in mask VDD Power supply (2.5V) VDDQ Power Supply for DQS(2.5V) VSS Ground VREF Power supply for reference VDDSPD Serial EEPROM Power Supply ( 2.3V to 3.6V) SDA Serial data I/O SCL Serial clock SA0 ~ 2 Address in EEPROM VDDID * Address input (Multiplexed) VDD identification flag NC 42 44 46 48 50 52 54 56 58 60 62 64 66 A0 ~ A12 No connection These pins are not used in this module. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM FUNCTIONAL BLOCK DIAGRAM S1 S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS1 DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 DQS2 DM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 BA0 - BA1 S D0 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS4 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 S D1 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S D5 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS7 DM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 DQS6 DM6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D4 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 DQS5 DM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 S UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 RAS: SDRAMs D0 - D7 CAS CAS: SDRAMs D0 - D7 CKE0 CKE: SDRAMs D0 - D3 CKE1 WE: SDRAMs D0 - D7 VS S V DDID LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S D3 Clock Wiring Clock Input CK0/CK0 CK1/CK1 CK2/CK2 SPD SDRAMs 4 SDRAMs 4 SDRAMs NC Card Edge *Clock Net Wiring SCL WP D0 - D7 D0 - D7 Strap: see Note 4 S D7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 CK CK Serial PD D0 - D7 D0 - D7 VREF D6 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 R=120 ± 5% CKE: SDRAMs D4 - D7 WE S Dram1 A0-A13 A0-A13: DDR SDRAMs D0 - D7 RAS VD D S PD D2 BA0-BA1: DDR SDRAMs D0 - D7 A0 - A13 V DD /VDDQ LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S SDA A0 A1 A2 SA0 SA1 SA2 Dram2 Dram3 Dram4 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM Absolute Maximum Rate Parameter Symbol Value Unit Voltage on any pin relative to V SS V IN, V OUT -0.5 ~ 3.6 V Voltage on V DD & V DDQ supply relative to V SS V DD , VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 12 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS =0V, T A=0 to 70°C) Parameter Symbol Min Max Supply voltage(for device with a nominal V DD of 2.5V) V DD 2.3 2.7 I/O Supply voltage V DDQ 2.3 2.7 V I/O Reference voltage V REF VDDQ/2-50mV VDDQ/2+50mV V 1 V TT V REF-0.04 V REF+0.04 V 2 Input logic high voltage V I H(DC) V REF+0.15 V DDQ +0.3 V 4 Input logic low voltage V IL (DC) -0.3 V REF-0.15 V 4 Input Voltage Level, CK and CK inputs V I N(DC) -0.3 V DDQ +0.3 V Input Differential Voltage, CK and CK inputs V I D(DC) 0.3 V DDQ +0.6 V 3 Input crossing point voltage, CK and CK inputs V IX (DC) 1.15 1.35 V 5 II -2 2 uA Output leakage current IO Z -5 5 uA Output High Current(Normal strengh driver) ;V OUT = VT T + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;V OUT = VT T - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;V OUT = V T T + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;V OUT = VT T - 0.45V IOL 9 mA I/O Termination voltage(system) Input leakage current Unit Note Notes 1. Includes ± 25mV margin for DC offset on V REF, and a combined total of ± 50mV margin for all AC noise and DC offset on V REF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF and internal DRAM noise coupled TO V REF, both of which may result in V REF noise. V REF should be de-coupled with an inductance of 3nH. 2.V TT is not applied directly to the device. V T T is a system supply for signal termination resistors, is expected to be set equal to V REF, and must track variations in the DC level of V REF 3. V I D is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 200MHZ. 5. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM DDR SDRAM SPEC Items and Test Conditions Conditions Symbol Operating current - One bank Active-Precharge; tRC=tRCmin; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle IDD0 Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition IDD1 Percharge power-down standby current; All banks idle; power - down mode; CKE = =VIH(min);All banks idle; CKE > = VIH(min); Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM IDD2F Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); Address and other control inputs stable with keeping >= VIH(min) or = VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD3N Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; 50% of data changing at every burst; lout = 0 m A IDD4R Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst IDD4W Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 DDR200 at 100Mhz, 10*tCK for DDR266A DDR266A & DDR266B DDR266B at 133Mhz ; distributed refresh IDD5 Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100Mhz for DDR200 DDR200, 133Mhz for DDR266A DDR266A & DDR266B DDR266B IDD6 Orerating current - Four bank operation ; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition IDD7A Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM DDR SDRAM IDD spec table Symbol A2(DDR266 DDR266@CL=2) B0(DDR266 DDR266@CL=2.5) A0(DDR200 DDR200@CL=2) Unit IDD0 760 760 660 mA IDD1 940 940 820 mA IDD2P 256 256 200 mA IDD2F 440 440 360 mA IDD2Q 360 360 280 mA IDD3P 400 400 320 mA IDD3N 560 440 mA 1320 1320 1100 mA IDD4W 1540 1540 1220 mA IDD5 1180 1180 1040 mA Normal 24 24 24 mA Low power IDD6 560 IDD4R 12 12 12 mA 2000 2000 1740 mA IDD7A * Module Notes IDD was calculated on the basis of component IDD and Optional can be differently measured according to DQ loading cap. < Detailed test conditions for DDR SDRAM IDD1 & IDD7 > IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 2. Timing patterns - DDR200 DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst IDD7A : Operating current: Four bank operation 1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 2. Timing patterns - DDR200 DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst - DDR266B DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst - DDR266A DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK,Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM AC Operating Conditions Parameter/Condition Symbol Max Min VID(AC) VIX(AC) 0.5*VDDQ-0.2 1 0.5*VDDQ+0.2 V 2 0.7 Input Crossing Point Voltage, CK and CK inputs 3 V VIL(AC) Input Differential Voltage, CK and CK inputs 3 V VDDQ+0.6 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Note VREF - 0.31 VIH(AC) Unit V Input High (Logic 1) Voltage, DQ, DQS and DM signals VREF + 0.31 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS (V DD =2.5V, V DDQ=2.5V, T A= 0 to 70 °C ) Parameter Value Unit 0.5 * V DDQ V 1.5 V V REF+0.3 1/V REF -0.3 1 V V REF V V tt V Input reference voltage for Clock Input signal maximum peak swing Input Levels(V IH /V IL) Input timing measurement reference level Output timing measurement reference level Output load condition Note See Load Circuit V tt =0.5*V DDQ RT =50 Output Z0=50 V REF =0.5*V DDQ CLOAD =30pF Output Load Circuit (SSTL_2) Input/Output CAPACITANCE (V DD =2.5V, V DDQ=2.5V, TA= 25 °C , f=1MHz) Parameter Symbol Min Max Unit Input capacitance(A 0 ~ A 11 , BA 0 ~ BA 1,RAS,CAS, WE ) C IN1 36 44 pF Input capacitance(CKE 0) C IN2 36 44 pF Input capacitance( CS 0 , CS 1) C IN3 26 30 pF Input capacitance( CLK 0, CLK 1 ) C IN4 34 38 pF Data & DQS input/output capacitance(DQ0 ~DQ6 3) C OUT 12 14 pF Input capacitance(DM 0~DM 8) C IN5 12 14 pF Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM AC Timming Parameters & Specifications Parameter Symbol (These AC charicteristics were tested on the Component) -TCA2(DDR266A DDR266A) -TCB0(DDR266B DDR266B) Min Max Min Max -TCA0 (DDR200 DDR200) Min Max Unit Row cycle time tRC 65 65 70 Refresh row cycle time tRFC 75 75 80 Row active time tRAS 45 RAS to CAS delay tRCD 20 20 20 ns tRP 20 20 20 ns Row active to Row active delay tRRD 15 15 15 ns Write recovery time tWR 15 15 15 ns Last data in to Read command tWTR 1 1 1 Note tCK Row precharge time Col. address to Col. address delay Clock cycle time tCCD CL=2.0 CL=2.5 tCK 120K 1 45 120K 1 ns ns 48 120K 1 7.5 12 10 12 7.5 12 7.5 ns tCK 10 12 12 ns 5 ns 5 Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS-out access time from CK/CK tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns Output data access time from CK/ CK tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns Data strobe edge to ouput data edge tDQSQ - 0.5 - 0.5 - 0.6 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 DQS-in cycle time tDSC 0.9 Address and Control Input setup time(fast) tIS 0.9 0.9 1.1 ns 6 Address and Control Input hold time(fast) tIH 0.9 0.9 1.1 ns 6 Address and Control Input setup time(slow) tIS 1.0 1.0 1.1 ns 6 Address and Control Input hold time(slow) tIH 1.0 1.0 1.1 ns 6 Data-out high impedence time from CK/CK tHZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 +0.75 -0.75 +0.75 -0.8 +0.8 Data-out low impedence time from CK/CK 1.1 0.9 1.1 0.9 5 2 tCK 1.1 tCK ns tLZ -0.75 tSL(I) 0.5 0.5 0.5 V/ns 6 Input Slew Rate(for I/O pins) tSL(IO) 0.5 0.5 0.5 V/ns 7 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 V/ns 10 Output Slew Rate(x16) tSL(O) 0.7 5 0.7 5 0.7 5 V/ns 10 Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 Input Slew Rate(for input only pins) ns Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 Parameter 200pin DDR SDRAM SODIMM Symbol -TCA2(DDR266A DDR266A) Min Max -TCB0(DDR266B DDR266B) Min Max -TCA0 (DDR200 DDR200) Min Max Unit Note Mode register set cycle time tMRD 15 15 16 ns DQ & DM setup time to DQS tDS 0.5 0.5 0.6 ns 7,8,9 7,8,9 DQ & DM hold time to DQS tDH 0.5 0.5 0.6 ns DQ & DM input pulse width tDIPW 1.75 1.75 2 ns Power down exit time tPDEX 7.5 7.5 10 ns Exit self refresh to non-Read command tXSNR 75 75 80 ns Exit self refresh to read command tXSRD 200 200 200 tCK tREFI 15.6 15.6 15.6 us 1 7.8 7.8 7.8 us 1 5 Refresh interval time 64Mb, 128Mb 256Mb Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - ns Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - 4 ns Data hold skew factor tQHS DQS write postamble time tWPST 0.4 tDAL (tWR/tCK) + (tRP/tCK) Autoprecharge write recovery + Precharge time 0.75 0.6 0.75 0.4 (tWR/tCK) + (tRP/tCK) 0.6 0.8 0.4 (tWR/tCK) + (tRP/tCK) ns 0.6 tCK 3 tCK 11 1. Maximum burst refresh of 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with t RCD satisfied after this command. 5. For registered DIMMs, t CL and t CH are 45% of the period including both the half period jitter (t JIT(HP) of the PLL and the half period jitter due to crosstalk (t JIT(crosstalk) on the DIMM. Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate tIS tIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 This derating table is used to increase t IS /tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate tDS tDH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 This derating table is used to increase t DS /tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level tDS tDH (mV) (ps) (ps) ± 280 +50 +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate tDS tDH (ns/V) (ps) (ps) 0 0 0 ±0.25 +50 +50 ±0.5 +100 +100 This derating table is used to increase t DS /tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cyc le time. The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) tIH/tIS (ps) tDSS/tDSH (ps) tAC/tDQSCK (ps) tLZ(min) (ps) tHZ(max) (ps) 1.0V/ns 0 0 0 0 0 0.75V/ns +50 +50 +50 -50 +50 0.5V/ns +100 +100 +100 -100 +100 Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM Command Truth Table (V=Valid, X=Don t Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA 0,1 A 10/AP 10/AP A 12, A 11 A9 ~ A0 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 L L L H X L H H H Auto Refresh H Entry Refresh Self Refresh Exit H L 3 L H H X X H X L L H H V Read & Column Address Auto Precharge Disable H X L H L H V Write & Column Address Auto Precharge Disable H X L H L L V H X L H H L H X L L H L Entry H L H X X X Exit L H Entry H L 3 X Bank Active & Row Addr. 3 Auto Precharge Enable 3 Row Address L Auto Precharge Enable Burst Stop Active Power Down L V V V X X X X X X H H X X V 5 X V X H H H 7 L X 4, 6 X L 4 4 X H 4 Column Address (A 0~A 8) L V All Banks Column Address (A 0~A 8) H H Bank Selection Precharge X V Precharge Power Down Mode X X Exit L H L DM H No operation (NOP) : Not defined H X X H X X X X L H H H 8 9 X 9 Note : 1. OP Code : Operand Code. A 0 ~ A12 & BA 0 ~ BA 1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA 1 : Bank select addresses. If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA 0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP A10/AP is "High" at row precharge, BA 0 and BA 1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 0.3 Dec. 2001 M470L3224BT0 M470L3224BT0 200pin DDR SDRAM SODIMM PACKAGE DIMENSIONS Units : Inches (Millimeters) 2.70 (67.60) 2.50 (63.60) 0.086 2.15 39 41 0.456 11.40 199 2- 0.07 (1.80) 1.896 (47.40) 0.17 (4.20) 0.096 (2.40) 0.07 (1.8) 1.25 0.79 0.24 (6 .0 ) 1 (2 0.00) 0.16 ± 0.039 (4.00 ± 0.10) (31 .7 5) Full R 2x Z Y 0.098 2.45 200 0 .1 57 Min ( 4.00 Min) 0.15 7 Min ( 4.00 Min) 0.150 Max (3.80 Max) 0.04 ± 0.0039 (1.00 ± 0.10) 0.16 ± 0.0039 (4.00 ± 0.10) 0.04 ± 0.0039 (1.00 ± 0.1) Detail Z 0.102 Mi n 40 42 (2 .5 5 Min) 2 0.018 ± 0.001 (0.45 ± 0.03 ) 0.01 (0.25) 0.024 TYP (0.60 TYP ) Detail Y Tolerances : ±.006(.15) unless otherwise specified The used device is 16Mx16 SDRAM, TSOP SDRAM Part No. : K4H561638B-TC/L K4H561638B-TC/L Rev. 0.3 Dec. 2001