M27C1001 FDIP32W LCCC32W PDIP32 PLCC32 TSOP32 A0-A16 AI00710B AI00712 AI00711 - Datasheet Archive

 

1 Mbit (128Kb x8) UV EPROM and OTP EPROM 5V ± 10% SUPPLY VOLTAGE in READ OPERATION FAST ACCESS TIME: 35ns LOW POWER

 

M27C1001 M27C1001 1 Mbit (128Kb x8) UV EPROM and OTP EPROM 5V ± 10% SUPPLY VOLTAGE in READ OPERATION FAST ACCESS TIME: 35ns LOW POWER CONSUMPTION: ­ Active Current 30mA at 5Mhz ­ Standby Current 100µA PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100µs/byte (typical) ELECTRONIC SIGNATURE ­ Manufacturer Code: 20h ­ Device Code: 05h DESCRIPTION The M27C1001 M27C1001 is a 1 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large programs and is organized as 131,072 words of 8 bits. The FDIP32W FDIP32W (window ceramic frit-seal package) and the LCCC32W LCCC32W (leadless chip carrier package) have a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C1001 M27C1001 is offered in PDIP32 PDIP32, PLCC32 PLCC32 and TSOP32 TSOP32 (8 x 20 mm) packages. 32 32 1 1 FDIP32W FDIP32W (F) PDIP32 PDIP32 (B) LCCC32W LCCC32W (L) PLCC32 PLCC32 (C) TSOP32 TSOP32 (N) 8 x 20mm Figure 1. Logic Diagram VCC VPP 17 8 A0-A16 A0-A16 Q0-Q7 Table 1. Signal Names A0-A16 A0-A16 Address Inputs Q0-Q7 Data Outputs E Chip Enable G Output Enable P Program VPP Program Supply VCC Supply Voltage VSS Ground September 1998 P M27C1001 M27C1001 E G VSS AI00710B AI00710B 1/16 M27C1001 M27C1001 Figure 2A. DIP Pin Connections VCC P NC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3 A12 A15 A16 VPP VCC P NC 1 32 A7 A6 A5 A4 A3 A2 A1 A0 Q0 9 M27C1001 M27C1001 25 A14 A13 A8 A9 A11 G A10 E Q7 17 VSS Q3 Q4 Q5 Q6 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 M27C1001 M27C1001 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Q1 Q2 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS Figure 2B. LCC Pin Connections AI00712 AI00712 AI00711 AI00711 Warning: NC = Not Connected. Warning: NC = Not Connected. Figure 2C. TSOP Pin Connections DEVICE OPERATION The operating modes of the M27C1001 M27C1001 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27C1001 M27C1001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equalto the delay from E to output (tELQV). Data is availableat the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least t AVQV-tGLQV. Standby Mode The M27C1001 M27C1001 has a standby mode which reduces the supply current from 30mA to 100µA. The M27C1001 M27C1001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. A11 A9 A8 A13 A14 NC P VCC VPP A16 A15 A12 A7 A6 A5 A4 1 8 9 32 M27C1001 M27C1001 (Normal) 16 25 24 17 AI01151B AI01151B Warning: NC = Not Connected. 2/16 G A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3 M27C1001 M27C1001 Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature (3) ­40 to 125 °C TBIAS Temperature Under Bias ­50 to 125 °C TSTG Storage Temperature ­65 to 150 °C VIO (2) Input or Output Voltages (except A9) ­2 to 7 V Supply Voltage ­2 to 7 V A9 Voltage ­2 to 13.5 V Program Supply Voltage ­2 to 14 V TA VCC VA9 (2) VPP Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is ­0.5V with possible undershoot to ­2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode E G P A9 VPP Q0 - Q7 Read VIL VIL X X VCC or VSS Data Out Output Disable VIL VIH X X VCC or VSS Hi-Z Program VIL VIH VIL Pulse X VPP Data In Verify VIL VIL VIH X VPP Data Out Program Inhibit VIH X X X VPP Hi-Z Standby VIH X X X VCC or VSS Hi-Z Electronic Signature VIL VIL VIH VID VCC Codes Note: X = VIH or VIL, VID = 12V ± 0.5V Table 4. Electronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer's Code VIL 0 0 1 0 0 0 0 0 20h Device Code VIH 0 0 0 0 0 1 0 1 05h Two Line Output Control BecauseEPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows : a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficientuse of thesetwo controllines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. 3/16 M27C1001 M27C1001 Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times 10ns 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V 1.5V 0.8V and 2V Input and Output Timing Ref. Voltages Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 1N914 1N914 3V 1.5V 3.3k 0V DEVICE UNDER TEST Standard 2.4V OUT CL 2.0V 0.8V 0.4V CL = 30pF for High Speed CL = 100pF for Standard AI01822 AI01822 CL includes JIG capacitance AI01823B AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol CIN C OUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitiveand inductiveloading of the deviceat the output. The associated transient voltage peaks can be suppressed by complying with the two line output 4/16 control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. M27C1001 M27C1001 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 °C, ­40 to 85 °C or ­40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol Parameter Test Condition ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS IPP Program Current VIL Input Low Voltage Input High Voltage VIH (2) VOL Max Unit 0V VIN VCC ±10 µA 0V VOUT VCC ±10 µA E = VIL, G = VIL, IOUT = 0mA, f = 5MHz 30 mA E = VIH 1 mA E > VCC ­ 0.2V 100 µA VPP = VCC 10 µA ­0.3 0.8 V 2 VCC + 1 V 0.4 V Output Low Voltage Min IOL = 2.1mA Output High Voltage TTL IOH = ­400µA 2.4 V Output High Voltage CMOS VOH IOH = ­100µA VCC ­ 0.7 V Note: 1. VCC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70 °C, ­40 to 85 °C or ­40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27C1001 M27C1001 Symbol Alt Parameter Test Condition -45 Min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV (3) -60 Max Min Unit -70 Max Min Max E = VIL, G = VIL 45 60 70 ns Chip Enable Low to Output Valid G = VIL 45 60 70 ns tOE Output Enable Low to Output Valid E = VIL 25 30 35 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 25 0 30 0 30 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 25 0 30 0 30 ns tOH Address Transition to Output Transition E = VIL, G = VIL 0 tAXQX 0 0 ns Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. In case of 45ns speed see High Speed AC measurament conditions. 5/16 M27C1001 M27C1001 Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70 °C, ­40 to 85 °C or ­40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27C1001 M27C1001 Symbol Alt Parameter Test Condition -80 Min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV -90 Max Min -12/-15/ -20/-25 -10 Max Min Max Unit Min Max E = VIL, G = VIL 80 90 100 120 ns Chip Enable Low to Output Valid G = VIL 80 90 100 120 ns tOE Output Enable Low to Output Valid E = VIL 40 45 50 60 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 30 0 30 0 30 0 40 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 30 0 30 0 30 0 40 ns tOH Address Transition to Output Transition E = VIL, G = VIL 0 tAXQX 0 0 0 ns Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A16 A0-A16 VALID tAVQV VALID tAXQX E tGLQV tEHQZ G tELQV Q0-Q7 tGHQZ Hi-Z AI00713B AI00713B Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C1001 M27C1001 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed,both '1's and '0's can be present in the data word. The only way to 6/16 changea '0' to a '1' is by die expositionto ultraviolet light (UV EPROM). The M27C1001 M27C1001 is in the programming mode when Vpp input is at 12.75V, E is at VIL and P is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V. M27C1001 M27C1001 Table 9. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Parameter Test Condition Min Max ±10 µA 50 mA 50 VIL VIN VIH Unit mA ILI Input Leakage Current ICC Supply Current IPP Program Current VIL Input Low Voltage ­0.3 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage 0.4 V VOH Output High Voltage TTL VID A9 Voltage E = VIL IOL = 2.1mA IOH = ­400µA 2.4 V 11.5 12.5 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 10. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Alt Parameter tAVPL tAS Address Valid to Program Low 2 µs tQVPL tDS Input Valid to Program Low 2 µs tVPHPL tVPS VPP High to Program Low 2 µs tVCHPL tVCS VCC High to Program Low 2 µs tELPL tCES Chip Enable Low to Program Low 2 µs tPLPH tPW Program Pulse Width 95 tPHQX tDH Program High to Input Transition 2 µs tQXGL tOES Input Transition to Output Enable Low 2 µs tGLQV tOE Output Enable Low to Output Valid tDFP Output Enable High to Output Hi-Z 0 tAH Output Enable High to Address Transition 0 tGHQZ (2) tGHAX Test Condition Min Max 105 Unit µs 100 ns 130 ns ns Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 7/16 M27C1001 M27C1001 Figure 6. Programming and Verify Modes AC Waveforms VALID A0-A16 A0-A16 tAVPL Q0-Q7 DATA IN tQVPL DATA OUT tPHQX VPP tVPHPL tGLQV tGHQZ VCC tVCHPL tGHAX E tELPL P tPLPH tQXGL G PROGRAM VERIFY AI00714 AI00714 Figure 7. Programming Flowchart VCC = 6.25V, VPP = 12.75V n =0 P = 100µs Pulse NO +n = 25 YES FAIL NO VERIFY + Addr YES Last Addr NO YES CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V AI00715C AI00715C 8/16 PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed, with a guaranteed margin, in a typical time of 13 seconds. Programming with PRESTO II involves in applying a sequence of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automaticallyactivated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C1001s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C1001 M27C1001 may be common. A TTL low level pulse applied to a M27C1001 M27C1001's P input, with E low and VPP at 12.75V, will program tha t M27C1001 M27C1001. A high level E input inhibits the other M27C1001s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at 12.75V and VCC at 6.25V. M27C1001 M27C1001 On-Board Programming The M27C1001 M27C1001 can be directly programmed in the application circuit. See the relevant Application Note AN620 AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programmingalgorithm. The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27C1001 M27C1001. To activate the ES mode, the programmingequipment must force 11.5V to 12.5V on address line A9 of the M27C1001 M27C1001, with VPP=VCC=5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device identifier code. For the STMicroelectronics M27C1001 M27C1001, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27C1001 M27C1001 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It shouldbe notedthat sunlight and some type of fluorescent lamps have wavelengthsin the 3000-4000Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C1001 M27C1001 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C1001 M27C1001 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C1001 M27C1001 window to prevent unintentional erasure. The recommended erasure procedurefor the M27C1001 M27C1001 is exposure to short wave ultraviolet light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating. The M27C1001 M27C1001 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. 9/16 M27C1001 M27C1001 ORDERING INFORMATION SCHEME Example: Speed M27C1001 M27C1001 -35 X VCC Tolerance C 1 TR Package Option Temperature Range 45 ns X ± 5% F FDIP32W FDIP32W 1 0 to 70 °C -60 60 ns blank ± 10% B PDIP32 PDIP32 3 ­40 to 125 °C -70 70 ns L LCCC32W LCCC32W 6 ­40 to 85 °C -80 80 ns C PLCC32 PLCC32 -90 90 ns N -10 100 ns TSOP32 TSOP32 8 x 20mm -12 120 ns -15 150 ns -20 200 ns -25 250 ns -45 (1) X TR Additional Burn-in Tape & Reel Packing Note: 1. High Speed, see AC Characteristics section for further information For a listof availableoptions (Speed, Package,etc.) or forfurther informationon any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 10/16 M27C1001 M27C1001 FDIP32W FDIP32W - 32 pin Ceramic Frit-seal DIP, with window mm Symb Typ inches Min Max A Typ Min 5.72 Max 0.225 A1 0.51 1.40 0.020 0.055 A2 3.91 4.57 0.154 0.180 A3 3.89 4.50 0.153 0.177 B 0.41 0.56 0.016 0.022 ­ ­ ­ ­ B1 1.45 0.057 C 0.23 0.30 0.009 0.012 D 41.73 42.04 1.643 1.655 ­ ­ 1.500 ­ ­ 0.600 D2 38.10 E 15.24 ­ e eA 14.99 13.36 ­ 2.54 ­ 13.06 E1 ­ 0.100 0.590 ­ ­ eB 16.18 3.18 S ­ ­ 4° 11° N 32 0.710 0.060 0.098 ­ ­ 4° 0.280 11° 32 A2 A3 A1 B1 ­ 0.637 2.49 ­ 7.11 ­ 0.125 1.52 ­ 0.526 ­ 18.03 L ­ 0.514 B A L e eA D2 C eB D S N E1 E 1 FDIPW-a Drawing is not to scale. 11/16 M27C1001 M27C1001 PDIP32 PDIP32 - 32 lead Plastic DIP, 600 mils width mm Symb Typ inches Min Max A Typ Min 5.08 A1 3.56 4.06 0.38 0.51 ­ ­ C 0.20 D 0.200 0.38 A2 0.015 1.52 0.140 0.160 0.015 0.020 ­ ­ 0.30 0.008 0.012 41.78 B B1 Max 42.04 1.645 1.655 0.060 D2 38.10 ­ ­ 1.500 ­ ­ E 15.24 ­ ­ 0.600 ­ ­ 13.59 13.84 0.535 0.545 E1 e1 2.54 ­ ­ 0.100 ­ ­ eA 15.24 ­ ­ 0.600 ­ ­ eB 15.24 17.78 0.600 0.700 L 3.18 3.43 0.125 0.135 S 1.78 2.03 0.070 0.080 0° 10° 0° 10° N 32 32 A2 A1 B1 B A L e1 eA D2 C eB D S N E1 E 1 PDIP Drawing is not to scale. 12/16 M27C1001 M27C1001 LCCC32W LCCC32W - 32 lead Leadless Ceramic Chip Carrier, square window mm Symb Typ Min A inches Max Typ Min Max 2.28 0.090 B 0.51 0.71 0.020 0.028 D 11.23 11.63 0.442 0.458 E 13.72 14.22 0.540 0.560 ­ ­ ­ ­ 0.39 ­ 0.015 ­ e 1.27 e1 0.050 e2 7.62 ­ ­ 0.300 ­ ­ e3 10.16 ­ ­ 0.400 ­ ­ h 1.02 ­ ­ 0.040 ­ ­ j 0.51 ­ ­ 0.020 ­ ­ L 1.14 1.40 0.045 0.055 L1 1.96 2.36 0.077 0.093 K 10.50 10.80 0.413 0.425 K1 8.03 8.23 0.316 0.324 N 32 32 e2 D j x 45o e N 1 L1 K E e3 e1 B K1 A h x 45o L LCCCW-a Drawing is not to scale. 13/16 M27C1001 M27C1001 PLCC32 PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular mm Symb Typ inches Min Max A 2.54 A1 A2 B Typ Min Max 3.56 0.100 0.140 1.52 2.41 0.060 0.095 ­ 0.38 ­ 0.015 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 e 1.27 R 0.89 ­ ­ 0.00 F 0.25 ­ 0.050 ­ ­ 0.010 ­ 0.035 ­ 0.000 ­ N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R PLCC Drawing is not to scale. 14/16 CP M27C1001 M27C1001 TSOP32 TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm mm Symb Typ inches Min Max A Typ Min 1.20 Max 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 - - - - L 0.50 0.70 0.020 0.028 0° 5° 0° 5° N 32 e 0.50 0.020 32 CP 0.10 0.004 A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a A1 L Drawing is not to scale. 15/16 M27C1001 M27C1001 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 16/16