M24C16 M24C08 M24C04 M24C02 M24C01 M24C16-S AI02033 AI02034D AI02035D AI02036D - Datasheet Archive

 

M24C04, M24C02, M24C01 16/8/4/2/1 Kbit Serial I²C Bus EEPROM s Two Wire I2C Serial Interface Supports 400 kHz Protocol s

 

M24C16 M24C16, M24C08 M24C08 M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 16/8/4/2/1 Kbit Serial I²C Bus EEPROM s Two Wire I2C Serial Interface Supports 400 kHz Protocol s Single Supply Voltage: SBGA ­ 4.5V to 5.5V for M24Cxx ­ 2.5V to 5.5V for M24Cxx-W 8 SBGA5 (EA) 75 mil width ­ 1.8V to 5.5V for M24Cxx-R ­ 1.8V to 3.6V for M24Cxx-S s s BYTE and PAGE WRITE (up to 16 Bytes) s RANDOM and SEQUENTIAL READ Modes s Self-Timed Programming Cycle s Automatic Address Incrementing s Enhanced ESD/Latch-Up Behavior s More than 1 Million Erase/Write Cycles s 1 Write Control Input More than 40 Year Data Retention DESCRIPTION These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 bit (M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01), and operate with a power supply down to 2.5 V (for the -W version of each device), and down to 1.8 V (for the -R and -S versions of each device). The M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages. The M24C16-S M24C16-S is also available in a Chip Scale package. PDIP8 (BN) 0.25 mm frame 8 1 SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width Figure 1. Logic Diagram VCC 3 E0-E2 Table 1. Signal Names E0, E1, E2 Serial Data SCL Serial Clock WC Write Control VCC Supply Voltage VSS M24Cxx Chip Enable SDA SCL SDA Ground WC VSS AI02033 AI02033 November 2001 1/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Figure 2A. DIP Connections M24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS 8 7 6 5 1 2 3 4 VCC WC SCL SDA AI02034D AI02034D Note: 1. NC = Not Connected Figure 2B. SO Connections M24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS 8 7 6 5 1 2 3 4 VCC WC SCL SDA AI02035D AI02035D Note: 1. NC = Not Connected Figure 2C. TSSOP Connections M24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS 8 7 6 5 1 2 3 4 VCC WC SCL SDA AI02036D AI02036D Note: 1. NC = Not Connected Figure 2D. SBGA Connections (top view, marking side, with balls on the underside) M24C16 M24C16 2 1 WC VCC 3 SDA 5 4 SCL VSS AI02796F AI02796F 2/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Table 2. Absolute Maximum Ratings 1 Symbol Value Unit Ambient Operating Temperature ­40 to 125 °C TSTG Storage Temperature ­65 to 150 °C TLEAD Lead Temperature during Soldering 260 235 235 °C TA Parameter PDIP8: 10 seconds SO8: 20 seconds (max) 2 TSSOP8: 20 seconds (max) 2 VIO Input or Output range ­0.6 to 6.5 V VCC Supply Voltage ­0.3 to 6.5 V VESD Electrostatic Discharge Voltage (Human Body model) 3 4000 V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. IPC/JEDEC J-STD-020A J-STD-020A 3. JEDEC Std JESD22-A114A JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ) These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus VCC Maximum RP value (k) 20 16 RL 12 RL SDA MASTER 8 fc = 100kHz 4 fc = 400kHz CBUS SCL CBUS 0 10 100 1000 CBUS (pF) AI01665 AI01665 3/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Figure 4. I2C Bus Protocol SCL SDA SDA Input START Condition SCL 1 SDA 2 SDA Change STOP Condition 3 7 8 9 MSB ACK START Condition SCL 1 SDA 2 3 MSB 7 8 9 ACK STOP Condition AI00792B AI00792B threshold value, and all operations are disabled ­ the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, 4/21 this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or VSS, to establish the Device Select Code. M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Table 3. Device Select Code 1 Device Type Identifier Chip Enable RW b7 b6 b5 b4 b3 b2 b1 b0 M24C01 M24C01 Select Code 1 0 1 0 E2 E1 E0 RW M24C02 M24C02 Select Code 1 0 1 0 E2 E1 E0 RW M24C04 M24C04 Select Code 1 0 1 0 E2 E1 A8 RW M24C08 M24C08 Select Code 1 0 1 0 E2 A9 A8 RW M24C16 M24C16 Select Code 1 0 1 0 A10 A9 A8 RW Note: 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. 3. A10, A9 and A8 represent most significant bits of the address. Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. DEVICE OPERATION The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Table 4. Operating Modes Current Address Read RW bit WC 1 Bytes 1 X 1 0 Mode X Random Address Read Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address 1 reSTART, Device Select, RW = 1 1 X Sequential Read 1 X 1 Byte Write 0 VIL 1 START, Device Select, RW = 0 Page Write 0 VIL 16 START, Device Select, RW = 0 Similar to Current or Random Address Read Note: 1. X = VIH or VIL. 5/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Figure 5. Write Mode Sequences with WC=1 (data write inhibited) WC ACK BYTE ADDR NO ACK DATA IN STOP DEV SEL START Byte Write ACK R/W WC ACK DEV SEL START Page Write ACK BYTE ADDR NO ACK DATA IN 1 NO ACK DATA IN 2 DATA IN 3 R/W WC (cont'd) NO ACK DATA IN N STOP Page Write (cont'd) NO ACK AI02803C AI02803C Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3 (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b. When the Device Select Code is received on Serial Data (SDA), the device only responds if the 6/21 Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode. Devices with larger memory capacities (the M24C16 M24C16, M24C08 M24C08 and M24C04 M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not available for devices that need to use address line A9, and E2 is not available for devices that need to use address line A10 (see Figures 2A to 2D and Table 3 for details). Using the E0, E1 and E2 inputs pins, up to eight M24C02 M24C02 (or M24C01 M24C01), four M24C04 M24C04, two M24C08 M24C08 or one M24C16 M24C16 device can be connected to one I 2C bus. In each case, and in M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Figure 6. Write Mode Sequences with WC=0 (data write enabled) WC ACK BYTE ADDR ACK DATA IN STOP DEV SEL START BYTE WRITE ACK R/W WC ACK DEV SEL START PAGE WRITE ACK BYTE ADDR ACK DATA IN 1 ACK DATA IN 2 DATA IN 3 R/W WC (cont'd) ACK DATA IN N STOP PAGE WRITE (cont'd) ACK AI02804 AI02804 the hybrid cases, this gives a total memory capacity of 16 Kbits, 2 KBytes (except where M24C01 M24C01 devices are used). Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 6, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the address byte) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 5. When the bus master generates a Stop condition immediately after the Ack bit (in the "10 th bit" time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. Byte Write After the Device Select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Writeprotected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 6. Page Write The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same 'row' in the memory: 7/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Figure 7. Write Cycle Polling Flowchart using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK Returned YES NO Next Operation is Addressing the Memory YES Send Address and Receive ACK ReSTART NO STOP START Condition YES DATA for the WRITE Operation DEVICE SELECT with RW = 1 Continue the WRITE Operation Continue the Random READ Operation that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `rollover' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. 8/21 AI01847C AI01847C Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Tables 8A and 8B, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: ­ Initial condition: a Write cycle is in progress. ­ Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). ­ Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Figure 8. Read Mode Sequences ACK DATA OUT STOP START DEV SEL NO ACK R/W ACK START DEV SEL * ACK BYTE ADDR R/W ACK START DEV SEL DATA OUT R/W ACK ACK DATA OUT 1 NO ACK DATA OUT N R/W ACK START DEV SEL * ACK BYTE ADDR R/W ACK ACK DEV SEL * START SEQUENTIAL RANDOM READ DEV SEL * NO ACK STOP SEQUENTIAL CURRENT READ ACK START RANDOM ADDRESS READ STOP CURRENT ADDRESS READ ACK DATA OUT 1 R/W NO ACK STOP DATA OUT N AI01942 AI01942 Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 st and 3rd bytes) must be identical. first byte of this instruction having been sent during Step 1). Read Operations Read operations are performed independently of the state of the Write Control (WC) signal. Random Address Read A dummy Write is performed to load the address into the address counter (as shown in Figure 8) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master 9/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 terminates the transfer with a Stop condition, as shown in Figure 8, without acknowledging the byte. Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode. Table 5. AC Measurement Conditions Figure 9. AC Testing Input Output Waveforms 50 ns Input Rise and Fall Times 0.8VCC Input Pulse Voltages Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC 0.7VCC 0.2VCC to 0.8VCC 0.3VCC 0.2VCC AI00825 AI00825 Table 6. Input Parameters1 (TA = 25 °C, f = 400 kHz) Symbol Parameter Test Condition Min. Max. Unit CIN Input Capacitance (SDA) 8 pF CIN Input Capacitance (other pins) 6 pF 70 k ZWCL WC Input Impedance VIN < 0.5 V 5 ZWCH WC Input Impedance VIN > 0.7VCC 500 Pulse width ignored (Input Filter on SCL and SDA) Single glitch tNS Note: 1. Sampled only, not 100% tested. 10/21 k 100 ns M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Table 7A. DC Characteristics (TA = ­40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V) (TA = ­40 to 85 °C; VCC = 1.8 to 5.5 V or 1.8 to 3.6 V) Symbol Parameter Test Condition Max. Unit VIN = VSS or VCC ±2 µA VOUT = VSS or VCC, SDA in Hi-Z ±2 µA VCC=5V, fc=400kHz (rise/fall time < 30ns) 2 mA -W series: VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1 mA -R series: VCC =1.8V, fc=100kHz (rise/fall time < 30ns) 0.81 mA -S series: VCC =1.8V, fc=400kHz (rise/fall time < 30ns) 0.81 mA VIN = VSS or VCC , VCC = 5 V 1 µA -W series: VIN = VSS or VCC , VCC = 2.5 V 0.5 µA -R,S series: VIN = VSS or VCC , VCC = 1.8 V 0.31 µA ILI Input Leakage Current (SCL, SDA) ILO Output Leakage Current ICC ICC1 Supply Current Supply Current (Stand-by) Min. 4.5 V VCC 5.5 V VIL Input Low Voltage (E0, E1, E2, SCL, SDA) -R,S series: 0.3 VCC V 2.5 V VCC 5.5 V ­ 0.3 0.3 VCC V 2.5 V VCC -W series: ­ 0.3 ­ 0.3 0.3 VCC1 V 1.8 V VCC < 2.5 V ­ 0.3 0.25 VCC1 V VIH Input High Voltage (E0, E1, E2, SCL, SDA) 0.7VCC VCC+1 V VIL Input Low Voltage (WC) ­ 0.3 0.5 V VIH Input High Voltage (WC) 0.7VCC VCC+1 V IOL = 3 mA, VCC = 5 V 0.4 V VOL Output Low Voltage -W series: IOL = 2.1 mA, VCC = 2.5 V 0.4 V -R,S series: IOL = 0.7 mA, VCC = 1.8 V 0.21 V Note: 1. This is preliminary data. 11/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Table 7B. DC Characteristics1 (TA = ­40 to 125 °C; VCC = 4.5 to 5.5 V) Symbol ILI Parameter Test Condition Max. Unit VIN = VSS or VCC ±2 µA VOUT = VSS or VCC, SDA in Hi-Z ±2 µA VCC=5V, fc=400kHz (rise/fall time < 30ns) 3 mA VIN = VSS or VCC , VCC = 5 V 5 µA Input Leakage Current (SCL, SDA) Min. ILO Output Leakage Current ICC Supply Current ICC1 Supply Current (Stand-by) VIL Input Low Voltage (E0, E1, E2, SCL, SDA) ­ 0.3 0.3 VCC V VIH Input High Voltage (E0, E1, E2, SCL, SDA) 0.7VCC VCC+1 V VIL Input Low Voltage (WC) ­ 0.3 0.5 V VIH Input High Voltage (WC) 0.7VCC VCC+1 V VOL Output Low Voltage 0.4 V IOL = 3 mA, VCC = 5 V Note: 1. This is preliminary data. Table 8A. AC Characteristics M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Symbol Alt. Parameter VCC=4.5 to 5.5 V TA=­40 to 85°C Min Max VCC=4.5 to 5.5 V; TA=­40 to 125°C4 Min Unit Max tCH1CH2 tR Clock Rise Time 300 300 ns tCL1CL2 tF Clock Fall Time 300 300 ns tDH1DH2 2 tR SDA Rise Time 20 300 20 300 ns tDL1DL2 2 tF SDA Fall Time 20 300 20 300 ns tCHDX 1 tSU:STA Clock High to Input Transition 600 600 ns tCHCL tHIGH Clock Pulse Width High 600 600 ns tDLCL tHD:STA Input Low to Clock Low (START) 600 600 ns Clock Low to Input Transition tCLDX tHD:DAT tCLCH tLOW 0 0 µs Clock Pulse Width Low 1.3 1.3 µs tDXCX tSU:DAT Input Transition to Clock Transition 100 100 ns tCHDH tSU:STO Clock High to Input High (STOP) 600 600 ns tDHDL tBUF Input High to Input Low (Bus Free) 1.3 1.3 µs tCLQV 3 tAA Clock Low to Data Out Valid 200 tCLQX tDH Data Out Hold Time After Clock Low 200 fC fSCL Clock Frequency tW tWR Write Time Note: 1. 2. 3. 4. 12/21 900 200 900 200 ns ns 400 400 kHz 5 10 ms For a reSTART condition, or following a write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. This is preliminary data. M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Table 8B. AC Characteristics M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Symbol Alt. Parameter -S series -R series -W series VCC=2.5 to 5.5 V VCC=1.8 to 5.5 V VCC=1.8 to 3.6 V Unit TA=­40 to 85°C TA=­40 to 85°C4 TA=­40 to 85°C4 Min Max Min Max Min Max tCH1CH2 tR Clock Rise Time 300 1000 300 ns tCL1CL2 300 300 300 ns tF Clock Fall Time 2 tR SDA Rise Time 20 300 20 1000 20 300 ns tDL1DL2 2 tF SDA Fall Time 20 300 20 300 20 300 ns tCHDX 1 tSU:STA Clock High to Input Transition 600 4700 600 ns tCHCL tHIGH Clock Pulse Width High 600 4000 600 ns tDLCL tHD:STA Input Low to Clock Low (START) 600 4000 600 ns tCLDX tHD:DAT Clock Low to Input Transition 0 0 0 µs tDH1DH2 tCLCH tLOW Clock Pulse Width Low 1.3 4.7 1.3 µs tDXCX tSU:DAT Input Transition to Clock Transition 100 250 100 ns tCHDH tSU:STO Clock High to Input High (STOP) 600 4000 600 ns 4.7 1.3 µs tDHDL tBUF Input High to Input Low (Bus Free) 1.3 tCLQV 3 tAA Clock Low to Data Out Valid 200 tCLQX tDH Data Out Hold Time After Clock Low 200 fC fSCL Clock Frequency 400 100 400 kHz tW tWR Write Time 10 10 10 ms Note: 1. 2. 3. 4. 900 200 3500 200 200 900 200 ns ns For a reSTART condition, or following a write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. This is preliminary data. 13/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Figure 10. AC Waveforms tCHCL tCLCH SCL tDLCL SDA In tCHDX tCLDX START Condition SDA Input SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition SCL SDA In tCHDH tW STOP Condition Write Cycle tCHDX START Condition SCL tCLQV SDA Out tCLQX Data Valid AI00795C AI00795C 14/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Table 9. Ordering Information Scheme Example: M24C08 M24C08 ­ W DW 6 T Memory Capacity Option 16 16 Kbit (2048 x 8) T Tape and Reel Packing 08 8 Kbit (1024 x 8) 04 4 Kbit (512 x 8) 02 2 Kbit (256 x 8) 6 ­40 °C to 85 °C 01 1 Kbit (128 x 8) 3 ­40 °C to 125 °C Temperature Range Operating Voltage Package blank 4.5 V to 5.5 V (400 kHz) BN PDIP8 (0.25 mm frame) W 2.5 V to 5.5 V (400 kHz) MN SO8 (150 mil width) R 1.8 V to 5.5 V (100 kHz) DW TSSOP8 (169 mil width) 1.8 V to 3.6 V (400 kHz) EA1 SBGA5 (75 mil width) S Note: 1. SBGA5 package available only for the M24C16 M24C16, 1.8V to 3.6V (400 kHz), ­40°C to 85°C (M24C16-SEA6 M24C16-SEA6) ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all 1s (FFh). The notation used for the device number is as shown in Table 9. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 15/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 PDIP8 ­ 8 pin Plastic DIP, 0.25mm lead frame E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B Note: 1. Drawing is not to scale. PDIP8 ­ 8 pin Plastic DIP, 0.25mm lead frame mm inches Symb. Typ. Min. A Max. Typ. Min. 5.33 A1 Max. 0.210 0.38 0.015 A2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 D 9.27 9.02 10.16 0.365 0.355 0.400 E 7.87 7.62 8.26 0.310 0.300 0.325 E1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 ­ ­ 0.100 ­ ­ eA 7.62 ­ ­ 0.300 ­ ­ eB L 16/21 10.92 3.30 2.92 3.81 0.430 0.130 0.115 0.150 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 SO8 narrow ­ 8 lead Plastic Small Outline, 150 mils body width h x 45° A C B CP e D N E H 1 A1 L SO-a Note: Drawing is not to scale. SO8 narrow ­ 8 lead Plastic Small Outline, 150 mils body width mm inches Symb. Typ. Min. Max. A 1.35 A1 Min. Max. 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 ­ ­ ­ ­ H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 0° 8° 0° 8° N 8 e CP 1.27 Typ. 0.050 8 0.10 0.004 17/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 TSSOP8 ­ 8 lead Thin Shrink Small Outline D 8 5 c E1 1 E 4 L A1 A A2 L1 CP b e TSSOP8-M Note: 1. Drawing is not to scale. TSSOP8 ­ 8 lead Thin Shrink Small Outline mm inches Symbol Typ. Min. A Max. Typ. 1.200 A1 0.050 0.800 1.050 b 0.190 c 0.090 1.000 CP Max. 0.0472 0.150 A2 Min. 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ­ ­ 0.0256 ­ ­ E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0° 8° 18/21 0.0394 0° 8° M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 SBGA5 ­ 5 ball Shell Ball Grid Array ­ Underside view (ball side) D D1 1 2 E1 3 4 e A E 5 A1 SBGA-00B SBGA-00B Note: 1. Drawing is not to scale. SBGA5 ­ 5 ball Shell Ball Grid Array mm inches Symb. Typ. Min. Max. Typ. Min. Max. A 0.430 0.380 0.480 0.017 0.015 0.019 A1 0.180 0.150 0.210 0.007 0.006 0.008 D 1.900 1.870 1.930 0.075 0.074 0.076 D1 1.190 1.160 1.220 0.047 0.046 0.048 E 1.750 1.720 1.780 0.069 0.068 0.070 E1 1.070 1.040 1.100 0.042 0.041 0.043 e 0.800 0.770 0.830 0.031 0.030 0.033 ball diameter 0.350 0.320 0.380 0.014 0.013 0.015 N 5 5 19/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Table 10. Revision History Date Rev. Description of Revision 10-Dec-1999 2.4 TSSOP8 Turned-Die package removed (p 2 and order information) Lead temperature added for TSSOP8 in table 2 18-Apr-2000 2.5 Labelling change to Fig-2D, correction of values for `E' and main caption for Tab-13 05-May-2000 2.6 Extra labelling to Fig-2D 23-Nov-2000 3.0 SBGA package information removed to an annex document -R range changed to being the -S range, and the new -R range added 19-Feb-2001 3.1 SBGA package information put back in this document Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated References to PSDIP changed to PDIP and Package Mechanical data updated Wording brought in to line with standard glossary 20-Apr-2001 3.2 Revision of DC and AC characteristics for the -S series 08-Oct-2001 3.3 Ball numbers added to the SBGA connections and package mechanical illustrations 09-Nov-2001 3.4 Specification of Test Condition for Leakage Currents in the DC Characteristics table improved 20/21 M24C16 M24C16, M24C08 M24C08, M24C04 M24C04, M24C02 M24C02, M24C01 M24C01 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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