M2006-01 GR-253 OC-192 GR-253-CORE M2006-01-622

M2006-01 An Integrated Circuit Systems Company Preliminary Specifications M2006-01 Frequency Synthesizer DESCRIPTION The M2006-01

Micro Networks M2006-01 M2006-01 An Integrated Circuit Systems Company Preliminary Specifications M2006-01 M2006-01 Frequency Synthesizer DESCRIPTION The M2006-01 M2006-01 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Synthesizer in a 9mm x 9mm surface mount package. The internal high "Q" SAW filter provides low jitter signal performance and determines the output frequency of the VCSO. Selecting between two differential LVPECL clocks or one single-ended LVCMOS / LVTTL clock provides the input reference signal to the Frequency Translator. The maximum input frequency is 700MHz. The M2006-01 M2006-01 will default to a multiplying factor of 32 on power-up. The multiplying factor can be changed by serially programming the input and feedback dividers via the configuration logic. FEATURES Output Clock Frequency up to 700MHz A differential LVPECL signal provides the output clock for the device. A second differential output which can be programmed to divide the output frequency by a factor of 4 is also available. The output frequency can be momentarily increased or decreased to add or subtract one net output clock cycle by asserting the ADD_CLK or DROP_CLK inputs, respectively. Intrinsic Jitter