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TMDX138LOGICEXP Texas Instruments OMAP-L138 Experimenter Kit
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK
TMDXL138LOGICEXP Texas Instruments OMAP-L138 Experimenter Kit
CS2000P-DZZ Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-DZZ Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-CZZ Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10

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Logic TTL manual

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: SP3508 ® Evaluation Board Manual FEATURES Easy Evaluation of SP3508 Multi-Protocol , /receiver Loopback as well as evaluate the SP3508 in a DCE or DTE configuration. This Manual is split into , Manual 1 © Copyright 2003 Sipex Corporation Figure 1 V AV BNC VCC CC AGND , Input frin external source V 1-2 2-3 Input toVCC JP20 123 R2 50 JP5 TTL , 2 GND CC GND JP50 2 1 ttl Vdd CVdd 1uF GNDTP V CC RTS DTR RTS Sipex
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EIA-530A TTC 6000a schematic 40mhz remote control receiver circuit TTC 103 firebird 6000a RS422 Line driver RS-232 RS-449/V EIA-530 DB-25 SP3508CF
Abstract: SP3508 ® Evaluation Board Manual FEATURES Easy Evaluation of SP3508 Multi-Protocol , /receiver Loopback as well as evaluate the SP3508 in a DCE or DTE configuration. This Manual is split into , Manual 1 © Copyright 2004 Sipex Corporation Figure 1 1 CC V BNC AGND 4 AC , Input to GND JP20 123 R2 50 JP5 TTL Jumper Configuration 1 Input toVCC Description GND VCC GND JP50 2 1 ttl Vdd CVdd 1uF GNDTP VCC DTR RTS ST Sipex
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CTS 41 EIA-449 SIPEX Selection Guide Motorola multimeter db25 Connector Pinout Details C326 SP3508CEB
Abstract: B868POWER : TECHNICAL MANUAL TABLE OF CONTENTS CHAPTER I. INTRODUCTION , . 50 3 B868POWER : TECHNICAL MANUAL CHAPTER 1 INTRODUCTION I.1. Aim of the Document , , standard and product's history. 4 B868POWER : TECHNICAL MANUAL I.2. Software and manuals The standard configuration and test software MTC is fully described in its own manual. It gives an user , many examples, are fully described in the "Functionalities & Operating Modes" manual. I.3. Product One RF Technology
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m868-power telemetry block diagram delta 6 radio ats2501 A 1458 B868 S253-S254 RS422/RS485
Abstract: SP508 ® Evaluation Board Manual FEATURES Easy Evaluation of SP508 Multi-Protocol , as well as evaluate the SP508 in a DCE or DTE configuration. This Manual is split into sections to , evaluation board for parametric testing. Rev. 5/9/05 SP508 Evaluation Board Manual 1 © Copyright , 20 21 27 1 0 LATCH 23 TERM_OFF 22 Logic High Logic Low VCC D2 1 1 0 1 0 , Board Manual 2 © Copyright 2005 Sipex Corporation SP508 EVALUATION BOARD BOARD LAYOUT 5. At Sipex
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DB25 connector PCB TTC 6000a rs449 pinout RS-449 SP508CF SP508EF SP508CEB
Abstract: SP508 ® Evaluation Board Manual FEATURES Easy Evaluation of SP508 Multi-Protocol , evaluate the SP508 in a DCE or DTE configuration. This Manual is split into sections to give the user the , testing. rev. 7/7/03 SP508 Evaluation Board Manual 1 © Copyright 2003 Sipex Corporation 1uF , OFF No Loopback 1 Logic high 0 Driver applies for DCE only on Pins 8 and 10. Logic , internal cable termination Figure 1 rev. 7/7/03 SP508 Evaluation Board Manual 2 © Copyright Sipex
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A7105 EIA530 CBB13 SP508CB
Abstract: Manual Chapter 7 - IO Control Boxes Page 7-19 10-Dec-13 (A1) 7.1.3 (p) - Set TTL Pulse , TTL Bit Mini-Circuits Portable Test Equipment Programming Manual Chapter 7 - IO Control Boxes , Mini-Circuits Portable Test Equipment Programming Manual Chapter 7 - Input/Output (IO) Control Boxes Mini-Circuits Portable Test Equipment Programming Manual Chapter 7 - IO Control Boxes Page , . 7-18 7.1.3 (o) - Set TTL Bit Mini-Circuits
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RELAY DEC BYTE63
Abstract: Data inputs. GND1, GND2 Ground Pins GND1 is a TTL I/O Ground and GND2 is an internal Logic and , volt nominal power supply pins. VCC1 powers TTL I/O, VCC2 powers ECL and VCC3 powers internal Logic , , GND2 is an internal Logic and Analog Ground. IGM I-Got-Mine (TTL Output) This pin signals , supply pins. VCC1 powers TTL I/O, and VCC2 powers internal Logic and Analog circuitry. same time DOi , /Am7969-125 Am7968/Am7969-175 Data Sheet and Technical Manual 1994 © 1994 Advanced Micro Advanced Micro Devices
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AM7968-125V/B3A TBB 1458 p HC18U working of ultrasonic transmitter Ultrasonic transmitter receiver transistor AE code PNP smd 7968/A 12330E-57
Abstract: ]X2 ]X1 ]GND2 (CML) ]GND1 (TTL) ]CLK 07370 F-6 Q Q Note: Pin 1 is marked for orientation. LOGIC , two bits of Command. GND1, GND2 Ground Pins GND1 is a TTL I/O Ground and GND2 is an internal Logic and , volt nominal power supply pins. Vcci powers TTL I/O, Vcc2 powers ECL and Vcc3 powers internal Logic and , GND1 is a TTL I/O Ground, GND2\s an internal Logic and Analog Ground. IGM l-Got-Mine (TTL Output) This , are +5.0 volt nominal power supply pins. Vcci powers TTL I/O, and Vcc2 powers internal Logic and -
OCR Scan
TRANSISTOR SMD m3a transistor 3B6 smd b3 8902 AM7969 tls1019 avalanche photodiode receiver 07370F-1
Abstract: with reset and flag â'¢ TTL shutdown with selectable positive or negative logic â'¢ Tracking for , ) 2.2.2 Rear Panel Switch S1 Default Settings SI-I TTL Shutdown Logic Selcct (OPEN=negative logic , Logic: LOW = ACTIVE . NOT USED TTL SHUTDOWN CURRENT LIMIT PROGRAM VOLTAGE PROGRAM CURRENT READBACK , -1 (TTL shutdown) to ON (closed) to obtain positive logic (high signal enables output). The factory-set , -1 Setting TTL Signal Level Output Condition OPEN (Negative logic) HIGH OFF LOW ON CLOSED (Positive logic -
OCR Scan
QN-2907-A ap d444 LT735 2501 optocoupler CJ 4148 ZENER lm 2491 R-2002-41 R-4991-41 R-3323-41 R-4750-41 R-1001-41 R-3011-41
Abstract: 111 Ferranti Logic Macro Function Library DS/100 DS Design Manual DS/110 VALID Workstation Manual , Contents Recommended TTL types for ease of logic conversion to ULA format Guide to the generation of test , . Utilising 'Differential Logic' Macros, the 1.5 micron, double metal Ferranti Advanced Bipolar process - FAB , Logic' flip-flop: clock to output delay 1.5ns clock frequency 250MHz Gate delay: Ins virtually independent of fan-out, supply voltage and clock frequency LOW POWER PERFORMANCE 'Differential Logic -
OCR Scan
ferranti ula ula ferranti ferranti ula flip flop ULA100DS 901 SERIES 100MH 165//W
Abstract: Ground. 0 Volts. 2 40 TCK Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is internally pulled up to V DD. 3 41 TCLR TIE Circuit Reset (TTL Input): A logic , Primary Reference Loss (TTL Input). Typically, external equipment applies a logic high to this input when , (Automatic or Manual) and state (Normal, Holdover or Freerun) of operation. The logic level at this input is , In Manual Control, a logic low selects the PRI (primary) reference source as the input reference -
OCR Scan
MT9044 DS5058 T9044AP T9044AL T9044
Abstract: TTL/Analog Analog Input or Logic Input/Output. 18 I/O2 I/O TTL/Analog Analog Input or Logic Input/Output. 19 I/O5 I/O TTL/Analog Analog Input or Logic Input/Output. 20 I/O4 I/O TTL/Analog Analog Input or Logic Input/Output. 21 RxD / A / - I/I , Technical Manual TABLE OF CONTENTS CHAPTER I. INTRODUCTION .1 I.1. AIM , these registers, please refer to the "Functionalities and Operating Modes" manual. I.2. Software & One RF Technology
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MSP430F148
Abstract: Pseudo-ECL Levels and TTL Levels MOTOROLA MC68836 USER'S MANUAL 1-1 1-2 MC68836 USER'S MANUAL , minimizes any interaction with the TTL circuits. MOTOROLA MC68836 USER'S MANUAL 4-3 TRANSMIT , .2-6 MC68836 USER'S MANUAL i TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number , .5-2 TTL Interface , .6-3 MC68836 USER'S MANUAL MOTOROLA LIST OF FIGURES Figure Number Title Page Number 2-1 2-2 Motorola
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ac drives ls 600 manual TRANSISTOR MOTOROLA MAC 224 MC68837 AN1051 MOTOROLA TRANSISTOR MOTOROLA MAC 223 MOTOROLA PLL HANDBOOK
Abstract: , Configurable Logic, Programmable Logic Graphics Accelerators I²C Peripherals Image Sensors, LCD and Peripherals Linear/Interfaces Circuits Logic: AHC-AHCT, CMOS, High-Speed CMOS,C²MOS,BiCMOS, LMOS, TTL, Military ALS/FAST/LS/TTL Memories: DRAM, SRAM, EDRAM, NVRAM, EPROM, EEPROM, Flash, FIFO, Modules , Reference Manual (1992) Atmel Configurable Logic (1995) Non Volatile Memory (1996) AVR Microcontroller , /Digital Analog Signal Processing Automotive Circuits BiCMOS Bus Interface Logic Bipolar IC's Bus Schuricht Elektronik
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logic ic databook Motorola Optoelectronics DL118 TOSHIBA IGBT DATA BOOK motorola bipolar transistor databook DL156 thermal printer 8051 microcontroller Z80-Z180 DW-200 DW-180
Abstract: Section 4. Architecture HIGHLIGHTS This section of the manual contains the following major topics , Reference Manual 4.1 Introduction The high performance of the PIC18CXXX devices can be attributed to a , learned. PIC18C Reference Manual Figure 4-2: General Enhanced MCU Block Diagram Data Bus , Latch 8 inc/dec logic 21 21 20 Address Latch Program Memory (up to 2M Bytes) RA0 , logic Decode TABLELATCH 8 ROMLATCH PORTD RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 Microchip Technology
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AD10 AD11 AD12 AD14 AN10 AN11 DS39504A-
Abstract: logic and I/O pins. P - Programming voltage input VPP I TTL Write control for parallel slave port (See , Section 4. Architecture HIGHLIGHTS This section of the manual contains the following major topics , . 4-16 4 2000 Microchip Technology Inc. DS39504A-page 4-1 PIC18C Reference Manual 4.1 , . DS39504A-page 4-3 PIC18C Reference Manual Figure 4-2: General Enhanced MCU Block Diagram Data Bus PORTA , > 4 BSR inc/dec logic RA0 RA1 RA2 RA3 RA4 RA5 RA6 PCU PCH PCL Program Counter 12 FSR0 Microchip Technology
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Abstract: ISL4260E/70E are compatible with all TTL and CMOS logic families when the VL supply pin is connected to , Systems These products directly interface with 5V CMOS and TTL logic families. Nevertheless, with the RS , Compatible with all CMOS and TTL families. Compatible with all TTL and CMOS logic families. 15kV , (including QFN and TSSOP), as well as manual and automatic powerdown and high ESD protection options , /1000kbps Transceivers with manual powerdown, baud rate select (MBAUD pin) features, and flow through Intersil
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ICL3207 ICL3232 ICL3207E ICL3232E AN9863 ICL3222 232E ICL32XX ISL42XX
Abstract: V+ 7 + + C3 0.1uF C4 0.1uF C1 0.1uF C2 0.1uF T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT T1OUT , T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT 12 8 15 R1 5k 16 R1IN R2OUT 10 1 EN R2 5k , 0.1uF 6 T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT 14 7 10 12 R1IN 9 R2OUT 6 , T1IN T2IN 9 10 11 12 T3IN 21 R1OUTB 20 R2OUTB 19 TTL/CMOS LOGIC LEVELS R1OUT T3OUT 4 R1IN , T1 V- C4 0.1uF + T1OUT 9 T1IN 13 T2IN 12 T3IN 20 R2OUTB TTL/CMOS LOGIC LEVELS 19 R1OUT R1 Intersil
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ICL3221 ICL3243 A/TIA-232 ICL324X ICL3223 ISO9000
Abstract: V+ 7 + + C3 0.1uF C4 0.1uF C1 0.1uF C2 0.1uF T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT T1OUT , T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT 12 8 15 R1 5k 16 R1IN R2OUT 10 1 EN R2 5k , 0.1uF 6 T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT 14 7 10 12 R1IN 9 R2OUT 6 , T1IN T2IN 9 10 11 12 T3IN 21 R1OUTB 20 R2OUTB 19 TTL/CMOS LOGIC LEVELS R1OUT T3OUT 4 R1IN , T1 V- C4 0.1uF + T1OUT 9 T1IN 13 T2IN 12 T3IN 20 R2OUTB TTL/CMOS LOGIC LEVELS 19 R1OUT R1 Intersil
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Abstract: + 6 17 C1+ VCC C1C2+ TTL/CMOS LOGIC LEVELS + T1 15 T2 11 T2IN , VCC GND 16 ICL3223 +3.3V C1 0.1uF C2 0.1uF T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT , +3.3V C1 0.1uF C2 0.1uF T1IN T2IN TTL/CMOS LOGIC LEVELS R1OUT + 0.1uF 1 + 3 4 , 12 RS-232 LEVELS 11 T3IN T3OUT 21 R1OUTB 20 R2OUTB 19 TTL/CMOS LOGIC LEVELS , T2OUT T3 12 RS-232 LEVELS 11 T3IN T3OUT 20 R2OUTB TTL/CMOS LOGIC LEVELS 19 Intersil
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MAX3221
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