LE79610 LE71HE0861/862 VDD250 LE71HE0795 AVDD12 LTC1844-3 LTC1844-2 I/O1-I/O15 - Datasheet Archive

 

Evaluation Board User's Guide for the Le79610 Packet Codec Rev. A, Ver. 2 October 3, 2007 Document Number: 081197 A Voice

 

Le71HE0861/Le71HE0862 Evaluation Board User's Guide for the Le79610 Packet Codec Rev. A, Ver. 2 October 3, 2007 Document Number: 081197 A Voice Solution TM For more information about all Zarlink products visit our Web Site at: www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo are trademarks, and Legerity, the Legerity logo and combinations thereof are registered trademarks of Zarlink Semiconductor Inc. All other trademarks and registered trademarks are the property of their respective owners. © 2007 Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE TABLE OF CONTENTS CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Le79610 Packet Codec and VoiceChipTM Family 790 Series . . . . . . . . . . . . . . . . . . . . . . . 1.3 Boards Covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 2 CHAPTER 2 VOICECHIPTM FAMILY 790 SERIES OVERALL BOARD DESCRIPTIONS . . . . . . . . . . . . . . . . 2.1 Le71HE0861/862 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Adapter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Le71HE0795 790 Series SLIC Device Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 CHAPTER 3 DETAILED BOARD DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Le79610 Packet Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.1 Device Installation and Chip Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.2 Battery Sense Inputs on the Le71HE0861/862 Evaluation Board. . . . . . . . . . . . . . 5 3.1.3 Board Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.4 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Le71HE0795 790 Series SLIC Device Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2.1 Le71HE0795 Evaluation Board Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.2 VHL Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3.1 External Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3.2 The +3.3 V Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.3 The CREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.1 Device Interface to Software platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.2 I/O Control Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.3 Le71HE0861/862 to Le71HE0795 Evaluation Board Interface . . . . . . . . . . . . . . . 12 CHAPTER 4 SOFTWARE SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 WinSLAC2TM Software Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 VoicePathTM Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHAPTER 5 BOARD LAYOUT FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Board Layout Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CHAPTER 6 HARDWARE/SOFTWARE REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Evaluation Board System Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 22 CHAPTER 7 SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Le71HE0861/862 Evaluation Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Adapter Board Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Le71HE0795 Evaluation Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 34 36 i Zarlink Semiconductor Inc. Document ID# 081197 Date: Rev: A Version: Distribution: Public Document 13 13 13 13 Oct 3, 2007 2 Le71HE0861/862 ii Zarlink Semiconductor Inc. Eval Board User Guide CHAPTER 1 1.1 INTRODUCTION INTRODUCTION Legerity provides evaluation boards for the Le796101LC and Le796102LC packet codec/filters of Legerity's VoiceChipTM family 790 series. When combined with Legerity's Le71HE0795 790 series evaluation board, software platform, and computer interface board with Legerity's control software, these boards provide a complete evaluation environment for the Le79610 packet codec/filters. This user's guide describes the boards used to evaluate the Le79610 device. Evaluation Board System Setup, on page 22 details installation, hardware set up, computer requirements, lab equipment needed, steps to set up power that can be run to verify operation of the entire Le79610 packet codec evaluation board and adapter board with the 790 series Le71HE0795 evaluation board. Both the Le71HE0795 SLIC device evaluation system and Le71HP0310 adapter board are covered in this section. 1.2 LE79610 LE79610 PACKET CODEC AND VOICECHIPTM FAMILY 790 SERIES Legerity's VoiceChipTM family 790 series includes a high voltage SLIC device and fully featured twochannel Le79610 packet codec/filters. These products are designed to support a variety of endapplications, with the common goal of reducing cost by implementing system functions in line card silicon. These enhanced voice functions include: DC feed, ringing generation, line test, self-test, foreign voltage measurement, adaptive hybrid balance, equalization, metering, DTMF generation, packet voice operations, such as echo cancellation, voice activity detection, and comfort noise generation capabilities. This chip set provides a complete software-configurable solution to the BORSCHT functions, providing flexible subscriber line DC feed characteristics, loop supervisory functions and metering, and integrates significant line and circuit test capabilities. These devices reduce cost per line by integrating many functions that would otherwise require external hardware, such as ringing generation, line test, self-test, foreign voltage measurement, metering, DTMF, and call progress tone generation. All transmission parameters, DC feed variables, and signaling parameters are fully programmable by an external microprocessor over the GPI, or SPI, and PCM highway. The Le71HE0861/862 evaluation boards have four layers. The digital interface signals reside on layers 1 and 4; these are separated by layers 2 and 3 with internal power and the ground layers. The analog signals to the 790 series SLIC devices reside on the top and bottom layers (1 and 4). The devices that make up the complete Le79610 evaluation system are listed in Table 1­1. 1 Zarlink Semiconductor Inc. Le71HE0861/862 Eval Board User Guide Table 1­1 Device and Board Identification Device Device Part Number Package Evaluation Board OPN Le79610 device Le796101LC 80-pin eLQFP package Le71HE0861 Le79610 device Le796102LC 100-pin eLQFP package Le71HE0862 Adapter Board N/A N/A Le79HP0310 Adapter Board N/A N/A Le79HP0311 790 series SLIC device Le79231JC 32-pin PLCC 70 V1 Le79HE0795 790 series SLIC device Le79R241JC 32-pin PLCC 100 V1 Le79HE0795 Note: 1. 1.3 Nominal operating range BOARDS COVERED There are two board types to support the Le79610 packet codec/filter-one each for the 80-pin eLQFP and the 100-pin eLQFP devices, and one for the 790 series SLIC devices. The boards available for each package and pin-out option of the devices are shown in Table 1­1. Each of the Le71HE0861/862 evaluation boards supports one device only. The 790 series SLIC device evaluation boards are equipped with two devices for two-channel capability. The minimum platform for a complete Le79610 packet codec/filter evaluation system consists of one Le71HE0861 evaluation board plus one Le71HE0795 790 series SLIC device board. 2 Zarlink Semiconductor Inc. CHAPTER 2 2.1 VOICECHIPTM FAMILY 790 SERIES OVERALL BOARD DESCRIPTIONS LE71HE0861/862 LE71HE0861/862 EVALUATION BOARD The Le71HE0861/862 evaluation board has a 64-pin connector to interface to the dual-channel 790 series SLIC device evaluation board. The 64-pin connector J1 brings all power, ground, voice-band, and interface signals to the 790 series SLIC PCB. The first nine pins of rows A and C on the connectors carry the various voltages with additional ground pins to the 790 series SLIC device evaluation board. The connector contains the odd and the even channels interface signals. A 96pin connector connects the Le71HE0861/862 evaluation board to the adapter board interface. One 10-pin connector (PW1) supplies power for the Le71HE0861/862 evaluation board and 790 series SLIC device evaluation board. Additionally, jumpers JP1, JP2, and JP4 are mounted on the board to supply separate power to VDD250 VDD250 (+2.5v), AVDD1 and DVDD1 (+3.3V) to the device from voltage regulators VR1 and VR2. 2.2 ADAPTER BOARD The Le71HP0310 adapter board has two 96-pin connectors (P1 and J1) that interface to the Le71HE0861/862 evaluation board and software platform system board. The 96-pin connector (J1) brings +3.3 V, +5 V, and +12 V power, ground, and digital interface signals to the Le71HE0861 Le79610 Packet Codec PCB. The 96-pin connector (P1) connects the adapter board to the software platform board for programming and control of the Le71HE0861/862 evaluation board via the Legerity VoicePathTM Script software program. One 5-pin Din connector (PWR1) supplies power for the Le71HE0861/862 evaluation board. The Le71HP0311 adapter board has two 96-pin connectors (P1 and J1) that interface to the New Generation Host with the emulator board. 2.3 LE71HE0795 LE71HE0795 790 SERIES SLIC DEVICE BOARD The Le71HE0795 790 series SLIC device evaluation board is designed to provide an evaluation platform for the Le79R231 and Le79R241 SLIC devices. The board has two channels (labeled Upper Channel and Lower Channel), on-board VHL circuitry, and surge-protection circuitry designed to work with negative only battery supplies. One 64-pin connector mates to the Le71HE0861/862 evaluation board. All power, ground, voiceband, and interface signals needed to operate the 790 series SLIC device pass through this connector. 3 Zarlink Semiconductor Inc. Le71HE0861/862 4 Zarlink Semiconductor Inc. Eval Board User Guide CHAPTER 3 3.1 DETAILED BOARD DESCRIPTIONS LE79610 LE79610 PACKET CODEC The Le71HE0861/862 evaluation board is designed to provide an evaluation platform for the Le79610 packet codec/filters. The Le79610 device's pin count determines which board is used. Refer to the table below. Table 3­1 Device and Board Identification Device Pin Count/Type Evaluation Board Revision Le796101LC Le79HE0861 A Le796102LC 100-pin eLQFP Le79HE0862 A Le79610 3.1.1 80-pin eLQFP 80/100-pin eLQFP Le71HP0310 A Device Installation and Chip Orientation Each Le71HE0861/862 evaluation board supports a single device. The orientation of the device depends on the evaluation board. The Le796101LC 80-pin eLQFP device is mounted in a type 80 pin socket. The pin 1 indicator of the Le79610 packet codec device goes to the upper right-hand corner. The silk-screen on the board also indicates where pin 1 should go. The Le796101LC 80-pin eLQFP device is mounted in an open-top, open top ZIF Well-CTI single beam contact socket and is numbered around the base of the chip to indicate proper orientation of the part. When placed in the socket, the pin 1 indicator faces the J1 connector and the corner of the socket has a beveled edge. Each of the corner pins is located by counting counter clockwise from pin 1 to probe around the device. 3.1.2 Battery Sense Inputs on the Le71HE0861/862 Evaluation Board Two of the battery sense inputs on the Le71HE0861/862 evaluation board, SHB and SLB, are serially connected to the VBH and VBL supplies via resistors RSHB and RSLB (refer to the schematic). The battery sense input signal for SPB is connected via the series resistor RSPB. 3.1.3 Board Jumper Options Each of the Le71HE0861/862 evaluation boards have four jumper blocks on the PCB; these are labeled JP1, JP2, JP3, and JP4. Their operation is described in the following table: Table 3­2 Board Jumper Settings Jumper Shorting Plugs Settings Description JP2 Selects the variable VCC supplied by PWR1 (+3.3 V) for AVDD12 AVDD12 device input. 2-3 JP1 1-2* Selects the fixed +3.3 V output from VR2 (LTC1844-3 LTC1844-3.3) 1-2 Selects the fixed +2.5 V output from VR1 (LTC1844-2 LTC1844-2.5) 2-3* Internal Device battery is supplied +2.5 V DC to device inputs 5 Zarlink Semiconductor Inc. Le71HE0861/862 Eval Board User Guide Table 3­2 Board Jumper Settings 1-2 2-3* Selects the variable SLIC-VCC +5 V supplied by PWR1 input 1-2* Selects the variable VCC supplied by PWR1 (+3.3 V) for PL_VDD and DVDD1-4 device inputs. 2-3 JP3 Select the fixed +3.3 V output from VR2 (LTC1844-3 LTC1844-3.3)SLIC Power Selects the fixed +3.3 V output from VR2 (LTC1844-3 LTC1844-3.3) for PL_VDD and DVDD1-4 device inputs. JP4 1-2 P5 3-4 5-6 Provides pull downs for the CONF[2:0] HBI configuration. Remove shorting straps to provide 10k pull up to +3.3v * Recommended 3.1.4 Test Points With the exception of the power voltages, SHB, SLB, SPB, and N/C (no connect) pins, all signals have test points. In addition, there are eight ground clip points: three DGND, one BGND and four AGND. I/O1-I/O15 I/O1-I/O15 are found on the 100-pin eLQFP board only. All I/Os on both boards have LED displays to show the activity of there function when at Active Low. All test points are detailed in Table 3-3 below. Table 3­3 Device Test Points Channel 1 Channel 2 LED Display (active low) Common ANALYZER Common LD1 LD2 I/O1 PD0 XSC1 VOUT1 VOUT2 I/O2 PD1 +3.3 V VIN1 VIN2 I/O3 PD2 P1 VHL1 VHL2 I/O4 PD3 P2 VSAB1 VSAB2 I/O5 PD4 P3 VILG1 VILG2 I/O6 PD5 CREF VIMT1 VIMT2 I/O7 PD6 IREF VLB1 VLB2 I/O8 PD7 VREF XSB1 XSB2 I/O9 PD8 VDD250 VDD250_1 GS11 GS12 I/O10 I/O10 PD9 PCLK1 GS21 GS22 I/O11 I/O11 PD10 FS1 I/O12 I/O12 PD11 INT I/O13 I/O13 PD12 CONF0 I/O14 I/O14 PD13 CONF1 I/O15 I/O15 PD14 CONF2 PD15 The Le79610 packet codec devices are accessed through the GPI or SPI. The VoiceChipTM Family 790 Series device can selectively be controlled in a standard PCM mode. The 100-pin eLQFP part 6 Zarlink Semiconductor Inc. Le71HE0861/862 Eval Board User Guide has extra digital signals (PD8-PD15 PD8-PD15, I/O6-I/O15 I/O6-I/O15) for additional software control functionality, as listed in Table 3­3. Twelve signals are required for the Le71HE0861/862 evaluation board, as shown in Table 3­4. Table 3­4 GPI-SPI Analyzer Test Points Common Common Common Common Common PCLK PWAIT PADDR INT PCS PRD PWR TSCA FS DX 3.2 RST DR LE71HE0795 LE71HE0795 790 SERIES SLIC DEVICE EVALUATION BOARD The Le71HE0795 evaluation board is a dual-channel PCB. All signals except Tip and Ring (power, ground, interface, and control) pass through the PCB via the 64-pin connector on the Le71HE0861/ 862 evaluation board. When viewed with the 64-pin connector to the left, the upper-half of the board (labeled Upper Channel) is channel two, and the lower half of the board (labeled Lower Channel) forms the channel one. The 790 series SLIC device board plugs into either the odd channel connector into the even/odd channel connector (J1) on the Le71HE0861/862 evaluation board. The test points are staggered from one to the other to allow the user to clip to any test point without shorting to another test point. The following signals have test points available on the Le71HE0795 evaluation board: Table 3­5 Signal Test Points Available on the Le71HE0795 Evaluation Board Upper Channel Lower Channel Common XSB (U) XSB (L) CREF VILB (U) VLB (L) VREF VIMT (U) VIMT (L) P1 VILG (U) VILG (L) P2 VSAB (U) VSAB (L) P3 VHL (U) VHL (L) AGND(x3) VIN (U) VIN (L) BDND(x2) LD (U) LD (L) HPA HPA HPB HPB BD BD AD AD SA SA SB SB Note: The first column shows the Upper Channel (U), the second column shows the Lower Channel (L), and the third column shows the signals that are common for both channels. The Le79610 Packet Codec channel 1 is associated with the Lower Channel (L) and the Le79610 Packet Codec channel 2 is associated with the Upper Channel (U) of the Le71HE0795 790 series SLIC evaluation board. 7 Zarlink Semiconductor Inc. Le71HE0861/862 Eval Board User Guide A standard RJ-11 RJ-11 phone jack provides tip/ring connection to the evaluation board from a standard station set. Two banana jacks, labeled TIP and RING, and two test points, labeled TIP and RING, allow the board to be connected to test equipment for signal measurement. A 50- thick film hybrid resistor is used for current limiting isolation between tip/ring and the A/B leads of the 790 series SLIC device. These resistors have a thermal fuse mounted on the ceramic substrate that opens in the event of high temperature, such as from excessive foreign voltage faults to tip or ring. An over-voltage protector circuit is connected between the AD and BD device pins to limit the voltage at the device in the event of excessive foreign voltage or surge application. Two jumpers in the protection circuit, JP1 and JP2 for the Lower Channel, and JP3 and JP4 for the Upper Channel, select the level at which the protection circuitry will activate. Placing a wire jumper between pins 1 and 2 will connect a diode from the AD lead to BGND and from the BD lead to BGND of the 790 series SLIC device. The user must install this connection when evaluating the Le79R231/ R241 device. Table 3­6 Device Settings Device JP2 & JP3 Le79231 Short pin 1 to pin 2 Short pin 1 to pin 2 Le79241 3.2.1 JP1 & JP4 Short pin 1 to pin 2 Short pin 1 to pin 2 Le71HE0795 Evaluation Board Jumper Options The Le71HE0795 790 series SLIC device evaluation board has three two-position jumpers and one three-position jumper for modes of operation for R1, R2, R3, and RYE. Jumpers J1 and J2 allow the user to remove the on-board test loads from the 790 series SLIC device pins. Jumper J3 allows the relay (K1) to be removed from external control. The table below describes the jumper positions. Table 3­7 Le71HE0795 Evaluation Board Jumper J1-J3 Settings Jumper Open JP2 & JP3 Shorted default J1 R2 is disconnected from RTSTM R2 routed to RTSTM J2 R3 is disconnected from RTSTL R3 routed to RTSTL J3 R1 has no control of relay K1 R1 controls relay K1(U/L) The J1 jumper for R2 is factory-set to connect the metallic test load circuitry, composed of D1 and RTSTM, to the R2 pin of the 790 series SLIC device. The metallic loop applied is 4.0 k without TL2 and TY1 shorting plugs. Either TL2 or TY1 will short one 2.0 k resistor to allow for a 2.0 k loop. The J2 jumper for R3 is factory-set to connect the longitudinal RTSTL 4.0 k resistor to the R3 pin of the 790 series SLIC device. The longitudinal RTSTL loop applied is 4.0 k without TL3 and TY1 shorting plugs. Either TL3 or TY1 will short one 2.0k ohm resistor to allow for a 2.0 k RTSTL value. The J3 jumper for R1 is factory-set to have the 790 series SLIC device control the operation of the ringing relay (K1). The relay also acts as a cut over/testing relay for internal ringing applications. The fourth jumper, J4, is a three-position jumper. Moving the jumper between pins allows the user to set RYE at BGND potential or to become active when BD is driven into a negative state. A diode is in-line with the BD-to-RYE connection to prevent damage to the chip when BD is driven into a reverse polarity (i.e., positive) state or when VBP is applied to the 790 series SLIC device. Table 3­8 Le71HE0795 Evaluation Board Jumper J4 Setting Pins 1-2 Pins 2-3 default position RYE set to BGND potential RYE controlled by BD state. 8 Zarlink Semiconductor Inc. Le71HE0861/862 Eval Board User Guide The following table shows test load configurations available on the Le71HE0795 evaluation board. Table 3­9 Test Load Configurations Relay Drivers vs. Configuration Le71HE0795 RD1 RD2 Ring Relay for external ringing RD3 4k ohm on BD to ground with J2 and J4 2-3 installed. Provides a longitudinal test 2k ohm on AD to Ground with J1 and J4 1-2 installed. Or 4k ohm loop on AD to BD with J1 and J4 2-3 installed. Provides a metallic loop test Comments The selection for the jumpers TY1, TL2 and TL3 can be used to reduce the resistance from 4k ohm in RD2 and RD3 configurations All interface components between the Le71HE0861/862 and Le71HE0795 evaluation boards are surface mounted with the exception of RRX, RTX, and RHL. RRX and RTX form the default impedance matching circuit in the voice path between the Le79610 packet codec device and 790 series SLIC devices. These components are through hole to help facilitate easy changing, if required, by the user. The function of the RHL resistor is discussed in the next section. On the revision F evaluation board, three additional sets of jumpers and an additional resistor have been added. The purpose of these jumpers is shown in Table 3­12. 3.2.2 VHL Filter Circuitry The VHL pin, as described in the data sheet, is a high-level loop control voltage used to control DC feed, internal ringing, metering, and polarity reversal for the 790 series SLIC device. Each channel of the 790 series SLIC device evaluation board has the VHL filter circuitry incorporated on it. The VHL circuit is a notch filter designed to reduce any voice band noise on the VHL line. On the revision F evaluation board, the circuitry is mounted on the reverse side of the board. Figure 3­1 VHL Filter Schematic RHL VHL RSN 34.0K X X RHL3 RHL2 8.06K 8.06K CHL1 RHL1 4.32K 3.3nF CHL2 VREF 330nF 3.3 POWER CONNECTIONS 3.3.1 External Power Connections One 10-pin connector, PW1, provides power to the evaluation system (one Le79610 codec/filter and two 790 series SLIC devices in one PCB). The OPN number for the cable is Le71HW0013. The pin-out and a short description are provided in the following table. 9 Zarlink Semiconductor Inc. Le71HE0861/862 Eval Board User Guide Table 3­10 Le71HE0861/862 Evaluation Board 10-Pin Connector Settings Pin #/ Color Signal Name Description 1 Digital ground (used for Le79610 packet codec device only) 2 +3.3 V Optional variable VCC supply for the Le79610 packet codec device. 3 AUX-VCC VCC supply for +2.5 V and +3.3 V voltage regulators 4 SLIC_VCC VCC supply for the 790 series SLIC devices only 5 AGND Analog ground 6 RING SOURCE Ringing signal input for use with Le79231 790 series SLIC 7 BGND Battery ground 8 VBP VBAT positive voltage 9 VBL VBAT low voltage 10 3.3.2 DGND VBH VBAT high voltage The +3.3 V Supply There are two methods of supplying voltage to the Le71HE0861/862 evaluation board. The first is via the fixed 3.3-V voltage regulator VR2 (LTC1844-3 LTC1844-3.3). The regulator is capable of supplying 300 mA of current over a wide load range. The voltage regulator is powered by the AUX_VCC supply. As stated in the preceding table, the AUX_VCC input supplies power for the voltage regulators, and is the source for the CREF signal to the 790 series SLIC device(s) using VR2; therefore, any current measurements reflect the total current used by everything. The second method is with the variable +3.3 V input from connector PW1, which supplies the AVDD, PL_VDD, and DVDD inputs of the Le71HE0861/862 evaluation board. The choice is made with jumpers JP1 and JP4. Shorting pin 1 to 2 on JP1 and JP4 allows the user to monitor the current used by the Le79610 Packet Codec device without any other device affecting the reading. The +3.3 V input from the power cable (PW1) supplies only the AVDD, PL_VDD, and DVDD inputs of the Le71HE0861/862 evaluation board. The method allows the digital side of the device to be isolated from the analog side by configuring shorting plug on JP4 pin 2 to pin 3. Also, the method allows the analog side of the device to be isolated from the digital side by configuring the shorting plug on JP1 pin 2 to pin 3. The following table details those positions on the jumpers that select the desired voltage configuration. Table 3­11 Le71HE0861/862 Evaluation Board Voltage Regulation Jumper Positions I Jumper Description (Recommended shorting plugs) JP1 pins 1-2 Selects the off-board variable +3.3 V input from the PW1 connector to AVDD and CREF JP2 pins 2-3 Selects the fixed +3.3 V input from the voltage regulator VR2 to AVDD and CREF JP4 pins 1-2 Selects the off-board variable +3.3 V input from PW1 to PLL_VDD and DVDD JP4 pins 2-3 Selects the fixed +3.3 V input from the voltage regulator VR2 to PLL_VDD and DVDD The default factory setting is with JP1 and JP4 shunted to pins 1-2. 10 Zarlink Semiconductor Inc. Le71HE0861/862 3.3.3 Eval Board User Guide The CREF Input The CREF input is used by the Le71HE0795 evaluation board reference. It is the digital high logic supply rail, which is used by the Le71HE0795 evaluation board when communicating with the Le79610 packet codec. This voltage level is generated by VR2 or PW1 +3.3 V input and must be present at all times. 3.4 SIGNAL CONNECTIONS 3.4.1 Device Interface to Software platform The interface signals required by the Le71HE0861/862 evaluation board come through a 96-pin connector that mates to the adapter board. All interface signals are 3.3-V tolerant. The signals in this connector are identified in the following table. Table 3­12 Le71HE0861/862 Evaluation Board 96-Pin Connector Interface Signals 80-Pin eLQFP Signal 100-Pin eLQFP Le79610 Device Le79610 Device PWAIT Analyzer Header J1 SICE Interface Header x INT x x x PADDR x x x PCLK x x x FS x x x PCS x DR x x x DX x x x TSCA x x x PRD x x x PWR x x x RST x x x CONF0-2 x x x I/O1-5 x x x PD0-7 x x PD0-15 PD0-15 x x ID x x IMS x x x ICK 3.4.2 x x x x I/O Control Ports The 80-pin and 100-pin Le71HE0861/862 evaluation boards have 5 or 15 control ports designated as I/O1 through I/O15 I/O15 respectively. These are programmable, general purpose, TTL-compatible, logic input/output pin connections. When configured as an input, I/Oi transitions can cause interrupts to the DSP. I/O15-I/O6 I/O15-I/O6 are not available in GPI mode on the 80-pin eLQFP. All the I/Oi data pins can be written or read individually or as a group. The pins are brought out to LED devices via a 6x2 board selector on the 80-pin for selector P4 and 100-pin for selectors P4, P5, and P6, which can be disconnected individually by removing the shorting plugs. 11 Zarlink Semiconductor Inc. Le71HE0861/862 3.4.3 Eval Board User Guide Le71HE0861/862 to Le71HE0795 Evaluation Board Interface A 64-pin connector, J1, is used to connect the Le71HE0861/862 and Le71HE0795 evaluation boards. This connector carries all power, ground, and interface signals required between the 790 series SLIC and Le79610 packet codec/filter devices. The pin assignments of this connector are shown in the table below. Table 3­13 Le71HE0861/862 to Le71HE095 Device Interface Pin Assignments Pin Signal Pin Signal Pin Signal A1 VBH A28 AGND C23 VREF A2 VBL A29 VHL 1 C24 XSB1 A3 VBP A30 AGND C25 AGND A4 BGND A31 VOUT1 C26 VIMT1 A5 BGND A32 AGND C27 AGND A6 RING SOURCE C1 VBH C28 VSAB1 A7 AGND C2 VBL C29 AGND A8 SLIC_VCC C3 VBP C30 VIN1 A9 AUX_VCC C4 BGND C31 AGND A10 AGND C5 BGND C32 LD1 A11 VLB2 C6 (N/C) A12 AGND C7 AGND A13 VILG 2 C8 SLIC_VCC A14 AGND C9 AGND A15 VHL2 C10 XSB2 A16 AGND C11 AGND A17 VOUT2 C12 VIMT2 A18 AGND C13 AGND A19 XSC C14 VSAB2 A20 AGND C15 AGND A21 P1 C16 VIN2 A22 P3 C17 AGND A23 VREF C18 LD 2 A24 AGND C19 CREF A25 VLB 1 C20 AGND A26 AGND C21 P2 A27 VILG 1 C22 AGND 12 Zarlink Semiconductor Inc. CHAPTER 4 SOFTWARE SUPPORT 4.1 OVERVIEW 4.1.1 WinSLAC2TM Software Program Legerity's WinSLAC2TM software program is a software tool that aids in the design and development of telephone line cards and related voice-band applications. It enables the user to design and generate coefficients for the programmable filters of the Le79610 packet/codec VoiceChipTM family and provides the user with predicted performance of system parameters. The program models the Le79610 packet/codec device, the line conditions, and associated line card 790 series SLIC device components. It calculates an optimum set of filter coefficients based on the overall system design conditions and generates the corresponding system responses for each of the programmable functions. It also calculates and plots predicted system responses for Two-Wire Return Loss (2WRL), Four-Wire Return Loss (4WRL), and Receive and Transmit frequency responses. The WinSLAC2 program uses gain-phase parameters (G-parameters) to describe the SLIC device circuitry for input to the program. The program, through Spice simulation of the 790 series SLIC device circuitry, typically produces the G-parameter arrays. They may also be entered manually, using data obtained by lab measurements on a real 790 series SLIC device circuit. In order to generate the G-parameters, the WinSLAC2 software incorporates and uses an evaluation version of Cadence Corporation's PSpice and Schematics (formerly known as MocroSim PSpice) programs to simulate the analog circuitry of the SLIC device. Although the evaluation versions of these programs are sufficient for most designs, their limitations may impose certain restrictions on more complex designs. In such cases, the full production version of these programs may be purchased directly from Cadence Corporation and easily integrated into the WinSLAC2TM software operation. 4.1.2 VoicePathTM Script The Windows operating system-based VoicePath Script (VP-Script) application is a product demonstration and evaluation tool for Legerity's currently manufactured devices, as well as for any future devices. VP-Script's Graphical User Interface (GUI) provides interactive control for all of the programmable features of each device. The application also controls the external host platforms, which generates the digital signals, required to operate the devices. By combining the control of the devices and the platforms into a scripting application, Legerity has provided a way of quickly creating and running tests to aid in the evaluation of its devices. 13 Zarlink Semiconductor Inc. Le71HE0861/862 14 Zarlink Semiconductor Inc. Eval Board User Guide CHAPTER 5 5.1 BOARD LAYOUT FIGURES BOARD LAYOUT FIGURES 15 Zarlink Semiconductor Inc. Le71HE0861/862 Figure 5­1 Eval Board User Guide Le79HE0861 LE796101LC LE796101LC 80-Pin eLQFP Device Evaluation Board 16 Zarlink Semiconductor Inc. Le71HE0861/862 Figure 5­2 Eval Board User Guide Le79HE0862 Le79610 100-Pin eLQFP Device Evaluation Board 17 Zarlink Semiconductor Inc. Le71HE0861/862 Figure 5­3 Le79HP0310 Adapter Board 18 Zarlink Semiconductor Inc. Eval Board User Guide Le71HE0861/862 Figure 5­4 Le79HP0311 Adapter Board 19 Zarlink Semiconductor Inc. Eval Board User Guide Le71HE0861/862 Figure 5­5 Eval Board User Guide Le79790 series SLICBRD Two-Channel Evaluation Board (Revision F 20 Zarlink Semiconductor Inc. CHAPTER 6 6.1 HARDWARE/SOFTWARE REQUIREMENTS OVERVIEW This section details the hardware and software requirements for the Le71HE0861/862 evaluation board. The computer on which the software is installed must meet the following minimum requirements: · An IBM®-PC or compatible computer · Fifth generation x86 processor · 16 MB RAM and 16 MB hard disk space · Windows 95, Windows 98, Windows 2000, or Windows NT® Workstation 4.0 operating system · Available COM port · Serial cable and any required adapters to connect the COM port of the PC to the DB-9 connector of the Software Platform board In addition to that listed above, the following lab equipment will be needed: · Switching AC adapter power supply (+9 V DC) to power the Software Platform board · Switching AC adapter power supply (+12 V DC) Le71HW0001 to power the Adapter board The Le71HE0861/862 evaluation board requires the following: · +3.3 V DC (fixed) · 3.3 V DC (variable); not needed if supplying power to the Packet Codec device via the voltage regulator, VR2. · Variable 0-(-100 V) DC supply for VBH · Variable 0-(-50 V) DC supply for VBL (note: VBL can be run from the same supply as VBH) · Variable 0-(+100 V) DC supply for VBP (only needed for the Le79251 device) Make all ground (DGND, AGND and BGND) connections common at the power supplies. 6.2 SOFTWARE INSTALLATION This section will assist the user in installing the Legerity WinSLAC2 software program. Perform the following steps to install the software from the CD-ROM: 1. Insert the CD into the CD-ROM drive. 2. Double-click on the CD-ROM icon to open it. 3. Open the Control Boards and Software folder. 4. Open the WinSLAC2 folder. 5. Open the Software folder. 6. Double-click on the SETUP.EXE icon. 7. Follow the steps for the WinSLAC software installation. 8. Once the installation is complete, close the folders; 9. Reboot the computer 10. Software Platform uses a 9 Pin Null Modem Serial Cable into J2 9 Pin connector 11. Hyperterm or Teraterm must be used for a setup of 115 kbps, 8 bits, No Parity, 1 Stop bit. 21 Zarlink Semiconductor Inc. Le71HE0861/862 6.3 Eval Board User Guide EVALUATION BOARD SYSTEM SETUP Once the WinSLAC2 software has been installed, you will need to connect the evaluation system to the computer. This is a four step process, detailed below. First, set up the software platform by doing the following: 1. Connect the null modem serial cable between the Software Platform DB-9 connector (J2), located in the top left-hand corner, and the COM port of the PC. 2. Connect the Software Platform Switching Power Supply plug into the J3 +9 V plug of the board for the +9 V supply input. 3. Plug the power supply into the AC wall plug. You will see several LED's along the board light up. This completes Software Platform board setup. Unplug the power supply. Then, set up the Le71HE0861/862 evaluation board by doing the following: 1. Connect the Packet Codec device evaluation board to the adapter board. The Packet Codec device board will mate to the J1 connector (the 96-pin connector along the right-hand side of the adapter board Le71HP0310). 2. Connect the AC Power Supply/Cable to the Adapter board input PWR1. The AC Power supply plugs into the AC wall plug to supply the +12 V to the adapter. Switch the SW4 to the left to enable the +12 V and +5 V LED green lights. The 3.3v output is also enabled and can be measured at the appropriate test point. Switch the SW4 to the right and turn off the power supply. 3. Connect the 10-pin power connector (IAV Cable) to PW1 (located at the top middle of the Quad ISLAC device board). 4. Use the following power supplies for the recommended power at VBL, VBH, VBP, +3.3 V, and +5 V power input to the above PW1 connector. Table 6­1 Le71HE0861/862 Evaluation Board Power Supply Selection Table Mfg. Type Qty. Type Description HP3631A HP3631A 1 DC power supply Equivalent HP6236B HP6236B or Agilent 3631A or HP6237B HP6237B with 3 DC outputs. HP3488A HP3488A 1 DC Power supply Equivalent HP3610 HP3610 or Agilent 3612A with single DC ouput. 5. Connect the cables to their respective power supplies. Each cable is labeled but not for identification purposes. See the following table for cable identification and for correct installation. Do not use the VBP violet wire and Ring Source blue wire. Table 6­2 Power Supply Cable Connections Pin # Supply Connection 1 DGND Common 2 Connect to the 3.3-V variable supply (not necessary if using the on-board regulator VR2). 3 Connect to the fixed +5-V supply. 4 Connect to the fixed +5-V supply (a separate supply or the same as pin 3). 5 AGND common. 6 Connect to the off-board ringing source. If there is no off-board source 7 BGND common. 8 Connect VBP to the positive high-voltage battery supply. Refer to Table 6­3 if evaluating the Le79R231 or Le79R241 devices. 9 Connect VBL to the low battery supply. 10 Connect VBH to the most-negative battery supply. 22 Zarlink Semiconductor Inc. Le71HE0861/862 Eval Board User Guide The following table shows typical voltage levels for the Le79610 packet codec device and the different 790 series SLIC devices (Le79R231, and Le79R241). Table 6­3 Voltage Levels for the Le79610 Codec and 790 Series SLIC Devices Signal Color Le79610 + Le79R231 Le79610 + Le79R241 DGND Black DGND1 DGND1 3.3-V Red Optional2 Optional2 AUX_VCC Orange +5 V +5 V SLIC_VCC Yellow +5 V +5 V AGND Brown AGND 1 AGND 1 RING SOURCE Blue VBH or external source VBH or N/C BGND Green BGND1 BGND1 VBP Violet BGND BGND VBL Gray -30 V3 -30 V VBH White -50 V -90 V Notes: 1. Tie all grounds (AGND/BGND/DGND) together at the power supplies. 2. If the board is jumpered to accept power from VR2, this connection can be left open. 3. Optional. VBL can be connected to VBH. Next, set up the Le71HE0795 evaluation board by doing the following: 1. Solder in a wire jumper from pin 1-2 of JP1 and JP2. This will ensure the board has proper protection against foreign voltages on the A and B leads. 2. Connect the Le71HE0795 evaluation boards to J1 of the PACKET CODEC device evaluation board. 3. Connect a standard station set to the RJ11 of each channel, or connect test equipment to the TIP/RING banana jacks or to the TIP/RING test/clip points. When completed, the setup should be similar to that shown in Figure 6­1. 23 Zarlink Semiconductor Inc. Software Platform +9V & GND PWR1 Adapter Board P1 Le71HP0310 J1 J1 Le79610 Evaluation P7 P7 PW1 Le71HW0001 AC Power Supply 12 DC ISLIC Le71HE0795 Le71HW0013 IAV/IA-DOV Power Cable Eval Board User Guide 24 Zarlink Semiconductor Inc. 6. The evaluation board system has been powered up. 5. All ICs are socketed properly on the evaluation boards. 4. All power and ground connections have been made to the Le71HE0861/862 device evaluation board. 3. The Software Platform board has been connected to an available COM port on the PC. 2. The WinSLAC2 software has been installed on the hard drive. 1. The Software Platform software has been installed on the PC Teraterm or Hyperterm is configured for 115Kbps, 8,N,1 P2 Power Supplies After following the above instructions, the following will have been completed: The power-on sequence is: VBH, VBL, VCC Serial Cable AC Power Supply 9V DC AC Power Supply 9V DC Typical Packet Codec Device Setup 9 Pin Null Modem Figure 6­1 Le71HE0861/862 Le71HE0861/862 Eval Board User Guide Table 6­4 Le79610 Packet Codec Evaluation Kit (Order # Le71HK0793) Board Number Quantity Board Name Le71HP0310 1 Adapter Board Le71HW0013 1 Adapter Board +12 V Le71HE0861 1 Evaluation Board Le796101LC Le71HW0001 1 IAV/DOV Power cable Le71HE0795 1 Comments 790 series SLIC evaluation board Power Supply Brick Table 6­5 Configuration Options for the Le71HE0861 Evaluation Board Board Number Jumper Description 1-2 PCS_N/SS_N Normal Le71HP0310 J2 Le71HP0310 J3 Le71HP0310 J4 Le71HP0310 J5 Le71HP0310 J6 Le71HP0310 J7 Le71HP0310 J8 ACIF HEADER 14x2 cable interface Le71HE0861 P4 Shorting Plugs allows LED display for I/O Normal Le71HE0861 P5 Shorting Plugs allows pull down on CONF0-2 Normal Le71HE0861 JP5 Le71HE0861 JP6 Le71HE0861 JP7 Le71HE0861 J2 2-3 PCS_N/SS_N Routes to J8 ACIF Interface 1-2 PRD_N/SI Normal 2-3 PRD_N/SI Routes to J8 ACIF Interface 1-2 PWR_N/SCK Normal 2-3 PWR_N/SCK Routes to J8 ACIF Interface 1-2 PD7/SO Normal 2-3 PD7/SO Routes to J8 ACIF Interface 1-2 FS Normal 2-3 FS Routes to J8 ACIF Interface 1-2 PCLK Normal 2-3 PCLK Routes to J8 ACIF Interface 1-2 PCLK Normal 2-3 Allows external PCLK provided into SMA plug 1-2 FS Normal 2-3 Allows external FS provided into SMA plug SICE header allows access to 7x2 interface J1 Analyzer Header for access to digital signals via POD Le71HE0862 No Change; same as Le71HE0861 Le71HP0311 No options 25 Zarlink Semiconductor Inc. CHAPTER 7 7.1 SCHEMATICS LE71HE0861/862 LE71HE0861/862 EVALUATION BOARD SCHEMATICS Schematics for the Le71HE0861/862 evaluation boards are included in the following pages. 27 Zarlink Semiconductor Inc. A B C D 33 33 33 33 33 B10 R13 R15 R16 R19 33 B29 33 B30 33 B31 33 B32 R27 R28 R29 R30 B27 33 B28 R26 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B9 B8 B7 B6 B5 33 33 B4 B3 R11 R8 B2 R9 33 R6 33 B32 B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 P7 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 33 5 2.) JP2 provides the option to select the 2.5v regulated power supply votage to the Le88610 VDD250 VDD250 inputs. By shunting JP2 pins 2 & 3 the VDD2503 VDD2503 pin 69 output power supply is used. When shunting JP2 pins 1 & 2 the fixed output from the voltage regulator (VR1) provides the 2.5 voltage. 33 33 33 33 33 33 33 33 R23 R24 R25 Notes: CONF1 PCLK CONF2 CONF0 TSCA FS DX INT DR PWAIT RST PRD PWR PCS DGND DGND DGND +3.3V 5V VBP VBL VBH 1 2 3 4 5 6 7 8 9 10 PW1 AUX_VCC +3.3V AUX_VCC C7 0.1uF 0.1uF C2 3 1 4 4.) JP4 is used to provide the option to select 3.3V for inputs DVDD(1, 2 & 3) & PL_VDD. By JP4 shorting pins 1 & 2 the 3.3Vexternal power supply is used to provide the power for inputs DVDD & PL_VDD. When shunting pins 2 & 3 the fixed 3.3V voltage regulator output via selection on JP4 is used for the supply. 3.) JP3 is used to select the 3.3v fixed or variable voltage to the ISLIC. Shunting pins JP3 2 & 3 selects the variable 3.3V supply to SLIC_VCC. Shunting pins JP3 1 & 2 selects 3.3V output from the voltage regulator (VR2). 33 33 33 33 R21 R22 33 R20 R17 R18 R14 R12 R10 R7 R3 R4 1.) JP1 provides the option to select the 3.3v regulated power supply votages to the Le88610 and ISLIC device for AVDD (1-2) and CREF inputs. By shunting pins 1 & 2 the external power supply is used. When shunting pins 2 & 3 the fixed output from the voltage regulator provides the 3.3 voltage. DGND GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 PD7/SO PD6 PD5 PD4 PD3 PD2 PD1 PD0 PADDR R5 B1 OUT 0.1uF OUT AGND -SHDN IN 28 3 49.9 R1 1 DGND BGND EC6 10uF AGND 2 2 +3.3V 3 1 DGND EC7 10uF 3 2 1 EC2 10uF R2 + EC1 10uF EC3 10uF 1 2 + 2 2 EC4 10uF SMA JFS1 DGND DGND + C5 10nF C3 10nF 49.9 DGND DGND FS JP6 Note: AGND and DGND planes are connected via strap near power supply ground input. JP1 SMA JPCLK1 TANTALUM +C6 3.3uF Note 1 TANTALUM 3.3uF +C1 VDD250 VDD250 BGND 0.1uF C8 5 VR2 LTC1844-3 LTC1844-3.3 TSOT23 TSOT23 AGND C4 5 3 2 1 PCLK JP5 3 Zarlink Semiconductor Inc. 3 1 -SHDN IN VR1 LTC1844-2 LTC1844-2.5 TSOT23 TSOT23 NOTE: JP5 and JP6 provides addition for external oscillator and frame sync signals. Jumpers 1 & 2 are on board selections for PCLK and FS. Jumpers 2 and 3 is selected for use with external oscillator signals . 2 DGND 4 GND GND 2 5 Le71HE0861 Evaluation Board Schematic, rev. F1 TAB 4 TAB 4 Figure 7­1 + Le71HE0861/862 + C9 10nF + C10 10nF 2 JP4 EC5 10uF C11 0.1uF 3 DGND 2 JP2 C12 100uF Note 2 1 2 JP3 Wednesday, November 19, 2003 Document Number Le71HE0861 1 Note 3 3 Le79610 Evaluation Board Date: Size B Title AGND + DGND DGND 1 Note 4 DGND 3 1 Sheet 1 AUX_VCC 1 VBH VBL VBP of RING_IN AGND SLIC_VCC 3 Rev A 3.3V_DVDD +3.3V DGND SLIC_VCC SLIC_POWER CREF VDD250 VDD250_Direct VDD250 VDD250_Output PCLK1 FS1 A B C D Eval Board User Guide 1 2 3 4 3.3V_DVDD VDD250 VDD250_Output VDD250 VDD250_Direct GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 CONF0 CONF1 CONF2 CREF AGND AGND1 AGND AGND2 AGND 1 3 5 7 9 11 1 3 5 AGND AGND3 A HDR3X2 P5 2 4 6 HDR6X2 2 4 6 8 10 12 P4 2 1 2 1 2 1 2 1 D2 D3 D4 D5 AGND +3.3V R73 R74 R75 10K 10K 10K 2 1 D1 AGND4 3 3 3 3 3 R68 R66 R62 R61 R60 +3.3V DGND DGND INT DGND DGND + FS1 INT 10uF C15 FS1 PCLK1 DGND1 DGND2 DGND3 VDD250 VDD250_1 Note: At P4 add 1-2, 3-4 & 5-6 shorting strap for pull downs. PCLK1 Note: At P3 1-2, 3-4, 5-6, 7-8 & 9-10 shorting straps provided for led display. 300 300 300 300 300 10nF C19 BGND B 10nF 10nF C22 50 69 13 31 25 26 27 28 32 33 34 35 14 15 16 17 46 47 48 49 36 37 38 39 40 18 19 20 21 22 23 24 54 6 U2 71 29 11 52 30 12 51 70 +3.3V 10K R56 10K RSVD DVSS1 DVSS2 DVSS3 PLL_VSS VDD2504 VDD2504 VDD2503 VDD2503 VDD2502 VDD2502 VDD2501 VDD2501 PD7/SO PD6/I/O12 PD6/I/O12 PD5/I/O11 PD5/I/O11 PD4/I/O10 PD4/I/O10 PD3/I/O9 PD2/I/O8 PD1/I/O7 PD0/I/O6 I/O1 I/O2 I/O3 I/O4 I/O5 CONF0 CONF1 CONF2 TSC DX DR FS PCLK RST INT PWAIT/I/O14 PWAIT/I/O14 PADDR/I/O13 PADDR/I/O13 PCS/SS PRD/SI PWR/SCK AVSS1 AVSS2 AVDD2 AVDD1 RSHB 750K IMS ICK +3.3V 10K R58 RST SICE_ID SICE_IMS SICE_ICK SICE_TRSTN PLL_VDD DVDD1 DVDD2 DVDD3 C18 22nF C14 10nF C17 22nF C21 BGND1 10nF C20 C16 22nF PD7/SO PD6 PD5 PD4 PD3 PD2 PD1 PD0 TSCA DX DR PWAIT PADDR PCS PRD PWR RST AGND C13 10nF 2 57 AGND R59 41 5 SW B3W-1100 B3W-1100 S1 2 1 3 4 42 GO_ICE SHB Le796101 D 2 4 6 8 10 12 14 R63 3.01K 154K GS12 GS22 VREF VILG1 VSAB1 XSC XSB2 VLB2 VIMT2 VILG2 VSAB2 VHL2 VIN2 VOUT2 LD2 MH2 MH4 VBH VBL VBP SLIC_POWER 6.19K R72 LD1 RSRC MH3 FID5 XSB2 BGND LD2 CREF VIN2 VSAB2 VIMT2 C 56 55 10 9 8 53 VREF AGND RREF 69.8K IREF 750K D FID2 1 1 FID3 1 1 1 FID4 1 1 FID6 E Wednesday, November 19, 2003 Document Number Le71HE0861 Le79610 Evaluation Board Date: Size C Title 1 FID1 1 1 1 3 FID8 AGND Sheet FID7 CREF LD1 VIN1 VSAB1 VIMT1 VREF XSB1 VIN1 SLIC_POWER VOUT1 VHL1 VILG1 VLB1 P1 P3 VREF XSC VOUT2 VHL2 P2 VOUT1 VIMT1 GS11 GS21 VHL1 VREF VREF VILB1 R67 XSB1 6.19K R65 61 P3 VREF 62 63 64 P2 154K 65 75K R71 58 P1 3.01K R70 59 66 67 68 7 79 78 77 76 75 1 R69 R64 75K VILG2 60 74 1 MH1 RING_IN AUX_VCC VBH VBL VBP 73 72 DGND +3.3V E of A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 J1 3 Rev A VBH VBL VBP CREF 1 2 3 4 Eval Board User Guide VLB2 1 3 5 7 9 11 13 JP7 C HEADER 7X2 29 IREF VREF P1 P2 P3 LD1 VOUT1 VIN1 VHL1 VSAB1 VILG1 GS21 GS11 VIMT1 VLB1 XSB1 LD2 VOUT2 VIN2 VHL2 VSAB2 VILG2 GS22 GS12 VIMT2 VLB2 XSB2 R57 300 +3.3V Zarlink Semiconductor Inc. RSLB RSPB 750K750K 750K750K 3 B ID SLB 4 A 43 Le71HE0861 Evaluation Board Schematic, rev. F1 (cont.) 44 SPB 5 Figure 7­2 Le71HE0861/862 45 XSC 80 Le71HE0861/862 Figure 7­3 Eval Board User Guide J1 Analyzer Header J2 PCS PADDR PD1 PD3 PD6 PD5 R31 33 R33 33 R38 33 R40 33 R41 33 R43 33 R44 33 PD7/SO TSCA DX DR PCLK1 FS1 GPIO5 RST GPIO3 GPIO4 GPIO2 GPIO1 R45 33 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 33 33 33 33 33 33 33 33 33 33 C25 D25 C24 D24 C23 D23 C22 D22 C21 D21 C20 D20 C19 D19 C18 D18 C17 D17 C16 D16 C15 D15 C14 D14 C13 D13 C12 D12 C11 D11 C10 D10 C9 D9 C8 D8 C7 D7 C6 D6 C5 D5 C4 D4 C3 D3 C2 D2 C1 D1 A25 B25 A24 B24 A23 B23 A22 B22 A21 B21 A20 B20 A19 B19 A18 B18 A17 B17 A16 B16 A15 B15 A14 B14 A13 B13 A12 B12 A11 B11 A10 B10 A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 C25 D25 C24 D24 C23 D23 C22 D22 C21 D21 C20 D20 C19 D19 C18 D18 C17 D17 C16 D16 C15 D15 C14 D14 C13 D13 C12 D12 C11 D11 C10 D10 C9 D9 C8 D8 C7 D7 C6 D6 C5 D5 C4 D4 C3 D3 C2 D2 C1 D1 A25 B25 A24 B24 A23 B23 A22 B22 A21 B21 A20 B20 A19 B19 A18 B18 A17 B17 A16 B16 A15 B15 A14 B14 A13 B13 A12 B12 A11 B11 A10 B10 A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 R32 R34 R35 R36 DGND Figure 7­4 30 Zarlink Semiconductor Inc. 33 R39 33 R42 DGND 33 33 R37 MOLC25 MOLC25_MIXED 33 33 33 INT PRD PWAIT PD0 PD2 PD4 PWR A B C D 33 33 33 33 33 33 B10 33 B11 33 B12 33 B13 33 B14 R13 R15 R16 R19 R94 R95 R96 R97 33 B15 33 B17 33 B18 R99 R100 R101 33 B29 33 B30 33 B31 33 B32 R27 R28 R29 R30 B27 33 B28 R26 B26 B25 B24 B23 B22 B21 B20 B19 33 B16 R98 B9 B8 B7 B6 B5 33 33 B4 B3 R11 R8 B2 R9 33 R6 R5 B32 B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 P7 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 A26 C26 A27 C27 A28 C28 A29 C29 A30 C30 A31 C31 A32 C32 R23 R24 R25 R22 R21 R20 R17 R18 R14 R12 R10 R7 R3 R4 5 2.) JP2 provides the option to select the 2.5v regulated power supply votage to the Le88610 VDD250 VDD250 inputs. By shunting JP2 pins 2 & 3 the VDD2503 VDD2503 pin 69 output power supply is used. When shunting JP2 pins 1 & 2 the fixed output from the voltage regulator (VR1) provides the 2.5 voltage. 1.) JP1 provides the option to select the 3.3v regulated power supply votages to the Le88610 and ISLIC device for AVDD (1-2) and CREF inputs. By shunting pins 1 & 2 the external power supply is used. When shunting pins 2 & 3 the fixed output from the voltage regulator provides the 3.3 voltage. GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 DGND PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7/SO PD6 PD5 PD4 PD3 PD2 PD1 PD0 PADDR B1 Notes: CONF1 PCLK CONF2 CONF0 TSCA FS DX INT DR PWAIT RST PRD PWR PCS DGND DGND DGND +3.3V 5V VBP VBL VBH 1 2 3 4 5 6 7 8 9 10 PW1 AUX_VCC +3.3V AUX_VCC C7 0.1uF 0.1uF C2 3 1 4 4.) JP4 is used to provide the option to select 3.3V for inputs DVDD(1, 2 & 3) & PL_VDD. By JP4 shorting pins 1 & 2 the 3.3Vexternal power supply is used to provide the power for inputs DVDD & PL_VDD. When shunting pins 2 & 3 the fixed 3.3V voltage regulator output via selection on JP4 is used for the supply. 3.) JP3 is used to select the 3.3v fixed or variable voltage to the ISLIC. Shunting pins JP3 2 & 3 selects the variable 3.3V supply to SLIC_VCC. Shunting pins JP3 1 & 2 selects 3.3V output from the voltage regulator (VR2). 33 33 33 33 33 33 33 33 33 33 33 33 33 33 OUT OUT AGND -SHDN IN 31 3 49.9 R1 1 DGND BGND EC6 10uF AGND 2 +3.3V 3 1 DGND EC7 10uF EC2 10uF + 1 2 2 2 DGND EC4 10uF SMA JFS1 + DGND EC3 10uF + DGND C5 10nF C3 10nF DGND 3 2 1 R2 49.9 EC1 10uF FS JP6 Note: AGND and DGND planes are connected via strap near power supply ground input. JP1 SMA 2 JPCLK1 TANTALUM 3.3uF +C6 Note 1 TANTALUM 3.3uF +C1 VDD250 VDD250 BGND 0.1uF C8 5 VR2 LTC1844-3 LTC1844-3.3 TSOT23 TSOT23 AGND 0.1uF C4 5 3 2 1 PCLK JP5 3 Zarlink Semiconductor Inc. 3 1 -SHDN IN VR1 LTC1844-2 LTC1844-2.5 TSOT23 TSOT23 NOTE: JP5 and JP6 provides addition for external oscillator and frame sync signals. Jumpers 1 & 2 are on board selections for PCLK and FS. Jumpers 2 and 3 is selected for use with external oscillator signals . 2 DGND 4 GND GND 2 5 Le71HE0862 Evaluation Board Schematic TAB 4 TAB 4 Figure 7­5 + Le71HE0861/862 + C9 10nF + DGND C10 10nF EC5 10uF 1 Note 4 DGND C12 100uF 2 JP2 DGND 2 JP3 Monday, November 10, 2003 Document Number Le71HE0862 1 Note 3 3 Le79610 Evaluation Board Date: Size B Title C11 0.1uF 3 DGND AGND + 2 JP4 Note 2 1 3 1 Sheet 1 1 VBH VBL VBP RING_IN of AGND SLIC_VCC 3 Rev A +3.3V_DVDD AUX_VCC +3.3V DGND SLIC_VCC SLIC_POWER CREF VDD250 VDD250_Direct VDD250 VDD250_Output PCLK1 FS1 A B C D Eval Board User Guide 1 2 3 4 R181 300 R180 300 R179 300 R178 300 R177 300 R176 300 R175 300 R174 300 R173 300 R172 300 R68 300 R66 300 R62 300 R61 300 CONF0 CONF1 CONF2 +3.3V_DVDD VDD250 VDD250_Output 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 A 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VDD250 VDD250_1 1 3 5 7 9 1 3 5 7 9 1 3 5 7 9 HDR5X2 2 4 6 8 10 P8 GPIO11 GPIO11 GPIO12 GPIO12 GPIO13 GPIO13 GPIO14 GPIO14 GPIO15 GPIO15 HDR5X2 2 4 6 8 10 P6 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO10 HDR5X2 2 4 6 8 10 P4 Note: At P4, P6, & P8 1-2, 3-4, 5-6, 7-8 & 9-10 shorting straps provided for led display. AGND DGND 10uF C15 1 3 5 +3.3v B 10nF C22 DGND 10nF C21 C18 22nF TSCA DX DR PWAIT PADDR PCS PRD PWR RST GPIO11 GPIO11 GPIO12 GPIO12 GPIO13 GPIO13 GPIO14 GPIO14 GPIO15 GPIO15 AGND R73 R74 R75 10K 10K 10K 10nF C20 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7/SO PD6 PD5 PD4 PD3 PD2 PD1 PD0 10nF C19 C17 22nF FS1 INT FS1 C16 22nF HDR3X2 P5 2 4 6 + PCLK1 PCLK1 INT C13 10nF 26 27 28 29 30 31 32 33 34 35 39 40 41 42 43 44 87 88 36 12 89 65 37 13 85 64 63 86 14 38 45 46 47 48 49 19 20 21 22 23 24 25 9 10 11 15 16 17 18 50 56 57 58 59 60 61 62 70 4 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7/SO PD6 PD5 PD4 PD3 PD2 PD1 PD0 PLL_VSS PLL_VDD DVDD1 DVDD2 DVDD3 DVDD4 DVSS1 DVSS2 DVSS3 DVSS4 VDD2504 VDD2504 VDD2503 VDD2503 VDD2502 VDD2502 VDD2501 VDD2501 TSC DX DR FS PCLK RST INT PWAIT PADDR PCS/SS PRD/SI PWR/SCK I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O10 I/O11 I/O11 I/O12 I/O12 I/O13 I/O13 I/O14 I/O14 I/O15 I/O15 AVSS1 AVSS2 AVDD2 AVDD1 U2 +3.3v 10K AGND2 AGND AGND1 AGND AGND AGND3 Note: At P4 add 1-2, 3-4 & 5-6 shorting strap for pull downs. 10nF C23 73 5 R59 AGND 100 C14 10nF SW B3W-1100 B3W-1100 S1 2 1 3 4 R56 10K 51 D1 52 AGND AGND4 RSVD 1 2 B SHB SLB SPB XSC IREF VREF P1 P2 P3 LD1 VOUT1 VIN1 VHL1 VSAB1 VILG1 GS21 GS11 VIMT1 VLB1 XSB1 LD2 VOUT2 VIN2 VHL2 VSAB2 VILG2 GS22 GS12 VIMT2 VLB2 XSB2 R57 300 DGND GS12 GS22 D R63 3.01K DGND 154K VREF VILG1 VSAB1 RSRC XSC FID6 XSB2 VLB2 VIMT2 VILG2 VSAB2 VHL2 VIN2 VOUT2 LD2 FID7 FID8 Title RING_IN SLIC_POWER AUX_VCC VBH VBL VBP E P1 VREF P3 VIN1 VOUT1 VIMT1 GS11 GS21 VHL1 VREF VREF VILB1 6.19K XSB1 R67 R65 VBH VBL VBP LD1 MH4 Le79610 Evaluation Board SLIC_POWER BGND LD2 CREF VIN2 VSAB2 VIMT2 XSB2 VOUT1 VHL1 VILG1 VLB1 P1 P3 VREF XSC VOUT2 VHL2 P2 P2 VREF IREF VREF AGND RREF 69.8K IREF RSPB 750K 98 72 71 8 7 6 1 C RSHB 750K 2 BGND BGND1 RSLB 750K 3 MH2 1 1 FID2 1 FID1 1 MH1 1 FID3 1 MH3 1 1 FID4 1 FID5 D 750K 1 1 1 Date: Size C E Monday, November 10, 2003 Document Number Le71HE0862 AGND Sheet CREF LD1 VIN1 VSAB1 VIMT1 77 69 VREF XSB1 78 79 80 81 6.19K 154K R72 75K 3.01K 74 GS21 R71 R69 75 GS11 R70 82 83 84 5 97 96 95 94 93 99 GS22 R64 75K 92 76 GS12 VILG2 91 90 32 DGND +3.3V 3 of A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 J1 3 Rev A VBH VBL VBP CREF 1 2 3 4 Eval Board User Guide VLB2 2 4 6 8 10 12 14 HEADER 7X2 1 3 5 7 9 11 13 JP7 C Zarlink Semiconductor Inc. DGND DGND1 DGND2 DGND3 Le796102 +3.3V 10K R58 RST SICE_ID SICE_IMS SICE_ICK SICE_TRSTN +3.3V Le71HE0862 Evaluation Board Schematic(cont.) 53 GO_ICE R60 300 VDD250 VDD250_Direct +3.3v CREF A GO_ICE 54 ID Figure 7­6 Le71HE0861/862 55 ICK IMS CONF0 CONF1 CONF2 66 67 68 Le71HE0861/862 Figure 7­7 Eval Board User Guide J1 Analyzer Header J2 R31 33 R33 33 R38 33 R40 33 R41 33 R43 33 R44 33 R46 R48 R49 R47 R51 33 33 33 33 33 R76 R77 R45 R93 R78 R79 R80 R81 R82 R83 R50 R84 R52 R53 R54 R55 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 C25 D25 C24 D24 C23 D23 C22 D22 C21 D21 C20 D20 C19 D19 C18 D18 C17 D17 C16 D16 C15 D15 C14 D14 C13 D13 C12 D12 C11 D11 C10 D10 C9 D9 C8 D8 C7 D7 C6 D6 C5 D5 C4 D4 C3 D3 C2 D2 C1 D1 A25 B25 A24 B24 A23 B23 A22 B22 A21 B21 A20 B20 A19 B19 A18 B18 A17 B17 A16 B16 A15 B15 A14 B14 A13 B13 A12 B12 A11 B11 A10 B10 A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 C25 D25 C24 D24 C23 D23 C22 D22 C21 D21 C20 D20 C19 D19 C18 D18 C17 D17 C16 D16 C15 D15 C14 D14 C13 D13 C12 D12 C11 D11 C10 D10 C9 D9 C8 D8 C7 D7 C6 D6 C5 D5 C4 D4 C3 D3 C2 D2 C1 D1 A25 B25 A24 B24 A23 B23 A22 B22 A21 B21 A20 B20 A19 B19 A18 B18 A17 B17 A16 B16 A15 B15 A14 B14 A13 B13 A12 B12 A11 B11 A10 B10 A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 R32 R34 R35 R36 DGND Figure 7­8 Le71HE0861 Adapter Board 33 Zarlink Semiconductor Inc. 33 R39 33 R42 33 R85 33 R86 33 R87 33 R88 33 R89 33 R90 33 R91 33 R92 DGND 33 33 R37 MOLC25 MOLC25_MIXED 33 33 33 INT PRD PWAIT PD0 PD2 PD4 PWR PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 A B C D From either the DEVA7 or JA PCB Female C1 B1 A1 C2 B2 A2 C3 B3 A3 C4 B4 A4 C5 B5 A5 C6 B6 A6 C7 B7 A7 C8 B8 A8 C9 B9 A9 C10 B10 A10 C11 B11 A11 C12 B12 A12 C13 B13 A13 C14 B14 A14 C15 B15 A15 C16 B16 A16 C17 B17 A17 C18 B18 A18 C19 B19 A19 C20 B20 A20 C21 B21 A21 C22 B22 A22 C23 B23 A23 C24 B24 A24 C25 B25 A25 C26 B26 A26 C27 B27 A27 C28 B28 A28 C29 B29 A29 C30 B30 A30 C31 B31 A31 C32 B32 A32 Male 5 Euro_65094 7-5 P1 5 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE DGND DGND DGND FS_DEVA7 DGND PCLK_DEVA7 DRA DXA TSCA_N I/O5 I/O4 I/O3 I/O2 I/O1 PD0 PD1 PD2 PD3 PD4 PD5 PD7/S0_DEVA7 DGND PD6 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PRD_N/SI_DEVA7 DGND PWR_N/SCK_DEVA7 DGND PCS_N/SS_N_DEVA7 PADDR PWAIT_N INT0_N RST_N CONF0 CONF1 CONF2 CS_2 INT1_N RINGLL MCLK DGND DGND J5 PRD Selector J4 PWR Selector J6 FS Selector J7 PCLK Selector TSCA DRA DXA FID2 1 1 FID1 1 MH2 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 R35 5K 5V INT2_N INT1_N RINGLL Row D DGND IDCS CS_3 CS_2 CS_1 INT3_N 1 FID4 1 MH4 1 FID5 1 MH5 1 FID6 1 MH8 4 1 FID7 1 DGND DRB DXB TSCB_N 12V 12V 12V DGND CONF2 CONF1 CONF0 DGND DGND J9 47uF 10V + C17 D13 +5V 1.0uF 16V + C18 5V + C60 10uF R34 10K 1 R3 R4 1K 470 5V 3 B1 D1 B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 B25 D25 B1 D1 B2 D2 B3 D3 B4 D4 B5 D5 B6 D6 B7 D7 B8 D8 B9 D9 B10 D10 B11 D11 B12 D12 B13 D13 B14 D14 B15 D15 B16 D16 B17 D17 B18 D18 B19 D19 B20 D20 B21 D21 B22 D22 B23 D23 B24 D24 B25 D25 FOLC25 FOLC25 A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 MIXED A1 C1 A2 C2 A3 C3 A4 C4 A5 C5 A6 C6 A7 C7 A8 C8 A9 C9 A10 C10 A11 C11 A12 C12 A13 C13 A14 C14 A15 C15 A16 C16 A17 C17 A18 C18 A19 C19 A20 C20 A21 C21 A22 C22 A23 C23 A24 C24 A25 C25 RING_IN RSVD RING_RET DGND 12V 12V 12V DGND VBH VBL VBP DGND 5V 5V 5V DGND 3.3V 3.3V 3.3V DGND DGND Row A DGND DRA DXA TSCA_N PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7/S0 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PWR_N/SCK PRD_N/SI PCS_N/SS_N PADDR PWAIT_N Row C Zarlink Semiconductor Inc. 34 3 DNT = Do Not Terminate on line module. RSVD = These pins are permanentley floated to gain extra isolation for the ring bus RSVD RSVD FS PCLK I/O8 GO_ICE ID IMS ICK I/O9 I/O10 I/O10 I/O11 I/O11 I/O12 I/O12 I/O13 I/O13 I/O14 I/O14 I/O1 RSVD I/O15 I/O15 I/O2 I/O3 I/O4 I/O5 I/O7 Passive I/O6 INT0_N RSVD RST_N PIN A1 4 DGND 4 1 +12V Row B DGND DGND ACIF INTERFACE MCLK FID3 1 FID8 J8 5 3 PWR1 FRONT VIEW SW4 SW DPDT DGND MH3 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 12V 1 HEADER 14x2/SM 5 PCLK Note: The Selectors above normal shorting plugs are postioned in pins 1 and 2. To provide test capability for PCM and test modes selection in the appropriate selectors positioned in pins 2 and 3 are used. MH1 6 FS_ACIF PCLK_ACIF TSCA_N DXA CSL DRA (DIO) DCLK 12V 2 PCLK_ACIF FS FS_ACIF PD7/S0 PWR_N/SCK PRD_N/SI J3 PCS Selector PCS_N/SS_N J2 PCS Selector SPARE SPARE SPARE SPARE 4 4 3 Le71HP0310 Adapter Board 1 4 Figure 7­9 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 2 2 3 ADAPTER BOARD SCHEMATICS OFF IN U5 MAX604 MAX604 SET OUT + J11 Socket C61 10uF 16V 3.3V Socket J10 5 8 3.3V 2 DGND 2 DGND B1 A1 B2 A2 7.2 B1 A1 B2 A2 Le71HE0861/862 Title INT2_N PD8 FS INT1_N PD7/S0 DXB INT0_N PD6 DXA PD5 DRB PD4 DRA PD3 PWAIT_N PD2 RST_N CS_3 PD1 RINGLL CS_2 PD0 PRD_N/SI CS_1 PADDR VBH RTI VBH VBH IDCS TTI PD15 PD14 MCLK PD13 DGND RING_RET 3.3V SPARE 5V SPARE RING_IN VBP SPARE Date: Size C VBP 12V VBL 12V 5V DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND Euro_65046 1-5 C32 B32 A32 C31 B31 A31 C30 B30 A30 C29 B29 A29 C28 B28 A28 C27 B27 A27 C26 B26 A26 C25 B25 A25 C24 B24 A24 C23 B23 A23 C22 B22 A22 C21 B21 A21 C20 B20 A20 C19 B19 A19 C18 B18 A18 C17 B17 A17 C16 B16 A16 C15 B15 A15 C14 B14 A14 C13 B13 A13 C12 B12 A12 C11 B11 A11 C10 B10 A10 C9 B9 A9 C8 B8 A8 C7 B7 A7 C6 B6 A6 C5 B5 A5 C4 B4 A4 C3 B3 A3 C2 B2 A2 C1 B1 A1 J1 1 Sheet Female Monday, October 20, 2003 Le71HP0310 Document Number DEVA7 Adapter I/O5 I/O4 3.3V I/O3 RING_RET 3.3V I/O2 RING_RET I/O1 RING_IN 5V VBP DGND RING_IN RTO VBL 12V SPARE RTO TTO VBL 12V CONF2 PD12 PCLK CONF1 PD11 DGND TTO SPARE SPARE SPARE RTI IDCS TTI MCLK PCLK TSCB_N CONF0 PD10 TSCB_N INT3_N PD9 TSCA_N INT3_N FS DGND PCS_N/SS_N DGND PWR_N/SCK Sig/Pwr/Gnd INT2_N DXB INT0_N DRB SPARE SPARE SPARE RST_N SPARE CS_3 PRD_N/SI CS_1 PWR_N/SCK PCS_N/SS_N 1 1 of Male 1 Rev A A B C D Eval Board User Guide To the Eval PCB A B C Female New Generation Host PD4 DRA PD5 DRB C26 B26 A26 C25 B25 A25 DGND I/O5 DGND DGND I/O4 DGND 3.3V I/O3 RING_RET 3.3V I/O2 RING_RET 5V I/O1 RING_IN 5V VBP DGND RING_IN VBP 12V VBL 12V VBL 12V RTO DGND DGND TTO VBH RTI VBH VBH IDCS TTI DGND PD15 DGND DGND PD14 DGND MCLK PD13 DGND CONF2 PD12 PCLK CONF1 PD11 DGND CONF0 PD10 TSCB_N INT3_N PD9 TSCA_N INT2_N PD8 FS INT1_N PD7/S0 DXB Male 5 Euro_65094 7-5 C1 B1 A1 C2 B2 A2 C3 B3 A3 C4 B4 A4 C5 B5 A5 C6 B6 A6 C7 B7 A7 C8 B8 A8 C9 B9 A9 C10 B10 A10 C11 B11 A11 C12 B12 A12 C13 B13 A13 C14 B14 A14 C15 B15 A15 C16 B16 A16 C17 B17 A17 C18 B18 A18 C19 B19 A19 C20 B20 A20 C21 B21 A21 C22 B22 A22 C23 B23 A23 INT0_N PD6 DXA PD3 PWAIT_N C24 B24 A24 PD2 RST_N C27 B27 A27 CS_3 PD1 RINGLL CS_2 PD0 PRD_N/SI CS_1 PADDR C28 B28 A28 C29 B29 A29 C30 B30 A30 C31 B31 A31 PCS_N/SS_N DGND PWR_N/SCK MH2 1 FID2 1 MH1 DGND RING_RET 3.3V RING_IN 5V VBP 12V RTO VBL TTO RTI IDCS TTI MCLK PCLK TSCB_N INT3_N FS INT2_N DXB INT0_N DRB RST_N CS_3 PRD_N/SI CS_1 PWR_N/SCK PCS_N/SS_N 1 FID1 1 1 FID3 1 MH3 1 FID4 1 MH4 1 FID5 1 MH5 1 FID6 1 MH6 1 FID7 1 FID8 4 12V 12V 1 2 4 3 RING_IN PWR1 J9 1.0uF 16V + C18 + C60 10uF 5V R34 10K A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 A17 B17 A18 B18 A19 B19 A20 B20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 MIXED DGND DRA DXA TSCA_N PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7/SO PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PWR_N/SCK PRD_N/SI PCS_N/SS_N PADDR PWAIT_N Row B DGND DRB DXB TSCB_N 12V 12V 12V DGND CONF2 CONF1 CONF0 DGND MCLK DGND DGND IDCS CS_3 CS_2 CS_1 INT3_N INT2_N INT1_N RINGLL Row A 35 3 DNT = Do Not Terminate on line module. RSVD = These pins are permanentley floated to gain extra isolation for the ring bus D1 C1 D2 C2 D3 C3 D4 C4 D5 C5 D6 C6 D7 C7 D8 C8 D9 C9 D10 C10 D11 C11 D12 C12 D13 C13 D14 C14 D15 C15 D16 C16 D17 C17 D18 C18 D19 C19 D20 C20 D21 C21 D22 C22 D23 C23 D24 C24 D25 C25 FOLC25 FOLC25 DGND 5K R35 4 Zarlink Semiconductor Inc. FS PCLK I/O8 I/O9 I/O10 I/O10 I/O11 I/O11 I/O12 I/O12 I/O13 I/O13 I/O14 I/O14 I/O15 I/O15 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 RST_N INT0_N 47uF 10V + C17 5V 4 Row C DGND DGND D13 +5V 5V 1 +12V 3 1 FRONT VIEW RING_RET DGND 12V 12V 12V DGND VBH VBL VBP DGND 5V 5V 5V DGND 3.3V 3.3V 3.3V DGND DGND Row D 5 3 SW4 SW DPDT R3 R4 1K 470 1 4 C32 B32 A32 4 2 2 3 D P1 5 OFF IN U5 MAX604 MAX604 SET OUT + J11 2 DGND DGND Socket C61 10uF 16V 3.3V Socket J10 5 8 3.3V 2 B1 A1 B2 A2 Figure 7­10 Le71HP0311 Adapter Board B1 A1 B2 A2 Le71HE0861/862 5 6 Date: Size C Title DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND Document Number Friday, October 31, 2003 Le71HP0311 1 Female Sheet Euro_6504 61-5 C32 B32 A32 C31 B31 A31 C30 B30 A30 C29 B29 A29 C28 B28 A28 C27 B27 A27 C26 B26 A26 C25 B25 A25 C24 B24 A24 C23 B23 A23 C22 B22 A22 C21 B21 A21 C20 B20 A20 C19 B19 A19 C18 B18 A18 C17 B17 A17 C16 B16 A16 C15 B15 A15 C14 B14 A14 C13 B13 A13 C12 B12 A12 C11 B11 A11 C10 B10 A10 C9 B9 A9 C8 B8 A8 C7 B7 A7 C6 B6 A6 C5 B5 A5 C4 B4 A4 C3 B3 A3 C2 B2 A2 New Generation Host Adapter SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE SPARE PCLK FS DRA DXA TSCA_N I/O5 I/O4 I/O3 I/O2 I/O1 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7/S0 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 DGND PWR_N/SCK PRD_N/SI DGND PCS_N/SS_N PADDR PWAIT_N INT0_N RST_N CONF0 CONF1 CONF2 CS_1 INT1_N RINGLL MCLK C1 B1 A1 J1 1 1 of Male 1 Rev A A B C D Eval Board User Guide PDSP Emulator 7.3 1 2 3 4 J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 A AGND A BGND XSC B P1 P3 XSB(U) XSC VREF CREF VIN(L) VSAB(L) VIMT(L) XSB(L) VIN(U) VSAB(U) VIMT(U) XSB(U) LD(U) VREF LD(L) P2 Channel One ISLIC Lower Channel 36 Channel Four Channel Two Quad ISLAC Even Channel Connector SLIC_VCC AUX_VCC AGND RING_IN Channel One Channel Two Dual ISLAC D D The above table shows which channel of the ISLIC Evaluation Board mates with which channel of the Quad and Dual ISLAC Evaluation Boards. Channel Three C RING_IN SLIC_VCC AUX_VCC AGND Quad ISLAC Odd Channel Connector ISLIC Upper Channel Sheet 2. P3 P2 P1 LD(L) XSB(L) XSC VREF CREF VBH VBL VBP BGND SLIC_VCC AUX_VCC AGND VBH VBL VBP BGND RING_IN VBH VBL VBP BGND RING_IN VBH VBL VBP BGND SLIC_VCC AUX_VCC AGND Zarlink Semiconductor Inc. P3 P2 P1 LD(L) XSB(L) XSC VREF CREF VOUT(L) VIN(L) VHL(L) VSAB(L) VILG(L) VIMT(L) VLB(L) ISLIC "Lower" Channel VOUT(L) VIN(L) VHL(L) VSAB(L) VILG(L) VIMT(L) VLB(L) SLIC_VCC P3 P2 P1 LD(U) Sheet 3. P3 P2 P1 VOUT(L) VHL(L) CREF VREF VILG(L) VLB(L) XSB(U) XSC VREF CREF VOUT(U) VIN(U) VHL(U) VSAB(U) VILG(U) VIMT(U) VLB(U) ISLIC "Upper" Channel C VBH VBL VBP SLIC_VCC AUX_VCC RING_IN VOUT(U) VIN(U) VHL(U) VSAB(U) VILG(U) VIMT(U) VLB(U) LD(U) VOUT(U) VHL(U) VILG(U) VLB(U) VBH VBL VBP B Figure 7­11 Le71HE0795 (rev. F) 790 Series SLIC Evaluation Board LE71HE0795 LE71HE0795 EVALUATION BOARD SCHEMATICS Le71HE0861/862 Date: Size C Title E Tuesday, November 25, 2003 Document Number ISLIC Evaluation Board Legerity, Inc. 4509 Freidrich Lane Austin, Texas 78744 E Sheet 1 of 3 Rev F 1 2 3 4 Eval Board User Guide 1 2 3 4 AGND SLIC_VCC AUX_VCC BGND VBH VBL VBP P3 P2 P1 LD(L) CREF VLB(L) VIN(L) VSAB(L) VHL(L) VOUT(L) VILG(L) VIMT(L) VREF XSB(L) XSC RING_IN AGND BGND VBL VBH VBP VSAB(L) VHL(L) VILG(L) A SLIC_VCC AUX_VCC VBH VBL VBP VIMT(L) VREF DL DHL DH DP A "X" CVBL 150nF CVBH 150nF CVBP 150nF P1 P2 P3 301 RSAB VOUT(L) XSC RHL 4.32K RHL1 8.06K RHL2 CREF VIN(L) 14 13 12 15 25 17 21 16 19 26 27 20 10 9 11 1 4 3 30 24 18 2 79231/R241/R251 79231/R241/R251 P3 P2 P1 LD CREF VLB VTX VSAB RSN ILG IMT VREF TMP TMS TMN BGND VBL VBH Note 4. RSVD [VBP] RSVD AGND VCC U1(L) RYE R3H R1 SB BD HPB HPA AD SA R2H 7 8 5 29 32 23 CHP 22nF 22 31 28 6 HPB HPA R3H RTSTL TL3 2.0K J2 AUX_VCC supplies power to the relay. VBP is required for the Am79R251 Am79R251 only. 8. 7. TY1 2 CBD 22nF CAD 22nF J1 1 3 J4 D2 RRYE 2.0K BD AD D1 AD 15 VBH 3 U3 B1100CC B1100CC -G 1 K A 2 2 1 B1100CC B1100CC U2 K 3 -G A Surge Protection Circuit. 200K RSB BD JP2 DS2 DS1 JP1 B 1 A G+ K 2 2 U5 B2100CC B2100CC 3 3 B2100CC B2100CC U4 VBP BD AD RGFDL 510 If using the Am79R251 Am79R251 leave JP1 and JP2 open. This will protect the part from any positive voltage spikes above VBP. to all channels do not carry the "U" (upper) or "L" Zarlink Semiconductor Inc. 37 C 1 K G+ A 9 7 Note 5. FRP 750K RSRB RRTN 50 If using the Am79R231/241 Am79R231/241 a wire jumper will need to be placed across JP1 and JP2. This will protect the parts from any voltage spikes above BGND. BD AD Box 1a. BD 11 5 1 D D The "U" designation at the end of each signal and component is there to differentiate between the "Upper" and "Lower" sections of the ISLIC Board. All signals that are common (i.e. XSC, VREF, P1, P2, P3, CREF, RING_IN, and supply voltages) (lower) designation as the last character of their reference designator. (also shown on the PCB artwork) and replacing the 34.0K RHLa resistor with a 4.99K resistor. 200K RSA AD TL2 2.0K RTSTM See Box 1a Below. R2H The VHL Filter Circuit is required for proper operation with early revisions (Rev. B and earlier) ISLAC devices. Future devices may not require the filter. The filter can be disabled by cutting PCB traces at the "X" points FRPa (Fuse Resistor Pair) protection resistors are 50 ohms total for each TIP and RING. 5. 6. SB Note 1. CSS 56pF SA Only required when doing metering injection in the GCI mode. RTX 80.6K RMGP 1.0K 2W SLIC_VCC supplies power to the ISLIC only. CSS is installed by the user. VLB(L) "X" RRX 90K 1.0K 2W RMGL C1a 0.1uF SLIC_VCC 4. 3. 2. 1. Notes: LD(L) VHL Filter Network Note 6. 34.0K 3.3nF CHL1 8.06K RHL3 CHL2 330nF XSB(L) C ISLIC Lower Channel B Figure 7­12 Le71HE0795 (rev. F1) 790 Series SLICTM Evaluation Board (Lower Channel) Le71HE0861/862 K1(L) 1 12 9 4 TPK1(L) Date: Size C Title 6 4 2 AUX_VCC SK(L) E Tuesday, November 25, 2003 Document Number Le71HE0795 ISLIC Evaluation Board Legerity, Inc. 4509 Freidrich Lane Austin, Texas 78744 J3a RELAY_TX2-5V 8 10 5 3 E 5 3 1 Sheet RING TIP 2 of 3 Rev F RING TIP 1 2 3 4 Eval Board User Guide 1 2 3 4 AGND SLIC_VCC AUX_VCC BGND VBH VBL VBP XSB(U) VBH VBL VBP VHL(U) VIMT(U) VREF A SLIC_VCC AUX_VCC DL DHL DH DP See Note 7. AGND BGND P3 P2 P1 LD(U) CREF VLB(U) VIN(U) VSAB(U) VHL(U) VOUT(U) VILG(U) VIMT(U) VREF VBL VBH VBP XSC RING_IN A P1 VSAB(U) VILG(U) CVBL 150nF CVBH 150nF CVBP 150nF P2 P3 301 RSAB "X" VOUT(U) XSB(U) RHL 34.0K RHL2 4.32K RHL1 8.06K VLB(U) RMGP 1.0K 2W SLIC_VCC supplies power to the ISLIC only. 79231/R241/R251 79231/R241/R251 P3 P2 P1 LD CREF VLB VTX VSAB RSN ILG IMT VREF TMP TMS TMN BGND VBL VBH Note 4. RSVD [VBP] RSVD AGND VCC RYE R3H R1 SB BD HPB HPA AD SA R2H 7 8 5 29 32 23 CHP 22nF 22 31 28 6 HPB HBA RTSTL 2.0K J2 CSS 56pF TL3 R3H TY1 SB Note 1. SA 1 3 J4 D2 RRYE 2.0K BD AD R2H AD RSA 200K AD 2.0K RTSTM TL2 RSB 15 VBH U3 B1100CC B1100CC 3 B1100CC B1100CC U2 3 -G -G 1 K A 2 2 A K 1 Surge Protection Circuit 200K BD 11 5 1 D JP3 Zarlink Semiconductor Inc. 38 D The "U" designation at the end of each signal and component is there to differentiate between the "Upper" and "Lower" sections of the ISLIC Board. 8. to all channels do not carry the "U" (upper) or "L" All signals that are common (i.e. XSC, VREF, P1, P2, P3, CREF, RING_IN, and supply voltages) (lower) designation as the last character of their reference designator. 7. The VHL Filter Circuit is required for proper operation with early revisions (Rev. B and earlier) ISLAC devices. Future devices may not require the filter. The filter can be disabled by cutting PCB traces at the "X" points (also shown on the PCB artwork) and replacing the 34.0K RHLU resistor with a 4.99K resistor. C 1 A G+ K 2 2 K G+ A 1 9 7 U5 B2100CC B2100CC 3 3 B2100CC B2100CC U4 Note 5. FRP VBP RRTN 50 BD AD RGFDL 510 If using the 79R251 79R251 leave JP1 and JP2 open. This will protect the part from any positive voltage spikes above VBP. 6. B DS2 DS1 JP4 750K RSRB If using the 79R231/241 79R231/241 a wire jumper will need to be placed across JP3 and JP4. This will protect the parts from any voltage spikes above BGND. BD AD Box 1b. BD See Box 1b Below. FRPb (Fuse Resistor Pair) protection resistors are 50 ohms total for each TIP and RING. 2 CBD 22nF CAD 22nF J1 D1 5. VBP is required for the Am79R251 Am79R251 only. AUX_VCC supplies power to the relay. 3. 4. 14 13 12 15 25 17 21 16 19 26 27 20 10 9 11 1 4 3 30 24 18 2 U1(U) Only required when doing metering injection in the GCI mode. RTX 80.6K CSS is installed by the user. VIN(U) "X" 90K RRX 1.0K 2W RMGL C1 0.1uF SLIC_VCC 2. 1. Notes: LD(U) CREF VHL Filter Circuit Note 6. 3.3nF CHL1 8.06K RHL3 CHL2 330nF XSC C ISLIC Upper Channel B Figure 7­13 Le71HE0795 (rev. F1) 790 Series SLICTM Evaluation Board (Upper Channel) Le71HE0861/862 1 12 9 4 J3 TPK1(U) Date: Size C Title SK(U) AUX_VCC 6 4 2 5 3 1 E Tuesday, November 25, 2003 Document Number Le71HE0795 ISLIC Evaluation Board Legerity, Inc. 4509 Freidrich Lane Austin, Texas 78744 8 10 5 3 K1(U) E Sheet RING TIP 3 of RING TIP 3 Rev F 1 2 3 4 Eval Board User Guide