LXT981 100BASE-TX 100BASE-FX LXT970 100BASE-T CLK25 100BASE-TX/ 100TX 100FX - Datasheet Archive

 

DECEMBER, 1998 Revision 1.1 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater with Integrated Management Support General

 

DATA SHEET DECEMBER, 1998 Revision 1.1 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater with Integrated Management Support General Description Features The LXT981 LXT981 is a 5-port Class II Fast Ethernet Repeater that is fully compliant with IEEE 802.3 standards. Four ports directly support 100BASE-TX 100BASE-TX copper media and also support 100BASE-FX 100BASE-FX fiber media via pseudo-ECL (PECL) interfaces. The fifth port, a 100 Mbps Media Independent Interface (MII), connects to Media Access Controllers (MACs) for bridge/switch applications. The MII can also be configured to interface to another PHY device, such as the LXT970 LXT970. · Four 100 Mbps ports with complete twisted-pair PHYs including integrated filters and 100BASE-FX 100BASE-FX PECL interfaces. The LXT981 LXT981 provides an Inter-Repeater Backplane (IRB) for expansion, operating at 100 Mbps. Up to 240 ports can logically be combined into one repeater using this backplane. The LXT981 LXT981 supports SNMP and RMON management via on-chip 32- and 64-bit counters. The counters and control information are accessible via a highspeed Serial Management Interface (SMI). The device supports two source address tracking registers per port and a source address matching function. · High-speed SMI. The LXT981 LXT981 enables cost-efficient 100BASE-TX 100BASE-TX intelligent repeater systems for stackable/modular and stand-alone applications. · Case temperature range: 0-115°C. · MII port connection to either MAC or PHY. · Cascadable IRBs. · Hardware assist for RMON and the Repeater MIB. · Two address-tracking registers per port. · Source address matching function. · Integrated LED drivers with user-selectable modes. · Available in 208-pin QFP package. LXT981 LXT981 Block Diagram 100 Mbps Backplane 100BASE-T 100BASE-T Repeater Twisted Pair_I/O 100Mbps E'net PHY 100M IRB 100Mbps E'net PHY Twisted Pair_I/O 100Mbps E'net PHY Twisted Pair_I/O 100Mbps E'net PHY Twisted Pair_I/O Fiber_I/O Fiber_I/O Mode Control Serial Management Port & Mgmt Status Indicators Serial Port Device Management LED Drivers RMON & SNMP Counters Refer to www.level1.com for most current information. MII Fiber_I/O Fiber_I/O Reversible MII ) LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater TABLE OF CONTENTS Pin Assignments and Signal Descriptions . 4 Functional Description . 11 Introduction .17 Port Configuration .14 Interface Descriptions.17 100BASE-TX 100BASE-TX Interface.17 100BASE-FX 100BASE-FX Interface.17 Media Independent Interface (MII) .17 Serial Management Interface .18 Inter-Repeater Backplane .18 Repeater Operation .18 Management Support .19 Configuration and Status.19 SNMP and RMON Support .19 Source Address Management Functions .19 LED Drivers .19 Requirements .19 Power .19 Clock .19 Bias Current .19 Reset .20 PROM.20 ChipID .20 Management Master I/O Link .20 IRB Bus Pull-ups .20 LED Operation.20 Blink Rates .20 Power-Up and Reset Conditions .20 Port LEDs .20 Segment LEDs .21 Management LEDs.21 IRB Operation.22 IRB Isolation . 22 MMSTRIN, MMSTROUT . 22 MII Port Operation .25 PHY Mode Operation .25 MAC Mode Operation.25 MII Port Timing Considerations .25 Serial Management Interface .27 Serial Clock . 27 Serial Data I/O .27 Read and Write Operations .27 Management Frame Format .27 Auto-Clearing Registers .28 2 LXT981 LXT981 Table of Contents Interrupt Functions .28 Address Arbitration.30 Serial EEPROM Interface . 32 Application Information . 33 General Design Guidelines . 33 Power Supply Filtering. 33 Power and Ground Plane Considerations . 34 MII Terminations . 34 The RBIAS Pin . 34 The Twisted-Pair Interface. 34 The Fiber Interface . 34 Magnetics Information . 35 Typical Application Circuitry . 36 Test Specifications . 43 Absolute Maximum Ratings . 43 Recommended Operating Conditions . 43 Input Clock Requirements. 43 I/O Electrical Characteristics . 44 IRB Electrical Characteristics. 44 100BASE-TX 100BASE-TX Transceiver Electrical Characteristics. 45 100BASE-FX 100BASE-FX Transceiver Electrical Characteristics. 45 Port-to-Port Delay Timing. 46 100BASE-TX 100BASE-TX Timing - PHY Mode MII . 47 100BASE-TX 100BASE-TX Timing - MAC Mode MII . 49 100BASE-FX 100BASE-FX Timing - PHY Mode MII . 51 100BASE-FX 100BASE-FX Timing - MAC Mode MII . 53 IRB Timing . 55 Serial Management Timing . 56 PROM Interface Timing. 56 Register Definitions. 57 Counter Registers . 57 Ethernet Address Registers . 61 Control and Status Registers . 62 Configuration Registers. 68 Mechanical Specifications. 73 Revision History . 74 ) 3 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS 52 . IRCLK 51 . VCC 50 . GND 49 . IRDAT4 48 . N/C 47 . N/C 46 . IRDAT3 45 . IRDAT2 44 . IRDAT1 43 . IRDAT0 42 . IRDV 41 . IRDEN 40 . IRCOL 39 . N/C 38 . IRSNGL 37 . IRCFSBP 36 . IRCFS 35 . VCC 34 . GND 33 . MII_RXD3 32 . MII_RXD2 31 . N/C 30 . MII_RXD1 29 . MII_RXD0 28 . VCC 27 . GNDA 26 . MII_RXDV 25 . MII_RXCLK 24 . MII_RXER 23 . N/C 22 . MII_TXER 21 . MII_TXCLK 20 . MII_TXEN 19 . MII_TXD0 18 . MII_TXD1 17 . MII_TXD2 16 . MII_TXD3 15 . N/C 14 . MII_COL 13 . MII_CRS 12 . VCC 11 . GND 10 . N/C 9 . N/C 8 . N/C 7 . N/C 6 . N/C 5 . N/C 4 . N/C 3 . N/C 2 . GND 1 . N/C Figure 1: LXT981 LXT981 Pin Assignments LXT981 LXT981 208 . LEDSEL0 207 . LEDSEL1 206 . VCC 205 . VCC 204 . VCC 203 . VCC 202 . GND 201 . VCC 200 . GND 199 . MMSTRIN 198 . ARBIN 197 . CONFIG0 196 . CONFIG1 195 . CONFIG2 194 . CONFIG3 193 . CONFIG4 192 . CONFIG5 191 . CONFIG6 190 . CONFIG7 189 . PORT1_SEL 188 . VCC 187 . PORT2_SEL 186 . VCC 185 . PORT3_SEL 184 . VCC 183 . PORT4_SEL 182 . VCC 181 . PORT1_LED1 180 . PORT1_LED2 179 . N/C 178 . GND 177 . PORT2_LED1 176 . PORT2_LED2 175 . N/C 174 . GND 173 . PORT3_LED1 172 . PORT3_LED2 171 . N/C 170 . VCC 169 . VCCV 168 . GNDV 167 . GND 166 . PORT4_LED1 165 . PORT4_LED2 164 . N/C 163 . GND 162 . PORT5_LED1 161 . PORT5_LED2 160 . N/C 159 . GND 158 . GND 157 . FIBIP1 TPIP4 . 105 TPIN4 . 106 VCCR . 107 TPOP4 . 108 GNDT . 109 TPON4 . 110 VCCT . 111 FIBOP4 . 112 FIBON4 . 113 SIGDET4 . 114 FIBIN4 . 115 FIBIP4 . 116 GNDR . 117 TPIP3 . 118 TPIN3 . 119 VCCR . 120 TPOP3 . 121 GNDT . 122 TPON3 . 123 VCCT . 124 FIBOP3 . 125 FIBON3 . 126 SIGDET3 . 127 FIBIN3 . 128 FIBIP3 . 129 GNDA . 130 RBIAS . 131 GNDR . 132 TPIP2 . 133 TPIN2 . 134 VCCR . 135 TPOP2 . 136 GNDT . 137 TPON2 . 138 VCCT . 139 FIBOP2 . 140 FIBON2 . 141 SIGDET2 . 142 FIBIN2 . 143 FIBIP2 . 144 GNDR . 145 TPIP1 . 146 TPIN1 . 147 VCCR . 148 TPOP1 . 149 GNDT . 150 TPON1 . 151 VCCT . 152 FIBOP1 . 153 FIBON1 . 154 SIGDET1 . 155 FIBIN1 . 156 RESET . 53 CLK25 CLK25 . 54 N/C . 55 IRISO . 56 VCC . 57 RECONFIG . 58 SRX . 59 STX . 60 SERCLK . 61 SER_MATCH . 62 MMSTROUT . 63 ARBOUT . 64 ARBSELECT . 65 MGR_PRES . 66 PROM_CLK . 67 PROM_CS . 68 PROM_DTOUT . 69 PROM_DTIN . 70 CHIPID0 . 71 CHIPID1 . 72 CHIPID2 . 73 GND . 74 GND . 75 VCC . 76 RPS_FAULT . 77 RPS_PRES . 78 N/C . 79 N/C . 80 IRQ . 81 GND . 82 GND . 83 VCC . 84 N/C . 85 COL_LED . 86 MGR_LED . 87 GND . 88 VCC . 89 N/C . 90 ACT_LED . 91 FAULT_LED . 92 GND . 93 VCCV . 94 GNDV . 95 VCC . 96 N/C . 97 RPS_LED . 98 PORT5_SEL . 99 VCC . 100 N/C . 101 N/C . 102 N/C . 103 GNDR . 104 4 LXT981 LXT981 Pin Assignments and Signal Descriptions Table 1: Mode Control Signal Descriptions Pin Symbol 189 PORT1_SEL 187 PORT2_SEL 185 PORT3_SEL 183 PORT4_SEL 99 PORT5_SEL Type1 Description TTL Input PU Mode Select - Ports 1 through 4. These pins set the default value of the Port Mode Control Register for the associated port as follows: Latched on reset Low = 100BASE-FX 100BASE-FX Input, PU Mode Select - Port 5. Selects operating mode of the MII interface. Pin is monitored at power-up and reset. Subsequent changes have no effect. High = PHY Mode (LXT981 LXT981 acts as PHY side of the MII) Low = MAC Mode (LXT981 LXT981 acts as MAC side of the MII) High = 100BASE-TX 100BASE-TX 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down. I/O = Input / Output TTL = Transistor-Transistor Logic. Table 2: Twisted-Pair Port Signal Descriptions Pin Symbol Type Description 149, 151 TPOP1, TPON1 Analog 136, 138 TPOP2, TPON2 Output Twisted-Pair Outputs - Ports 1 through 4. These pins are the positive and negative outputs from the respective ports' twisted-pair line drivers. These pins can be left open when not used. 121, 123 TPOP3, TPON3 108, 110 TPOP4, TPON4 146, 147 TPIP1, TPIN1 Analog 133, 134 TPIP2, TPIN2 Input Twisted-Pair Inputs - Ports 1 through 4. These pins are the positive and negative inputs to the respective ports' twisted-pair receivers. These pins can be left open when not used. 118, 119 TPIP3, TPIN3 105, 106 TPIP4, TPIN4 Table 3: Fiber Port Signal Descriptions Pin Symbol 153, 154 FIBOP1, FIBON1 140, 141 FIBOP2, FIBON2 125, 126 FIBOP3, FIBON3 Type Description Output PECL Fiber Outputs - Ports 1 through 4. These pins are the positive and negative outputs from the respective ports' PECL drivers. These pins can be left open when not used. 112, 113 FIBOP4, FIBON4 ) 5 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Table 3: Fiber Port Signal Descriptions ­ continued Pin Symbol Type Description Input PECL Fiber Inputs - Ports 1 through 4. These pins are the positive and negative inputs to the respective ports' PECL receivers. These pins can be left open when not used. Input PECL 157, 156 FIBIP1, FIBIN1 Signal Detect - Ports 1 through 4. Signal detect for the fiber ports. These pins can be left open when not used. 144, 143 FIBIP2, FIBIN2 129, 128 FIBIP3, FIBIN3 116, 115 FIBIP4, FIBIN4 155 SIGDET1 142 SIGDET2 127 SIGDET3 114 SIGDET4 Table 4: PHY Mode MII Interface Signal Descriptions Pin Symbol Type1 29 MII_RXD0 Output 30 MII_RXD1 Receive Data. The LXT981 LXT981 transmits received data to the controller on these outputs. Data is driven on the falling edge of MII_RXCLK. 32 MII_RXD2 33 MII_RXD3 26 MII_RXDV Output Receive Data Valid. Active High signal, synchronous to MII_RXCLK, indicates valid data on MII_RXD. 25 MII_RXCLK Output Receive Clock. MII receive clock for expansion port. This is a 2.5 or 25 MHz clock derived from the CLK25 CLK25 input (refer to Table 11). 24 MII_RXER Output Receive Error. Active High signal, synchronous to MII_RXCLK, indicates invalid data on MII_RXD. 22 MII_TXER Input Transmit Error. The MAC asserts this input when an error has occurred in the transmit data stream and responds by sending `Invalid Code Symbols' on the line. 21 MII_TXCLK 20 MII_TXEN Input Transmit Enable. External controllers drive this input High to indicate that data is being transmitted on the MII_TXD pins. Tie this input Low if it is unused. 19 MII_TXD0 Input 18 MII_TXD1 17 MII_TXD2 Transmit Data. External controllers use these inputs to transmit data to the LXT981 LXT981. The LXT981 LXT981 samples MII_TXD on the rising edge of MII_TXCLK, when MII_TXEN is High. 16 MII_TXD3 14 MII_COL Output Collision. Signal is driven High to indicate that a collision has occurred. 13 MII_CRS Output Carrier Sense. Active High signal indicates transmitting or receiving. Output Description Transmit Clock. 2.5 or 25 MHz continuous output derived from the 25 MHz input clock. 1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for PHY mode. All MII signals are Transistor-Transistor Logic (TTL). 6 LXT981 LXT981 Pin Assignments and Signal Descriptions Table 5: MAC Mode MII Interface Signal Descriptions Pin Symbol Type1 29 MII_RXD0 Input 30 MII_RXD1 Receive Data. The LXT981 LXT981 receives data from the PHY on these pins. Data is sampled on the rising edge of MII_RXCLK. 32 MII_RXD2 33 MII_RXD3 26 MII_RXDV Input Receive Data Valid. The PHY asserts this active High signal, synchronous to MII_RXCLK, to indicate valid data on MII_RXD. 25 MII_RXCLK Input Receive Clock. MII receive clock for expansion port. This is a 25 MHz clock. 24 MII_RXER Input Receive Error. The PHY asserts this active High signal, synchronous to MII_RXCLK, to indicate invalid data on MII_RXD. Description Transmit Error. The LXT981 LXT981 asserts this signal asserted when an error has occurred in the transmit data stream. 22 MII_TXER Output 21 MII_TXCLK Input Transmit Clock. 25 MHz continuous input clock. Must be supplied from same source as CLK25 CLK25 system clock. 20 MII_TXEN Output Transmit Enable. The LXT981 LXT981 drives this output High to indicate that data is being transmitted on the MII_TXD pins. 19 MII_TXD0 Output 18 MII_TXD1 17 MII_TXD2 Transmit Data. The LXT981 LXT981 drives these outputs to transmit data to the PHY. The device drives MII_TXD on the rising edge of MII_TXCLK, when MII_TXEN is High. 16 MII_TXD3 14 MII_COL Input Collision. The PHY asserts this active High signal to notify the LXT981 LXT981 that a collision has occurred. 13 MII_CRS Input Carrier Sense. The PHY asserts this active High signal to notify the LXT981 LXT981 that the PHY is transmitting or receiving. 1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for MAC mode. All MII signals are Transistor-Transistor Logic (TTL). ) 7 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Table 6: Inter-Repeater Backplane Signal Descriptions Pin Symbol Type1 Description2 TTL Input PD, NC Management Master Input. The Management Master (MM) daisy chain ensures that collisions will be counted correctly in multi-board applications. Attach the MMSTRIN input of each device to the MMSTROUT output of the previous device. Ground MMSTRIN of the first or only device. 199 MMSTRIN 63 MMSTROUT 36 IRCFS Analog I/O IRB Collision Force Sense. IRCFS is a three-level signal that determines the number of active ports on the "logical repeater." High level (5V) indicates no ports active; Mid level (approx. 2.8V) indicates one port active; Low level (0V) indicates more than one port active, resulting in a collision. This signal requires a 240 pull-up resistor and connects between chips on the same board. Do not connect between boards. 37 IRCFSBP Analog IO, NC IRB Collision Force Sense - Backplane. This three-level signal functions the same as IRCFS, but connects between chips with ChipID = 0, on different boards. This signal requires a single 82 pull-up resistor on each stack. 38 IRSNGL I/O, Schmitt MOS PU Single Driver State. This active Low signal is asserted by the device with ChipID = 000 when a packet is being received from one or more ports. This signal should not be connected between boards. 40 IRCOL I/O, Schmitt MOS PU 100 Mbps Multiple Driver State. This active Low signal is asserted by the device with ChipID = 000 when a packet is being received from more than one port (collision). It should not be connected between boards. 41 IRDEN Open Drain Output IRB Driver Enable. This output provides directional control for an external bidirectional transceiver (`245) used to buffer the 100 Mbps IRB in multiboard applications. It must be pulled up by a 330 resistor. When there are multiple devices on one board, tie all IRDEN outputs together. If IRDEN is tied directly to the DIR pin on a `245, attach the on-board IRDAT, IRCLK and IRDV signals to the "B" side of the `245, and connect the off-board signals to the "A" side of the `245. 42 IRDV I/O, Open Drain, Schmitt MOS PU IRB Data Valid. This active Low signal indicates repeater port activity. IRDV frames the clock and data of the packet on the backplane. This signal requires a 120 pull-up resistor. 43 44 45 46 49 IRDAT0 IRDAT1 IRDAT2 IRDAT3 IRDAT4 I/O Tri-state IRB Data. These bidirectional signals carry data on the IRB. Data is driven on the falling edge and sampled on the rising edge of IRCLK. These signals can be buffered between boards. Output Management Master Output. MM daisy chain output. In hot-swap applications, a 1 k - 3 k resistor can be used as a bypass between MMSTRIN and MMSTROUT. Schmitt MOS PU 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down. I/O = Input / Output. 2. Even if the IRB is not used, required pull-up resistors must be installed as listed above. 8 LXT981 LXT981 Pin Assignments and Signal Descriptions Table 6: Inter-Repeater Backplane Signal Descriptions ­ continued Pin Symbol Type1 Description2 52 IRCLK I/O Tri-state Schmitt MOS, PD IRB Clock. This bidirectional, non-continuous, 25 MHz clock is recovered from received network traffic. Schmitt triggering is used to increase noise immunity. This signal must be pulled to VCC when idle. One 1 k pull-up resistor on both sides of a `245 buffer is recommended. 56 IRISO Output Stack IRB Isolate. This output allows one LXT981 LXT981 per board the ability to enable or disable an external bidirectional transceiver (`245). Attach the output to the Enable input of the `245. The output is driven High (disable) to isolate the IRB. 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down. I/O = Input / Output. 2. Even if the IRB is not used, required pull-up resistors must be installed as listed above. Table 7: Serial Management Interface Signal Descriptions Type1 Description TTL Input PD, NC Reconfigure. This input controls the driving of the clock signal on the high-speed Serial Management Interface (SERCLK). When this input is High, the LXT981 LXT981 drives SERCLK with a 625 kHz output. When this input is Low, SERCLK is an input to the LXT981 LXT981. In addition, a Low-to-High transition on RECONFIG causes the LXT981 LXT981 to drive 13 continuous 0s on the Serial Management Interface (SMI), causing a re-arbitration to occur. Pin Symbol 58 RECONFIG 62 SER_MATCH 59 SRX TTL Input, PD Serial Receive. Receive data input for the SMI. Must be tied to STX externally. SRX is sampled on the rising edge of SERCLK. 60 STX Open Drain Output Serial Transmit. Transmit data output for the SMI. Must be tied to SRX externally. Data transmitted on STX is compared with data received on SRX. In the event of a mismatch, STX is put in the high impedance state. STX is driven on the falling edge of SERCLK. 61 SERCLK TTL Output, Tri-state, PD Serial Clock. Clock for the SMI. Depending on RECONFIG, this pin is either a 625 kHz output or a 0 to 2 MHz input. 198 ARBIN TTL Input, PD, NC 64 ARBOUT Output, NC Output Serial Match. The LXT981 LXT981 device with ChipID = 0 asserts this active High output whenever it detects a message on the SMI that matches the local Hub ID. Refer to Figure 10 on page 29. Arbitration In/Out. Used with Chain Arbitration. If used, tie ARBIN to ARBOUT of the previous device. ARBIN at the top of the daisy chain can be connected to ground or to ARBOUT of the SCC. If unused, tie ARBIN High. 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. ) 9 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Table 7: Serial Management Interface Signal Descriptions ­ continued Pin Symbol Type1 65 ARBSELECT TTL Input, PU 66 MGR_PRES Input, PU, NC Description Arbitration Mode Select. 0 = EEPROM based, 1 = chain based. Manager Present. This signal is sensed at power-up and hardware reset. If the signal is High, it indicates that no local manager is present, and the LXT981 LXT981 enables all ports and sets all LEDs to operate in "hardware mode". If it is Low, indicating that a manager is present, the LXT981 LXT981 disables all ports, pending control of network manager. 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. Table 8: LED Signal Descriptions Pin Type1 Symbol 208 LEDSEL0 207 PORT1_LED1 177 PORT2_LED1 173 PORT3_LED1 166 PORT4_LED1 162 PORT5_LED1 180 PORT1_LED2 176 PORT2_LED2 172 PORT3_LED2 165 PORT4_LED2 161 PORT5_LED2 86 TTL Input, PD LED Mode Select. Must be static. LEDSEL1 181 Description 00 = Mode 1, 01 = Mode 2, 10 = Mode 3 Output LED Driver 1 - Ports 1 through 5. Programmable LED driver. Active Low. Refer to "Port LEDs" on page 20. Output LED Driver 2 - Ports 1 through 5. Programmable LED driver. Active Low. Refer to "Port LEDs" on page 20. COL_LED Output Collision LED Driver. Active Low indicates collision. 87 MGR_LED Output Manager Present LED Driver. Active Low indicates Manager present. 91 ACT_LED Output Activity LED Driver. Active Low indicates activity. 92 FAULT_LED Output Fault LED Driver. Active Low indicates global fault. 98 RPS_LED Output Remote Power Supply LED Driver. Active Low indicates RPS fault. 1. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. 10 LXT981 LXT981 Pin Assignments and Signal Descriptions Table 9: PROM Interface Signal Descriptions Type1 Pin Symbol Description 67 PROM_CLK 68 PROM_CS Output Tri-State PROM Chip Select. Selects EPROM. An active High signal driven only by the chip with ID of 0. 69 PROM_DTOUT Output Tri-State PROM Data Output. Selects read instruction for EPROM. Active High signal driven only by the chip with ID of 0. 70 PROM_DTIN TTL Input TriState Output, PD TTL Input, PD PROM Clock. 1 MHz clock for reading PROM data (ChipID = 0). If a PROM is not used, this pin must be tied Low. PROM Data Input. If PROM not used, can be tied Low or High. 1. PD = Input contains pull-down. Table 10: Power Supply and Indication Signal Descriptions Pin Symbol Type1 Description 12, 28, 35, 51, 57, 76, 84, 89, 96, 100, 170, 182, 184, 186, 188, 201, 203206 VCC Digital Power Supply Inputs. Each of these pins must be connected to a common +5 VDC power supply. A de-coupling capacitor to digital ground should be supplied for every one of these pins. 2, 11, 34, 50, 74, 75, 82, 83, 88, 93, 158, 159, 163, 167, 174, 178, 200, 202 GND Digital Ground. Connect each of these pins to digital ground. 94, 169 VCCV Analog VCO Supply Inputs. Each of these pins must be connected to a common +5 VDC power supply. A de-coupling capacitor to GNDV should be supplied for each of these pins 95, 168 GNDV Analog VCO Ground. 111, 124, 139, 152 VCCT Analog Transmitter Supply Inputs. Each of these pins must be connected to a common +5 VDC power supply. A de-coupling capacitor to GNDT should be supplied for every one of these pins. 109, 122, 137, 150 GNDT Analog Transmitter Ground. 107, 120, 135, 148 VCCR Analog Receiver Supply Inputs. Each of these pins must be connected to a common +5 VDC power supply. A de-coupling capacitor to GNDR should be supplied for every one of these pins 1. PU = Input contains pull-up; PD = Input contains pull down. ) 11 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Table 10: Power Supply and Indication Signal Descriptions ­ continued Pin Symbol Type1 Description 104, 117, 132, 145, GNDR Analog Receiver Ground. 131 RBIAS Analog RBIAS. Used to provide bias current for internal circuitry. The 100 µA bias current is provided through an external 22.1 k, 1% resistor to GNDA. 27, 130 GNDA Analog Analog Ground. 78 RPS_PRES TTL Input, PD Redundant Power Supply Present. Active High input indicates presence of redundant power supply. Tie Low if not used. 77 RPS_FAULT TTL Input, PU Redundant Power Supply Fault. Active Low input indicates redundant power supply fault. The state of this input is reflected in the RPS_LED output (refer to Table 8). Tie High if not used. 1. PU = Input contains pull-up; PD = Input contains pull down. Table 11: Miscellaneous Signal Descriptions Pin Symbol Type1 Description 53 RESET CMOS Input Schmitt, NC Reset. This active Low input causes internal circuits, state machines, and counters to reset (address tracking registers do not reset). On power-up, devices should not be brought out of reset until the power supply has stabilized and reached 4.5V. When there are multiple devices, it is recommended that all be supplied by a common reset that is driven by an `LS14 or similar device. 54 CLK25 CLK25 CMOS Input Schmitt 25 MHz system clock. Drive with MOS levels. 71 CHIPID0 72 CHIPID1 73 CHIPID2 81 IRQ TTL Input, PD Chip ID. These pins assign unique ChipIDs to as many as eight devices on a single board. One device on each board must be assigned ChipID = 0. Open Drain Output Interrupt request. Active Low interrupt. Refer to Tables 58 and Figure 59 on page 66 for criteria and clearing options. 1. NC = No Clamp. Pad will not clamp input in the absence of power PU = Input contains pull-up; PD = Input contains pull down. TTL = Transistor-Transistor Logic. 12 LXT981 LXT981 Pin Assignments and Signal Descriptions Table 11: Miscellaneous Signal Descriptions ­ continued Pin Symbol 197 196 195 194 193 192 191 190 CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 CONFIG7 1, 3-10, 15, N/C 23, 31, 39, 47, 48, 55, 79, 80, 85, 90, 97, 101-103, 160, 164, 171, 175, 179 Type1 TTL Input Description Configuration Register Inputs. These inputs allow the user to store system-specific information (board type, plug-in cards, status, etc.) in the Serial Configuration Register (address AC). This register may be read remotely through the Serial Management Interface. PD - No Connects. Leave these pins unconnected. 1. NC = No Clamp. Pad will not clamp input in the absence of power PU = Input contains pull-up; PD = Input contains pull down. TTL = Transistor-Transistor Logic. ) 13 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater FUNCTIONAL DESCRIPTION Introduction As a fully integrated IEEE 802.3 repeater with 100 Mbps functionality, the LXT981 LXT981 is a very versatile device allowing great flexibility in Ethernet design solutions. Figures 2, 3, and 4 show some typical applications, and Figure 5 shows a more complete I/O circuit. Refer to Application Information (page 33) for specific circuit implementations. This multi-port repeater provides four 100BASE-TX/ 100BASE-TX/ 100BASE-FX 100BASE-FX ports. In addition, there is a bidirectional Media Independent Interface (MII) expansion port that may be connected to either a MAC, or to a PHY. The LXT981 LXT981 incorporates RMON support by providing on-chip counters and hardware assistance for a fully managed environment. The backplane allows multiple devices to be stacked and function as one logical repeater. Port Configuration At power-up, hardware reset or software reset (but not at repeater reset), the LXT981 LXT981 reads the hardware configuration pins to determine operating conditions for each of its ports. Each of the four media ports has its own configuration pin (PORTn_SEL) to select 100TX 100TX or 100FX 100FX operation (High = TX, Low = FX). The LXT981 LXT981 provides a repeater state machine and an Inter-Repeater Backplane (IRB) for 100 Mbps operation. The repeater fully meets IEEE 802.3 Class II requirements. Each port may be configured independent of the other ports. Figure 2: Typical LXT981 LXT981 Managed Repeater Architectures LXT981 LXT981 LXT981 LXT981 Chassis Backplane 100 Mbps 100M Backplane LXT981E LXT981E'net PHY Buffer 100M Backplane 100 Mbps 100 Mbps 100BASE-T 100BASE-T E'net PHY Backplane Repeater 100 Mbps 100 Mbps 100BASE-T 100BASE-T E'net PHY Backplane Repeater 100 Mbps 100BASE-T 100BASE-T 1 Backplane Repeater0 0 M b p s E'net PHY 100 Mbps E'net PHY Device 100 Mbps Management E'net PHY Serial Port Device Management 100 Mbps Device M a n a g e mE'net 0 0 M b p s e n t 1 PHY Serial Port E'net PHY 100 Mbps MII E'net PHY RMON & SNMP MII RMON & 100 Mbps Counters SNMP MII R M O N E'net 0 0 M b p s & 1 PHY Counters LED Drivers SNMP E'net PHY 100 Mbps Counters LED Drivers E'net PHY LED Drivers Serial Port Serial Management to SCC (8530) 14 ) LXT981 LXT981 Functional Description Figure 3: Typical Unmanaged Repeater Architectures LXT981 LXT981 LXT981 LXT981 100 Mbps LXT981E LXT981E'net PHY 100M Backplane Chassis Backplane Buffer 100M Backplane 100 Mbps 100 Mbps 100BASE-T 100BASE-T E'net PHY Backplane Repeater 100 Mbps 100 Mbps 100BASE-T 100BASE-T E'net PHY Backplane Repeater 100 Mbps 100BASE-T 100BASE-T 1 Backplane Repeater0 0 M b p s E'net PHY 100 Mbps E'net PHY Device 100 Mbps Management E'net PHY Serial Port Device Serial Port Serial Port Management 100 Mbps Device M a n a g e mE'net 0 0 M b p s e n t 1 PHY E'net PHY 100 Mbps E'net PHY MII RMON & SNMP RMON & 100 Mbps Counters SNMP MII R M O N E'net 0 0 M b p s & 1 PHY Counters LED Drivers SNMP E'net PHY 100 Mbps Counters LED Drivers E'net PHY LED Drivers MII LED Banks Figure 4: Typical Hybrid Switch/Repeater Application LXT981 LXT981 100M Backplane Chassis Backplane LXT981 LXT981 100 Mbps LXT981E LXT981E'net PHY Buffer 100M Backplane Serial Management to SCC (8530) MII Switch Connection ) 100 Mbps 100 Mbps 100BASE-T 100BASE-T E'net PHY Backplane Repeater 100 Mbps 100 Mbps 100BASE-T 100BASE-T E'net PHY Backplane Repeater 100 Mbps 100BASE-T 100BASE-T 1 Backplane Repeater0 0 M b p s E'net PHY 100 Mbps E'net PHY Device 100 Mbps Management E'net PHY Serial Port Device Management 100 Mbps Device M a n a g e mE'net 0 0 M b p s e n t 1 PHY Serial Port E'net PHY 100 Mbps MII E'net PHY RMON & SNMP MII RMON & 100 Mbps Counters SNMP MII R M O N E'net 0 0 M b p s & 1 PHY Counters LED Drivers SNMP E'net PHY 100 Mbps Counters LED Drivers E'net PHY LED Drivers Serial Port 15 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Figure 5: Typical LXT981 LXT981 Application Block Diagram Xfmrs SCC Serial Mgmt I/F SRX STX 8530 LXT981 LXT981 SERCLK RECONFIG MG_PRSNT MII_RXCLK MII_RXD MII_RXDV MII_RXER MII_COL MII_CRS MII_TXCLK MII_TXD MII_TXEN MII_TXER MII (Port 5, PHY Mode) 4 100-TX 100-TX Ports TP2 TP3 TP4 Fiber Module FIBOP1 FIBON1 FIBIP1 FIBIN1 SIGDET1 4 100-FX 100-FX Ports FO2 FO3 FO4 CHIPID2 CHIPID1 CHIPID0 ChipID assignment HubID assignment RJ45s TPOP1 TPON1 TPIP1 TPIN1 PROM_CS PROM_DTOUT PROM_CLK PROM_DTIN PROM to next LXT981 LXT981 MMSTRIN MMSTROUT Resistor Packs V C C PORT1_LED1 PORT1_LED2 PORT2_LED1 PORT2_LED2 Inter-Repeater Backplane PORT3_LED1 PORT3_LED2 IRCOL IRCFS IRSNGL Local IRB to onboard LXT981 LXT981 IRENA IRDAT IRCLK '245 InterModule IRB to stack connector 16 PORT4_LED1 PORT4_LED2 PORT5_LED1 PORT5_LED2 ACT_LED COL_LED IRDEN IRISO IRCOLBP IRCFSBP Port LEDs MGR_LED RPS_LED FAULT_LED Segment LEDs Global LEDs LXT981 LXT981 Functional Description Interface Descriptions 100BASE-TX 100BASE-TX Interface The twisted-pair interface for each port consists of two differential signal pairsone for transmit and one for receive. The transmit signal pair is TPOP/TPON, the receive signal pair is TPIP/TPIN. Refer to Table 2 for 100BASE-T 100BASE-T port pin assignments and signal descriptions. The twisted-pair interface for a given port is enabled at all times except when 100FX 100FX is selected. The transmitter is current driven and requires magnetics with 2:1 turns ratio. A 400 resistive load should be placed across the TPOP/N pair, in parallel with the magnetics. The centertap of the primary side of the transmit winding must be tied to a quiet VCC for proper operation. When the twisted-pair interface is disabled, the transmitter outputs are tri-stated. The receiver requires magnetics with a 1:1 turns ratio, and a load of 100. When the twisted-pair port is enabled, the receiver actively biases its inputs to approximately 2.8V. When the twisted-pair interface is disabled, no biasing is provided. A 4 k load is always present across the TPIP/TPIN pair. The LXT981 LXT981 sends and receives a continuous, scrambled 125 Mbaud MLT-3 waveform on this interface. In the absence of data, IDLE symbols are sent and received in order to keep the link up. 100BASE-FX 100BASE-FX Interface Each fiber interface consists of the FIBOP/FIBON (transmit) and FIBIP/FIBIN (receive) signal pair. Refer to Table 3 for 100BASE-FX 100BASE-FX port pin assignments and signal descriptions. Each interface also provides a Signal Detect input that can be tied to the corresponding output on the fiber transceiver for determining signal presence and quality. The transmit pair is biased to approximately 1.5V and generally must be AC-coupled to the transceiver. The receive pair will accommodate an input bias in the 2V5V range, and can be DC-coupled to the transceiver. Refer to Figure18 for a typical interface circuit. The fiber interface for each port is enabled when the mode select is set to 100FX 100FX, and is disabled in all other cases. When a fiber port is disabled, its outputs are pulled to ground, and its inputs are tri-stated. The input and output pins on unused fiber ports may be left unconnected. Each fiber port transmits and receives a continuous, 1V peak-to-peak, non-scrambled, NRZI waveform. The LXT981 LXT981 does not support scrambling on the fiber interface. Remote Fault Reporting The SD pin detects signal quality and reports a remote fault if the signal quality starts to degrade. Loss of signal quality will also block any further data from being received and causes loss of the link. The remote fault code consists of 84 consecutive 1s followed by a single 0, and is transmitted at least three times. The LXT981 LXT981 transmits the remote fault code and sets the associated interrupts when both of the following conditions are true: · Fiber mode is selected · Signal Detect indicates no signal, or the receive PLL cannot lock Media Independent Interface The LXT981 LXT981 supports a standard Media Independent Interface (MII) interface. This interface can be programmed to operate either as the PHY side of the interface (PHY mode) or as the MAC side of the interface (MAC mode). The MII always operates as a nibble-wide (4B) interface. Symbol mode (5B interface) is not supported on the LXT981 LXT981 MII. NOTE The MII does not auto-negotiate, auto-speed select, auto-link, or partition. ) 17 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Serial Management Interface The Serial Management Interface (SMI) provides system access to the status, control, and statistic gathering abilities of the LXT981 LXT981. The interface is designed to allow multiple devices to be managed from a single multi-drop (daisy-chain) connection, and to use the minimum number of signals (2) for ease of system design. The interface itself consists of two digital NRZ signals -clock and data. Refer to Table 7 for serial management I/F pin assignments and signal descriptions. Data is framed into HDLC-like packets, with a start/stop flag, header and CRC field for error checking. Zero-bit insertion/removal is used. The interface can operate at any speed from 0 to 2 Mbps. Address assignment is provided via one of two arbitration mechanisms which are activated whenever the device is powered up or reset/reconfigured. Refer to the section on the SMI Refer to "Address Arbitration" on page 30. Inter-Repeater Backplane The LXT981 LXT981 provides an Inter-Repeater Backplane (IRB), which allows multiple cascaded LXT981 LXT981 devices to function as one large repeater. Up to 240 ports can be supported in a single cascade (192 TP ports + 48 MII ports). This provides support for stackable and modular hub architectures. Refer to Table 6 on page 8 for IRB pin assignments and signal descriptions. Repeater Operation The LXT981 LXT981 contains a complete 100 Mbps Repeater State Machine (100RSM 100RSM) that is fully IEEE 802.3 Class II compliant. Multiple LXT981s can be cascaded on the IRB and operate as one repeater segment. Data from any port will be forwarded to any other port in the cascade. The IRB is a 5-bit symbol-mode interface. It is designed to be stackable. The LXT981 LXT981 maintains a complete set of statistics for its local repeater segment. These are accessible through the high-speed management interface. The LXT981 LXT981 performs the following 100 Mbps repeater functions: · Signal amplification, wave-shape restoration, and data-frame forwarding. 18 · Handling of received code violations. The LXT981 LXT981 will substitute the "H" symbol for all invalid received codes. · SOP, SOJ, EOP, EOJ delay 32-bits) running at a high clock rate. General Design Guidelines Adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. Up to 50 mV of noise is considered acceptable. 50 to 80 mV of noise is considered marginal. High-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: · Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC or ground plane that is not located adjacent to the signal layer. · Use ample bulk and decoupling capacitors throughout the design (a value of .01 µF is recommended for decoupling caps). · Provide ample power and ground planes. · Provide termination on all high-speed switching signals and clock lines. · Provide impedance matching on long traces to prevent reflections. · Route high-speed signals next to a continuous, unbroken ground plane. · Filter and shield DC-DC converters, oscillators, etc. · Do not route any digital signals between the LXT981 LXT981 and the RJ45 connectors at the edge of the board. · Do not extend any circuit power or ground plane past the center of the magnetics or to the edge of the board. Use this area for chassis ground, or leave it void. Power Supply Filtering · DC-to-DC converters. Many of these issues can be improved just by following good general design guidelines. In addition, Level One also recommends filtering between the power supply and the analog VCC pins of the LXT981 LXT981. Filtering has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT981 LXT981, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI problems. The recommended implementation is to divide the VCC plane into two sections. The digital section supplies power to the digital VCC pin and to the external components. The analog section supplies power to VCCH, VCCT, and VCCR pins of the LXT981 LXT981. The break between the two planes should run under the device. In designs with more than one LXT981 LXT981, a single continuous analog VCC plane can be used to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 impedance at 100 MHz. The beads should be placed so that current flow is evenly distributed. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. Each LXT981 LXT981 draws a maximum of 500 mA from the analog supply so beads rated at 750 mA should be used. A bulk cap (2.2 -10 µF) should be placed on each side of each ferrite bead to stop switching noise from traveling through the ferrite. In addition, a high-frequency bypass cap (.01µf) should be placed near each analog VCC pin. Ground Noise The best approach to minimize ground noise is strict use of good general design guidelines and by filtering the VCC plane. Power supply ripple and digital switching noise on the VCC plane can cause EMI problems and degrade line performance. It is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having these problems: ) 33 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Power and Ground Plane Layout Considerations Great care needs to be taken when laying out the power and ground planes. The following guidelines are recommended: parasitic shunt capacitance in order to meet return loss specifications. These steps include: · Use compensating inductor in the output stage (see Figure 19 on page 40). · Place magnetics as close as possible to the LXT981 LXT981. · Keep transmit pair traces short. · Follow the guidelines in the LXT980 LXT980 Design and Layout Guide for locating the split between the digital and analog VCC planes. · Keep the digital VCC plane away from the TPOP/N and TPIP/N signals, away from the magnetics, and away from the RJ45 connectors. · Place the layers so that the TPOP/N and TPIP/N signals can be routed near or next to the ground plane. For EMI reasons, it is more important to shield TPOP and TPIP/N. Chassis Ground For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. Chassis ground should extend from the RJ45 connectors to the magnetics, and can be used to terminate unused signal pairs (`Bob Smith' termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kV isolation capacitor. In multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kV isolation to the Bob Smith termination. MII Terminations Series termination resistors are recommended on all MII signals driven by the LXT981 LXT981. The proper value = nominal trace impedance minus 13. If the nominal trace impedance is not known, use 55. · Do not route transmit pair adjacent to a ground plane. If possible, eliminate planes under the transmit traces completely. Otherwise, keep planes 3-4 layers away. · Some magnetic vendors are producing magnetics with higher than average return loss performance. Use of these improved magnetics increases the return loss budget available to the system designer. · Improve EMI performance by filtering the output centertap. A single ferrite bead may be used to supply centertap current to all four ports. In addition, follow all the standard guidelines for a twistedpair interface: · Route the signal pairs differentially, close together. Allow nothing to come between them. · Keep distances as short as possible; both traces should have the same length. · Avoid vias and layer changes as much as possible. · Keep the transmit and receive pairs apart to avoid cross-talk. · If possible, place entire receive termination network on one side and transmit on the other. · Keep termination circuits close together and on the same side of the board. · Always put termination circuits close to the source end of any circuit. · Bypass common-mode noise to ground on the inboard side of the magnetics using 0.01 µF capacitors. The RBIAS Pin The Fiber Interface The LXT981 LXT981 requires a 22.1 k, 1% resistor directly connected between the RBIAS pin and ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, and sink the other side of the resistor to ground. Surround the RBIAS trace with ground; do not run high-speed signals next to RBIAS. The fiber interface consists of a pseudo-ECL (PECL) transmit and receive pair to an external fiber optic transceiver. The transmit pair should be AC coupled to the transceiver, and biased to 3.7V with a 50 equivalent impedance. The receive pair can be DC-coupled, and should be biased to 3.0V with a 50 equivalent impedance. Figure 18 on page 39 shows the correct bias networks to achieve these requirements. The Twisted-Pair Interface Because the LXT981 LXT981 transmitter uses 2:1 magnetics, system designers must take extra precautions to minimize 34 ) LXT981 LXT981 Application Information Magnetics Information The LXT980 LXT980 requires a 1:1 ratio for the receive transformers and a 2:1 ratio for the transmit transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from static voltages across the connectors and cables. Refer to Table 21 for transformer specifications and Magnetic Manufacturers for Networking Product Applications (App. Note 73) for a reference list of compatible magnetic components. Before committing to a specific component, designers should test and validate the magnetics in the specific application to verify that system requirements are met. Table 21: LXT980 LXT980 Magnetics Specifications Parameter Min Nom Max Units Test Condition Rx turns ratio ­ 1:1 ­ ­ Tx turns ratio ­ 2:1 ­ ­ Insertion loss 0.0 ­ 1.1 dB Primary inductance 350 ­ ­ µH Transformer isolation ­ 2 ­ kV Differential to common mode rejection ­ ­ -40 dB .1 to 60 MHz ­ ­ -35 dB 60 to 100 MHz ­ ­ -16 dB 30 MHz ­ ­ -10 dB 80 MHz ­ ­ -20 dB 30 MHz ­ ­ -15 dB 80 MHz Return Loss - standard Return Loss - improved ) 80 MHz 35 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Typical Application Circuitry Figures 14 through 16 are simplified block diagrams showing typical applications. Figures 17 through 22 show application circuitry details. Figure 14: Managed Repeater Stack Serial Comm Controller (8530) Bridge (Optional) To 10M Repeater 10M MAC RMON (Optional) 100M MAC MAC Inter-Repeater Backplanes Inter-Repeater Backplanes LXT981 LXT981 LXT981 LXT981 MII 100M IRB 100M IRB MII MII 100M IRB 100M IRB MII Serial Port TP/Fiber Ports TP/Fiber Ports Serial Port Serial Port TP/Fiber Ports TP/Fiber Ports Serial Port 16 100-X 100-X Ports Figure 15: Unmanaged Repeater Stack Inter-Repeater Backplanes LXT981 LXT981 100M LEDs IRB TP/Fiber Ports Inter-Repeater Backplanes LXT981 LXT981 100M LEDs IRB MII MII TP/Fiber Ports LXT981 LXT981 LEDs TP/Fiber Ports 100M IRB MII LXT981 LXT981 100M LEDs IRB MII TP/Fiber Ports 16 100-X 100-X Ports 36 LXT981 LXT981 Application Information Figure 16: Hybrid Switch/Repeater Application Ethernet Switch Memory 100 Mbps MAC LXT981 LXT981 100M IRB TP/Fiber Ports MII 100 Mbps MAC LXT981 LXT981 100M IRB MII TP/Fiber Ports Control 100 Mbps MAC LXT981 LXT981 100M IRB MII TP/Fiber Ports 100 Mbps MAC LXT981 LXT981 100M IRB MII TP/Fiber Ports 16 100-X 100-X Ports ) 37 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Figure 17: Power and Ground Connections To Output Magnetics Centertap LXT981 LXT981 VCCT .1µF .01µF .1µF .01µF GNDT VCCV GNDV 22.1 k 1% RBIAS GNDA VCCR .1µF .01µF GNDR 1 0µF Analog Supply Plane + Ferrite Beads Digital Supply Plane 1 0µF VCC +5V 0.1µF GND 38 LXT981 LXT981 Application Information Figure 18: Typical Fiber Port Interface V C C T +5 V 1 69 : 69 0.1 PF : GNDA 0.01µF TD F I B O P n 0.01µF TD 191 LXT981 LXT981 : 191 : Fiber Txcvr GNDA SIGDETn 3 VCCR +5 V 2 80 : 80 To Fiber Network FIBONn 0.1 PF : GNDA FIBIN n RD FIBIP n RD 130 : 130 : GNDA 1. Suggested supply layout for fiber-only applications. In combination twisted-pair and fiber applications, use VCCD/GNDD. 2. If the Fiber Interface is not used, FIBIN, FIBIP, FIBON, FIBOP and SIGDET may be left unconnected. 3. Refer to fiber transceiver manufacturers recommendations for termination circuitry. Suitable fiber transceivers include the HFBR-5103 HFBR-5103 and HFBR-5105 HFBR-5105. ) 39 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Figure 19: Typical Twisted-Pair Port Interface Output Stage with Compensating Inductor 0.1µF 1 GNDR TPIP RJ45 50 1% 1:1 2 50 1% 3 75 TPIN 50 50 4 TPOP LXT981 LXT981 200 1% 5 6 50 320 nH TPON 200 1% 50 2:1 To Twisted-Pair Network 1 7 75 2 50 50 8 0.001µF/2kV VCCT 0.1µF .01µF GNDT 1. Receiver common mode bypass cap may improve BER performance in systems with noisy power supplies. 2. A single ferrite bead may be used to supply centertap current to all 4 ports. 40 LXT981 LXT981 Application Information Figure 20: Typical Serial Management Interface Connections VCC VCC 1k 1k STX '05 '05 VCC VCC VCC 1k 1k SRX 1k SERDAT '05 '05 * This resistor installed in base module only. Figure 21: Typical IRB Implementation +5V +5V +5V 1 k '245 IRCLKBP IRDATBP A B IRDVBP\ 1 k 240 1% 120 IRCLK IRDAT IRDV\ IRDV\ DIR 82 1%* IRCLK IRDAT 330 +5V IRDEN\ IRDEN\ IRCOL\ IRCFS\ IRSNGL IRCFSBP\ *Note: This resistor is installed in base module FPS only ) LXT981 LXT981 LXT981 LXT981 LXT981 LXT981 41 LXT981 LXT981 Single-Speed, 5-Port Fast Ethernet Repeater Figure 22: Typical Reset Circuit VCC D R2 C '14 t(CR1) > Power supply ramp up time. R2 discharges C when supply goes away. ` 14 needed for multiple LXT981 LXT981 devices. R1 42 LXT981 LXT981 Test Specifications TEST SPECIFICATIONS NOTE Tables 22 through 40 and Figures 23 through 34 represent the performance specifications of the LXT981 LXT981 and are guaranteed by test except, where noted, by design. The minimum and maximum values liste