LXT980/980A LXT980 100BASE-TX/10BASE-T 100BASE-FX LXT970 LXT980A 100BASE-TX - Datasheet Archive

 

Ethernet Repeater Datasheet General Description The LXT980 is a 5-port 10/100 Class II Repeater that is fully compliant with IEEE

 

LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Datasheet General Description The LXT980 LXT980 is a 5-port 10/100 Class II Repeater that is fully compliant with IEEE 802.3 standards. Four ports directly support either 100BASE-TX/10BASE-T 100BASE-TX/10BASE-T copper media or 100BASE-FX 100BASE-FX fiber media via pseudo-ECL (PECL) interfaces. The fifth port, a 10 or 100 Mbps Media Independent Interface (MII), connects to Media Access Controllers (MACs) for bridge/ switch applications. At 100 Mbps, the MII can also be configured to interface to another PHY device, such as the LXT970 LXT970. This data sheet applies to all LXT980 LXT980 products (LXT980 LXT980, LXT980A LXT980A, and any subsequent variants), except as specifically noted. The LXT980 LXT980 provides auto-negotiation with parallel detection for the four PHY ports. These ports can also be manually configured, either by hardware or software. The LXT980 LXT980 provides two internal repeater state machines-one operating at 10 Mbps and one at 100 Mbps. Once configured, the LXT980 LXT980 automatically connects each port to the appropriate repeater. The LXT980 LXT980 also provides two Inter-Repeater Backplanes (IRBs) for expansion - one operating at 10 Mbps and one at 100 Mbps. Up to 240 ports can logically be combined into one repeater using these buses. The LXT980 LXT980 supports SNMP and RMON management via on-chip 32- and 64-bit counters. The counters and control information are accessible via a high-speed Serial Management Interface (SMI). The device supports two Source Address Tracking registers per port and a Source Address Matching Function. Product Features s s s s s Four 10/100 ports with complete twistedpair PHYs including integrated filters and 100BASE-FX 100BASE-FX PECL interfaces. 10/100 MII port connection to either MAC or PHY. Independent segments for 10 and 100 Mbps operation. Cascadable Inter-Repeater Backplanes (IRBs). Hardware assist for RMON and the Repeater MIB. s s s s s s High-speed Serial Management Interface (SMI). Two address-tracking registers per port. Source Address matching function. Integrated LED drivers with user-selectable modes. Available in 208-pin QFP package. Case temperature range: 0-115°C. As of January 15, 2001, this document replaces the Level One document LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater. Order Number: 249111-001 January 2001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Contents 1.0 Pin Assignments and Signal Descriptions .10 2.0 Functional Description.20 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.0 Application Information .48 3.1 Datasheet Introduction.20 2.1.1 TP/FX Port Configuration .24 2.1.2 MII Port Configuration .25 2.1.3 Interface Descriptions.25 2.1.4 Repeater Operation.27 2.1.5 Management Support.29 2.1.6 LED Drivers .30 Requirements .30 2.2.1 Power .30 2.2.2 Clock .30 2.2.3 Bias Resistor .30 2.2.4 Reset .30 2.2.5 PROM.30 2.2.6 Chip ID .31 2.2.7 Management Master I/O Link .31 2.2.8 IRB Bus Pull-ups .31 LED Operation.31 2.3.1 Blink Rates .32 2.3.2 Power-Up and Reset Conditions .32 2.3.3 Port LEDs .32 2.3.4 Segment LEDs .32 2.3.5 Global LEDs .33 IRB Operation.35 2.4.1 MAC IRB Access.35 2.4.2 IRB Isolation .35 2.4.3 MMSTRIN, MMSTROUT.36 MII Port Operation .37 2.5.1 PHY Mode Operation .38 2.5.2 MAC Mode Operation.38 2.5.3 MII Port Timing Considerations .39 Serial Management I/F .40 2.6.1 Serial Clock .41 2.6.2 Serial Data I/O.41 2.6.3 Read and Write Operations.41 2.6.4 Interrupt Functions .43 2.6.5 Address Arbitration.44 Serial EEPROM Interface.46 Design Recommendations .48 3.1.1 General Design Guidelines .48 3.1.2 Power Supply Filtering .48 3.1.3 Power and Ground Plane Layout Considerations .49 3.1.4 MII Terminations.49 3 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 3.2 3.1.5 The RBIAS Pin . 50 3.1.6 The Twisted-Pair Interface . 50 3.1.7 The Fiber Interface. 50 3.1.8 Magnetics Information. 51 Typical Application Circuitry . 52 4.0 Test Specifications . 59 5.0 Register Definitions . 79 5.1 5.2 5.3 5.4 5.5 6.0 4 Counter Registers . 79 5.1.1 Port Counter Registers. 79 5.1.2 RMON Counter Registers . 81 Ethernet Address Registers . 82 5.2.1 Port Address Tracking Registers. 82 5.2.2 Search Address Registers . 83 Control and Status Registers . 83 5.3.1 Port Link Control Register . 83 5.3.2 General Port Control Registers . 84 5.3.3 Port Learn and Speed Control Registers . 85 5.3.4 Port Status Registers . 85 5.3.5 Interrupt Status/Mask Registers . 86 5.3.6 MII Status Register. 87 Configuration Registers. 88 5.4.1 Repeater Configuration Register. 89 Auto-Negotiation Registers . 92 Mechanical Specifications . 95 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater . 9 Pin Assignments .10 Typical Managed Repeater Architectures .21 Typical Unmanaged 100 Mbps Repeater Architectures .21 Typical Hybrid Switch/Repeater Application .22 Typical Application Block Diagram .23 IRB Block Diagram .36 MII (Port 5) Operation .38 MII Timing Issues .40 Typical Serial Bus Architecture .41 Serial Management Frame Format .43 Address Arbitration Mechanisms .46 Serial EEPROM Interface .47 Optional R/W Serial EEPROM Interface .47 Managed 10/100 Repeater Stack .52 Hybrid Switch/Repeater Application - for Balanced 10/100 Performance .52 Hybrid Switch/Repeater Application - Weighted Toward 100 Mbps Performance . 53 Unmanaged 100-Only Repeater Stack .53 Power and Ground Connections .54 Typical Fiber Port Interface .55 Typical Twisted-Pair Port Interface and Power Supply Filtering .56 Typical 100 Mbps IRB Implementation .57 Typical 10 Mbps IRB Implementation .57 Typical Serial Management Interface Connections .58 Typical Reset Circuit .58 100 Mbps Port-to-Port Delay Timing .63 100BASE-TX 100BASE-TX Transmit Timing - PHY MODE MII .64 100BASE-TX 100BASE-TX Receive Timing - PHY Mode MII .65 100BASE-TX 100BASE-TX Transmit Timing - MAC Mode MII .66 100BASE-TX 100BASE-TX Receive Timing - MAC Mode MII .67 100BASE-FX 100BASE-FX Transmit Timing - PHY Mode MII .68 100BASE-FX 100BASE-FX Receive Timing - PHY Mode MII .69 100BASE-FX 100BASE-FX Transmit Timing - MAC Mode MII .70 100BASE-FX 100BASE-FX Receive Timing - MAC Mode MII .71 10BASE-T 10BASE-T Transmit Timing - PHY Mode MII .72 10BASE-T 10BASE-T Receive Timing - PHY Mode MII .73 100 Mbps IRB Timing .74 10 Mbps IRB Receive Timing .75 10 Mbps IRB Transmit Timing .76 Serial Management Interface Timing .77 PROM Interface Timing .78 Package Specifications .95 5 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 6 Mode Control Signal Descriptions. 11 PHY Mode MII Interface Signal Descriptions . 11 MAC Mode MII Interface Signal Descriptions . 12 Inter-Repeater Backplane Signal Descriptions . 13 Twisted-Pair Port Signal Descriptions . 15 Fiber Port Signal Descriptions. 15 Serial Management Interface Signal Descriptions . 15 LED Signal Descriptions . 16 Power Supply and Indication Signal Descriptions . 17 PROM Interface Signal Descriptions. 18 Miscellaneous Signal Descriptions. 18 Manual Speed Selection . 24 LED Mode 1 Indications . 34 LED Mode 2 Indications . 34 LED Mode 3 Indications . 35 IRB Signal Types . 36 IRB Signal Details . 37 MII (Port 5) Mode & Speed Control. 38 Serial Management Interface Message Fields. 42 Serial Management Header Storage. 43 Serial Management Interface Command Set . 43 Typical Serial Management Packets. 44 Magnetics Specifications. 51 Absolute Maximum Ratings . 59 Operating Conditions . 59 Input Clock Requirements. 59 I/O Electrical Characteristics . 60 100 Mbps IRB Electrical Characteristics . 60 10 Mbps IRB Electrical Characteristics . 61 100BASE-TX 100BASE-TX Transceiver Electrical Characteristics. 61 100BASE-FX 100BASE-FX Transceiver Electrical Characteristics. 61 10BASE-T 10BASE-T Transceiver Electrical Characteristics . 62 100 Mbps Port-to-Port Delay Timing Parameters . 63 100BASE-TX 100BASE-TX Transmit Timing Parameters - PHY Mode MII. 64 100BASE-TX 100BASE-TX Receive Timing Parameters - PHY Mode MII. 65 100BASE-TX 100BASE-TX Transmit Timing Parameters - MAC Mode MII . 66 100BASE-TX 100BASE-TX Receive Timing - MAC Mode MII. 67 100BASE-FX 100BASE-FX Transmit Timing Parameters - PHY Mode MII. 68 100BASE-FX 100BASE-FX Receive Timing - PHY Mode MII . 69 100BASE-FX 100BASE-FX Transmit Timing - MAC Mode MII. 70 100BASE-FX 100BASE-FX Receive Timing - MAC Mode MII. 71 10BASE-T 10BASE-T Transmit Timing Parameters - PHY Mode MII . 72 10BASE-T 10BASE-T Receive Timing Parameters - PHY Mode MII . 73 100 Mbps IRB Timing Parameters1 . 74 10 Mbps IRB Receive Timing Parameters1 . 75 10 Mbps IRB Transmit Timing Parameters . 76 Serial Interface Timing Characteristics 1 . 77 PROM Interface Timing Characteristics. 78 Register Set . 79 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Datasheet Counter Register Bit Assignments .79 Port Counter Registers.80 RMON Counter Registers .81 Ethernet Address Register Bit Assignments .82 Port Address Tracking Registers.82 Search Address Registers.83 Port Link Control and Status Register Bit Assignments .83 Port Link Control Register .83 General Port Control and Status Register Bit Assignments .84 General Port Control Registers .84 Port Learn and Speed Control Registers .85 Port Learn and Speed Control Registers .85 Port Status Register Bit Assignments .85 Port Status Registers .86 Interrupt Status/Mask Register Bit Assignments .86 Interrupt Status/Mask Register.86 Interrupt Status Register Bit Definitions .87 MII Status Register Bit Assignment.87 MII Status Register.88 Configuration Registers.88 Repeater Configuration Register Bit Assignments .90 Repeater Configuration Register Bit Definitions.90 Device/Revision Register Bit Assignment .91 Global LED Control Register Bit Assignments .91 Port LED Control Register Bit Assignments .91 LED Timer Control Register Bit Assignments .91 Address Assignment Register Bit Assignments .91 EPROM Address Register Bit Assignments.91 Auto-Negotiation Registers .92 Auto-Negotiation Link Partner Ability Registers .92 Auto-Negotiation Status Registers .93 Auto-Negotiation Advertisement Register .93 Auto-Negotiation Configuration Register.94 7 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Revision History Revision 8 Date Description Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Figure 1. LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 100M IRB 10BASE-T 10BASE-T Repeater 10/100 E'net PHY 100 Mbps Backplane 100BASE-X 100BASE-X Repeater 10/100 E'net PHY Twisted Pair_I/O 10/100 E'net PHY Twisted Pair_I/O 10/100 E'net PHY Twisted Pair_I/O Mode Control Serial Mgmt Port & Mgmt Status Indicators Datasheet Twisted Pair_I/O 10 Mbps Backplane Serial Port Device Management LED Drivers RMON & SNMP Counters Port Switching Logic 10M IRB MII Fiber_I/O Fiber_I/O Fiber_I/O Fiber_I/O Reversible MII 9 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 1.0 Pin Assignments and Signal Descriptions 52. IR100CLK IR100CLK 51. VCC 50. GND 49. IR100DAT4 IR100DAT4 48. N/C 47. N/C 46. IR100DAT3 IR100DAT3 45. IR100DAT2 IR100DAT2 44. IR100DAT1 IR100DAT1 43. IR100DAT0 IR100DAT0 42. IR100DV IR100DV 41. IR100DEN IR100DEN 40. IR100COL IR100COL 39. N/C 38. IR100SNGL IR100SNGL 37. IR100CFSB IR100CFSB 36. IR100CFS IR100CFS 35. VCC 34. GND 33. MII_RXD3 32 . MII_RXD2 31. N/C 30. MII_RXD1 29. MII_RXD0 28. VCC 27. GNDA 26. MII_RXDV 25. MII_RXCLK 24. MII_RXER 23. N/C 22. MII_TXER 21. MII_TXCLK 20. MII_TXEN 19. MII_TXD0 18. MII_TXD1 17. MII_TXD2 16. MII_TXD3 15. N/C 14. MII_COL 13. MII_CRS 12. VCC 11. GND 10. IR10CLK IR10CLK 9. IR10DAT IR10DAT 8. IR10ENA IR10ENA 7. N/C 6. IR10DEN IR10DEN 5. IR10CFSBP IR10CFSBP 4. IR10COLBP IR10COLBP 3. IR10COL IR10COL 2. GND 1. IR10CFS IR10CFS Figure 2. Pin Assignments RESET .53 CLK25 CLK25 .54 IR10ISO IR10ISO .55 IR100ISO IR100ISO .56 VCC .57 RECONFIG .58 SRX .59 STX .60 SERCLK .61 SER_MATCH .62 MMSTROUT .63 ARBOUT .64 ARBSELECT .65 MGR_PRES .66 PROM_CLK .67 PROM_CS .68 PROM_DTOUT .69 PROM_DTIN .70 CHIPID0 .71 CHIPID1 .72 CHIPID2 .73 AUTO_BLINK/GND .74 GND .75 VCC .76 RPS_FAULT .77 RPS_PRES .78 MACACTIVE .79 HOLDCOL .80 IRQ .81 GND .82 GND .83 VCC .84 COL10 COL10_LED .85 COL100 COL100_LED .86 MGR_LED .87 GND .88 VCC .89 ACT10 ACT10_LED .90 ACT100 ACT100_LED .91 FAULT_LED .92 GND .93 VCCV .94 GNDV .95 VCC .96 N/C .97 RPS_LED .98 PORT5_SEL .99 PORT5_SPD .100 N/C .101 N/C .102 N/C .103 GNDR .104 LXT980 LXT980 XX XXXXXX XXXXXXXX Rev # TPIP4. 105 TPIN4. 106 VCCR. 107 TPOP4. 108 GNDT. 109 TPON4. 110 VCCT. 111 FIBOP4. 112 FIBON4. 113 SIGDET4. 114 FIBIN4. 115 FIBIP4. 116 GNDR. 117 TPIP3. 118 TPIN3. 119 VCCR. 120 TPOP3. 121 GNDT. 122 TPON3. 123 VCCT. 124 FIBOP3. 125 FIBON3. 126 SIGDET3. 127 FIBIN3. 128 FIBIP3. 129 GNDA. 130 RBIAS. 131 GNDR. 132 TPIP2. 133 TPIN2. 134 VCCR. 135 TPOP2. 136 GNDT. 137 TPON2. 138 VCCT. 139 FIBOP2. 140 FIBON2. 141 SIGDET2. 142 FIBIN2. 143 FIBIP2. 144 GNDR. 145 TPIP1. 146 TPIN1. 147 VCCR. 148 TPOP1. 149 GNDT. 150 TPON1. 151 VCCT. 152 FIBOP1. 153 FIBON1. 154 SIGDET1. 155 FIBIN1. 156 Part # LOT # FPO # 208. LEDSEL0 207. LEDSEL1 206. VCC 205. VCC 204. VCC 203. VCC 202. GND 201. VCC 200. GND 199. MMSTRIN 198. ARBIN 197. CONFIG0 196. CONFIG1 195. CONFIG2 194. CONFIG3 193. CONFIG4 192. CONFIG5 191. CONFIG6 190. CONFIG7 189. PORT1_SPD0 188. PORT1_SPD1 187. PORT2_SPD0 186. PORT2_SPD1 185. PORT3_SPD0 184. PORT3_SPD1 183. PORT4_SPD0 182. PORT4_SPD1 181. PORT1_LED1 180. PORT1_LED2 179. PORT1_LED3 178. GND 177. PORT2_LED1 176. PORT2_LED2 175. PORT2_LED3 174. GND 173. PORT3_LED1 172. PORT3_LED2 171. PORT3_LED3 170. VCC 169. VCCV 168. GNDV 167. GND 166. PORT4_LED1 165. PORT4_LED2 164. PORT4_LED3 163. GND 162. PORT5_LED1 161. PORT5_LED2 160. PORT5_LED3 159. GND 158. GND 157. FIBIP1 Note: For Pin 74 Signal Description, see Table 9 on page 17 (LXT980 LXT980) and Table 11 on page 18 Package Topside Markings Marking Definition Part # LXT980 LXT980 is the unique identifier for this product family. Rev # Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping information.) Lot # Identifies the batch. FPO # Identifies the Finish Process Order. 10 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 1. Mode Control Signal Descriptions Pin 189 PORT1_SPD0 188 PORT1_SPD1 187 PORT2_SPD0 186 PORT2_SPD1 Type1 Symbol 185 PORT3_SPD0 184 PORT3_SPD1 183 PORT5_SPD 99 PORT5_SEL 197 196 195 194 193 192 191 190 CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 CONFIG7 TTL Input, PU, Latched on reset SPD1 SPD0 Mode 0 0 Allow 10/100 auto-negotiation/parallel detection. 0 1 Force 10BASE-T 10BASE-T. 1 0 Force 100BASE-FX 100BASE-FX. 1 1 Force 100BASE-TX 100BASE-TX. PORT4_SPD1 100 Speed Select - Ports 1 through 4. These pins set the default value of the Port Speed Control Register for the associated port as follows: PORT4_SPD0 182 Description TTL Input, PU TTL Input, PU TTL Input, PD Speed Select - Port 5. Selects operating speed of the MII (MAC) interface. Also selects the segment on which statistics are kept. High = 100 Mbps. Low = 10 Mbps. (Port 5 speed of 10 Mbps is available when PHY mode is selected.) Mode Select - Port 5. Selects operating mode of the MII interface. Pin is monitored at power-up and reset. Subsequent changes have no effect. High = PHY Mode (LXT980 LXT980 acts as PHY side of the MII.) Low = MAC Mode (LXT980 LXT980 acts as MAC side of the MII.) Configuration Register Inputs. These inputs allow the user to store systemspecific information (board type, plug-in cards, status, etc.) in the Serial Configuration Register (address AC). This register may be read remotely through the Serial Management Interface (SMI). 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. Table 2. Pin PHY Mode MII Interface Signal Descriptions Symbol Type1 Description Output TTL Receive Data. The LXT980 LXT980 transmits received data to the controller on these outputs. Data is driven on the falling edge of MII_RXCLK. 29 MII_RXD0 30 MII_RXD1 32 MII_RXD2 33 MII_RXD3 26 MII_RXDV Output TTL Receive Data Valid. Active High signal, synchronous to MII_RXCLK, indicates valid data on MII_RXD. 25 MII_RXCLK Output TTL Receive Clock. MII receive clock for expansion port. This is a 2.5 or 25 MHz clock derived from the CLK25 CLK25 input (refer to Table 11). 24 MII_RXER Output TTL Receive Error. Active High signal, synchronous to MII_RXCLK, indicates invalid data on MII_RXD. 22 MII_TXER Input TTL Transmit Error. MII_TXER is a 100M-only signal. The MAC asserts this input when an error has occurred in the transmit data stream. The LXT980 LXT980 responds by sending `Invalid Code Symbols' on the line. 1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for PHY mode. Datasheet 11 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 2. PHY Mode MII Interface Signal Descriptions (Continued) Pin Symbol Type1 21 MII_TXCLK Output TTL 20 MII_TXEN Input TTL Transmit Enable. External controllers drive this input High to indicate that data is being transmitted on the MII_TXD pins. Tie this input Low if it is unused. 19 MII_TXD0 18 MII_TXD1 17 MII_TXD2 Input TTL Transmit Data. External controllers use these inputs to transmit data to the LXT980 LXT980. The LXT980 LXT980 samples MII_TXD on the rising edge of MII_TXCLK, when MII_TXEN is High. 16 MII_TXD3 14 MII_COL Output TTL Collision. The LXT980 LXT980 drives this signal High to indicate that a collision has occurred. 13 MII_CRS Output TTL Carrier Sense. Active High signal indicates LXT980 LXT980 is transmitting or receiving. Description Transmit Clock. 2.5 or 25 MHz continuous output derived from the 25 MHz input clock. 1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for PHY mode. Table 3. Pin MAC Mode MII Interface Signal Descriptions Symbol Type1 Description Input TTL Receive Data. The LXT980 LXT980 receives data from the PHY on these pins. Data is sampled on the rising edge of MII_RXCLK. 29 MII_RXD0 30 MII_RXD1 32 MII_RXD2 33 MII_RXD3 26 MII_RXDV Input TTL Receive Data Valid. The PHY asserts this active High signal, synchronous to MII_RXCLK, to indicate valid data on MII_RXD. 25 MII_RXCLK Input TTL Receive Clock. MII receive clock for expansion port. This is a 25 MHz clock. 24 MII_RXER Input TTL Receive Error. The PHY asserts this active High signal, synchronous to MII_RXCLK, to indicate invalid data on MII_RXD. 22 MII_TXER Output TTL Transmit Error. The LXT980 LXT980 asserts this signal when an error has occurred in the transmit data stream. 21 MII_TXCLK Input TTL Transmit Clock. 25 MHz continuous input clock. Must be supplied from same source as CLK25 CLK25 system clock. 20 MII_TXEN Output TTL Transmit Enable. The LXT980 LXT980 drives this output High to indicate that data is being transmitted on the MII_TXD pins. 19 MII_TXD0 18 MII_TXD1 17 MII_TXD2 Output TTL Transmit Data. The LXT980 LXT980 drives these outputs to transmit data to the PHY. The device drives MII_TXD on the rising edge of MII_TXCLK, when MII_TXEN is High. 16 MII_TXD3 14 MII_COL Input TTL Collision. The PHY asserts this active High signal to notify the LXT980 LXT980 that a collision has occurred. 13 MII_CRS Input TTL Carrier Sense. The PHY asserts this active High signal to notify the LXT980 LXT980 that the PHY is transmitting or receiving. 1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for MAC mode. 12 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 4. Pin Inter-Repeater Backplane Signal Descriptions Symbol Type1 Description Common IRB Signals 199 MMSTRIN 63 MMSTROUT TTL Input PD, NC TTL Output Management Master Input. The Management Master (MM) daisy chain ensures that collisions are counted correctly in multi-board applications. Attach the MMSTRIN input of each device to the MMSTROUT output of the previous device. Ground MMSTRIN of the first or only device. Management Master Output. MM daisy chain output. In hot-swap applications, a 1 k - 3 k resistor can be used as a by-pass between MMSTRIN and MMSTROUT. 100 Mbps IRB Signals (Refer to Figure 22 on page 57) 36 IR100CFS IR100CFS Analog I/O 100 Mbps IRB Collision Force Sense. A three-level signal that determines number of active ports on the "logical" repeater. High level (5V) indicates no ports active; Mid level (approx. 2.8V) indicates one port active; Low level (0V) indicates more than one port active, resulting in a collision. This signal requires a 240 pull-up resistor, and connects between chips on the same board. 37 IR100CFSBP IR100CFSBP Analog I/O NC 100 Mbps IRB Collision Force Sense - Backplane. This three-level signal functions the same as IRCFS; however, it connects between chips with ChipID=0, on different boards. IR100CFSBP IR100CFSBP requires a single 91 pull-up resistor on each stack. 38 IR100SNGL IR100SNGL Schmitt CMOS I/O PU 100 Mbps Single Driver State. This active Low signal is asserted by the device with ChipID = 000 when a packet is being received from one or more ports. This signal should not be connected between boards. 40 IR100COL IR100COL Schmitt CMOS I/O PU 100 Mbps Multiple Driver State. This active Low signal is asserted by the device with ChipID = 000 when a packet is being received from more than one port (collision). It should not be connected between boards. TTL Output OD 100 Mbps IRB Driver Enable. This output provides directional control for an external bidirectional transceiver (`245) used to buffer the 100 Mbps IRB in multi-board applications. It must be pulled up by a 330 resistor. When there are multiple devices on one board, tie all IR100DEN IR100DEN outputs together. If IR100DEN IR100DEN is tied directly to the DIR pin on a `245, attach the on-board IR100DAT IR100DAT, IR100CLK IR100CLK, and IR100DV IR100DV signals to the "B" side of the `245, and connect the off-board signals to the "A" side of the `245. 41 IR100DEN IR100DEN 42 IR100DV IR100DV Schmitt CMOS I/O OD, PU 100 Mbps IRB Data Valid. This active Low signal indicates port activity on the repeater. IR100DV IR100DV frames the clock and data of the packet on the backplane. This signal requires a 120 pull-up resistor. 43 44 45 46 49 IR100DAT0 IR100DAT0 IR100DAT1 IR100DAT1 IR100DAT2 IR100DAT2 IR100DAT3 IR100DAT3 IR100DAT4 IR100DAT4 Tri-state Schmitt CMOS I/O PU 100 Mbps IRB Data. These bidirectional signals carry data on the 100 Mbps IRB. Data is driven on the falling edge and sampled on the rising edge of IR100CLK IR100CLK. These signals can be buffered between boards. 52 IR100CLK IR100CLK Tri-state Schmitt CMOS I/O PD 100 Mbps IRB Clock. This bidirectional, non-continuous, 25 MHz clock is recovered from received network traffic. Schmitt triggering is used to increase noise immunity. This signal must be pulled to VCC when idle. One 1 k pull-up resistor on both side of a `245 buffer is recommended. 56 IR100ISO IR100ISO TTL Output 100 Mbps Stack Backplane Isolate. This output allows one LXT980 LXT980 per Board the ability to enable or disable an external bidirectional transceiver (`245). Attach the output to the Enable input of the `245. The output is driven High (disable) to isolate the 100 Mbps IRB. 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down. I/O = Input / Output. OD = Open Drain TTL = Transistor-Transistor Logic Even if the IRB is not used, required pull-up resistors must be installed as listed above. Datasheet 13 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 4. Pin Inter-Repeater Backplane Signal Descriptions (Continued) Symbol Type1 Description 10 Mbps IRB Signals (Refer to Figure 23 on page 57) 10 Mbps IRB Data. Carries data on the 10 Mbps IRB. Data is driven and sampled on the rising edge of the corresponding IRCLK. This signal must be pulled up by a 330 resistor. Between boards, this signal can be buffered. 9 IR10DAT IR10DAT CMOS I/O OD, PD 10 IR10CLK IR10CLK Tri-state Schmitt CMOS I/O PD 10 Mbps IRB Clock. This bidirectional, non-continuous, 10 MHz clock is recovered from received network traffic. During idle periods, the output is high-impedanced. Schmitt triggering is used to increase noise immunity. 6 IR10DEN IR10DEN TTL Output OD 10 Mbps IRB Driver Enable. This output provides directional control for an external bidirectional transceiver (`245) used to buffer the IRBs in multi-board applications. It must be pulled up by a 330 resistor. When there are multiple devices on one board, tie all IR10DEN IR10DEN outputs together. If IR10DEN IR10DEN is tied directly to the DIR pin on a `245, attach the on-board IR10DAT IR10DAT, IR10CLK IR10CLK and IR10ENA IR10ENA signals to the "B" side of the `245, and connect the off-board signals to the "A" side of the `245. 8 IR10ENA IR10ENA CMOS I/O OD, PU 10 Mbps IRB Enable. This active Low output indicates carrier presence on the IRB. A 330 pull-up resistor is required to pull the IR10ENA IR10ENA output High when the IRB is idle. When there are multiple devices, tie all IR10ENA IR10ENA outputs together. This signal may be buffered between boards. 3 IR10COL IR10COL CMOS I/O OD, PU 10 Mbps IRB Collision. This output is driven Low to indicate that a collision has occurred on the 10 Mbps segment. A 330 resistor is required in each box to pull this signal High when there is no collision. This signal should not be connected between boards and it may not be buffered. 4 IR10COLBP IR10COLBP CMOS I/O OD, NC 10 Mbps IRB Collision - Backplane. This active Low output has the same function as IR10COL IR10COL, but is used between boards. Attach this signal only from the device with ChipID = 0 to the backplane or connector, without buffering. The output must be pulled up by one 330 resistor per system. 1 IR10CFS IR10CFS Analog I/O OD 10 Mbps IRB Collision Force Sense. This three-state analog signal indicates transmit collision when driven Low. IR10CFS IR10CFS requires a 680, 1% pull-up resistor. Do not connect this signal between boards and do not buffer. 5 IR10CFSBP IR10CFSBP Analog I/O OD, NC 10 Mbps IRB Collision Force Sense - Backplane. Functions the same as IR10CFS IR10CFS, but connects between boards. Attach this signal only from the device with ChipID = 0 to the backplane or connector, without buffering. This signal requires one 330, 1% pullup resistor per system. TTL Input PD MAC Active. A TTL-level signal. Active High input allows external ASICs to participate in 10 Mbps IRB. Driving data onto the IRB requires that the external ASIC assert MACACTIVE High for one clock cycle, then assert IR10ENA IR10ENA Low. ASIC monitors IR10COL IR10COL (active Low) for collision. By using MACACTIVE, the repeater-not the MAC-drives the three-level IR10CFS IR10CFS pin. TTL Output 10 Mbps IRB Isolate. By using IR10 IS, one LXT980 LXT980 per board can enable or disable an external bidirectional transceiver (`245). Attach the output to the Enable input of the `245. Driven High (disable) to isolate the 10 Mbps IRB. TTL I/O PD Hold Collision for 10 Mbps mode. This active High signal is driven by the device with ChipID = 0 to extend a non-local transmit collision to other devices on the same board. The HOLDCOL signals from different boards should NOT be attached together. 79 MACACTIVE 55 IR10 ISO 80 HOLDCOL 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down. I/O = Input / Output. OD = Open Drain TTL = Transistor-Transistor Logic Even if the IRB is not used, required pull-up resistors must be installed as listed above. 14 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 5. Pin Twisted-Pair Port Signal Descriptions Symbol 149, 151 TPOP2, TPON2 Description TPOP1, TPON1 136, 138 Type 121, 123 Analog Output TPOP3, TPON3 108, 110 TPOP4, TPON4 146, 147 TPIP1, TPIN1 133, 134 TPIP2, TPIN2 Analog 118, 119 TPIP3, TPIN3 Input 105, 106 Twisted-Pair Outputs - Ports 1 through 4. These pins are the positive and negative outputs from the respective ports' twisted-pair line drivers. These pins can be left open when not used. TPIP4, TPIN4 Table 6. Pin Twisted-Pair Inputs - Ports 1 through 4. These pins are the positive and negative inputs to the respective ports' twisted-pair receivers. These pins can be left open when not used. Fiber Port Signal Descriptions Symbol Type FIBOP3, FIBON3 112, 113 FIBIP1, FIBIN1 144, 143 FIBIP2, FIBIN2 129, 128 FIBIP3, FIBIN3 116, 115 Signal Detect - Ports 1 through 4. Signal detect for the fiber ports. These pins can be left open when not used. FIBOP4, FIBON4 157, 156 Fiber Inputs - Ports 1 through 4. These pins are the positive and negative inputs to the respective ports' PECL receivers. These pins can be left open when not used. PECL Input FIBOP2, FIBON2 125, 126 Fiber Outputs - Ports 1 through 4. These pins are the positive and negative outputs from the respective ports' PECL drivers. These pins can be left open when not used. FIBOP1, FIBON1 140, 141 PECL Output PECL Input 153, 154 Description FIBIP4, FIBIN4 155 SIGDET1 142 SIGDET2 127 SIGDET3 114 SIGDET4 Table 7. Pin Serial Management Interface Signal Descriptions Symbol 58 RECONFIG 62 SER_MATCH 59 SRX Type1 Description TTL Input PD, NC Reconfigure. This input controls the driving of the clock signal on the high-speed Serial Management Interface (SERCLK). When this input is High, the LXT980 LXT980 drives SERCLK with a 625 kHz output. When this input is Low, SERCLK is an input to the LXT980 LXT980. In addition, a Low-to-High transition on RECONFIG causes the LXT980 LXT980 to drive 13 continuous 0s on the SMI, causing a re-arbitration to occur. TTL Output Serial Match. The LXT980 LXT980 device with ChipID = 0 asserts this active High output whenever it detects a message on the SMI that matches the local Hub ID. Refer to Figure 11 on page 43. TTL Input, PD Serial Receive. Receive data input for high-speed serial management interface. Must be tied to STX externally. SRX is sampled on the rising edge of SERCLK. 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down OD = Open Drain TTL = Transistor-Transistor Logic. Datasheet 15 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 7. Pin Serial Management Interface Signal Descriptions (Continued) Symbol Type1 Description 60 STX TTL Output OD Serial Transmit. Transmit data output for high-speed serial management interface. Must be tied to SRX externally. Data transmitted on STX is compared with data received on SRX. In the event of a mismatch, STX is put in the high impedance state. STX is driven on the falling edge of SERCLK. 61 SERCLK Tri-state TTL I/O, PD Serial Clock. Clock for serial management interface. Depending on RECONFIG, this pin is either a 625 kHz output or a 0 to 2 MHz input. 198 ARBIN TTL Input, PD, NC 64 ARBOUT 65 ARBSELECT 66 MGR_PRES TTL Output NC TTL Input PU TTL Input NC, PU Arbitration In/Out. Used with Chain Arbitration. If used, tie ARBIN to ARBOUT of the previous device. ARBIN at the top of the daisy chain can be connected to ground or to ARBOUT of the SCC. If unused, tie ARBIN High. Arbitration Mode Select. 0 = EEPROM based, 1 = chain based. Manager Present. This signal is sensed at power up and hardware reset. If the signal is High, it indicates that no local manager is present, and the LXT980 LXT980 enables all ports and sets all LEDs to operate in "hardware mode". If it is Low, indicating that a manager is present, the LXT980 LXT980 disables all ports, pending control of network manager. 1. NC = No Clamp. Pad will not clamp input in the absence of power. PU = Input contains pull-up. PD = Input contains pull-down OD = Open Drain TTL = Transistor-Transistor Logic. Table 8. Pin LED Signal Descriptions Symbol 208 LEDSEL0 207 LEDSEL1 181 PORT3_LED1 166 PORT4_LED1 162 PORT5_LED1 180 PORT1_LED2 176 PORT2_LED2 172 PORT3_LED2 165 LED Mode Select. Must be static. PORT2_LED1 173 Description PORT1_LED1 177 Type1 PORT4_LED2 161 PORT2_LED3 171 PORT3_LED3 164 PORT5_LED3 85 COL10 COL10_LED LED Driver 2 - Ports 1 through 5. Programmable LED driver. Active Low. See "Port LEDs" on page 32. PORT4_LED3 160 TTL Output LED Driver 1 - Ports 1 through 5. Programmable LED driver. Active Low. See "Port LEDs" on page 32. PORT1_LED3 175 TTL Output 00 = Mode 1, 01 = Mode 2, 10 = Mode 3 PORT5_LED2 179 TTL Input PD TTL Output TTL Output LED Driver 3 - Ports 1 through 5. Programmable LED driver. Active Low. See "Port LEDs" on page 32. 10 Mbps Collision LED Driver. Active Low indicates collision on 10Mbps segment. 1. PD = Input contains pull-down. TTL = Transistor-Transistor Logic 16 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 8. Pin LED Signal Descriptions (Continued) Symbol Type1 Description 86 COL100 COL100_LED TTL Output 100 Mbps Collision LED Driver. Active Low indicates collision on 100 Mbps segment. 87 MGR_LED TTL Output Manager Present LED Driver. Active Low indicates Manager present. 90 ACT10 ACT10_LED TTL Output 10 Mbps Activity LED Driver. Active Low indicates activity on 10 Mbps segment. 91 ACT100 ACT100_LED TTL Output 100 Mbps Activity LED Driver. Active Low indicates activity on 100 Mbps segment. 92 FAULT_LED TTL Output Fault LED Driver. Active Low indicates global fault. 98 RPS_LED TTL Output Redundant Power Supply LED Driver. Active Low indicates RPS fault. 1. PD = Input contains pull-down. TTL = Transistor-Transistor Logic Table 9. Pin Power Supply and Indication Signal Descriptions Type1 Symbol Description 12, 28, 35, 51, 57, 76, 84, 89, 96, 170, 201, 203-206 VCC Digital Power Supply Inputs. Each of these pins must be connected to a common +5 VDC power supply. A de-coupling capacitor to digital ground should be supplied for every one of these pins. 2, 11, 34, 50, 75, 82, 83, 88, 93, 158, 159, 163, 167, 174, 178, 200, 202 GND Digital Ground. Connect each of these pins to digital ground. GND (LXT980 LXT980 only) Digital Ground. Connect this pin to digital ground. Note: For LXT980A LXT980A, refer to Table 11 on page 18. 94, 169 VCCV Analog VCO Supply Inputs. Each of these pins must be connected to a common +5 VDC power supply. A de-coupling capacitor to GNDV should be supplied for every one of these pins. 95, 168 GNDV Analog VCO Ground. 111, 124, 139, 152 VCCT Analog Transmitter Supply Inputs. Each of these pins must be connected to a common +5 VDC power supply. A de-coupling capacitor to GNDT should be supplied for every one of these pins. 109, 122, 137, 150 GNDT Analog Transmitter Ground. 107, 120, 135, 148 VCCR Analog Receiver Supply Inputs. Each of these pins must be connected to a common +5 VDC power supply. A de-coupling capacitor to GNDR should be supplied for every one of these pins 104, 117, 132, 145, GNDR Analog Receiver Ground. 74 1. PU = Input contains pull-up. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. Datasheet 17 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 9. Power Supply and Indication Signal Descriptions (Continued) Pin Type1 Symbol 131 RBIAS 27, 130 GNDA Analog Analog 78 RPS_PRES TTL Input PD 77 RPS_FAULT TTL Input PU Description RBIAS. Used to provide bias current for internal circuitry. The 100 µA bias current is provided through an external 22.1 k, 1% resistor to GNDA. Analog Ground. Redundant Power Supply Present. Active High input indicates presence of redundant power supply. Tie Low if not used. Redundant Power Supply Fault. Active Low input indicates redundant power supply fault. The state of this input is reflected in the RPS_LED output (refer to Table 8 on page 16). Tie High if not used. 1. PU = Input contains pull-up. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. Table 10. PROM Interface Signal Descriptions Type1 Pin Symbol 67 PROM_CLK Tri-State TTL I/O, PD 68 PROM_CS Tri-State TTL Output PROM Chip Select. Selects EPROM. Active High signal driven by chip with ID of 0. 69 PROM_DTOUT Tri-State TTL Output PROM Data Output. Selects read instruction for EPROM. Active High signal driven only by chip with ID of 0. 70 PROM_DTIN TTL Input, PD Description PROM Clock. 1 MHz clock for reading PROM data (ChipID=0). If a PROM is not used, this pin must be tied Low. PROM Data Input. If PROM not used, input tied Low or High. 1. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. Table 11. Miscellaneous Signal Descriptions Pin Symbol Type1 Description Reset. This active Low input causes internal circuits, state machines, and counters to reset (address tracking registers do not reset). On power-up, devices should not be brought out of reset until the power supply has stabilized and reached 4.5V. When there are multiple devices, it is recommended that all be supplied by a common reset that is driven by an `LS14 or similar device. 53 RESET Schmitt CMOS Input NC 54 CLK25 CLK25 Schmitt CMOS Input 25 MHz system clock. Drive with MOS levels. 71 CHIPID0 72 CHIPID1 TTL Input, PD Chip ID. These pins assign unique ChipIDs to as many as eight devices on a single board. One device on each board must be assigned ChipID = 0. 73 CHIPID2 1. NC = No Clamp. Pad will not clamp input in the absence of power. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. 18 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 11. Miscellaneous Signal Descriptions (Continued) Pin Symbol Type1 Description 74 AUTO_BLINK (LXT980A LXT980A only) TTL Input, PD AUTO_BLINK. Setting this pin High disables the Blink indication that shows a "No Link" condition for PortnLED3. Note: For LXT980 LXT980, refer to Table 9 on page 17. 81 IRQ TTL Output OD Interrupt request. Active Low interrupt. Refer to Table 70 and Table 71 for criteria and clearing options. 7, 15, 23, 31, 39, 47, 48, 97, 101, 102, 103, NC - No Connects. Leave these pins unconnected. 1. NC = No Clamp. Pad will not clamp input in the absence of power. PD = Input contains pull-down. TTL = Transistor-Transistor Logic. Datasheet 19 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 2.0 Functional Description 2.1 Introduction As a fully integrated IEEE 802.3 repeater capable of 10 Mbps and 100 Mbps functionality, the LXT980 LXT980 is a very versatile device allowing great flexibility in Ethernet design solutions. Figure 3, "Typical Unmanaged 100 Mbps Repeater Architectures" on page 21, and Figure 5 show some typical applications, and Figure 6 shows a more complete I/O circuit. Refer to "Application Information" on page 48 for specific circuit implementations. This multi-port repeater provides four 10BASE-T/100BASE-TX/100BASE-FX 10BASE-T/100BASE-TX/100BASE-FX ports. In addition, there is a bidirectional Media Independent Interface (MII) expansion port that may be connected to either a 10/100 MAC, or to a 100 Mbps PHY. The LXT980 LXT980 provides two repeater state machines and two Inter-Repeater Backplanes (IRB) on a single chip-one for 10 Mbps operation and one for 100 Mbps operation. The 100 Mbps repeater fully meets IEEE 802.3 Class II requirements. Each port's operating speed may be selected independent of the other ports. The auto-negotiation capability of the LXT980 LXT980 allows it to poll connected nodes and configure itself accordingly. The LXT980 LXT980 incorporates full RMON support by providing on-chip counters and hardware assistance for a fully managed environment. The segmented backplane simplifies dual-speed operation, and allows multiple devices to be stacked and function as one logical repeater. Up to 240 ports (192 TP ports and 48 MII ports) can be supported in a single cascade. 20 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Figure 3. Typical Managed Repeater Architectures LXT980 LXT980 LXT980 LXT980 10BASE-T 10BASE-T 10/100 LXT980 LXT980 Repeater PHY 10BASE-T 10BASE-T E'net10/100 10 Mbps Backplane 10 Mbps Buffer Backplane Repeater PHY 10 Mbps 10BASE-T 10BASE-T E'net10/100 Backplane Repeater E'net PHY 100 Mbps 100BASE-T 100BASE-T 10/100 Backplane Repeater PHY 100 Mbps 100BASE-T 100BASE-T E'net10/100 10M Backplane 100M Backplane 10M Backplane Chassis Backplanes Backplane 100 Mbps Backplane Repeater PHY 100BASE-X 100BASE-X E'net10/100 Repeater E'net PHY Device 10/100 Management E'net10/100 PHY Device Serial Port Management Device E'net10/100 PHY Serial Port Management E'net PHY Serial Port 10/100 E'net10/100 PHY MII RMON & E'net10/100 PHY SNMP & MII RMON E'net PHY Counters SNMP & MII RMON Counters SNMP LED Drivers Counters LED Drivers LED Drivers Buffer 100M Backplane Serial Management SCC (8530) MII-to-MII Bridge (Any 2 LXT980s) Figure 4. Typical Unmanaged 100 Mbps Repeater Architectures LXT980 LXT980 100M Backplane Chassis Backplane Buffer 100M Backplane 10 Mbps 10BASE-T 10BASE-T 10/100 LXT980 LXT980 Backplane Repeater E'net PHY 10 Mbps 10BASE-T 10BASE-T 10/100 LXT980 LXT980 Backplane Repeater E'net PHY 10 Mbps 10BASE-T 10BASE-T 10/100 100 Mbps 100BASE-T 100BASE-T 10/100 Backplane Repeater E'net PHY Backplane Repeater E'net PHY 100 Mbps 100BASE-T 100BASE-T 10/100 Backplane Repeater E'net PHY 100 Mbps 10/100 Device 100BASE-X 100BASE-X 10/100 Backplane Repeater E'net PHY Management E'net PHY Serial Port Device 10/100 Management E'net PHY Serial Port Device 10/100 10/100 Management E'net PHY Serial Port E'net PHY 10/100 MII RMON & E'net PHY SNMP 10/100 MII RMON & Counters E'net PHY SNMP LED Drivers MII RMON & Counters LED Drivers LED Banks Datasheet SNMP Counters LED Drivers 21 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Figure 5. Typical Hybrid Switch/Repeater Application LXT980 LXT980 10 Mbps Backplane 10M Backplane 100M Backplane 10 Mbps 10BASE-T 10BASE-T 10/100 Backplane Repeater E'net PHY 100 Mbps 100BASE-T 100BASE-T 10/100 Backplane Repeater E'net PHY 100 Mbps Backplane Serial Port Serial Management to SCC (8530) 10BASE-T 10BASE-T 10/100 LXT980 LXT980 E'net PHY Repeater 100BASE-X 100BASE-X 10/100 Repeater E'net PHY Device 10/100 Management E'net PHY Serial Port MII MII Switch Connections 1 each for 10 M and 100M MII LED Drivers Device Management 10/100 E'net PHY 10/100 E'net PHY RMON & SNMP Counters RMON & SNMP Counters 10/100 E'net PHY LED Drivers 22 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Figure 6. Typical Application Block Diagram Xfmrs Serial Mgmt I/F SCC SRX STX 8530 LXT980 LXT980 RECONFIG MG_PRSNT MII_RXCLK MII_RXD MII_RXDV MII_RXER MII_COL MII_CRS MII_TXCLK MII_TXD MII_TXEN MII_TXER Input allows MAC to drive IRB (10M Only) Fiber Module FIBOP1 FIBON1 FIBIP1 FIBIN1 SIGDET1 4 100 M FO Ports FO2 FO3 FO4 MACACTIVE ChipID assignment 4 TP Ports Independently switchable to either 10 or 100 M backplane TP2 TP3 TP4 SERCLK MII (Port 5, PHY Mode) RJ45s TPOP1 TPON1 TPIP1 TPIN1 CHIPID2 CHIPID1 CHIPID0 HubID assignment PROM_CS PROM_DTOUT PROM_CLK PROM_DTIN PROM MMSTRIN MMSTROUT PORT2_LED1 PORT2_LED2 PORT2_LED3 2 Independent IRBs, 10 & 100 PORT3_LED1 PORT3_LED2 PORT3_LED3 IRCOL IRCFS HOLDCOL Local IRB to onboard LXT980 LXT980 IRB10 IRB10 IRDEN ISOLATE IRCOLBP IRCFSBP Port LEDs PORT4_LED1 PORT4_LED2 PORT4_LED3 IRENA IRDAT IRCLK '245 Local IRB VCC PORT1_LED1 PORT1_LED2 PORT1_LED3 to next LXT980 LXT980 InterModule IRB to stack connector Resistor Packs PORT5_LED1 PORT5_LED2 PORT5_LED3 ACT10 ACT10_LED COL10 COL10_LED ACT100 ACT100_LED COL100 COL100_LED MGR_LED RPS_LED FAULT_LED Segment LEDs Global LEDs IRB100 IRB100 Inter-Module IRB Datasheet 23 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 2.1.1 TP/FX Port Configuration The LXT980 LXT980 reads the hardware configuration pins at power-up, hardware reset, or software reset (but not at repeater reset), to determine operating conditions for each of its twisted-pair (TP) or fiber (FX) ports. Each port has its own configuration pins so that it can be individually configured. Software can monitor or change the configuration through the Port Speed Control Register (see Table 61 on page 85). The four possible configurations for each port are summarized in Table 12. Table 12. Manual Speed Selection SPD1 Speed Selection 0 0 Allow 10/100 auto-negotiation/parallel detection on copper media 0 1 Force port to 10BASE-T 10BASE-T mode 1 0 Force port to 100BASE-FX 100BASE-FX mode 1 2.1.1.1 SPD0 1 Force port to 100BASE-TX 100BASE-TX mode Forced Operation A port can be directly configured to operate in one of three modes: 100FX 100FX, 100TX 100TX, or 10BT. When a port is configured for forced operation via hardware or software, it immediately begins operating in the selected mode. Forced operation is the only way to enable 100FX 100FX operation. All links are established as half-duplex only. As a repeater, the LXT980 LXT980 cannot support full-duplex operation. 2.1.1.2 Auto-Negotiation Any port can be configured to establish its link via auto-negotiation. The port and its link partner establish link conditions by exchanging Fast Link Pulse (FLP) bursts. Each FLP burst contains 16 bits of data that advertise the port's capabilities. The FLP bursts sent by the port are maintained in its Auto-negotiation Advertisement Register (Table 81 on page 93). The link partner's abilities are stored in the auto-negotiation link partner register (Table 79 on page 92). Status can be observed in the respective Auto-negotiation Status Register (Table 80 on page 93). Each port has its own advertisement, link partner advertisement, and Auto-negotiation Status Registers. When auto-negotiation is enabled, the capabilities advertised by the LXT980 LXT980 are predetermined and cannot be changed; the advertisement register is read only, except for bit 13 (remote fault). The LXT980 LXT980 always advertises 100 half duplex and 10 half duplex. it never advertises 10 or 100 fullduplex. If the link partner does not support auto-negotiation, the LXT980 LXT980 determines link state by listening for 100 Mbps IDLE symbols or 10 Mbps link pulses. If it detects either of these signals, it configures the port and updates the status registers appropriately. 2.1.1.3 Link Establishment and TP Port Connection Once a port establishes link, the LXT980 LXT980 automatically connects it to the appropriate repeater state machine. If link loss is detected and auto-negotiation is enabled, the port returns to the autonegotiation state. 2.1.1.4 Changing Port Speed In order to change port speed while operating, the following sequence is required: 24 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater · Disable the port(s) to be changed. · Set Port Speed Control Register to desired speed. · Perform a repeater reset (LXT980 LXT980 will not read hardware configuration pins. Refer to Table 69 on page 88.) · Re-enable the port(s). Note: 2.1.2 The entire repeater must be reset in order to change the port speed on any port. MII Port Configuration At power-up or reset, the MII is configured via external pins to one of the three modes of operation: · 100 Mbps, PHY side of interface-for interfacing to 100 Mbps MAC. · 10 Mbps, PHY side of interface-for interfacing to 10 Mbps MAC. · 100 Mbps, MAC side of interface-to drive fifth 100 Mbps port via an LXT970 LXT970 or other MIIcompliant PHY. In this mode, the external PHY must be configured as either a 100-TX 100-TX or 100FX 100FX connection. 2.1.3 Interface Descriptions The LXT980 LXT980 provides four network interface ports. Each port provides both a twisted-pair and a fiber interface. The twisted-pair interface directly supports 100BASE-TX 100BASE-TX (100TX 100TX) and 10BASE-T 10BASE-T (10T) Ethernet applications. A common termination circuit is used for both media types. The fiber interface indirectly supports 100BASE-FX 100BASE-FX (100FX 100FX) media through a PECL connection to an external fiber-optic transceiver. Both interfaces fully comply with IEEE 802.3 standards. 2.1.3.1 Twisted-Pair Interface The twisted-pair interface for each port consists of two differential signal pairs - one for transmit and one for receive. The transmit signal pair is TPOP/TPON, the receive signal pair is TPIP/TPIN. The twisted-pair interface for a given port is enabled when the port configuration is set to autonegotiate, forced 10T or forced 100TX 100TX operation. The twisted-pair interface is disabled when 100FX 100FX is selected. The transmitter is current driven and requires magnetics with 2:1 turns ratio. A 400 resistive load should be placed across the TPOP/N pair, in parallel with the magnetics. The center tap of the primary side of the transmit winding must be tied to a quiet VCC for proper operation. When the twisted-pair interface is disabled, the transmitter outputs are tri-stated. The receiver requires magnetics with a 1:1 turns ratio, and a load of 100 . When the twisted-pair port is enabled, the receiver actively biases its inputs to approximately 2.8V. When the twisted-pair interface is disabled, no biasing is provided. A 4 k load is always present across the TPIP/TPIN pair. When used in 100TX 100TX applications, the LXT980 LXT980 sends and receives a continuous, scrambled 125 Mbaud MLT-3 waveform on this interface. In the absence of data, IDLE symbols are sent and received in order to keep the link up. Datasheet 25 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater When used in 10T applications, the LXT980 LXT980 sends and receives a non-continuous, 10 Mbaud Manchester-encoded waveform. To maintain link during idle periods, the LXT980 LXT980 sends link pulses every 16 ms, and expects to receive them every 10 to 20 ms. Each 10BASE-T 10BASE-T port automatically detects and sends link pulses, and disables its transmitter if link pulses are not detected. Each receiver can also be configured to ignore link pulses, and leave its transmitter enabled all the time (link pulse transmission cannot be disabled). Each 10BASE-T 10BASE-T port can detect and automatically correct for polarity reversal on the TPIP/N inputs. The 10BASE-T 10BASE-T interface provides integrated filters using Intel's patented filter technology. These filters facilitate low-cost system designs which meet EMI requirements. In applications where the twisted-pair interface is not used, the inputs and outputs may be left unconnected. 2.1.3.2 Fiber Interface Each fiber interface consists of the FIBOP/FIBON (transmit) and FIBIP/FIBIN (receive) signal pair. Each interface also provides a "Signal Detect" input which can be tied to the corresponding output on the fiber transceiver for determining signal quality. The transmit pair is biased to approximately 1.5V and generally must be AC-coupled to the transceiver. The receive pair will accommodate an input bias in the 2V- 5V range, and can be DCcoupled to the transceiver. Refer to Figure 20 on page 55 for a typical interface circuit. The fiber interface for each port is enabled when the speed select is set to 100FX 100FX, and is disabled in all other cases. When a fiber port is disabled, its outputs are pulled to ground, and its inputs are tristated. The input and output pins on unused fiber ports may be left unconnected. Each fiber port transmits and receives a continuous, 1V peak-to-peak, non-scrambled, NRZI waveform. The LXT980 LXT980 does not support scrambling or auto-negotiation on the fiber interface. Remote Fault Reporting The SD pin detects signal quality and reports a remote fault if the signal quality starts to degrade. Loss of signal quality also blocks any further data from being received and causes loss of the link. The remote fault code consists of 84 consecutive 1s followed by a single `0', and is transmitted at least three times. The LXT980 LXT980 transmits the remote fault code and sets the associated interrupts when both of the following conditions are true: · Fiber mode is selected. · Signal Detect indicates no signal, or the receive PLL cannot lock. 2.1.3.3 Media Independent Interface The LXT980 LXT980 supports a standard Media Independent Interface (MII). This interface can be programmed to operate as either the PHY or the MAC side of the interface. When the MII is operating as the MAC side of the interface (MAC mode), it always operates at 100 Mbps. When the MII is operating as the PHY side of the interface (PHY mode), it can be programmed to operate either at 10 Mbps or at 100 Mbps. Once the MII is configured, the LXT980 LXT980 automatically connects it to the corresponding internal repeater. Note: 26 The MII does not support auto-negotiation, auto-speed, auto-link, or partition functions. Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater On the LXT980 LXT980, the MII always operates as a nibble-wide (4B) interface. Symbol mode (5B interface) is not supported on the LXT980 LXT980 MII. 2.1.3.4 Serial Management Interface The Serial Management Interface (SMI) provides system access to the status, control and statistic gathering abilities of the LXT980 LXT980. This interface is designed to allow multiple devices to be managed from a single multi-drop (daisy-chain) connection, and to use the minimum number of signals (2) for ease of system design. The interface itself consists of two digital NRZ signals - clock and data. Refer to Table 7 on page 15 for serial management I/F pin assignments and signal descriptions. Data is framed into HDLC-like packets, with a start/stop flag, header and CRC field for error checking. Zero-bit insertion/removal is used. The interface can operate at any speed from 0 to 2 Mbps. Address assignment is provided via one of two arbitration mechanisms which are activated whenever the device is powered up or reset/reconfigured. Refer to the section "Serial Management I/F" on page 40. 2.1.4 Repeater Operation The LXT980 LXT980 contains two internal repeater state machines - one operating at 10 Mbps and the other at 100 Mbps. The LXT980 LXT980 automatically switches each port to the correct repeater, once the operational state of that port has been determined. Each repeater connects all ports configured to the same speed (including the MII), and the corresponding Inter-Repeater Backplane. Both repeaters perform the standard jabber, partition, and isolate functions as required. 2.1.4.1 100 Mbps Repeater Operation The LXT980 LXT980 contains a complete 100 Mbps Repeater State Machine (100RSM 100RSM) that is fully IEEE 802.3 Class II compliant. Any port configured for 100 Mbps operation is automatically connected to the 100 Mbps Repeater. This includes any of the four media ports if they are configured for 100TX 100TX or 100FX 100FX operation, and the MII port if it is configured for 100 Mbps operation. The 100 Mbps RSM has its own Inter-Repeater Backplane (100IRB 100IRB). Multiple LXT980s can be cascaded on the 100IRB 100IRB and operate as one repeater segment. Data from any port will be forwarded to any other port in the cascade. The 100IRB 100IRB is a 5-bit symbol-mode interface. It is designed to be stackable. The LXT980 LXT980 maintains a complete set of statistics for its local repeater segment as long as the MII port is configured for 100 Mbps operation. These are accessible through the high-speed management interface. The LXT980 LXT980 performs the following 100 Mbps repeater functions: · Signal amplification, wave-shape restoration, and data-frame forwarding. · Handling of received code violations. The LXT980 LXT980 will substitute the "H" symbol for all invalid received codes. · SOP, SOJ, EOP, EOJ delay < 46BT; class II compliant (see Figure 26). · Collision Enforcement. During a 100 Mbps collision, the LXT980 LXT980 drives a 1010 jam signal (encoded as Data 5 on TX links) to all ports until the collision ends. There is no minimum enforcement time. Datasheet 27 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater · Partition. The LXT980 LXT980 partitions any port participating in excess of 60 consecutive collisions or one long collision approximately 575.2 µs long. Once partitioned, the LXT980 LXT980 continues monitoring and transmitting to the port, but does not repeat data received from the port until it properly un-partitions. · Un-partition. The LXT980 LXT980 supports two un-partition algorithms. The default algorithm, which complies with the IEEE 802.3 specification, un-partitions a port only when data can be transmitted to the port for 450-560 bit times without a collision on that port. · The alternate un-partition algorithm is available through the management interface. The alternate algorithm will un-partition a port on either transmit or receive of at least 450-560 bits without collision on the partitioned port. · Isolate. The LXT980 LXT980 isolates any port transmitting more than two successive false carrier events. A false carrier event is defined as a packet not starting with a /J/K symbol pair. Note: this is not the same as "100IRB 100IRB isolate," which involves segmenting the backplane. · Un-isolate. The LXT980 LXT980 will un-isolate a port that remains in the IDLE state for 33000 +/25% BT or that receives a valid frame at least 450-500 BT in length. · /T/R generation. The LXT980 LXT980 can insert a /T/R symbol pair (End of Stream Delimiter) on any incoming packet that does not include one. This feature is optional, and is enabled through the management interface. · Jabber. The LXT980 LXT980 ignores any receiver remaining active more than 57,500 bit times. The LXT980 LXT980 exits this state when all jabbering receivers return to the idle condition. The isolate and symbol error functions do not apply to the MII port. 2.1.4.2 10 Mbps Repeater Operation The LXT980 LXT980 contains a complete 10 Mbps Repeater State Machine (10RSM 10RSM) that is fully IEEE 802.3 compliant. Any port configured for 10 Mbps operation is automatically connected to the 10 Mbps Repeater. This includes any of the four media ports if they are configured for 10BT operation, and the MII port if it is configured for 10 Mbps operation. The 10RSM 10RSM has its own Inter-Repeater Backplane (10IRB 10IRB). Multiple LXT980s can be cascaded on the 10IRB 10IRB and operate as one repeater segment. Data from any port will be forwarded to any other port in the cascade. The 10IRB 10IRB is 1-bit wide and runs at 10 MHz. It is designed to be stackable. The LXT980 LXT980 maintains a complete set of statistics on its repeater segment, as long as the MII port is configured for 10 Mbps operation. These are accessible through the high-speed management interface. The LXT980 LXT980 performs the following 10 Mbps repeater functions: · Signal amplification, wave-shape restoration, and data-frame forwarding. · Preamble regeneration. All outgoing packets will have a minimum of 56 bits of preamble and 8 bits of SFD. · SOP, SOJ, EOP, EOJ delays meet requirements of IEEE 802.3 section 9.5.5 and 9.5.6. · Collision Enforcement. During a 10 Mbps collision, the LXT980 LXT980 drives a jam signal ("1010") to all ports for a minimum of 96 bit times and until the collision ends. · Partition. The LXT980 LXT980 will partition any port that participates in excess of 32 consecutive collisions. Once partitioned, the LXT980 LXT980 will continue monitoring and transmitting to the port, but will not repeat data received from the port until it properly un-partitions. 28 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater · Un-partition. The LXT980 LXT980 supports two un-partition algorithms. The default algorithm, which complies with the IEEE 802.3 specification, un-partitions a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port. · The LXT980 LXT980 also provides an alternate un-partition algorithm, which is available through the management interface. The alternate algorithm will un-partition a port only when data can be transmitted to the port for 450-560 bit times without a collision on that port. · Jabber. The LXT980 LXT980 will assert a minimum-IFG idle period when any port remains actively transmitting for longer than 40,000 to 75,000 bit times. 2.1.5 Management Support 2.1.5.1 Configuration and Status The LXT980 LXT980 provides management control and visibility of the following functions: · · · · · · · 2.1.5.2 Reset and Zeroing of counters Auto-negotiation (Control, Status, Advertisement, Link Partner) Device and Board Configuration LED Functions Source Address Tracking (per port) Source Address Matching (per chip) Device/Revision ID SNMP and RMON Support The LXT980 LXT980 provides SNMP and RMON support through its statistics gathering function. Statistics are gathered on all data that flow through the device for each of the ports, including the MII. The LXT980 LXT980 also maintains statistics for either the entire 10 or 100 Mbps repeater, depending on the speed setting of the MII port. (Two LXT980s are required to maintain statistics on both repeaters. Since cascaded LXT980s operate as a single logical 10/100 repeater, any device in the cascade maintains the same 10 or 100 repeater statistics as any other device). All statistics are stored as 32- or 64-bit quantities. Per-port counters include: Readable Frames FCS Errors Alignment Errors FramesTooLong ShortEvents Runts Collisions LateEvents VeryLongEvents DataRateMismatch AutoPartitions Broadcast Multicast SA Changes Isolates 2.1.5.3 Readable Octets Symbol Errors Source Address Management The LXT980 LXT980 provides two source address management functions for all ports: source address tracking and source address matching. These functions allow a network manager to track source addresses at each port, or to identify any port that sourced a particular source address. Datasheet 29 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 2.1.6 LED Drivers The LXT980 LXT980 provides 23 LED drivers: · 3 mode-selectable port LED drivers (15 total) · 2 segment LED drivers (4 total) · 4 global LED drivers Refer to Table 8 on page 16 for LED Interface pin assignments and signal descriptions. 2.2 Requirements 2.2.1 Power The LXT980 LXT980 has four types of +5V power supply input pins (VCC, VCCV, VCCR, and VCCT). These inputs may be supplied from a single power supply, although ferrites should be used to filter the power going to the analog and digital power planes. As a matter of good practice, these supplies should be as clean as possible. Specific operating recommendations are shown in the Test Specifications section, Table 25 on page 59. Each supply input should be decoupled to its respective ground. Refer to Table 9 on page 17 for power and ground pin assignments, and to "Design Recommendations" on page 48. 2.2.2 Clock A stable, external 25 MHz system clock source (CMOS) is required by the LXT980 LXT980. This is connected to the CLK25 CLK25 pin. Refer to Test Specifications, Table 26 on page 59, for clock input requirements. 2.2.3 Bias Resistor The LXT980 LXT980 requires a 22.1 k, 1% resistor connecting its RBIAS input to ground. 2.2.4 Reset At power-up, the reset input must be held low until VCC reaches at least 4.5V. An `LS14 or equivalent should be used to drive reset if there are multiple LXT980 LXT980 devices (See Figure 25 on page 58). 2.2.5 PROM An external, auto-incrementing 48-bit PROM can be used for two purposes: · to assign a unique ID to all LXT980s on a board · to support the EPROM-based address arbitration mechanism on the Serial Management Interface (refer to page 44) 30 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Multiple devices on the same board can share a single common PROM. The LXT980 LXT980 with ChipID = 0 actively reads the PROM at power-up; all other LXT980s listen in. If PROM arbitration is not used, the PROM data input signal must be tied either High or Low. Refer to Table 10 on page 18 for PROM interface pin assignments and signal descriptions. 2.2.6 Chip ID Each LXT980 LXT980 on a board requires a unique 3-bit Chip ID value asserted on these pins in order for the Serial Management Interface (SMI) to function correctly. One LXT980 LXT980 on each board must be assigned ChipID = 0. 2.2.6.1 When Substituting a LXT983 LXT983 Device The LXT983 LXT983 can be substituted in LXT980 LXT980 designs for a 10/100Mbps unmanaged solution without changing the LXT980 LXT980 Chip ID pin states. The LXT980 LXT980 Chip ID 0, Chip ID 1, and Chip ID 2 pins are renamed FPS, GND, and GND respectively for the LXT983 LXT983. For cascading, the first LXT983 LXT983 device is addressed 000 and all others 001 as indicated by the pin names. The LXT983 LXT983 requires one chip to have the LXT980-equivalent address 000 and all other LXT983s a non-000 address. 2.2.7 Management Master I/O Link In multiple device applications, the Management Master daisy chain (MMSTRIN/MMSTROUT) ensures that collisions are counted correctly. Connect the MMSTRIN input to the MMSTROUT output of the previous device, even across board boundaries. Ground the MMSTRIN input of the first or only device in the system. In hot-swap applications, resistive bypassing can be used with a value between 1 and 3 k. 2.2.8 IRB Bus Pull-ups Even when the LXT980 LXT980 is used in a stand-alone configuration, pull-up resistors are required on the IRB signals listed below. See Figure 22 on page 57 and Figure 23 on page 57 for sample circuits. 100 Mbps IRB 10Mbps IRB IR100CFS IR100CFS IR10DAT IR10DAT IR100CFSBP IR100CFSBP IR10ENA IR10ENA IR100DV IR100DV IR10COL IR10COL IR100CLK IR100CLK IR10CFS IR10CFS IR10COLBP IR10COLBP IR10CFSBP IR10CFSBP 2.3 LED Operation The LXT980 LXT980 provides three types of LED indicators: port, segment, and global (refer to Table 8 on page 16). Three user-selectable LED modes determine pin conditions and how particular conditions are indicated. The LED mode is selected via the LEDSEL pins and reflected in an Datasheet 31 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater internal register. The LEDs generally operate under hardware control although some limited software overrides are available. In addition to On and Off states, some LED drivers provide a blink state output. 2.3.1 Blink Rates Two programmable blink rates are provided. The default period for the slow blink rate is 1.6s. The default period is 0.4s for the fast blink rate. These rates may be changed via the LED Timer Register. The slow blink rate is defined by the upper 8 bits and the fast blink rate is defined by the lower 8 bits of the LED Timer Register. Refer to Table 73 through Table 75 for details. 2.3.2 Power-Up and Reset Conditions During reset or power-up, all LED drivers turn on steady and remain on for approximately 2 seconds after reset is cleared. After reset, the Collision, Activity, and Redundant Power Supply LEDs revert to hardware control. The Global Fault and Port LEDs revert to hardware control unless a manager is present in the system. 2.3.3 Port LEDs Port LEDs provide status for the four twisted-pair ports and the MII port. The LXT980 LXT980 has 3 LED driver pins for each port as described in Table 8. These pins drive standard LEDs. Three userselectable modes are provided for the port LEDs. Port LED states are also affected by port speed and auto-negotiation status, see Table 13 through Table 15. 2.3.3.1 Link Loss During link loss, the Speed LED indicates10M, and the Partition LED indicates "No partition," regardless of actual partition status. 2.3.3.2 Software Overrides of Port LEDs The Port LED Control Register allows limited software overrides of the Port LEDs. Two bits per port provide independent control of each port. However, all three LEDs for the respective port receive the same override (all Port n LEDs will be simultaneously set to On, Off, or Blink). Refer to Table 69 and Table 74 for coding and bit assignments. 2.3.4 Segment LEDs These outputs can directly drive LEDs to indicate activity and collision status on a per segment basis. No software overrides are provided for these LED drivers, and they are not affected by LED mode selection. Pulse stretchers are used to extend the on-time for these LEDs. 2.3.4.1 Collision LEDs The collision LEDs turn on for approximately 120 µs when the LXT980 LXT980 detects a collision on the respective 10 Mbps or 100 Mbps segment. During the time that the collision LED is on, any additional collisions are ignored by the collision LED logic. 32 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 2.3.4.2 Activity LEDs The activity LEDs turn on for approximately 4 ms when the LXT980 LXT980 detects any activity on the respective 10 Mbps or 100 Mbps segment. During the time that the activity LED is on, any additional activity is ignored by the activity LED logic. 2.3.5 Global LEDs These LED driver outputs indicate global status conditions. 2.3.5.1 Manager Present LED When active, this LED indicates the presence of a manager in the system. It is not affected by LED mode selection and does not allow software overrides. 2.3.5.2 Global Fault LED The global fault LED indicates one or more of the following conditions: any port partitioned, any port isolated or RPS fault. How the condition is indicated depends on the LED mode as shown in Table 13 through Table 15. Software Overrides of the Global Fault LED Two bits in the global LED Control Register allow software overrides to control the global Fault LED. Refer to Table 69 on page 88 and Table 73 on page 91 for coding and bit assignments. 2.3.5.3 Redundant Power Supply LED · The redundant power supply LED is controlled by the RPS_FLT and RPS_PRES pins. The LED state reflects the states of these two inputs, depending on the LED mode selected as listed in Table 13 through Table 15. Datasheet 33 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 13. LED Mode 1 Indications LED Hardware Control Operating Mode Software Control On Blink Off 10 Mbps operation Link up, not partitioned N/A Any other state 100 Mbps operation Link up, not partitioned, not isolated N/A Any other state 10 Mbps operation Link up, partitioned N/A Any other state 100 Mbps operation Link up, partitioned or isolated N/A Any other state Auto-neg enabled 100 Mbps link up No link, (fast blink)1 Any other state Auto-neg disabled 100 Mbps link selected, link may be up or down N/A Any other state RPS Any Present, fault N/A Any other state N/A Global FAULT Any Any port partitioned, any port isolated or RPS fault N/A Any other state Off via global LED Control Register, address 0B1 PORTnLED1 PORTnLED2 Off via Port LED Control Register, address 0B2 PORTnLED3 1. Setting AUTO_BLINK (Pin 74) High disables blink (LXT980A LXT980A only). Table 14. LED Mode 2 Indications LED Hardware Control Operating Mode Software Control On Blink Off 10M: Port enabled, link up, not partitioned 10M: Port enabled, link up, and partitioned Any 100M: Port enabled, link up, not partitioned, and not isolated 100M: Port enabled, link (partitioned or isolate) (slow blink) Any other state Any N/A N/A Always off 10 or 100 Mbps ops Receive activity (20 ms pulse) N/A Any other state Auto-neg enabled 100 Mbps link up No link (fast blink)1 10 Mbps link up Auto-neg disabled 100 Mbps selected, link may be up or down N/A 10 Mbps selected, link may be up or down RPS Any Present, no fault Present, fault Not present N/A Global FAULT Any N/A Any port partitioned, any port isolated or RPS fault (slow blink) Any other state On, off, or slow blink via global LED Control Register, address 0B1 PORTnLED1 PORTnLED2 (LXT980 LXT980) PORTnLED2 (LXT980A LXT980A) PORTnLED3 On, Off or fast Blink via Port LED Control Register, Address 0B2 1. Setting AUTO_BLINK (Pin 74) High disables blink (LXT980A LXT980A only). 34 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 15. LED Mode 3 Indications LED Hardware Control Operating Mode Software Control On Blink Off 10 Mbps operation Link up, not partitioned N/A Any other state 100 Mbps operation Link up, not partitioned, not isolated N/A Any other state 10 or 100 Mbps ops Receive activity (20 ms pulse) N/A Any other state Auto-neg enabled 100 Mbps link up No link (fast blink)1 10 Mbps link up Auto-neg disabled 100 Mbps link selected, link may be up or down N/A 10 Mbps link selected, link may be up or down Any Present, fault N/A Any other state N/A Any Any port partitioned, any port isolated or RPS fault N/A Any other state Off via global LED Control Register, address 0B1 PORTnLED1 PORTnLED2 PORTnLED3 RPS Global FAULT Off via port LED Control Register, address 0B2 1. Setting AUTO_BLINK (Pin 74) High disables blink (LXT980A LXT980A only). 2.4 IRB Operation The Inter Repeater Backplane (IRB) allows multiple devices to operate as a single logical repeater, exchanging data collision status information. Each segment on the LXT980 LXT980 has its own complete, independent IRB. The backplanes use a combination of digital and analog signals as shown in Figure 7. IRB signals can be characterized by connection type as Local (connected between devices on the same board), Stack (connected between boards) or Full (connected between devices on the same board and between different boards). Refer to Table 16 and Table 17 for details on buffering and pull-up requirements, and to Figure 22 on page 57 and Figure 23 on page 57 for application circuitry. 2.4.1 MAC IRB Access The MACACTIVE TTL-level pin allows an external MAC or other digital ASIC to interface directly to the 10 Mbps IRB. When the MACACTIVE pin is asserted, the LXT980 LXT980 will drive the IR10CFS IR10CFS and IR10CFSBP IR10CFSBP signals on behalf of the external device, allowing it to participate in collision detection functions. 2.4.2 IRB Isolation The ISOLATE outputs (IR10ISO IR10ISO and IR100ISO IR100ISO) are provided to control the enable pins of external bidirectional transceivers. In multi-board applications, they can be used to isolate one board from the rest of the system. Only one device can control these signals. The output states of these pins are controlled by the Isolate bits in the Master Configuration Register. Note: Datasheet Inter-board analog signals will be isolated internally by the device. 35 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 2.4.3 MMSTRIN, MMSTROUT This daisy chain is provided for correct gathering of statistics in multiple-device configurations. In multiple-board applications, this daisy chain must be maintained across boards. In stand-alone applications, or for the first device in a chain, the MMSTRIN input must be pulled Low in order for the management counters to work correctly. Figure 7. IRB Block Diagram Digital IRB Signals Hub Board 1 Analog IRB Signals '245 MMSTR IN 980 ChipID = 0 ISOLATE MMSTR OUT / IN 980 ChipID = 1 MMSTR OUT / IN 980 ChipID = n MMSTR OUT HOLDCOL IRDEN MMSTR OUT MMSTR IN Digital IRB Signals Hub Board 2 Analog IRB Signals '245 980 ChipID = 0 ISOLATE MMSTR OUT / IN 980 ChipID = 1 MMSTR OUT / IN 980 ChipID = n MMSTR OUT HOLDCOL IRDEN MMSTR OUT MMSTR IN Digital IRB Signals Hub Board n Analog IRB Signals '245 980 ChipID = 0 ISOLATE MMSTR OUT / IN 980 ChipID = 1 MMSTR OUT / IN 980 ChipID = n MMSTR OUT HOLDCOL IRDEN MMSTR OUT / IN This diagram shows a single IRB. The LXT980 LXT980 actually has two independent IRBs, one per speed/segment. Digital IRB signals include IRnDAT, IRnENA and IRnCLK. Local Analog IRB signals include IRnCOL and IRnCFS. Inter-Board Analog IRB signals include IRnCOLBP and IRnCFSBP. HOLDCOL is used on the 10Mbps IRB Only. Table 16. IRB Signal Types Connection Type Connections Between Devices (same board) Connections Between Boards Full Connect all. Connect using buffers. Local Connect all. Do not connect. Stack For devices with ChipID 0, pull-up at each device and do not interconnect. Connect devices with ChipID = 0 between boards. Use one pull-up resistor per stack. Special (xxISO) For devices with ChipID 0, leave open. For device with ChipID = 0, connect to buffer enable. Do not connect. 36 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater Table 17. IRB Signal Details Name Pad Type Buffer Pull-up Connection Type 100 Mbps IRB Signals IR100DAT IR100DAT Digital Yes No Full IR100CLK IR100CLK Digital Yes 1 k Full IR100DV IR100DV Digital, Open Drain Yes 120 Full IR100CFS IR100CFS Analog No 240, 1% Local IR100CFSBP IR100CFSBP Analog No 91, 1%2 Stack IR100COL IR100COL Digital No No Local IR100SNGL IR100SNGL Digital No No Local 1 IR100DEN IR100DEN Digital, Open Drain N/A IR100ISO IR100ISO Digital N/A1 330 Local No Special 10 Mbps IRB Signals Digital, Open Drain Yes 330 Full IR10CLK IR10CLK Digital Yes No Full IR10ENA IR10ENA Digital, Open Drain Yes 330 Full IR10CFS IR10CFS Analog No 680, 1% Local IR10CFSBP IR10CFSBP Analog No 330, 1% Stack IR10COL IR10COL Analog No 330, 1% Local IR10COLBP IR10COLBP Analog No 330, 1% Stack IR10DEN IR10DEN Digital, Open Drain N/A1 330 Local No Special IR10DAT IR10DAT IR10ISO IR10ISO Digital N/A 1 1. Isolate and Driver Enable signals are provided to control an external bidirectional transceiver. 2. 91 resistors provide greater noise immunity. Systems using 91 resistors are backwards stackable with systems using 100 resistors. 2.5 MII Port Operation The LXT980 LXT980 MII allows a MAC or PHY to directly connect into the repeater environment. The MII port (Port 5) can operate at either 10 or 100 Mbps. The LXT980 LXT980 maintains the same statistics for this `Port' as it does for the other 10/100 ports (except for illegal symbols). Utilizing two LXT980s allows the user to have a MAC interface to both the 10 and 100 Mbps segments, in addition to providing segment statistics for both. The LXT980 LXT980 does not provide MDIO/MDC capability, as this is provided via the serial controller interface. Mode and speed control is provided via PORT5_SPD and PORT5_SEL pins as listed in Table 18. Datasheet 37 LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 2.5.1 PHY Mode Operation PHY Mode is available at both 10 and 100 Mbps. It allows the LXT980 LXT980 to interface to a 10 or 100 Mbps MAC. When operating at 100 Mbps, the LXT980 LXT980 passes the full 56 bits of preamble through before sending the SFD. When operating at 10 Mbps, the LXT980 LXT980 sends data across the MII starting with the 8-bit SFD (no preamble bits). 2.5.2 MAC Mode Operation MAC Mode (available at 100 Mbps only) allows the user to attach an additional PHY to the LXT980 LXT980. In this mode the PHY provides both MII_TXCLK and MII_RXCLK. The MII_TXCLK must be frequency-locked to the 25 MHz oscillator used by the LXT980 LXT980. The LXT980 LXT980 does not provide an elasticity buffer to compensate for frequency differences. When operating in MAC mode, the LXT980 LXT980 generates the full 56 bits of preamble before sending the SFD across the MII. Table 18. MII (Port 5) Mode & Speed Control PORT5_SPD PORT5_SEL Speed & Statistics Mode High Low 100 Mbps MAC Low High 10 Mbps PHY High High 100 Mbps PHY Figure 8. MII (Port 5) Operation The LXT980 LXT980 MII port is reversible. When PHY mode is selected, the LXT980 LXT980 acts as the PHY side of the MII. In this mode an external MAC sends TX Data to the LXT980 LXT980 to be repeated to the network. The LXT980 LXT980 repeats network data to the MAC via the RX Data lines. When MAC mode is selected, the LXT980 LXT980 acts as the MAC side of the MII. In this mode the LXT980 LXT980 repeats network data to the PHY via the TX Data lines. The external PHY sends data to the LXT980 LXT980 to be repeated to the network via the RX Data lines. LXT980 LXT980 TP Ports MII Port Port 1 Port 5 Port 2 PHY Port 3 Port 4 LXT980 LXT980 TP Ports MII Port Port 1 Port 5 Port 2 MAC Mode MII_TXD MII_TXEN MII_TXER MII_TXCLK MII_RXCLK MII_RXD 10/100 MAC MII_RXDV MII_RXER MII_CRS MII_COL MII_TXD MII_TXEN MII_TXER 100 Mbps PHY MII_TXCLK MII_RXCLK MII_RXD Port 3 MII_RXDV MII_RXER Port 4 MII_CRS MII_COL 38 Datasheet LXT980/980A LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater 2.5.3 MII Port Timing Considerations The IEEE 802.3u specification provides propagation delay constraints for standard PHY devices in Section 24.6, and for repeater devices in Section 27. The LXT980 LXT980 MII port is a hybrid that does not fit either of these categories. The critical consideration that applies to the LXT980 LXT980 MII port is the overall end-to-end system propagation delay (132 bit times m