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LXT9785/LXT9785E LXT9785 LXT9785E LXT97985E 10BASE-T 100BASE-TX 100BASE-FX - Datasheet Archive
Advanced 10/100 8-Port Transceivers Datasheet The LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers that support
LXT9785/LXT9785E LXT9785/LXT9785E Advanced 10/100 8-Port Transceivers Datasheet The LXT9785 LXT9785 and LXT9785E LXT9785E are 8-port Fast Ethernet PHY Transceivers that support IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide both Serial/ Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9785 LXT9785 and LXT9785E LXT9785E are identical except for the IP telephony features included in the LXT9785E LXT9785E transceiver. The LXT9785E LXT9785E is an enhanced version of the LXT9785 LXT9785 that detects Data Terminal Equipment (DTE) capable of being powered remotely from the switch over a Category 5 cable. The system can use the information collected by the LXT97985E LXT97985E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone. All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for both 10 Mbps or 100 Mbps (10BASE-T 10BASE-T and 100BASE-TX 100BASE-TX) Ethernet over twisted-pair, or 100 Mbps (100BASE-FX 100BASE-FX) Ethernet over fiber-optic media. The LXT9785/9785E LXT9785/9785E provides three discrete LED driver outputs for each port. The devices support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single 2.5V power supply. Applications I I Enterprise switches IP telephony switches I I Storage Area Networks Multi-port Network Interface Cards (NICs) Product Features I I I I I I I I Eight IEEE 802.3-compliant 10BASE-T 10BASE-T or 100BASE-TX 100BASE-TX ports with integrated filters. 100BASE-FX 100BASE-FX fiber-optic capability on all ports. 2.5V operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDIX crossover capabilities. Proprietary Optimal Signal ProcessingTM architecture improves SNR by 3 dB over ideal analog filters. Optimized for dual-high stacked RJ-45 RJ-45 applications. I I I I I I I I MDIO sectionalization into 2x4 or 1x8 configurations. Supports both auto-negotiation systems and legacy systems without auto-negotiation capability. Robust baseline wander correction. Configurable via MDIO port or external control pins. JTAG boundary scan. 208-pin PQFP: LXT9785HC LXT9785HC, LXT9785EHC LXT9785EHC 241-ball BGA: LXT9785BC LXT9785BC, LXT9785EBC LXT9785EBC DTE detection for remote powering applications (LXT9785E LXT9785E only). As of January 15, 2001, this document replaces the Level One document known as LXT9785/9785E LXT9785/9785E Advanced 10/100 8-Port PHY Datasheet. Order Number: 249241-003 April 2001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT9785/9785E LXT9785/9785E may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. 2 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Contents Contents 1.0 Pin Assignments and Signal Descriptions . 12 1.1 2.0 Signal Name Conventions . 39 Functional Description. 51 2.1 2.2 2.3 2.4 2.5 2.6 Introduction . 51 2.1.1 OSPTM Architecture . 51 2.1.2 Comprehensive Functionality . 51 2.1.2.1 Sectionalization. 52 Interface Descriptions . 52 2.2.1 10/100 Network Interface. 52 2.2.1.1 Twisted-Pair Interface . 53 2.2.1.2 MDI Crossover (MDIX). 53 2.2.1.3 Fiber Interface. 53 Media Independent Interface (MII) Interfaces. 53 2.3.1 Global MII Mode Select . 54 2.3.2 Internal Loopback . 54 2.3.3 RMII Data Interface. 54 2.3.4 Serial Media Independent Interface (SMII) and Source Synchronous- Serial Media Independent Interface (SS-SMII)54 2.3.4.1 SMII Interface. 54 2.3.4.2 Source Synchronous-Serial Media Independent Interface . 55 2.3.5 Configuration Management Interface . 55 2.3.6 MII Isolate . 55 2.3.6.1 MDIO Management Interface. 55 2.3.6.2 MII Sectionalization. 57 2.3.6.3 MII Interrupts . 57 2.3.6.4 Global Hardware Control Interface . 57 Operating Requirements. 58 2.4.1 Power Requirements . 58 2.4.2 Clock/SYNC Requirements. 58 2.4.2.1 Reference Clock . 58 2.4.2.2 TxCLK Signal (SS-SMII only). 58 2.4.2.3 TxSYNC Signal (SMII/SS-SMII). 58 2.4.2.4 RxSYNC Signal (SS-SMII only) . 58 2.4.2.5 RxCLK Signal (SS-SMII only) . 58 Initialization . 59 2.5.1 MDIO Control Mode . 59 2.5.2 Hardware Control Mode. 59 2.5.3 Power-Down Mode . 60 2.5.3.1 Global (Hardware) Power Down . 60 2.5.3.2 Port (Software) Power Down . 61 2.5.4 Reset . 61 2.5.5 Hardware Configuration Settings . 62 Link Establishment. 62 2.6.1 Auto-Negotiation . 62 2.6.1.1 Base Page Exchange . 62 2.6.1.2 Next Page Exchange . 62 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 3 Contents 2.7 2.8 2.9 2.10 2.11 2.12 4 2.6.1.3 Controlling Auto-Negotiation . 63 2.6.1.4 Link Criteria. 63 2.6.1.5 Parallel Detection. 63 Serial MII Operation. 64 2.7.1 SMII Reference Clock. 67 2.7.2 TxSYNC Pulse (SMII/SS-SMII). 67 2.7.3 Transmit Data Stream. 67 2.7.3.1 Transmit Enable. 67 2.7.3.2 Transmit Error . 67 2.7.4 Receive Data Stream. 68 2.7.4.1 Carrier Sense. 68 2.7.4.2 Receive Data Valid . 68 2.7.4.3 Receive Error . 68 2.7.4.4 Receive Status Encoding. 68 2.7.5 Collision . 69 2.7.5.1 Source Synchronous-Serial Media Independent Interface . 69 RMII Operation . 74 2.8.1 RMII Reference Clock. 74 2.8.2 Transmit Enable. 74 2.8.3 Carrier Sense & Data Valid. 74 2.8.4 Receive Error. 74 2.8.5 Out-of-Band Signalling. 74 2.8.6 4B/5B Coding Operations . 74 100 Mbps Operation . 78 2.9.1 100BASE-X 100BASE-X Network Operations. 78 2.9.2 100BASE-X 100BASE-X Protocol Sublayer Operations. 78 2.9.2.1 PCS Sublayer . 78 2.9.3 PMA Sublayer. 80 2.9.3.1 Twisted-Pair PMD Sublayer. 82 2.9.3.2 Fiber PMD Sublayer. 82 10 Mbps Operation . 83 2.10.1 Preamble Handling . 83 2.10.2 Dribble Bits . 83 2.10.3 Link Test . 83 2.10.3.1 Link Failure . 84 2.10.4 Jabber. 84 DTE Discovery Process. 85 2.11.1 Definitions . 85 2.11.2 Interaction between Processor, MAC and PHY. 86 2.11.3 Management Interface and Control . 87 2.11.4 DTE Discovery Process Function Description . 88 Monitoring Operations . 91 2.12.1 Monitoring Auto-Negotiation . 91 2.12.2 Per-Port LED Driver Functions . 91 2.12.3 Out-of-Band Signalling. 92 2.12.4 Boundary Scan Interface . 93 2.12.5 State Machine. 93 2.12.6 Instruction Register. 93 2.12.7 Boundary Scan Register. 93 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Contents 3.0 Application Information . 94 3.1 3.2 3.3 Design Recommendations. 94 General Design Guidelines . 94 3.2.1 Power Supply Filtering . 94 3.2.2 Power and Ground Plane Layout Considerations. 95 3.2.2.1 Chassis Ground . 95 3.2.3 MII Terminations . 95 3.2.4 Twisted-Pair Interface. 96 3.2.4.1 Magnetic Requirements . 96 3.2.5 The Fiber Interface . 96 3.2.6 LED Circuit. 97 Typical Application Circuits . 98 4.0 Test Specifications.100 5.0 Register Definitions.125 6.0 Package Specifications.143 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 5 Contents Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 6 LXT9785/9785E LXT9785/9785E Block Diagram . 11 LXT9785/9785E LXT9785/9785E RMII 208-Pin PQFP Assignments . 12 LXT9785/9785E LXT9785/9785E SMII 208-Pin PQFP Assignments . 13 LXT9785/9785E LXT9785/9785E SS-SMII 208-Pin PQFP Assignments . 14 LXT9785/9785E LXT9785/9785E RMII 241-Ball PBGA Assignments . 15 LXT9785/9785E LXT9785/9785E SMII 241-Ball PBGA Assignments . 16 LXT9785/9785E LXT9785/9785E SS-SMII 241-Ball PBGA Assignments . 17 LXT9785/9785E LXT9785/9785E Interfaces. 52 Internal Loopback . 54 Management Interface Read Frame Structure . 56 Management Interface Write Frame Structure . 56 Port Address Scheme. 56 Interrupt Logic. 57 Initialization Sequence. 60 Auto-Negotiation Operation . 63 Typical SMII Interface Diagram . 65 Typical SMII Quad Sectionalization Diagram . 66 100 Mbps Serial MII Data Flow . 67 Serial MII Transmit Synchronization. 68 Serial MII Receive Synchronization. 69 Typical SS-SMII Interface Diagram . 71 Typical SS-SMII Quad Sectionalization Diagram . 72 SS-SMII Transmit Timing . 73 SS-SMII Receive Timing . 73 RMII Data Flow. 75 Typical RMII Interface Diagram . 76 Typical RMII Quad Sectionalization Diagram . 77 100BASE-X 100BASE-X Frame Format. 78 Protocol Sublayers . 79 Typical IP Telephone System Connection. 85 LXT9785E LXT9785E Negotiation Flow Chart . 90 LED Pulse Stretching . 92 RMII Programmable Out-of-Bank Signaling . 92 LED Circuit . 97 Power and Ground Supply Connections . 98 Typical Twisted-Pair Interface . 99 Typical Fiber Interface . 99 SMII - 100BASE-TX 100BASE-TX Receive Timing . 104 SMII - 100BASE-TX 100BASE-TX Transmit Timing. 105 SMII - 100BASE-FX 100BASE-FX Receive Timing . 106 SMII - 100BASE-FX 100BASE-FX Transmit Timing. 107 SMII - 10BASE-T 10BASE-T Receive Timing . 108 SMII - 10BASE-T 10BASE-T Transmit Timing . 109 SS-SMII - 100BASE-TX 100BASE-TX Receive Timing . 110 SS-SMII - 100BASE-TX 100BASE-TX Transmit Timing. 111 SS-SMII - 100BASE-FX 100BASE-FX Receive Timing . 112 SS-SMII - 100BASE-FX 100BASE-FX Transmit Timing. 113 SS-SMII - 10BASE-T 10BASE-T Receiving Timing . 114 SS-SMII - 10BASE-T 10BASE-T Transmit Timing . 115 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Contents 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RMII - 100BASE-TX 100BASE-TX Receive Timing.116 RMII - 100BASE-TX 100BASE-TX Transmit Timing.117 RMII - 100BASE-FX 100BASE-FX Receive Timing.118 RMII - 100BASE-FX 100BASE-FX Transmit Timing.119 RMII - 10BASE-T 10BASE-T Receive Timing .120 RMII - 10BASE-T 10BASE-T Transmit Timing .121 Auto-Negotiation and Fast Link Pulse Timing.122 Fast Link Pulse Timing .122 MDIO Write Timing (MDIO Sourced by MAC) . 123 MDIO Read Timing (MDIO Sourced by PHY).123 Power-Up Timing .124 Reset Recovery Timing .124 PHY Identifier Bit Mapping. 128 LXT9785/9785E LXT9785/9785E 208-Pin PQFP Plastic Package Specification.143 LXT9785/9785E LXT9785/9785E 241-Ball PBGA Package Specs - Top/Side View(LXT9785BC/LXT9785EBC LXT9785BC/LXT9785EBC) . 144 65 LXT9785/9785E LXT9785/9785E 241-Ball PBGA Package Specs - Bottom View (LXT9785BC/LXT9785EBC LXT9785BC/LXT9785EBC)145 Tables 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 RMII PQFP Pin List. 18 SMII PQFP Pin List. 25 SS-SMII PQFP Pin List. 32 LXT9785/9785E LXT9785/9785E RMII Signal Descriptions . 39 LXT9785/9785E LXT9785/9785E SMII Specific Signal Descriptions . 41 LXT9785/9785E LXT9785/9785E SMII / SS-SMII Common Signal Descriptions. 41 LXT9785/9785E LXT9785/9785E SS-SMII Specific Signal Descriptions . 42 MDIO Control Interface Signals . 43 LXT9785/9785E LXT9785/9785E Signal Detect . 44 LXT9785/9785E LXT9785/9785E Network Interface Signal Descriptions. 44 LXT9785/9785E LXT9785/9785E JTAG Test Signal Descriptions. 45 LXT9785/9785E LXT9785/9785E Miscellaneous Signal Descriptions . 46 LXT9785/9785E LXT9785/9785E LED Signal Descriptions . 48 LXT9785/9785E LXT9785/9785E Power Supply Signal Descriptions. 49 Unused / Reserved Pins . 50 MDIX Selection . 53 MII Mode Select. 54 Global Hardware Configuration Settings . 62 SMII Signal Summary . 64 RX Status Encoding Bit Definitions. 69 SS-SMII . 70 4B/5B Coding. 80 Next Page Message #5 Code Word Definitions . 89 BSR Mode of Operation. 93 Supported JTAG Instructions. 93 Magnetics Requirements . 96 Absolute Maximum Ratings .100 Operating Conditions .100 Digital I/O DC Electrical Characteristics (VCCIO = 2.5V +/- 5%).101 Digital I/O DC Electrical Characteristics (VCCIO = 3.3V +/- 5%).102 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 7 Contents 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 8 Required Clock Characteristics . 102 100BASE-TX 100BASE-TX Transceiver Characteristics. 102 100BASE-FX 100BASE-FX Transceiver Characteristics. 103 10BASE-T 10BASE-T Transceiver Characteristics . 103 SMII - 100BASE-TX 100BASE-TX Receive Timing Parameters . 104 SMII - 100BASE-TX 100BASE-TX Transmit Timing Parameters . 105 SMII - 100BASE-FX 100BASE-FX Receive Timing Parameters . 106 SMII - 100BASE-FX 100BASE-FX Transmit Timing Parameters . 107 SMII - 10BASE-T 10BASE-T Receive Timing Parameters. 108 SMII-10BASE-T SMII-10BASE-T Transmit Timing Parameters. 109 SS-SMII - 100BASE-TX 100BASE-TX Receive Timing Parameters . 110 SS-SMII - 100BASE-TX 100BASE-TX Transmit Timing. 111 SS-SMII - 100BASE-FX 100BASE-FX Receive Timing Parameters . 112 SS-SMII - 100BASE-FX 100BASE-FX Transmit Timing Parameters . 113 SS-SMII - 10BASE-T 10BASE-T Receive Timing Parameters. 114 SS-SMII - 10BASE-T 10BASE-T Transmit Timing Parameters. 115 RMII - 100BASE-TX 100BASE-TX Receive Timing Parameters . 116 RMII - 100BASE-TX 100BASE-TX Transmit Timing Parameters . 117 RMII - 100BASE-FX 100BASE-FX Receive Timing Parameters . 118 RMII - 100BASE-FX 100BASE-FX Transmit Timing Parameters . 119 RMII - 10BASE-T 10BASE-T Receive Timing Parameters . 120 RMII - 10BASE-T 10BASE-T Transmit Timing Parameters . 121 Auto-Negotiation and Fast Link Pulse Timing Parameters . 122 MDIO Timing Parameters . 123 Power-Up Timing Parameters . 124 Reset Recovery Timing Parameters. 124 Register Set. 125 Control Register (Address 0) . 126 Status Register (Address 1) . 127 PHY Identification Register 1 (Address 2) . 128 PHY Identification Register 2 (Address 3) . 128 Auto-Negotiation Advertisement Register (Address 4)6. 129 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) . 130 Auto-Negotiation Expansion (Address 6) . 131 Auto-Negotiation Next Page Transmit Register (Address 7) . 131 Auto-Negotiation Link Partner Next Page Receive Register (Address 8). 132 Port Configuration Register (Address 16, Hex 10) . 133 Quick Status Register (Address 17, Hex 11). 134 Interrupt Enable Register (Address 18, Hex 12). 135 Interrupt Status Register (Address 19, Hex 13). 136 LED Configuration Register (Address 20, Hex 14). 137 Receive Error Count Register (Address 21) . 138 RMII Out-of-Band Signalling Register (Address 25) . 139 Trim Enable Register (Address 27) . 140 Trim Status Register (Address 28) . 140 Register Bit Map . 141 LXT9785/9785E LXT9785/9785E 241-Ball PBGA Package Dimensions. 145 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Contents Revision History Date Revision Page Description 1 LED Circuit: Modified paragraph language. 97 LED Circuit diagram: Modified diagram. 99 Replaced Typical Fiber Interface diagram. 102 Required Clock Characteristics table: Replaced SMII Input frequency and RMII Input frequency symbol with "f". 122 Auto-Negotiation and Fast Link Pulse Timing Parameters: FLP burst width under Typ = 2. 126 Control Register table: Modified table and table notes. 128 PHY Identification Register 2 (Address 3): Modified table. 128 PHY Identifier Bit Mapping: Modified diagram. 131 Auto-Negotiation Expansion: Modified table and table notes. 133 Port Configuration Register table: Modified table and table notes. 140 Trim Enable Register: Modified table (DTE Discovery). 141 Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Supported JTAG Instructions table: replaced long hit streams with hex. 97 Datasheet Added new section on DTE discovery. 93 003 Reset: Modified language in first paragraph. 85 April 2001 Modified and added new language to front page. 61 Modified Register Bit Map table. 9 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Figure 1. LXT9785/9785E LXT9785/9785E Block Diagram 8-Port Global Functions RMII/SMII Contr ADD_ MDIO Management / Mode Select Logic & LED Drivers 2 MDC 2 MDINT RESET PWRDN Clock Generator REFCLK SYNC (SMII only) 2 Register Set Manchester Encoder TX PCS TxDatan Parallel/Serial Converter Scrambler & Encoder Auto Negotiation Mgmt Counters 10 100 Pulse Shaper TP Driver ECL Driver CIM + TP / Fiber Out + Fiber select n Media Select Clock Generator + Adaptive EQ with BL Wander Cancellation 100TX 100TX + RX PCS RxDatan Port LED Drivers 3 Serial to Parallel Converter Carrier Sense Data Valid Error Detect TPFONn - Register Set LEDn_ TPFOPn 10 100 Manchester Decoder 100FX 100FX Slicer TP / Fiber In TPFIPn TPFINn - Decoder & Descrambler + 10BT Per-Port Functions PORT 0 - PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 11 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY 1.0 Pin Assignments and Signal Descriptions 208 . VCCIO 207 . GNDIO 206 . RxData6_0 205 . RxData6_1 204 . TxData7_1 203 . TxData7_0 202 . TxEN7 201 . RxER7 200 . CRS_DV7 199 . GNDIO 198 . RxData7_0 197 . RxData71 196 . VCCD 195 . GNDD 194 . LED7_3 193 . LED7_2 192 . LED7_1 191 . LED6_3 190 . LED6_2 189 . LED6_1 188 . GNDIO 187 . LED5_3 186 . LED5_2 185 . LED5_1 184 . VCCD 183 . GNDD 182 . LED4_3 181 . LED4_2 180 . LED4_1 179 . SGND 178 . ModeSel1 177 . ModeSel0 176 . Section 175 . RESET 174 . PWRDWN 173 . G_FX/TP 172 . N/C 171. TRST 170 . TCK 169 . TMS 168 . TDO 167 . TDI 166 . SD7 165 . SD6 164 . VCCPECL 163 . GNDPECL 162 . SD5 161 . SD4 160 . N/C 159 . N/C 158 . VCCR7 157 . TPFIP7 Figure 2. LXT9785/9785E LXT9785/9785E RMII 208-Pin PQFP Assignments Part # LOT # FPO # LXT9785/9785E LXT9785/9785E XX XXXXXX XXXXXXXX Rev # 156 .TPFIN7 155 .GNDR7 154 .TPFOP7 153 .TPFON7 152 .VCCT6/7 151 .TPFON6 150 .TPFOP6 149 .GNDR6 148 .GNDT6/7 147 .TPFIN6 146 .TPFIP6 145 .VCCR6 144 .VCCR5 143 .TPFIP5 142 .TPFIN5 141 .GNDR5 140 .TPFOP5 139 .TPFON5 138 .VCCT4/5 137 .TPFON4 136 .TPFOP4 135 .GNDR4 134 .GNDT4/5 133 .TPFIN4 132 .TPFIP4 131 .VCCR4 130 .VCCR3 129 .TPFIP3 128 .TPFIN3 127 .GNDT2/3 126 .GNDR3 125 .TPFOP3 124 .TPFON3 123 .VCCT2/3 122 .TPFON2 121 .TPFOP2 120 .GNDR2 119 .TPFIN2 118 .TPFIP2 117 .VCCR2 116 .VCCR1 115 .TPFIP1 114 .TPFIN1 113 .GNDT0/1 112 .GNDR1 111 .TPFOP1 110 .TPFON1 109 .VCCT0/1 108 .TPFON0 107 .TPFOP0 106 .GNDR0 105 .TPFIN0 TxData1_1 . 53 RxData0_1 . 54 RxData0_0 . 55 VCCIO . 56 GNDIO . 57 CRS_DV0 . 58 RxER0/MDIX . 59 TxEN0 . 60 TxData0_0 . 61 TxData0_1 . 62 MDC0 . 63 MDIO0 . 64 VCCD . 65 GNDD . 66 MDINT0 . 67 LED3_3 . 68 LED3_2 . 69 LED3_1 . 70 LED2_3 . 71 LED2_2 . 72 LED2_1 . 73 GNDIO . 74 LED1_3 . 75 LED1_2 . 76 LED1_1 . 77 VCCD . 78 GNDD . 79 LED0_3 . 80 LED0_2 . 81 LED0_1 . 82 AMDIX_EN . 83 MDDIS . 84 CFG_3 . 85 CFG_2 . 86 CFG_1 . 87 ADD_4 . 88 ADD_3 . 89 ADD_2 . 90 ADD_1 . 91 ADD_0 . 92 TxSlew_1 . 93 TxSlew_0 . 94 SD_2P5V . 95 SD0 . 96 SD1 . 97 VCCPECL . 98 GNDPECL . 99 SD2 . 100 SD3 . 101 N/C . 102 VCCR0 . 103 TPFIP0 . 104 CRS_DV6 . 1 RxER6 . 2 TxEN6 . 3 TxData6_0 . 4 TxData6_1 . 5 REFCLK1 . 6 RxData5_1 . 7 RxData5_0 . 8 GNDIO . 9 CRS_DV5 . 10 RxER5 . 11 TxEN5 . 12 TxData5_0 . 13 TxData5_1 . 14 RxData4_1 . 15 RxData4_0 . 16 CRS_DV4 . 17 VCCIO . 18 GNDIO . 19 RxER4 . 20 TxEN4 . 21 TxData4_0 . 22 TxData4_1 . 23 MDC1 . 24 MDIO1 . 25 MDINT1 . 26 RxData3_1 . 27 RxData3_0 . 28 VCCIO . 29 GNDIO . 30 CRS_DV3 . 31 RxER3 . 32 TxEN3 . 33 TxData3_0 . 34 TxData3_1 . 35 RxData2_1 . 36 RxData2_0 . 37 GNDIO . 38 CRS_DV2 . 39 RxER2 . 40 TxEN2 . 41 TxData2_0 . 42 TxData2_1 . 43 REFCLK0 . 44 RxData1_1 . 45 RxData1_0 . 46 VCCIO . 47 GNDIO . 48 CRS_DV1 . 49 xER1/PAUSE . 50 TxEN1 . 51 TxData1_0 . 52 12 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E 208 . 207 . 206 . 205 . 204 . 203 . 202 . 201 . 200 . 199 . 198 . 197 . 196 . 195 . 194 . 193 . 192 . 191 . 190 . 189 . 188 . 187 . 186 . 185 . 184 . 183 . 182 . 181 . 180 . 179 . 178 . 177 . 176 . 175 . 174 . 173 . 172 . 171. 170 . 169 . 168 . 167 . 166 . 165 . 164 . 163 . 162 . 161 . 160 . 159 . 158 . 157 . VCCIO GNDIO RxData6 N/C SYNC1 TxData7 N/C N/C N/C GNDIO RxData7 N/C VCCD GNDD LED7_3 LED7_2 LED7_1 LED6_3 LED6_2 LED6_1 GNDIO LED5_3 LED5_2 LED5_1 VCCD GNDD LED4_3 LED4_2 LED4_1 SGND ModeSel_1 ModeSel_0 Section RESET PWRDWN G_FX/TP N/C TRST TCK TMS TDO TDI SD7 SD6 VCCPECL GNDPECL SD5 SD4 N/C N/C VCCR7 TPFIP7 Figure 3. LXT9785/9785E LXT9785/9785E SMII 208-Pin PQFP Assignments Part # LOT # FPO # LXT9785/9785E LXT9785/9785E XX XXXXXX XXXXXXXX Rev # 156 .TPFIN7 155 .GNDR7 154 .TPFOP7 153 .TPFON7 152 .VCCT6/7 151 .TPFON6 150 .TPFOP6 149 .GNDR6 148 .GNDT6/7 147 .TPFIN6 146 .TPFIP6 145 .VCCR6 144 .VCCR5 143 .TPFIP5 142 .TPFIN5 141 .GNDR5 140 .TPFOP5 139 .TPFON5 138 .VCCT4/5 137 .TPFON4 136 .TPFOP4 135 .GNDR4 134 .GNDT4/5 133 .TPFIN4 132 .TPFIP4 131 .VCCR4 130 .VCCR3 129 .TPFIP3 128 .TPFIN3 127 .GNDT2/3 126 .GNDR3 125 .TPFOP3 124 .TPFON3 123 .VCCT2/3 122 .TPFON2 121 .TPFOP2 120 .GNDR2 119 .TPFIN2 118 .TPFIP2 117 .VCCR2 116 .VCCR1 115 .TPFIP1 114 .TPFIN1 113 .GNDT0/1 112 .GNDR1 111 .TPFOP1 110 .TPFON1 109 .VCCT0/1 108 .TPFON0 107 .TPFOP0 106 .GNDR0 105 .TPFIN0 N/C . 53 N/C . 54 RxData0 . 55 VCCIO . 56 GNDIO . 57 N/C . 58 MDIX . 59 N/C . 60 TxData0 . 61 N/C . 62 MDC0 . 63 MDIO0 . 64 VCCD . 65 GNDD . 66 MDINT0 . 67 LED3_3 . 68 LED3_2 . 69 LED3_1 . 70 LED2_3 . 71 LED2_2 . 72 LED2_1 . 73 GNDIO . 74 LED1_3 . 75 LED1_2 . 76 LED1_1 . 77 VCCD . 78 GNDD . 79 LED0_3 . 80 LED0_2 . 81 LED0_1 . 82 AMDIX_EN . 83 MDDIS . 84 CFG_3 . 85 CFG_2 . 86 CFG_1 . 87 ADD_4 . 88 ADD_3 . 89 ADD_2 . 90 ADD_1 . 91 ADD_0 . 92 TxSlew_1 . 93 TxSlew_0 . 94 SD_2P5V . 95 SD0 . 96 SD1 . 97 VCCPECL . 98 GNDPECL . 99 SD2 . 100 SD3 . 101 N/C . 102 VCCR0 . 103 TPFIP0 . 104 N/C . 1 N/C . 2 N/C . 3 TxData6 . 4 N/C . 5 REFCLK1 . 6 N/C . 7 RxData5 . 8 GNDIO . 9 N/C . 10 N/C . 11 N/C . 12 TxData5 . 13 N/C . 14 N/C . 15 RxData4 . 16 N/C . 17 VCCIO . 18 GNDIO . 19 N/C . 20 N/C . 21 TxData4 . 22 N/C . 23 MDC1 . 24 MDIO1 . 25 MDINT1 . 26 N/C . 27 RxData3 . 28 VCCIO . 29 GNDIO . 30 N/C . 31 N/C . 32 N/C . 33 TxData3 . 34 SYNC0 . 35 N/C . 36 RxData2 . 37 GNDIO . 38 N/C . 39 N/C . 40 N/C . 41 TxData2 . 42 N/C . 43 REFCLK0 . 44 N/C . 45 RxData1 . 46 VCCIO . 47 GNDIO . 48 N/C . 49 PAUSE . 50 N/C . 51 TxData1 . 52 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 13 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY 208 . VCCIO 207 . GNDIO 206 . N/C 205 . RxData6 204 . TxSYNC1 203 . TxData7 202 . N/C 201 . TxCLK1 200 . N/C 199 . GNDIO 198 . N/C 197 . RxData7 196 . VCCD 195 . GNDD 194 . LED7_3 193 . LED7_2 192 . LED7_1 191 . LED6_3 190 . LED6_2 189 . LED6_1 188 . GNDIO 187 . LED5_3 186 . LED5_2 185 . LED5_1 184 . VCCD 183 . GNDD 182 . LED4_3 181 . LED4_2 180 . LED4_1 179 . SGND 178 . ModeSel_1 177 . ModeSel_0 176 . Section 175 . RESET 174 . PWRDWN 173 . G_FX/TP 172 . N/C 171. TRST 170 . TCK 169 . TMS 168 . TDO 167 . TDI 166 . SD7 165 . SD6 164 . VCCPECL 163 . GNDPECL 162 . SD5 161 . SD4 160 . N/C 159 . N/C 158 . VCCR7 157 . TPFIP7 Figure 4. LXT9785/9785E LXT9785/9785E SS-SMII 208-Pin PQFP Assignments Part # LOT # FPO # LXT9785/9785E LXT9785/9785E XX XXXXXX XXXXXXXX Rev # 156 .TPFIN7 155 .GNDR7 154 .TPFOP7 153 .TPFON7 152 .VCCT6/7 151 .TPFON6 150 .TPFOP6 149 .GNDR6 148 .GNDT6/7 147 .TPFIN6 146 .TPFIP6 145 .VCCR6 144 .VCCR5 143 .TPFIP5 142 .TPFIN5 141 .GNDR5 140 .TPFOP5 139 .TPFON5 138 .VCCT4/5 137 .TPFON4 136 .TPFOP4 135 .GNDR4 134 .GNDT4/5 133 .TPFIN4 132 .TPFIP4 131 .VCCR4 130 .VCCR3 129 .TPFIP3 128 .TPFIN3 127 .GNDT2/3 126 .GNDR3 125 .TPFOP3 124 .TPFON3 123 .VCCT2/3 122 .TPFON2 121 .TPFOP2 120 .GNDR2 119 .TPFIN2 118 .TPFIP2 117 .VCCR2 116 .VCCR1 115 .TPFIP1 114 .TPFIN1 113 .GNDT0/1 112 .GNDR1 111 .TPFOP1 110 .TPFON1 109 .VCCT0/1 108 .TPFON0 107 .TPFOP0 106 .GNDR0 105 .TPFIN0 N/C . 53 RxData0 . 54 N/C . 55 VCCIO . 56 GNDIO . 57 RxSYNC0 . 58 MDIX . 59 RxCLK0 . 60 TxData0 . 61 N/C . 62 MDC0 . 63 MDIO0 . 64 VCCD . 65 GNDD . 66 MDINT0 . 67 LED3_3 . 68 LED3_2 . 69 LED3_1 . 70 LED2_3 . 71 LED2_2 . 72 LED2_1 . 73 GNDIO . 74 LED1_3 . 75 LED1_2 . 76 LED1_1 . 77 VCCD . 78 GNDD . 79 LED0_3 . 80 LED0_2 . 81 LED0_1 . 82 AMDIX_EN . 83 MDDIS . 84 CFG_3 . 85 CFG_2 . 86 CFG_1 . 87 ADD_4 . 88 ADD_3 . 89 ADD_2 . 90 ADD_1 . 91 ADD_0 . 92 TxSlew_1 . 93 TxSlew_0 . 94 SD_2P5V . 95 SD0 . 96 SD1 . 97 VCCPECL . 98 GNDPECL . 99 SD2 . 100 SD3 . 101 N/C . 102 VCCR0 . 103 TPFIP0 . 104 N/C . 1 N/C . 2 N/C . 3 TxData6 . 4 N/C . 5 REFCLK1 . 6 RxData5 . 7 N/C . 8 GNDIO . 9 N/C . 10 N/C . 11 N/C . 12 TxData5 . 13 N/C . 14 RxData4 . 15 N/C . 16 RxSYNC1 . 17 VCCIO . 18 GNDIO . 19 N/C . 20 RxCLK1 . 21 TxData4 . 22 N/C . 23 MDC1 . 24 MDIO1 . 25 MDINT1 . 26 RxData3 . 27 N/C . 28 VCCIO . 29 GNDIO . 30 N/C . 31 TxCLK0 . 32 N/C . 33 TxData3 . 34 TxSYNC0 . 35 RxData2 . 36 N/C . 37 GNDIO . 38 N/C . 39 N/C . 40 N/C . 41 TxData2 . 42 N/C . 43 REFCLK0 . 44 RxData1 . 45 N/C . 46 VCCIO . 47 GNDIO . 48 N/C . 49 PAUSE . 50 N/C . 51 TxData1 . 52 14 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Figure 5. LXT9785/9785E LXT9785/9785E RMII 241-Ball PBGA Assignments RMI I 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A GNDD VCCIO RxData 1_0 TxData 2_1 CRS_D V2 TxData 3_1 TxEN3 VCCIO GNDD MDIO1 TxData 4_0 RxER4 RxData 4_0 TxEN5 RxER5 TxData 6_1 RxER6 B RxData 0_1 TxEN1 GNDD RxData 1_1 TxData 2_0 RxData 2_0 GNDD CRS_D V3 RxData 3_1 MDC1 TxEN4 CRS_D V4 TxData 5_0 RxData 5_0 RxData 5_1 CRS_ DV6 RXD6_ 1 B C VCCIO RXD0_ 0 TXD1_0 CRS_D V1 GNDD TxEN2 RxData 2_1 RxER3 MDINT1 TxData 4_1 VCCIO RxData 4_1 GNDD TxEN6 RxData 6_0 TxData 7_1 GNDD C D GNDD RxER0/ MDIX GNDD TxData 1_1 RxER1/ PAUSE GNDD RxER2 TxData 3_0 RxData 3_0 GNDD TxData 5_1 CRS_D V5 TxData 6_0 VCCIO GNDD TxEN7 RxER7 D E MDC0 TxData 0_0 TxEN0 CRS_D V0 GNDD REF CLK0 GNDD GNDD REF CLK1 GNDD TXD7_0 CRS_D V7 RxData 7_0 GNDD E F MDINT0 LED3_1 MDIO0 TxData 0_1 VCCD GNDD RXD7_ 1 N/C LED7_3 LED7_2 F G LED2_3 N/C LED3_2 LED3_3 N/C VCCD N/C LED7_1 N/C LED6_3 G H LED1_3 LED2_1 LED2_2 N/C N/C LED6_1 LED6_2 LED5_3 H J LED0_3 N/C LED1_2 LED1_1 VCCD LED5_1 LED5_2 LED4_3 J K AMDIX_ EN LED0_2 LED0_1 N/C SGND N/C LED4_1 LED4_2 K L MDDIS CFG_3 CFG_2 ADD_4 VCC PECL VCC PECL PWR DWN SEC TION MODE SEL_0 MODE SEL_1 L M CFG_1 ADD_3 ADD_2 TxSLE W_1 GND PECL GND PECL G_FX/ TP RESET TCK TRST M N ADD_1 ADD_0 TxSLE W_0 SD1 SD3 VCCT VCCT P SD_2P5 V SD0 SD2 VCCR GNDR GNDR VCCR VCCR VCCR R GNDT TPFIP (0) GNDT TPFON( 1) GNDT TPFIP (2) GNDR TPFIN (3) T TPFIN (0) TPFOP (0) TPFOP (1) TPFIN (1) TPFIN (2) TPFOP (2) TPFON (3) U TPFON (0) GNDT TPFIP (1) GNDT TPFON (2) GNDT 1 2 3 4 5 6 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 GNDD GNDD GNDD GNDD GNDD GNDD GNDD VCCD GNDD GNDD GNDD VCCT N/C A VCCT VCCT VCCR TDI TDO TMS SD7 N VCCR VCCR VCCR GNDR GNDT SD4 SD5 SD6 P GNDR TPFON (4) GNDR TPFIP (6) GNDR TPFOP (7) GNDT TPFIP (7) GNDT R TPFIP (3) TPFIP (4) TPFOP (4) TPFOP (5) TPFIN (5) TPFIN (6) TPFOP (6) TPFON (7) TPFIN (7) GNDT T TPFOP (3) GNDR TPFIN (4) GNDT TPFON (5) GNDT TPFIP (5) GNDT TPFON (6) GNDT GNDT U 7 8 9 10 11 12 13 14 15 16 17 15 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Figure 6. LXT9785/9785E LXT9785/9785E SMII 241-Ball PBGA Assignments SMI I 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A GNDD VCCIO RxData 1 N/C N/C SYNC0 N/C VCCIO GNDD MDIO1 TxData 4 N/C RxData 4 N/C N/C N/C N/C B N/C N/C GNDD N/C TxData 2 RxData 2 GNDD N/C N/C MDC1 N/C N/C TxData 5 RxData 5 N/C N/C N/C B C VCCIO RxData 0 TxData 1 N/C GNDD N/C N/C N/C MDINT1 N/C VCCIO N/C GNDD N/C RxData 6 SYNC1 GNDD C D GNDD MDIX GNDD N/C PAUSE GNDD N/C TxData 3 RxData 3 GNDD N/C N/C TxData 6 VCCIO GNDD N/C N/C D E MDC0 TxData 0 N/C N/C GNDD REF CLK0 GNDD GNDD REF CLK1 GNDD TxData 7 N/C RxData 7 GNDD E F MDINT0 LED3_1 MDIO0 N/C VCCD GNDD N/C N/C LED7_3 LED7_2 F G LED2_3 N/C LED3_2 LED3_3 N/C VCCD N/C LED7_1 N/C LED6_3 G H LED1_3 LED2_1 LED2_2 N/C N/C LED6_1 LED6_2 LED5_3 H J LED0_3 N/C LED1_2 LED1_1 VCCD LED5_1 LED5_2 LED4_3 J K AMDIX_ EN LED0_2 LED0_1 N/C N/C LED4_1 LED4_2 K L MDDIS CFG_3 CFG_2 ADD_4 VCC PECL VCC PECL PWR DWN SECTIO N MODE SEL_0 MODE SEL_1 L M CFG_1 ADD_3 ADD_2 TxSLE W_1 GND PECL GND PECL G_FX/ TP RESET TCK TRST M N ADD_1 ADD_0 TxSLE W_0 SD1 SD3 VCCT VCCT P SD_2P5 V SD0 SD2 VCCR GNDR GNDR VCCR VCCR VCCR R GNDT TPFIP (0) GNDT TPFON( 1) GNDT TPFIP (2) GNDR TPFIN (3) T TPFIN(0 ) TPFOP( 0) TPFOP( 1) TPFIN(1 ) TPFIN(2 ) TPFOP( 2) TPFON( 3) U TPFON( 0) GNDT TPFIP (1) GNDT TPFON( 2) GNDT 1 16 1 2 3 4 5 6 GNDD GNDD GNDD GNDD GNDD GNDD GNDD VCCD GNDD GNDD GNDD VCCT N/C SGND A VCCT VCCT VCCR TDI TDO TMS SD7 N VCCR VCCR VCCR GNDR GNDT SD4 SD5 SD6 P GNDR TPFON( 4) GNDR TPFIP (6) GNDR TPFOP( 7) GNDT TPFIP (7) GNDT R TPFIP (3) TPFIP (4) TPFOP( 4) TPFOP( 5) TPFIN (5) TPFIN (6) TPFOP( 6) TPFON( 7) TPFIN(7 ) GNDT T TPFOP( 3) GNDR TPFIN (4) GNDT TPFON( 5) GNDT TPFIP (5) GNDT TPFON( 6) GNDT GNDT U 7 8 9 10 11 12 13 14 15 16 17 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Figure 7. LXT9785/9785E LXT9785/9785E SS-SMII 241-Ball PBGA Assignments SSSMI I 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A GNDD VCCIO N/C N/C N/C TxSYN C0 N/C VCCIO GNDD MDIO1 TxData 4 N/C N/C N/C N/C N/C N/C B RxData 0 N/C GNDD RxData 1 TxData 2 N/C GNDD N/C RxData 3 MDC1 Rx CLK1 RxSYN C1 TxData 5 N/C RxData 5 N/C RxData 6 B C VCCIO RxData 0 TxData 1 N/C GNDD N/C RxData 2 TxCLK 0 MDINT1 N/C VCCIO RxData 4 GNDD N/C N/C TxSYN C1 GNDD C D GNDD MDIX GNDD N/C PAUSE GNDD N/C TxData 3 N/C GNDD N/C N/C TxData 6 VCCIO GNDD N/C TxCLK 1 D E MDC0 TXD0 Rx CLK0 RxSYN C0 GNDD REF CLK0 GNDD GNDD REF CLK1 GNDD TxData 7 N/C N/C GNDD E F MDINT0 LED3_1 MDIO0 N/C VCCD GNDD RxData 7 N/C LED7_3 LED7_2 F G LED2_3 N/C LED3_2 LED3_3 N/C VCCD N/C LED7_1 N/C LED6_3 G H LED1_3 LED2_1 LED2_2 N/C N/C LED6_1 LED6_2 LED5_3 H J LED0_3 N/C LED1_2 LED1_1 VCCD LED5_1 LED5_2 LED4_3 J K AMDIX_ EN LED0_2 LED0_1 N/C SGND N/C LED4_1 LED4_2 K L MDDIS CFG_3 CFG_2 ADD_4 VCC PECL VCC PECL PWR DWN SEC TION MODE SEL_0 MODE SEL_1 L M CFG_1 ADD_3 ADD_2 TxSLE W_1 GND PECL GND PECL G_FX/ TP RESET TCK TRST M N ADD_1 ADD_0 TxSLE W_0 SD1 SD3 VCCT VCCT P SD_2P 5V SD0 SD2 VCCR GNDR GNDR VCCR VCCR VCCR R GNDT TPFIP (0) GNDT TPFON (1) GNDT TPFIP (2) GNDR TPFIN (3) T TPFIN (0) TPFOP (0) TPFOP (1) TPFIN (1) TPFIN (2) TPFOP (2) TPFON (3) U TPFON (0) GNDT TPFIP (1) GNDT TPFON (2) GNDT 1 2 3 4 5 6 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 GNDD GNDD GNDD GNDD GNDD GNDD GNDD VCCD GNDD GNDD GNDD VCCT N/C A VCCT VCCT VCCR TDI TDO TMS SD7 N VCCR VCCR VCCR GNDR GNDT SD4 SD5 SD6 P GNDR TPFON (4) GNDR TPFIP (6) GNDR TPFOP (7) GNDT TPFIP (7) GNDT R TPFIP (3) TPFIP (4) TPFOP (4) TPFOP (5) TPFIN (5) TPFIN (6) TPFOP (6) TPFON (7) TPFIN (7) GNDT T TPFOP (3) GNDR TPFIN (4) GNDT TPFON (5) GNDT TPFIP (5) GNDT TPFON (6) GNDT GNDT U 7 8 9 10 11 12 13 14 15 16 17 17 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 1. RMII PQFP Pin List Pin Type1 Symbol Reference for Full Description 1 CRS_DV6 O, TS, SL Table 4 on page 39 2 RxER6 O, TS, SL, ID Table 4 on page 39 3 TxEN6 I, ID Table 4 on page 39 4 TxData6_0 I, ID Table 4 on page 39 5 TxData6_1 I, ID Table 4 on page 39 6 REFCLK1 I Table 4 on page 39 7 RxData5_1 O, TS, ID Table 4 on page 39 8 RxData5_0 O, TS Table 4 on page 39 9 GNDIO Table 14 on page 49 10 CRS_DV5 O, TS, SL Table 4 on page 39 11 RxER5 O, TS, SL, ID Table 4 on page 39 12 TxEN5 I, ID Table 4 on page 39 13 TxData5_0 I, ID Table 4 on page 39 14 TxData5_1 I, ID Table 4 on page 39 15 RxData4_1 O, TS,ID Table 4 on page 39 16 RxData4_0 O, TS Table 4 on page 39 17 CRS_DV4 O, TS, SL Table 4 on page 39 18 VCCIO Table 14 on page 49 19 GNDIO Table 14 on page 49 20 RxER4 O, TS, SL, ID Table 4 on page 39 21 TxEN4 I, ID Table 4 on page 39 22 TxData4_0 I, ID Table 4 on page 39 23 TxData4_1 I, ID Table 4 on page 39 24 MDC1 I, ST, ID Table 8 on page 43 25 MDIO1 I/O, TS, SL, IP Table 8 on page 43 26 MDINT1 OD, TS, SL, IP Table 8 on page 43 27 RxData3_1 O, TS, ID Table 4 on page 39 28 RxData3_0 O, TS Table 4 on page 39 29 VCCIO Table 14 on page 49 30 GNDIO Table 14 on page 49 31 CRS_DV3 O, TS, SL Table 4 on page 39 32 RxER3 O, TS, SL, ID Table 4 on page 39 33 TxEN3 I, ID Table 4 on page 39 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 18 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 1. RMII PQFP Pin List (Continued) Pin Type1 Symbol 34 TxData3_0 35 36 Reference for Full Description I, ID Table 4 on page 39 TxData3_1 I, ID Table 4 on page 39 RxData2_1 O, TS, ID Table 4 on page 39 37 RxData2_0 O, TS Table 4 on page 39 38 GNDIO Table 14 on page 49 39 CRS_DV2 O, TS, SL Table 4 on page 39 40 RxER2 O, TS, SL, ID Table 4 on page 39 41 TxEN2 I, ID Table 4 on page 39 42 TxData2_0 I, ID Table 4 on page 39 43 TxData2_1 I, ID Table 4 on page 39 44 REFCLK0 I Table 4 on page 39 45 RxData1_1 O, TS, ID Table 4 on page 39 46 RxData1_0 O, TS Table 4 on page 39 47 VCCIO Table 14 on page 49 48 GNDIO Table 14 on page 49 49 CRS_DV1 O, TS, SL Table 4 on page 39 50 RxER1/PAUSE O, TS, SL, ID Table 12 on page 46 51 TxEN1 I, ID Table 4 on page 39 52 TxData1_0 I, ID Table 4 on page 39 53 TxData1_1 I, ID Table 4 on page 39 54 RxData0_1 O, TS, ID Table 4 on page 39 55 RxData0_0 O, TS Table 4 on page 39 56 VCCIO Table 14 on page 49 57 GNDIO Table 14 on page 49 58 CRS_DV0 O, TS, SL Table 4 on page 39 59 RxER0/MDIX O, TS, SL, ID Table 12 on page 46 60 TxEN0 I, ID Table 4 on page 39 61 TxData0_0 I, ID Table 4 on page 39 62 TxData0_1 I, ID Table 4 on page 39 63 MDC0 I, ST, ID Table 8 on page 43 64 MDIO0 I/O, TS, SL, IP Table 8 on page 43 65 VCCD Table 14 on page 49 66 GNDD Table 14 on page 49 67 MDINT0 OD, TS, SL, IP Table 8 on page 43 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 19 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 1. RMII PQFP Pin List (Continued) Pin Type1 Symbol Reference for Full Description 68 LED3_3 OD, TS, SO, IP Table 13 on page 48 69 LED3_2 OD, TS, SL, IP Table 13 on page 48 70 LED3_1 OD, TS, SL, IP Table 13 on page 48 71 LED2_3 OD, TS, SL, IP Table 13 on page 48 72 LED2_2 OD, TS, SL, IP Table 13 on page 48 73 LED2_1 OD, TS, SL, IP Table 13 on page 48 74 GNDIO Table 14 on page 49 75 LED1_3 OD, TS, SL, IP Table 13 on page 48 76 LED1_2 OD, TS, SL, IP Table 13 on page 48 77 LED1_1 OD, TS, SL, IP Table 13 on page 48 78 VCCD Table 14 on page 49 79 GNDD Table 14 on page 49 80 LED0_3 OD, TS, SL, IP Table 13 on page 48 81 LED0_2 OD, TS, SL, IP Table 13 on page 48 82 LED0_1 OD, TS, SL, IP Table 13 on page 48 83 AMDIX_EN I, ST, IP Table 12 on page 46 84 MDDIS I, ST, ID Table 8 on page 43 85 CFG_3 I, ST, ID Table 12 on page 46 86 CFG_2 I, ST, ID Table 12 on page 46 87 CFG_1 I, ST, ID Table 12 on page 46 88 ADD_4 I, ST, ID Table 12 on page 46 89 ADD_3 I, ST, ID Table 12 on page 46 90 ADD_2 I, ST, ID Table 12 on page 46 91 ADD_1 I, ST, ID Table 12 on page 46 92 ADD_0 I, ST, ID Table 12 on page 46 93 TxSLEW_1 I, ST, ID Table 12 on page 46 94 TxSLEW_0 I, ST, ID Table 12 on page 46 95 SD_2P5V I, ST, ID Table 9 on page 44 96 SD0 I Table 9 on page 44 97 SD1 I Table 9 on page 44 98 VCCPECL Table 14 on page 49 99 GNDPECL Table 14 on page 49 100 SD2 I Table 9 on page 44 101 SD3 I Table 9 on page 44 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 20 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 1. RMII PQFP Pin List (Continued) Pin Type1 Symbol 102 N/C 103 104 Reference for Full Description Table 15 on page 50 VCCR0 Table 14 on page 49 TPFIP0 AO/AI Table 10 on page 44 105 TPFIN0 AO/AI Table 10 on page 44 106 GNDR0 Table 14 on page 49 107 TPFOP0 AO/AI Table 10 on page 44 108 TPFON0 AO/AI Table 10 on page 44 109 VCCT0/1 Table 14 on page 49 110 TPFON1 AO/AI Table 10 on page 44 111 TPFOP1 AO/AI Table 10 on page 44 112 GNDR1 Table 14 on page 49 113 GNDT0/1 Table 14 on page 49 114 TPFIN1 AO/AI Table 10 on page 44 115 TPFIP1 AO/AI Table 10 on page 44 116 VCCR1 Table 14 on page 49 117 VCCR2 Table 14 on page 49 118 TPFIP2 AO/AI Table 10 on page 44 119 TPFIN2 AO/AI Table 10 on page 44 120 GNDR2 Table 14 on page 49 121 TPFOP2 AO/AI Table 10 on page 44 122 TPFON2 AO/AI Table 10 on page 44 123 VCCT2/3 Table 14 on page 49 124 TPFON3 AO/AI Table 10 on page 44 125 TPFOP3 AO/AI Table 10 on page 44 126 GNDR3 Table 14 on page 49 127 GNDT2/3 Table 14 on page 49 128 TPFIN3 AO/AI Table 10 on page 44 129 TPFIP3 AO/AI Table 10 on page 44 130 VCCR3 Table 14 on page 49 131 VCCR4 Table 14 on page 49 132 TPFIP4 AO/AI Table 10 on page 44 133 TPFIN4 AO/AI Table 10 on page 44 134 GNDT4/5 Table 14 on page 49 135 GNDR4 Table 14 on page 49 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 21 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 1. RMII PQFP Pin List (Continued) Pin Type1 Symbol Reference for Full Description 136 TPFOP4 AO/AI Table 10 on page 44 137 TPFON4 AO/AI Table 10 on page 44 138 VCCT4/5 Table 14 on page 49 139 TPFON5 AO/AI Table 10 on page 44 140 TPFOP5 AO/AI Table 10 on page 44 141 GNDR5 Table 14 on page 49 142 TPFIN5 AO/AI Table 10 on page 44 143 TPFIP5 AO/AI Table 10 on page 44 144 VCCR5 Table 14 on page 49 145 VCCR6 Table 14 on page 49 146 TPFIP6 AO/AI Table 10 on page 44 147 TPFIN6 AO/AI Table 10 on page 44 148 GNDT6/7 Table 14 on page 49 149 GNDR6 Table 14 on page 49 150 TPFOP6 AO/AI Table 10 on page 44 151 TPFON6 AO/AI Table 10 on page 44 152 VCCT6/7 Table 14 on page 49 153 TPFON7 AO/AI Table 10 on page 44 154 TPFOP7 AO/AI Table 10 on page 44 155 GNDR7 Table 14 on page 49 156 TPFIN7 AO/AI Table 10 on page 44 157 TPFIP7 AO/AI Table 10 on page 44 158 VCCR7 Table 14 on page 49 159 N/C Table 15 on page 50 160 N/C Table 15 on page 50 161 SD4 I Table 9 on page 44 162 SD5 I Table 9 on page 44 163 GNDPECL Table 14 on page 49 164 VCCPECL Table 14 on page 49 165 SD6 I Table 9 on page 44 166 SD7 I Table 9 on page 44 167 TDI I, ST, IP Table 11 on page 45 168 TDO O, TS Table 11 on page 45 169 TMS I, ST, IP Table 11 on page 45 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 22 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 1. RMII PQFP Pin List (Continued) Pin Type1 Symbol Reference for Full Description 170 TCK I, ST, ID Table 11 on page 45 171 TRST I, ST, IP Table 11 on page 45 172 N/C Table 15 on page 50 173 G_FX/TP I, ST, ID Table 12 on page 46 174 PWRDWN I, ST, ID Table 12 on page 46 175 RESET I, ST, IP Table 12 on page 46 176 Section I, ST, ID Table 12 on page 46 177 ModeSel0 I, ST, ID Table 12 on page 46 178 ModeSel1 I, ST, ID Table 12 on page 46 179 SGND Table 14 on page 49 180 LED4_1 OD, TS, SL, IP Table 13 on page 48 181 LED4_2 OD, TS, SL, IP Table 13 on page 48 182 LED4_3 OD, TS, SL, IP Table 13 on page 48 183 GNDD Table 14 on page 49 184 VCCD Table 14 on page 49 185 LED5_1 OD, TS, SL, IP Table 13 on page 48 186 LED5_2 OD, TS, SL, IP Table 13 on page 48 187 LED5_3 OD, TS, SL, IP Table 13 on page 48 188 GNDIO Table 14 on page 49 189 LED6_1 OD, TS, SL, IP Table 13 on page 48 190 LED6_2 OD, TS, SL, IP Table 13 on page 48 191 LED6_3 OD, TS, SL, IP Table 13 on page 48 192 LED7_1 OD, TS, SL, IP Table 13 on page 48 193 LED7_2 OD, TS, SL, IP Table 13 on page 48 194 LED7_3 OD, TS, SL, IP Table 13 on page 48 195 GNDD Table 14 on page 49 196 VCCD Table 14 on page 49 197 RxData7_1 O, TS, ID Table 4 on page 39 198 RxData7_0 O, TS Table 4 on page 39 199 GNDIO Table 14 on page 49 200 CRS_DV7 O, TS, SL Table 4 on page 39 201 RxER7 O, TS, SL, ID Table 4 on page 39 202 TxEN7 I, ID Table 4 on page 39 203 TxData7_0 I, ID Table 4 on page 39 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 23 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 1. RMII PQFP Pin List (Continued) Pin Type1 Symbol Reference for Full Description 204 TxData7_1 I, ID Table 4 on page 39 205 RxData6_1 O, TS, ID Table 4 on page 39 206 RxData6_0 O, TS Table 4 on page 39 207 GNDIO Table 14 on page 49 208 VCCIO Table 14 on page 49 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 24 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 2. SMII PQFP Pin List Pin Symbol Type 1 Reference for Full Description 1 N/C Table 15 on page 50 2 N/C Table 15 on page 50 3 N/C Table 15 on page 50 4 TxData6 I, ID Table 15 on page 50 5 N/C I, ID Table 15 on page 50 6 REFCLK1 I Table 5 on page 41 7 N/C Table 15 on page 50 8 RxData5 O, TS Table 6 on page 41 9 GNDIO Table 14 on page 49 10 N/C Table 15 on page 50 11 N/C Table 15 on page 50 12 N/C Table 15 on page 50 13 TxData5 I, ID Table 5 on page 41 14 N/C Table 15 on page 50 15 N/C O, TS,ID Table 15 on page 50 16 RxData4 O, TS Table 6 on page 41 17 N/C Table 15 on page 50 18 VCCIO Table 14 on page 49 19 GNDIO Table 14 on page 49 20 N/C O, TS, SL, ID Table 15 on page 50 21 N/C I, ID Table 15 on page 50 22 TxData4 I, ID Table 5 on page 41 23 N/C Table 15 on page 50 24 MDC1 I, ST, ID Table 8 on page 43 25 MDIO1 I/O, TS, SL, IP Table 8 on page 43 OD, TS, SL, IP Table 8 on page 43 Table 15 on page 50 O, TS Table 6 on page 41 26 MDINT1 27 N/C 28 RxData3 29 VCCIO Table 14 on page 49 30 GNDIO Table 14 on page 49 31 N/C Table 15 on page 50 32 N/C Table 15 on page 50 33 N/C Table 15 on page 50 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 25 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 2. SMII PQFP Pin List (Continued) Pin Symbol Type1 Reference for Full Description 34 TxData3 I, ID Table 5 on page 41 35 SYNC0 I, ID Table 6 on page 41 36 N/C Table 15 on page 50 37 RxData2 O, TS Table 6 on page 41 38 GNDIO Table 14 on page 49 39 N/C Table 15 on page 50 40 N/C Table 15 on page 50 41 N/C Table 15 on page 50 42 TxData2 I, ID Table 5 on page 41 43 N/C Table 15 on page 50 44 REFCLK0 I Table 5 on page 41 45 N/C Table 15 on page 50 46 RxData1 O, TS Table 6 on page 41 47 VCCIO Table 14 on page 49 48 GNDIO Table 14 on page 49 49 N/C Table 15 on page 50 50 PAUSE I, ID Table 12 on page 46 51 N/C 52 TxData1 Table 15 on page 50 I, ID Table 5 on page 41 53 N/C Table 15 on page 50 54 N/C Table 15 on page 50 55 RxData0 O, TS Table 6 on page 41 56 VCCIO Table 14 on page 49 57 GNDIO Table 14 on page 49 58 N/C Table 15 on page 50 59 MDIX I, ID Table 12 on page 46 60 N/C Table 15 on page 50 61 TxData0 I, ID Table 5 on page 41 62 N/C Table 15 on page 50 63 MDC0 I, ST, ID Table 8 on page 43 64 MDIO0 I/O, TS, SL, IP Table 8 on page 43 65 VCCD Table 14 on page 49 66 GNDD Table 14 on page 49 67 MDINT0 OD, TS, SL, IP Table 8 on page 43 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 26 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 2. SMII PQFP Pin List (Continued) Pin Symbol Type 1 Reference for Full Description 68 LED3_3 OD, TS, SO, IP Table 13 on page 48 69 LED3_2 OD, TS, SL, IP Table 13 on page 48 70 LED3_1 OD, TS, SL, IP Table 13 on page 48 71 LED2_3 OD, TS, SL, IP Table 13 on page 48 72 LED2_2 OD, TS, SL, IP Table 13 on page 48 73 LED2_1 OD, TS, SL, IP Table 13 on page 48 74 GNDIO Table 14 on page 49 75 LED1_3 OD, TS, SL, IP Table 13 on page 48 76 LED1_2 OD, TS, SL, IP Table 13 on page 48 77 LED1_1 OD, TS, SL, IP Table 13 on page 48 78 VCCD Table 14 on page 49 79 GNDD Table 14 on page 49 80 LED0_3 OD, TS, SL, IP Table 13 on page 48 81 LED0_2 OD, TS, SL, IP Table 13 on page 48 82 LED0_1 OD, TS, SL, IP Table 13 on page 48 83 AMDIX_EN I, ST, IP Table 12 on page 46 84 MDDIS I, ST, ID Table 8 on page 43 85 CFG_3 I, ST, ID Table 12 on page 46 86 CFG_2 I, ST, ID Table 12 on page 46 87 CFG_1 I, ST, ID Table 12 on page 46 88 ADD_4 I, ST, ID Table 12 on page 46 89 ADD_3 I, ST, ID Table 12 on page 46 90 ADD_2 I, ST, ID Table 12 on page 46 91 ADD_1 I, ST, ID Table 12 on page 46 92 ADD_0 I, ST, ID Table 12 on page 46 93 TxSLEW_1 I, ST, ID Table 12 on page 46 94 TxSLEW_0 I, ST, ID Table 12 on page 46 95 SD_2P5V I, ST, ID Table 9 on page 44 96 SD0 I Table 9 on page 44 97 SD1 I Table 9 on page 44 98 VCCPECL Table 14 on page 49 99 GNDPECL Table 14 on page 49 100 SD2 I Table 9 on page 44 101 SD3 I Table 9 on page 44 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 27 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 2. SMII PQFP Pin List (Continued) Pin 102 Symbol N/C Type1 Reference for Full Description Table 15 on page 50 103 VCCR0 Table 14 on page 49 104 TPFIP0 AI/AO Table 10 on page 44 105 TPFIN0 AI/AO Table 10 on page 44 106 GNDR0 Table 14 on page 49 107 TPFOP0 AO/AI Table 10 on page 44 108 TPFON0 AO/AI Table 10 on page 44 109 VCCT0/1 Table 14 on page 49 110 TPFON1 AO/AI Table 10 on page 44 111 TPFOP1 AO/AI Table 10 on page 44 112 GNDR1 Table 14 on page 49 113 GNDT0/1 Table 14 on page 49 114 TPFIN1 AI/AO Table 10 on page 44 115 TPFIP1 AI/AO Table 10 on page 44 116 VCCR1 Table 14 on page 49 117 VCCR2 Table 14 on page 49 118 TPFIP2 AI/AO Table 10 on page 44 119 TPFIN2 AI/AO Table 10 on page 44 120 GNDR2 Table 14 on page 49 121 TPFOP2 AO/AI Table 10 on page 44 122 TPFON2 AO/AI Table 10 on page 44 123 VCCT2/3 Table 14 on page 49 124 TPFON3 AO/AI Table 10 on page 44 125 TPFOP3 AO/AI Table 10 on page 44 126 GNDR3 Table 14 on page 49 127 GNDT2/3 Table 14 on page 49 128 TPFIN3 AI/AO Table 10 on page 44 129 TPFIP3 AI/AO Table 10 on page 44 130 VCCR3 Table 14 on page 49 131 VCCR4 Table 14 on page 49 132 TPFIP4 AI/AO Table 10 on page 44 133 TPFIN4 AI/AO Table 10 on page 44 134 GNDT4/5 Table 14 on page 49 135 GNDR4 Table 14 on page 49 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 28 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 2. SMII PQFP Pin List (Continued) Type 1 Reference for Full Description TPFOP4 AO/AI Table 10 on page 44 137 TPFON4 AO/AI Table 10 on page 44 138 VCCT4/5 Table 14 on page 49 139 TPFON5 AO/AI Table 10 on page 44 140 TPFOP5 AO/AI Table 10 on page 44 Pin 136 Symbol 141 GNDR5 Table 14 on page 49 142 TPFIN5 AI/AO Table 10 on page 44 143 TPFIP5 AI/AO Table 10 on page 44 144 VCCR5 Table 14 on page 49 145 VCCR6 Table 14 on page 49 146 TPFIP6 AI/AO Table 10 on page 44 147 TPFIN6 AI/AO Table 10 on page 44 148 GNDT6/7 Table 14 on page 49 149 GNDR6 Table 14 on page 49 150 TPFOP6 AO/AI Table 10 on page 44 151 TPFON6 AO/AI Table 10 on page 44 152 VCCT6/7 Table 14 on page 49 153 TPFON7 AO/AI Table 10 on page 44 154 TPFOP7 AO/AI Table 10 on page 44 155 GNDR7 Table 14 on page 49 156 TPFIN7 AI/AO Table 10 on page 44 157 TPFIP7 AI/AO Table 10 on page 44 158 VCCR7 Table 14 on page 49 159 N/C Table 15 on page 50 160 N/C Table 15 on page 50 161 SD4 I Table 9 on page 44 162 SD5 I Table 9 on page 44 163 GNDPECL Table 14 on page 49 164 VCCPECL Table 14 on page 49 165 SD6 I Table 9 on page 44 166 SD7 I Table 9 on page 44 167 TDI I, ST, IP Table 11 on page 45 168 TDO O, TS Table 11 on page 45 169 TMS I, ST, IP Table 11 on page 45 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 29 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 2. SMII PQFP Pin List (Continued) Pin Symbol Type1 Reference for Full Description 170 TCK I, ST, ID Table 11 on page 45 171 TRST I, ST, IP Table 11 on page 45 172 N/C Table 15 on page 50 173 G_FX/TP I, ST, ID Table 12 on page 46 174 PWRDWN I, ST, ID Table 12 on page 46 175 RESET I, ST, IP Table 12 on page 46 176 Section I, ST, ID Table 12 on page 46 177 ModeSel0 I, ST, ID Table 12 on page 46 178 ModeSel1 I, ST, ID Table 12 on page 46 179 SGND Table 14 on page 49 180 LED4_1 OD, TS, SL, IP Table 13 on page 48 181 LED4_2 OD, TS, SL, IP Table 13 on page 48 182 LED4_3 OD, TS, SL, IP Table 13 on page 48 183 GNDD Table 14 on page 49 184 VCCD Table 14 on page 49 185 LED5_1 OD, TS, SL, IP Table 13 on page 48 186 LED5_2 OD, TS, SL, IP Table 13 on page 48 187 LED5_3 OD, TS, SL, IP Table 13 on page 48 188 GNDIO Table 14 on page 49 189 LED6_1 OD, TS, SL, IP Table 13 on page 48 190 LED6_2 OD, TS, SL, IP Table 13 on page 48 191 LED6_3 OD, TS, SL, IP Table 13 on page 48 192 LED7_1 OD, TS, SL, IP Table 13 on page 48 193 LED7_2 OD, TS, SL, IP Table 13 on page 48 194 LED7_3 OD, TS, SL, IP Table 13 on page 48 195 GNDD Table 14 on page 49 196 VCCD Table 14 on page 49 197 N/C O, TS, ID Table 4 on page 39 198 RxData7 O, TS Table 6 on page 41 199 GNDIO Table 14 on page 49 200 N/C Table 15 on page 50 201 N/C Table 15 on page 50 202 N/C Table 15 on page 50 203 TxData7 I, ID Table 5 on page 41 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 30 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 2. SMII PQFP Pin List (Continued) Pin Symbol Type 1 Reference for Full Description 204 SYNC1 I, ID Table 6 on page 41 205 N/C 206 RxData6 Table 15 on page 50 O, TS Table 6 on page 41 207 GNDIO Table 14 on page 49 208 VCCIO Table 14 on page 49 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 31 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 3. SS-SMII PQFP Pin List Pin Symbol Type1 Reference for Full Description 1 N/C Table 15 on page 50 2 N/C Table 15 on page 50 3 N/C Table 15 on page 50 4 TxData6 I, ID Table 5 on page 41 5 N/C I, ID Table 15 on page 50 6 REFCLK1 7 RxData5 8 9 I Table 5 on page 41 O, TS, ID Table 7 on page 42 N/C Table 15 on page 50 GNDIO Table 14 on page 49 10 N/C Table 15 on page 50 11 N/C Table 15 on page 50 12 N/C Table 15 on page 50 13 TxData5 I, ID Table 5 on page 41 14 N/C 15 RxData4 Table 15 on page 50 O, TS, ID Table 7 on page 42 16 N/C Table 15 on page 50 17 RxSYNC1 O, TS, ID Table 7 on page 42 18 19 VCCIO Table 14 on page 49 GNDIO Table 14 on page 49 20 N/C Table 15 on page 50 21 RxCLK1 O, TS, ID Table 7 on page 42 22 TxData4 I, ID Table 5 on page 41 23 N/C Table 15 on page 50 24 MDC1 I, ST, ID Table 8 on page 43 25 MDIO1 I/O, TS, SL, IP Table 8 on page 43 26 MDINT1 OD, TS, SL, IP Table 8 on page 43 27 RxData3 O, TS, ID Table 7 on page 42 28 N/C Table 15 on page 50 29 VCCIO Table 14 on page 49 30 GNDIO Table 14 on page 49 31 N/C Table 15 on page 50 32 TxCLK0 I, ID Table 7 on page 42 33 N/C Table 15 on page 50 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 32 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol 34 TxData3 35 36 37 Type1 Reference for Full Description I, ID Table 5 on page 41 TxSYNC0 I, ID Table 7 on page 42 RxData2 O, TS, ID Table 7 on page 42 N/C Table 15 on page 50 38 GNDIO Table 14 on page 49 39 N/C Table 15 on page 50 40 N/C Table 15 on page 50 41 N/C Table 15 on page 50 42 TxData2 I, ID Table 5 on page 41 43 N/C Table 15 on page 50 44 REFCLK0 I Table 5 on page 41 45 RxData1 O, TS, ID Table 7 on page 42 46 N/C Table 15 on page 50 47 VCCIO Table 14 on page 49 48 GNDIO Table 14 on page 49 49 N/C Table 15 on page 50 50 PAUSE I, ID Table 12 on page 46 51 N/C 52 TxData1 53 N/C 54 RxData0 55 56 Table 15 on page 50 I, ID Table 5 on page 41 Table 15 on page 50 O, TS, ID Table 7 on page 42 N/C Table 15 on page 50 VCCIO Table 14 on page 49 57 GNDIO Table 14 on page 49 58 RxSYNC0 O, TS, ID Table 7 on page 42 59 MDIX I, ID Table 12 on page 46 60 RxCLK0 Table 7 on page 42 61 TxData0 I, ID Table 5 on page 41 62 N/C Table 15 on page 50 63 MDC0 I, ST, ID Table 8 on page 43 64 MDIO0 I/O, TS, SL, IP Table 8 on page 43 65 VCCD Table 14 on page 49 66 GNDD Table 14 on page 49 67 MDINT0 OD, TS, SL, IP Table 8 on page 43 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 33 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol Type1 Reference for Full Description 68 LED3_3 OD, TS, SO, IP Table 13 on page 48 69 LED3_2 OD, TS, SL, IP Table 13 on page 48 70 LED3_1 OD, TS, SL, IP Table 13 on page 48 71 LED2_3 OD, TS, SL, IP Table 13 on page 48 72 LED2_2 OD, TS, SL, IP Table 13 on page 48 73 LED2_1 OD, TS, SL, IP Table 13 on page 48 74 GNDIO Table 14 on page 49 75 LED1_3 OD, TS, SL, IP Table 13 on page 48 76 LED1_2 OD, TS, SL, IP Table 13 on page 48 77 LED1_1 OD, TS, SL, IP Table 13 on page 48 78 VCCD Table 14 on page 49 79 GNDD Table 14 on page 49 80 LED0_3 OD, TS, SL, IP Table 13 on page 48 81 LED0_2 OD, TS, SL, IP Table 13 on page 48 82 LED0_1 OD, TS, SL, IP Table 13 on page 48 83 AMDIX_EN I, ST, IP Table 12 on page 46 84 MDDIS I, ST, ID Table 8 on page 43 85 CFG_3 I, ST, ID Table 12 on page 46 86 CFG_2 I, ST, ID Table 12 on page 46 87 CFG_1 I, ST, ID Table 12 on page 46 88 ADD_4 I, ST, ID Table 12 on page 46 89 ADD_3 I, ST, ID Table 12 on page 46 90 ADD_2 I, ST, ID Table 12 on page 46 91 ADD_1 I, ST, ID Table 12 on page 46 92 ADD_0 I, ST, ID Table 12 on page 46 93 TxSLEW_1 I, ST, ID Table 12 on page 46 94 TxSLEW_0 I, ST, ID Table 12 on page 46 95 SD_2P5V I, ST, ID Table 9 on page 44 96 SD0 I Table 9 on page 44 97 SD1 I Table 9 on page 44 98 VCCPECL Table 14 on page 49 99 GNDPECL Table 14 on page 49 100 SD2 I Table 9 on page 44 101 SD3 I Table 9 on page 44 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 34 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 3. SS-SMII PQFP Pin List (Continued) Pin 102 Symbol N/C Type1 Reference for Full Description Table 15 on page 50 103 VCCR0 Table 14 on page 49 104 TPFIP0 AI/AO Table 10 on page 44 105 TPFIN0 AI/AO Table 10 on page 44 106 GNDR0 Table 14 on page 49 107 TPFOP0 AO/AI Table 10 on page 44 108 TPFON0 AO/AI Table 10 on page 44 109 VCCT0/1 Table 14 on page 49 110 TPFON1 AO/AI Table 10 on page 44 111 TPFOP1 AO/AI Table 10 on page 44 112 GNDR1 Table 14 on page 49 113 GNDT0/1 Table 14 on page 49 114 TPFIN1 AI/AO Table 10 on page 44 115 TPFIP1 AI/AO Table 10 on page 44 116 VCCR1 Table 14 on page 49 117 VCCR2 Table 14 on page 49 118 TPFIP2 AI/AO Table 10 on page 44 119 TPFIN2 AI/AO Table 10 on page 44 120 GNDR2 Table 14 on page 49 121 TPFOP2 AO/AI Table 10 on page 44 122 TPFON2 AO/AI Table 10 on page 44 123 VCCT2/3 Table 14 on page 49 124 TPFON3 AO/AI Table 10 on page 44 125 TPFOP3 AO/AI Table 10 on page 44 126 GNDR3 Table 14 on page 49 127 GNDT2/3 Table 14 on page 49 128 TPFIN3 AI/AO Table 10 on page 44 129 TPFIP3 AI/AO Table 10 on page 44 130 VCCR3 Table 14 on page 49 131 VCCR4 Table 14 on page 49 132 TPFIP4 AI/AO Table 10 on page 44 133 TPFIN4 AI/AO Table 10 on page 44 134 GNDT4/5 Table 14 on page 49 135 GNDR4 Table 14 on page 49 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 35 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol Type1 Reference for Full Description 136 TPFOP4 AO/AI Table 10 on page 44 137 TPFON4 AO/AI Table 10 on page 44 138 VCCT4/5 Table 14 on page 49 139 TPFON5 AO/AI Table 10 on page 44 140 TPFOP5 AO/AI Table 10 on page 44 141 GNDR5 Table 14 on page 49 142 TPFIN5 AI/AO Table 10 on page 44 143 TPFIP5 AI/AO Table 10 on page 44 144 VCCR5 Table 14 on page 49 145 VCCR6 Table 14 on page 49 146 TPFIP6 AI/AO Table 10 on page 44 147 TPFIN6 AI/AO Table 10 on page 44 148 GNDT6/7 Table 14 on page 49 149 GNDR6 Table 14 on page 49 150 TPFOP6 AO/AI Table 10 on page 44 151 TPFON6 AO/AI Table 10 on page 44 152 VCCT6/7 Table 14 on page 49 153 TPFON7 AO/AI Table 10 on page 44 154 TPFOP7 AO/AI Table 10 on page 44 155 GNDR7 Table 14 on page 49 156 TPFIN7 AI/AO Table 10 on page 44 157 TPFIP7 AI/AO Table 10 on page 44 158 VCCR7 Table 14 on page 49 159 N/C Table 15 on page 50 160 N/C Table 15 on page 50 161 SD4 I Table 9 on page 44 162 SD5 I Table 9 on page 44 163 GNDPECL Table 14 on page 49 164 VCCPECL Table 14 on page 49 165 SD6 I Table 9 on page 44 166 SD7 I Table 9 on page 44 167 TDI I, ST, IP Table 11 on page 45 168 TDO O, TS Table 11 on page 45 169 TMS I, ST, IP Table 11 on page 45 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 36 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E Table 3. SS-SMII PQFP Pin List (Continued) Pin Symbol Type1 Reference for Full Description 170 TCK I, ST, ID Table 11 on page 45 171 TRST I, ST, IP Table 11 on page 45 172 N/C Table 15 on page 50 173 G_FX/TP I, ST, ID Table 12 on page 46 174 PWRDWN I, ST, ID Table 12 on page 46 175 RESET I, ST, IP Table 12 on page 46 176 Section I, ST, ID Table 12 on page 46 177 ModeSel0 I, ST, ID Table 12 on page 46 178 ModeSel1 I, ST, ID Table 12 on page 46 179 SGND Table 14 on page 49 180 LED4_1 OD, TS, SL, IP Table 13 on page 48 181 LED4_2 OD, TS, SL, IP Table 13 on page 48 182 LED4_3 OD, TS, SL, IP Table 13 on page 48 183 GNDD Table 14 on page 49 184 VCCD Table 14 on page 49 185 LED5_1 OD, TS, SL, IP Table 13 on page 48 186 LED5_2 OD, TS, SL, IP Table 13 on page 48 187 LED5_3 OD, TS, SL, IP Table 13 on page 48 188 GNDIO Table 14 on page 49 189 LED6_1 OD, TS, SL, IP Table 13 on page 48 190 LED6_2 OD, TS, SL, IP Table 13 on page 48 191 LED6_3 OD, TS, SL, IP Table 13 on page 48 192 LED7_1 OD, TS, SL, IP Table 13 on page 48 193 LED7_2 OD, TS, SL, IP Table 13 on page 48 194 LED7_3 OD, TS, SL, IP Table 13 on page 48 195 GNDD Table 14 on page 49 196 VCCD Table 14 on page 49 197 RxData7 O, TS, ID Table 7 on page 42 198 N/C Table 15 on page 50 199 GNDIO Table 14 on page 49 200 N/C Table 15 on page 50 201 TxCLK1 I, ID Table 7 on page 42 202 N/C Table 15 on page 50 203 TxData7 I, ID Table 5 on page 41 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 37 LXT9785/9785E LXT9785/9785E - Advanced 10/100 8-Port PHY Table 3. SS-SMII PQFP Pin List (Continued) Type1 Reference for Full Description Pin Symbol 204 TxSYNC1 I, ID Table 7 on page 42 205 RxData6 O, TS, ID Table 7 on page 42 206 N/C Table 15 on page 50 207 GNDIO Table 14 on page 49 208 VCCIO Table 14 on page 49 1. AI=Analog Input, AO=Analog Output, I=Input, O=Output, OD=Open Drain output, ST=Schmitt Triggered input, TS=TriState-able output, SL=Slew-rate Limited output, IP=Weak Internal Pull-up, ID=Weak Internal Pull-down 38 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Advanced 10/100 8-Port PHY - LXT9785/9785E LXT9785/9785E 1.1 Signal Name Conventions Signal names may contain either a port designation or a serial designation, or a combination of the two designations. Signal naming conventions are as follows: · Port Number Only. Individual signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2. · Serial Number Only. A set of signals which are not tied to any specific port are designated by the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3. · Port and