LXT974A/LXT975A LXT974A LXT975A LXT970 100BASE-TX 100TX 100BASE-FX 100FX - Datasheet Archive

 

Layout Guide Application Note January 2001 Order Number: 249012-001 As of January 15, 2001, this document replaces the Level One

 

LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide Application Note January 2001 Order Number: 249012-001 As of January 15, 2001, this document replaces the Level One document known as AN84. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide Contents 1.0 General Description . 5 2.0 Features . 6 3.0 Design Guidelines . 7 3.1 3.2 3.3 4.0 Power and Ground . 9 4.1 4.2 4.3 5.0 General Guidelines. 7 Differential Signal Layout Guidelines . 7 Clock Circuit . 7 Power and Ground Planes .9 Design Considerations .10 Design Implementation.11 Twisted-Pair Interface .13 5.1 5.2 5.3 5.4 Receive Interface Circuit .13 5.1.1 Common-Mode Choke .13 5.1.2 Termination Circuitry .13 Transmit Interface Circuit .14 5.2.1 Common-Mode Choke .15 Return Loss .16 5.3.1 Meeting IEEE Requirements .17 5.3.1.1 Guidelines for Reducing System Shunt Capacitance.17 5.3.1.2 Guidelines for Magnetics Selection .18 Bob Smith Termination.18 6.0 Fiber Interface.19 7.0 Magnetic and Crystal Reference .20 7.1 Crystal Information .21 1 2 3 4 5 6 7 8 9 10 11 12 LXT974A LXT974A and LXT975A LXT975A Quad PHY Transceivers. 6 Signal Layer Filling . 8 Power and Ground Placement .10 Internal Routing of Analog and Digital Power Signals .11 Power Supply Current .12 Power and Ground Decoupling .12 Receive Interface Circuitry .14 Effects of a 2:1 Turns Ratio .15 Transmit Interface Circuitry .15 IEEE Return Loss Requirements .16 Bob Smith Termination Circuit .18 Fiber Interface Circuitry .19 Figures Application Note 3 LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide Tables 1 2 3 4 5 6 7 4 Criteria for Analog Noise Levels. 10 Parasitic Capacitance Limits . 17 Magnetics Requirements . 20 LXT974A LXT974A Magnetics Manufacturers. 20 LXT975A LXT975A Magnetics Manufacturers. 21 Crystal Requirements. 21 Crystal Manufacturer. 21 Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide 1.0 General Description This application note provides detailed design and layout guidelines for the LXT974A LXT974A and LXT975A LXT975A Quad PHY Transceivers. Adherence to these guidelines will help designers layout a system that meets all IEEE specifications, including EMI and return loss. The LXT974A LXT974A and LXT975A LXT975A are four-port 10/100 Ethernet transceivers based on the LXT970 LXT970. Each port can directly drive a 100BASE-TX 100BASE-TX line (>130 meters). Their robust receiver design provides independent equalization, gain control and baseline wander correction. Each port on the LXT974A LXT974A offers support for 100BASE-TX 100BASE-TX (100TX 100TX), 100BASE-FX 100BASE-FX (100FX 100FX), and 10BASE-T 10BASE-T (10BT) applications. The LXT975A LXT975A is similar to the LXT974A LXT974A and is optimized for dual-high stacked RJ45 module applications. Each port on the LXT975A LXT975A supports 100TX 100TX and 10BT applications. Two ports offer a 100FX 100FX pseudo-ECL fiber interface. Refer to the LXT974A/975A LXT974A/975A data sheet for more complete details on all the device functions and capabilities. Internal power and ground structures have been re-designed to provide the best performance. Fiber and copper interface pins have been multiplexed so that the device could be offered in a 160-pin package. Power consumption has been reduced by cutting the transmit power by four. In addition, a number of significant enhancements have been made to the LXT974A/975A LXT974A/975A: · Transmit jitter reduced to 2.4V). · Jitter less than 0.5 ns. Figure 2. Signal Layer Filling Layer Name Plane Fill Signal 1 Layer 2 Signal 3 VCC Layer Layer 4 Layer 5 Signal 4 8 Layer 1 GND Layer Signal 2 Layer 6 Layer 3 VCC VCC GND GND Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide 4.0 Power and Ground 4.1 Power and Ground Planes For high-speed communications design, the power and ground planes may be conceptually divided into four regions (the analog and digital power planes and the chassis and signal ground planes) as shown in Figure 3. The analog power region extends from the magnetics back to the LXT974A/975A LXT974A/975A. The power plane in this area should be filtered. Only components and signals pertaining to the interface should be placed or routed through this region. The digital power region extends from the MII interfaces of the LXT974A/975A LXT974A/975A through the rest of the board. Good design practices listed in the previous section should be followed throughout this area. The digital section supplies power to the digital VCC pin, MII VCC pin, and to the external components. The analog section supplies power to VCCH, VCCT, and VCCR pins of the LXT974A/975A LXT974A/975A. Refer to Figure 4 for internal routing of power signals. The chassis ground region extends from the front edge of the board (RJ45 connectors) to the magnetics, and around the entire perimeter of the board. No signals should pass through this region except for external interfaces and LED signals. This region can be used for a separate chassis ground plane, which can be connected to the chassis, cable shields, unused signals and safety earth ground. The signal ground region is one continuous, unbroken plane that extends from the magnetics through the rest of the board. The signal ground plane may be combined with chassis ground or isolated from it. For isolation place a "moat" around the signal ground plane to separate signal ground from chassis ground. If the ground planes are combined, an isolation area is not required. Keep all high-speed digital signals out of the ground planes. When laying out ground planes, special care must be taken to avoid creating loop antenna effect. · Run all ground planes as solid square or rectangular regions. · Avoid creating loops with ground planes around other planes. The only exception to this rule is chassis ground as shown in Figure 3. · Ensure the chassis ground area (running the perimeter of the board) is voided at some point. · Ensure the gap of the voided area in chassis ground is large enough to prevent a ground loop. Application Note 9 LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide Figure 3. Power and Ground Placement Keep all highspeed digital logic signals out of the analog LEDs power plane and ground planes Keep all highspeed digital logic signals inside the digital power plane Chassis Ground Ground Plane Digital VCC Plane Ferrites Analog VCC Magnetics Plane MAC SCC LXT974A LXT974A RJ45s RAM Ferrites Filter the analog and digital power planes with ferrite beads 4.2 Tie to Safety/ Earth Ground Void area to prevent loop antenna effect Optional isolation Area Design Considerations Power supply ripple and digital switching noise can be created by: · Poorly-regulated or over-burdened power supplies. · Wide data busses (>32-bits) running at a high clock rate. · DC-to-DC converters. Noise created by these sources can be coupled through the power and ground planes into the transmitter and receiver and out onto the network. Coupling can occur via the termination circuits or through the analog power and ground pins of the LXT974A/975A LXT974A/975A. Use the criteria found in Table 1 for evaluating acceptable noise levels in the analog region of the power and ground planes . Table 1. Criteria for Analog Noise Levels Noise Level Under 50 mV 50 mV to 80 mV Above 80 mV 10 Acceptability Acceptable Marginally Acceptable Unacceptable Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide 4.3 Design Implementation Following good general design and layout guidelines will prevent most common signal and noise issues. The following recommendations apply to the design and layout of the power and ground planes: · Divide the VCC plane into two sections as shown in Figure 3 (analog and digital). The break between the two planes should run under the device. · When dividing VCC plane, it is not necessary to add extra layers to the board. Simply create moats or cut-out regions in existing layers. · Place a high-frequency bypass cap (.01µf) near each analog VCC pin as shown in Figure 6. · Join the digital and analog sections at one or more points by ferrite beads. Ensure the maximum current rating of the bead is at least 150% of the nominal current that is expected to flow through it. Each LXT974A/975A LXT974A/975A and its transformer draws a maximum of 500 mA from the analog supply so beads rated at 750 mA should used. See Figure Figure 5 for current load listings. Figure 4. Internal Routing of Analog and Digital Power Signals Analog Circuitry Digital Circuitry VCCMII (3.3V or 5V) VCCT VCCR VCCH VCC (5V) Bias 10M Rx & Tx PLLs 100M Tx PLL Rcvrs 100M Rx PLL Txmtrs GNDH GNDR GNDT MII Interface Digital Logic Clock GND Substrate GNDA · Place a bulk capacitor (10 µF) on each side of each ferrite bead to stop switching noise from traveling through the ferrite. · For designs with multiple LXT974A/975As, it is acceptable to supply all from one analog VCC plane. This plane can be joined to the digital VCC plane at multiple points, with a ferrite bead at each one. It is also acceptable to create an individual analog VCC mini-plane for each device. · For additional performance, add a second ferrite bead between the analog plane and the transmit centertap as shown in Figure 5. A single bead can be used to supply centertap current for all four ports. Application Note 11 LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide Figure 5. Power Supply Current VCC 570 mA Total 70 mA VCC (Digital) 500 mA Ferrite bead rated at 750 mA (500 mA X 1.5) VCCR - 136 mA VCCH - 23 mA Direct supply to the LXT974A/975A LXT974A/975A VCCT - 68 mA Ferrite bead rated at 400 mA VCCT - 272 mA To TPO magnetic center taps (all four ports) Figure 6. Power and Ground Decoupling LXT974A/975A LXT974A/975A VCCH .01µF GNDH VCCT .01µF GNDT 22k 1% RBIAS GNDA VCCR .01µF GNDR 10µF Analog Supply Plane + Ferrite Beads Digital Supply Plane 10µF VCC +5V .01µF GND .01µF VCCMII 12 3.3V or +5V Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide 5.0 Twisted-Pair Interface The twisted-pair interface consists of magnetics, connectors, and termination networks for the receiver and transmitter. The LXT974A/975A LXT974A/975A requires magnetics with a 1:1 turns ratio for the receive ratio and a 2:1 ratio for the transmit transformers. A circuit known as a "Bob Smith" termination ( Figure 11 on page 18) is used to ground unused signal pairs. 5.1 Receive Interface Circuit The receive interface circuit consists of magnetics, which include a main winding and a commonmode choke, and termination resistance to match the line impedance. 5.1.1 Common-Mode Choke Receive magnetics generally include a common-mode choke. Some vendors place this filter on the line (primary) side of the main winding; others place it on the device (secondary) side. Either approach is acceptable. If using a magnetic with the common-mode choke on the device side, do not attach a bypass cap from the device-side center-tap to ground. Noise from the ground can couple through the cap into the center-tap, bypassing the common-mode choke, and cause EMI problems. 5.1.2 Termination Circuitry Figure 7 shows two options for receive termination. In both options a 100 load is placed across the TPIP/TPIN input pair. The first option, Figure 7A, consists of a single 100 resistor across the input. The second option, Figure 7B, is to divide the resistor in two with a common-mode bypass cap (.01 µF) to ground. Testing done to date has shown neither option is consistently better. Results are strongly dependent on the specific application. Some guidelines to consider are: · The advantage of the two-resistor approach is that the bypass cap can provide additional common-mode shielding if the ground is quiet. · The disadvantage of the two-resistor approach is that any imbalance or mismatch between the two resistors can create common-mode noise. Application Note 13 LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide Figure 7. Receive Interface Circuitry Magnetics RJ45 Alternate Magnetics TPIN Main Winding A LXT974A LXT974A CM Choke CM Choke Main Winding 100 1% To Chip TPIP Secondary 1:1 Primary To Line Secondary 1:1 Primary Chassis GND TPIN 50 1% B LXT974A LXT974A 50 1% TPIP 5.2 C1 GNDR Option B may result in an imbalance between the two halves of the divided impedance which can create commonmode noise and degrade performance. Transmit Interface Circuit Figure 9 shows the recommended termination circuitry to be used with the magnetics on the transmit interface. This circuit includes: · Compensating inductor (200 - 400 nH). · Two 200 1% resistors between TPOP and TPON. · Magnetics centertap (device-side) tied to VCCT via a ferrite bead and bypassed to GNDT using .01 µF capacitor. · One ferrite bead rated at 400 mA to supply centertap current to all four ports. Refer to note 2 in Figure 9. The value of the inductor shown in Figure 9 (320 nH) is optimized for the LXT974A/975A LXT974A/975A demonstration board. This value can be optimized for each specific application and should be in the range of 200 - 400 nH. The output stages for the receiver and transmitter shown in Figure 7 and Figure 9 are designed to match the 100 characteristic impedance of twisted-pair wire. On the transmit side, the 2:1 turns ratio causes the 400 termination to appear as a 100 termination to the line (Figure 8) 14 Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide . Figure 8. Effects of a 2:1 Turns Ratio 2:1 Chip side Z1 From the Chip side, the 2:1 transformer causes the line impedance (Z2) to appear 4x larger than it actually is. 5.2.1 Line side Z2 From the Line side, the 2:1 transformer causes the termination impedance (Z1) to appear 4x smaller than it actually is. Common-Mode Choke The transmit magnetics always include a common-mode choke. Some vendors place this choke on the line-side (secondary) of the main winding while others place it on the device-side (primary). A few vendors include two transmit chokes one on each side of the main winding. The line-side centertap can be bypassed to chassis ground, but this should be carefully evaluated in the system application. Bypassing both center-taps of the transmit winding may produce undesirable results by creating a low-impedance AC coupling between the chassis ground and circuit ground. Consider potential noise sources and ground plane characteristics when evaluating bypass options. For additional information refer to "Guidelines for Magnetics Selection" on page 18. . Figure 9. Transmit Interface Circuitry 0.1µF 1 GNDR TPIP 1:1 1 2 50 1% 3 75 TPIN 50 50 4 TPOP LXT974A/975A LXT974A/975A TPON 5 6 50 320 nH 200 1% 50 2:1 200 1% To Twisted-Pair Network RJ45 50 1% 7 75 2 50 50 8 0.001µF/2kV VCCT 0.1µF .01µF GNDT 1. Receiver common mode bypass cap may improve BER performance in systems with noisy power supplies. 2. A single ferrite bead (rated at 400 mA) may be used to supply center tap current to all 4 ports. Application Note 15 LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide 5.3 Return Loss Return loss measures the amount of energy that is lost because it is reflected rather than absorbed. These reflections occur because of impedance mis-matches between the line and the receiver. Mathematically, return loss is defined as: Zo ­ Zl 20 log 10 - Zo + Zl where, ZO is the line impedance (100), and Zl is the load impedance of the receiver. Reflected energy is a loss to the system; it reduces overall efficiency and creates nuisance noise. In any communication system it is particularly important to minimize return loss at the receiver because it improves system efficiency and cuts reflections at their source. As a secondary concern, return loss should also be minimized at the transmitter to prevent the signal from being reflected again, back toward the receiver. The transmit and receive requirements for 100BASE-TX 100BASE-TX applications are defined by the ANSI X3.263 TP-PMD specification. The specified return loss requirements for both the transmitter and receiver are shown in Figure 10. Return Loss (dB) Figure 10. IEEE Return Loss Requirements -10 Unacceptable -16 Acceptable Range 30 60 80 Frequency (MHz) The impedance characteristics of the transmitter and receiver are degraded by parasitic capacitance at high frequencies. Capacitive reactance (Xc) of parasitic capacitance is frequency-dependent and is given by the following equation: 6 10 Xc = -2 × f × Cs where: f = Frequency in MHz. CS = parasitic shunt capacitance in pF. This capacitive reactance (XC) appears in parallel with the impedance (Zl) presented by the load itself, thus changing the effective load impedance (ZL). The effect of parasitic capacitance on effective load impedance (ZL) is given by the following equation: 16 Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide ZlXc Z L = -2 2 Zl + Xc The return loss template is shown in Figure 10. The section that is most difficult to meet is at 80 MHz where maximum return loss is -10 dB. To meet this, the total capacitance due to parasitics can be no more than 32 pF. In addition to the parasitics of the circuit, magnetics already have their own built-in parasitics. Normally these are not specified by the manufacturer. However, they can be calculated from the return loss performance data that is usually available. The parasitics in the magnetics limit the tolerable parasitics in the circuit to a number smaller than 32 pF. The output magnetics 2:1 turns ratio further reduces the allowable shunt capacitance by a factor of four. Table 2 lists the maximum parasitic capacitance allowed by various magnetic performance levels . Table 2. Parasitic Capacitance Limits Magnetic PerformanceReturn Loss at 80 MHz Allowable Circuit Parasitics Receiver (1:1 Ratio) Transmitter (2:1 Ratio) -12 dB 6.0 1.5 -14 dB 10 2.5 -16 dB 3.5 16.5 4.1 -20 dB 5.3.1 14 -18 dB 18.5 4.5 Meeting IEEE Requirements Designers should focus on two key areas to obtain maximum return loss performance with the LXT974A/975A LXT974A/975A. First, to minimize shunt capacitance on the board and second, careful selection of the magnetics. Adherence to the following guidelines will help to ensure each design will meet IEEE requirements for the 100TX 100TX PMD layer as called out in the ANSI X3.263 specification. 5.3.1.1 Guidelines for Reducing System Shunt Capacitance · Keep transmit traces as short as possible. · Keep the magnetics as close as possible to the LXT974A/975A LXT974A/975A, and keep TPOP and TPON traces as short as possible. · Use quad magnetics to allow the most compact layout. · Use the termination circuit shown in Figure 9. The compensating inductor will tune out 1.5 2.0 pF of parasitic capacitance. · Provide EMI shielding by placing a ground plane under TPOP and TPON and the magnetics. To achieve an optimum layout for EMI and return loss performance, place the shielding ground plane 2 to 3 layers away to minimize shunt capacitance between the traces and the ground plane. Application Note 17 LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide 5.3.1.2 Guidelines for Magnetics Selection Most magnetics are adequate for designing a reliable network connection in a typical application. Intel continues to work with magnetic vendors to improve magnetics return loss characteristics. These improved magnetics simplify design requirements by increasing parasitic tolerances allowed in a system. Refer to the Magnetic Manufacturers Cross-Reference Guide, on the Intel web site (www.intel.com) for the most current magnetic information. The LXT974A/975A LXT974A/975A allows the user to adjust the rise time of the output pulse to match the appropriate magnetic performance. A slowed rise time (default, bit 16.8 = 0) provides the best match for most magnetics. Set bit 16.8 = 1 to adjust the output pulse for magnetics requiring a faster rise time. 5.4 Bob Smith Termination A "Bob Smith" termination is often provided for the unused signal pairs of a twisted-pair interface (RJ45 pins 4, 5, 7, and 8). Although there are many variations on this technique, the most common implementation is shown in Figure 11. Note that the signals are referenced to chassis ground rather than circuit ground Figure 11. Bob Smith Termination Circuit 50 50 RJ45 8 7 RX To / From Chip 6 50 50 5 50 4 3 TX 2 1 * * * *= To / From Twisted-Pair Line 50 0.001µF 2kV NOTE: RJ45 connections shown for standard NIC. Tx/Rx crossover may be required for repeater & switch applications. 18 Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide 6.0 Fiber Interface The Fiber Interface consists of two pseudo-ECL signal pairs, which attach to an external fiber optic transceiver. The output pair (FIBOP/N) should be AC-coupled to the transceiver to adjust for bias differences. The LXT974A/975A LXT974A/975A biases its outputs to 1.5V. Most transceivers require the inputs to be biased between 3V and 4V, ideally at 3.7V. The input pair (FIBIP/N) should be DC-coupled to the transceiver, and biased to 3.0V Figure 12 shows both circuits. The combinations of bias resistors shown provide the ideal biasing points, for an equivalent load impedance of 50. . Figure 12. Fiber Interface Circuitry VCCT +5 V 69 0.1 µF 69 GNDA 0.01µF TD FIBOPn 0.01µF LXT974A/975A LXT974A/975A TD +5 V 191 Fiber Txcvr 191 80 SD/TPn SD VCCR +5 V 130 GNDA 80 1 0.1 mF 80 To Fiber Network FIBONn GNDA FIBINn RD FIBIPn RD 130 130 1. Refer to fiber transceiver manufacturers recommendations for termination circuitry. Suitable fiber transceivers include the HFBR-5103 HFBR-5103 and HFBR-5105 HFBR-5105. Application Note 19 LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide 7.0 Magnetic and Crystal Reference The LXT974A/975A LXT974A/975A requires a 1:1 ratio for the receive transformer and a 2:1 ratio for the transmit transformer. Refer to Table 3 for magnetics requirements. Table 4 and Table 5 list magnetic manufacturers and part numbers. This listing constitutes a reference only, and is not a recommendation. It is the responsibility of the system designer to ensure that all components, both individually and collectively, are suitable for the intended application. Table 3. Magnetics Requirements Parameter Min Nom Max Units Rx turns ratio ­ 1:1 ­ ­ Tx turns ratio ­ 2:1 ­ ­ Insertion loss 0.0 ­ 1.1 dB Primary inductance Test Condition 350 ­ ­ µH Transformer isolation ­ 2 ­ kV Differential to common mode rejection 40 ­ ­ dB .1 to 60 MHz 35 ­ ­ dB 60 to 100 MHz ­ ­ -16 dB 30 MHz ­ ­ -10 dB 80 MHz ­ ­ -20 dB 30 MHz ­ ­ -15 dB 80 MHz Return Loss - standard Return Loss - improved1 1. Magnetics with improved return loss performance simplify the design requirements for meeting ANSI X3.263 return loss specifications. Table 4. LXT974A LXT974A Magnetics Manufacturers Dual Port Single-High Manufacturer2 Belfuse Delta 5558-5999-F5 5558-5999-F5 LF8254 LF8254 Quad Port Single-High Quad Port Dual-High3 S558-5999-E4 S558-5999-E4 S558-5999-D9 S558-5999-D9 S558-5999-F4 S558-5999-F4 S558-5999-J0 S558-5999-J0 LF8251A LF8251A ­ LF8251D1 LF8251D1 HALO TG110-S220NX TG110-S220NX TG110-S222NX TG110-S222NX TG110-S420NX TG110-S420NX TG110-S460NX TG110-S460NX TG110-S465NX TG110-S465NX ­ Nanopulse 6872-30 6888-30 6889-30 6922-30 6932-30 1. Magnetics with improved return loss performance. 2. Device manufacturers may have additional magnetics with varying pinouts. 3. The LXT975A LXT975A is preferred for dual-high applications. Each design must be evaluated for cross-talk and return loss performance. 20 Application Note LXT974A/LXT975A LXT974A/LXT975A Design and Layout Guide Table 4. LXT974A LXT974A Magnetics Manufacturers (Continued) Dual Port Single-High Manufacturer2 Quad Port Single-High Quad Port Dual-High3 Pulse ­ H1069 H1069 H1074 H1074 H1068 H1068 VALOR ST6174T ST6174T ST6180T1 ST6180T1 ST6402T1 ST6402T1 ST6186T1 ST6186T1 YCL PH406002 PH406002 ­ ­ 1. Magnetics with improved return loss performance. 2. Device manufacturers may have additional magnetics with varying pinouts. 3. The LXT975A LXT975A is preferred for dual-high applications. Each design must be evaluated for cross-talk and return loss performance. Table 5. LXT975A LXT975A Magnetics Manufacturers Quad Port Dual-High Manufacturer2 Belfuse S558-5999-F6 S558-5999-F6 LF8713 LF8713 Delta LF8701 LF8701 HALO TG110-S422NX TG110-S422NX TG110-S462NX TG110-S462NX Pulse H1076 H1076 VALOR ST6417T1 ST6417T1 1. Magnetics with improved return loss performance. 2. Device manufacturers may have additional magnetics with varying pinouts. 7.1 Crystal Information The LXT974A/975A LXT974A/975A requires a parallel-resonant fundamental-mode crystal that meets the specifications as shown in Table 6. Table 7 lists a crystal manufacturer. Designers should test and validate all crystals before committing to a specific component. Table 6. Crystal Requirements Parameter Min Nom Max Units Frequency ­ 25.0 ­ MHz ­ Frequency Stability ­ ­ ±100 ppm -40 - 85oC Table 7. Test Condition Crystal Manufacturer Manufacturer Epson America Application Note Part Number MA-505-25 MA-505-25.000M 21