LXT974A/LXT975A LXT974A LXT975A 10BASE-T 100BASE-TX LXT974 LXT975 100BASE-FX - Datasheet Archive

 

JUNE 1998 Revision 1.2 LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceivers General Description Features The LXT974A and

 

DATA SHEET JUNE 1998 Revision 1.2 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceivers General Description Features The LXT974A LXT974A and LXT975A LXT975A are four-port PHY Fast Ethernet Transceivers which support IEEE 802.3 physical layer applications at both 10 Mbps and 100 Mbps. They provide all of the active circuitry to interface four 802.3 Media Independent Interface (MII) compliant controllers to 10BASE-T 10BASE-T and/or 100BASE-TX 100BASE-TX media. This data sheet applies to all LXT974 LXT974_ and LXT975 LXT975_ products including LXT974 LXT974, LXT975 LXT975 and any subsequent variants, except as specifically noted. · Four independent IEEE 802.3-compliant 10BASE-T 10BASE-T or 100BASE-TX 100BASE-TX ports in a single chip. · 100BASE-FX 100BASE-FX fiber-optic capable. · Standard CSMA/CD or full-duplex operation. · Supports auto-negotiation and legacy systems without auto-negotiation capability. · Baseline wander correction. · 100BASE-TX 100BASE-TX line performance over 130 meters. · Configurable LED drivers and serial LED output. · Configurable through MII serial port or via external control pins. · Available in 160-pin PQFP with heat spreader. · Commercial temperature range (0-70oC ambient). · Part numbers: LXT974AHC LXT974AHC (new designation) LXT974QC LXT974QC (original designation) LXT975AHC LXT975AHC (new designation) LXT975QC LXT975QC (original designation) All four ports on the LXT974A LXT974A provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for a 10/100BASE-TX 10/100BASE-TX or 100BASE-FX 100BASE-FX connection. The LXT975A LXT975A is pin compatible with the LXT974A LXT974A except for the network ports. The LXT975A LXT975A is optimized for dualhigh stacked RJ45 modular applications and provides a twisted-pair interface on every port, but the PECL interface on only two. The LXT974A/975A LXT974A/975A provides three separate LED drivers for each of the four PHY ports and a serial LED interface. In addition to standard Ethernet, each chip supports fullduplex operation at 10 Mbps and 100 Mbps. The LXT974A/975A LXT974A/975A requires only a single 5V power supply. The MII may be operated independently with either a 3.3V or 5V supply. Applications · 10BASE-T 10BASE-T, 10/100-TX 10/100-TX, or 100BASE-FX 100BASE-FX Switches and multi-port NICs. · LXT975A LXT975A optimized for dual-high stacked modular RJ45 applications. LXT974A/975A LXT974A/975A Block Diagram VCCMII MII_MD CFG Management / Mode Select Logic ADDR MDIO MDC MDINT MII Power Supply 3.3V or 5V CLK25M CLK25M Global Functions Internal Clocks 3 Register Set Manchester 10 Encoder T X _ E Nn MII T X _ E Rn Parallel/Serial Converter T X Dn < 3 : 0 > Scrambler 100 & Encoder Pulse Shaper Tristate Control Clock Generator R X _ C L Kn RXDn C R Sn C O Ln R X _ D Vn R X _ E Rn Carrier Sense Collision Detect Data Valid Error Detect + TP Out T P O P / F I B I Nn + / Serial to Parallel Converter 10 Manchester Decoder - Decoder & 100 Descrambler TP Rcvr Baseline Wander Correction Per-Port Functions 3 L E Dn < 2 : 0 > S D / T Xn Media Select & Line Energy Monitor Slicer T P O N / F I B I Pn Fiber In FDX Status & LED Drivers T X _ C L Kn MII TP Driver ECL Driver Auto Negotiation T R S T En Pwr Supply / PwrDown VCC GND PWRDN RESET SerLED LEDENA LEDCLK LEDDAT + Fiber Out T P I P / F I B O Pn - / T P I N / F I B O Nn TP In ECL Rcvr + - PORT 0 PORT 1 PORT 2 PORT 3 Refer to www.level1.com for current product information. LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver TABLE OF CONTENTS PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS . 4 FUNCTIONAL DESCRIPTION . 14 Introduction . 14 Network Media/Protocol Support . 15 10/100 Mbps Network Interface. 15 Twisted-Pair Interface. 15 Fiber Interface . 15 MII Interface. 16 MII Data Interface . 16 Loopback . 17 MII Management Interface. 18 MII Interrupts . 18 Hardware Control Interface. 19 Initialization . 21 MDIO Control Mode. 21 Manual Control Mode . 21 Link Configuration. 21 Auto-Negotiation . 22 100 Mbps Operation . 23 4B/5B Coding Table . 24 100BASE-X 100BASE-X Protocol Sublayer Operations. 25 10 Mbps Operation . 28 LED Functions . 29 Serial LED Output. 29 Per-Port LEDs. 29 Operating Requirements. 30 Power Requirements . 30 Clock Requirements . 30 APPLICATION INFORMATION . 31 Design Recommendations. 31 Power Supply Filtering. 31 Power and Ground Plane Layout Considerations. 32 Twisted-Pair and Fiber Interfaces . 33 Magnetics Information . 34 Magnetics With Improved Return Loss Performance . 34 Typical Application Circuitry . 36 2 LXT974A/LXT975A LXT974A/LXT975A Table of Contents TEST SPECIFICATIONS . 42 Absolute Maximum Ratings . 42 Operating Conditions . 42 Digital I/O Characteristics. 43 Digital I/O Characteristics - MII Pins . 43 Required CLK25M CLK25M Characteristics . 43 Low-Voltage Fault Detect Characteristics . 44 100BASE-TX 100BASE-TX Transceiver Characteristics . 44 100BASE-FX 100BASE-FX Transceiver Characteristics . 45 10BASE-T 10BASE-T Transceiver Characteristics. 45 MII-100BASE-TX MII-100BASE-TX Receive Timing . 46 MII-100BASE-TX MII-100BASE-TX Transmit Timing . 47 MII-100BASE-FX MII-100BASE-FX Receive Timing . 48 MII-100BASE-FX MII-100BASE-FX Transmit Timing . 49 MII-10BASE-T MII-10BASE-T Receive Timing . 50 MII-10BASE-T MII-10BASE-T Transmit Timing. 51 10BASE-T 10BASE-T SQE (Heartbeat) Timing. 52 10BASE-T 10BASE-T Jab and Unjab Timing . 52 Auto Negotiation and Fast Link Pulse Timing . 53 MDIO and MII Timing . 54 Reset and Power-Down Recovery Timing . 55 Serial LED Timing . 55 REGISTER DEFINITIONS . 56 Control Register (Address 0). 57 Status Register (Address 1) . 58 PHY Identification Register 1 (Address 2). 59 PHY Identification Register 2 (Address 3). 59 Auto Negotiation Advertisement Register (Address 4). 60 Auto Negotiation Link Partner Ability Register (Address 5). 61 Auto Negotiation Expansion (Address 6) . 62 LED Configuration Register (Address 16, hex 10) . 63 Interrupt Enable Register (Address 17, hex 11) . 64 Interrupt Status Register (Address 18, hex 12) . 64 Port Configuration Register (Address 19, hex 13) . 65 Port Status Register (Address 20, hex 14). 66 PACKAGE SPECIFICATION. 67 REVISION HISTORY . 68 3 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS 160 . GND 159 . TEST 158 . SD0/TP0 157 . TPON/FIBIP0 156 . VCCT 155 . GNDT 154 . TPOP/FIBIN0 153 . VCCR 152 . TPIN/FIBON0 151 . TPIP/FIBOP0 150 . GNDR 149 . SD1/TP1 148 . TPON/FIBIP1 147 . VCCT 146 . GNDT 145 . TPOP/FIBIN1 144 . VCCR 143 . TPIN/FIBON1 142 . TPIP/FIBOP1 141 . GNDR 140 . RBIAS 139 . SD2/TP2 138 . TPON/FIBIP2 137 . VCCT 136 . GNDT 135 . TPOP/FIBIN2 134 . VCCR 133 . TPIN/FIBON2 132 . TPIP/FIBOP2 131 . GNDR 130 . SD3/TP3 129 . TPON/FIBIP3 128 . VCCT 127 . GNDT 126 . TPOP/FIBIN3 125 . VCCR 124 . TPIN/FIBON3 123 . TPIP/FIBOP3 122 . GNDR 121 . GNDR Figure 1: LXT974 LXT974 Pin Assignments (Date Code) (Part#) XXXX XXXX LXT974AHC LXT974AHC or LXT974QC LXT974QC (Lot#) XXXXXX 120 . N/C 119 . N/C 118 . CLK25M CLK25M 117 . FDE_FX 116 . CFG_0 115 . CFG_1 114 . CFG_2 113 . BYPSCR 112 . TEST 111 . AUTOENA 110 . FDE 109 . RESET 108 . GNDH 107 . VCCH 106 . TRSTE0 105 . TRSTE1 104 . TRSTE2 103 . TRSTE3 102 . PWRDN 101 . TEST 100 . MDDIS 99 . MDC 98 . MDINT 97 . MDIO 96 . VCC 95 . GND 94 . CRS3 93 . COL3 92 . TXD3_3 91 . TXD3_2 90 . TXD3_1 89 . TXD3_0 88 . TX_EN3 87 . TX_CLK3 86 . TX_ER3 85 . RX_ER3 84 . RX_CLK3 83 . RX_DV3 82 . RXD3_0 81 . RXD3_1 N/C.41 RXD1_3.42 RXD1_2.43 RXD1_1.44 RXD1_0.45 RX_DV1 .46 RX_CLK1.47 RX_ER1 .48 TX_ER1 .49 TX_CLK1.50 TX_EN1 .51 TXD1_0.52 TXD1_1.53 TXD1_2.54 TXD1_3.55 GND.56 COL1.57 CRS1 .58 GND.59 VCC.60 RXD2_3.61 RXD2_2.62 RXD2_1.63 RXD2_0.64 RX_DV2 .65 RX_CLK2.66 RX_ER2 .67 TX_ER2 .68 TX_CLK2.69 TX_EN2 .70 TXD2_0.71 TXD2_1.72 TXD2_2.73 TXD2_3.74 COL2.75 CRS2 .76 GND.77 VCCMII .78 RXD3_3.79 RXD3_2.80 LED3_0 . 1 LED3_1 . 2 LED3_2 . 3 LED2_0 . 4 LED2_1 . 5 LED2_2 . 6 GND . 7 LED1_0 . 8 LED1_1 . 9 LED1_2 . 10 LED0_0 . 11 LED0_1 . 12 LED0_2 . 13 GND . 14 LEDCLK . 15 LEDDAT . 16 LEDENA . 17 ADD2 . 18 ADD3 . 19 ADD4 . 20 GNDA . 21 VCC . 22 RXD0_3 . 23 RXD0_2 . 24 RXD0_1 . 25 RXD0_0 . 26 RX_DV0 . 27 RX_CLK0 . 28 RX_ER0 . 29 TX_ER0 . 30 TX_CLK0 . 31 TX_EN0 . 32 TXD0_0 . 33 TXD0_1 . 34 TXD0_2 . 35 TXD0_3 . 36 COL0 . 37 CRS0 . 38 GND . 39 VCCMII . 40 4 LXT974A/LXT975A LXT974A/LXT975A Pin Assignments and Signal Descriptions Table 1: LXT974A LXT974A Signal Detect/TP Select Signal Descriptions Pin#2 Symbol Type1 Signal Description 158 149 139 130 SD0/TP0 SD1/TP1 SD2/TP2 SD3/TP3 I Signal Detect - Ports 0 - 3. When SD/TPn pins are tied High or to a 5V PECL input, bit 19.2 = 1 and the operating mode of each respective port is forced to FX mode. In this mode, full-duplex is set via pin 117 (FDE_FX). When not using FX mode, SD/ TPn pins should be tied to GNDT. TP Select - Ports 0 - 3. When SD/TPn pins are tied Low, bit 19.2 = 0. The operating mode of each port can be set to 10BASE-T 10BASE-T, 100BASE-TX 100BASE-TX, or 100BASE-FX 100BASE-FX via the hardware control interface pins as shown in Table 8 on page 11. Note: Hardware control interface pins (CFG_0, CFG_1, CFG_2, FDE, BYPSCR, and AUTOENA) are global and set all ports simultaneously. In TP mode, network pins operate as described in Table 2. In FX mode, network pins are re-mapped and operate as described in Table 3. 1. Type Column Coding: I = Input, O = Output. 2. When not using fiber mode, SD/TPn pins should be tied to GNDT. Table 2: LXT974A LXT974A Twisted-Pair Interface Signal Descriptions Pin# Symbol Type1 154, 157 145, 148 135, 138 126, 129 TPOP0, TPON0 TPOP1, TPON1 TPOP2, TPON2 TPOP3, TPON3 O 151, 152 142, 143 132, 133 123, 124 TPIP0, TPIN0 TPIP1, TPIN1 TPIP2, TPIN2 TPIP3, TPIN3 I Signal Description Twisted-Pair Outputs, Positive & Negative - Ports 0-3. During 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T operation, TPO pins drive 802.3 compliant pulses onto the line. Twisted-Pair Inputs, Positive & Negative - Ports 0-3. During 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T operation, TPI pins receive differential 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T signals from the line. 1. Type Column Coding: I = Input, O = Output. Table 3: LXT974A LXT974A Fiber Interface Signal Descriptions Pin# Symbol Type1 154, 157 145, 148 135, 138 126, 129 FIBIN0, FIBIP0 FIBIN1, FIBIP1 FIBIN2, FIBIP2 FIBIN3, FIBIP3 I 151, 152 142, 143 132, 133 123, 124 FIBOP0, FIBON0 FIBOP1, FIBON1 FIBOP2, FIBON2 FIBOP3, FIBON3 O Signal Description Fiber Inputs, Positive & Negative - Ports 0-3. During 100BASE-FX 100BASE-FX operation, FIBI pins receive differential PECL inputs from fiber transceivers. Fiber Outputs, Positive & Negative - Ports 0-3. During 100BASE-FX 100BASE-FX operation, FIBO pins produce differential PECL outputs for fiber transceivers. 1. Type Column Coding: I = Input, O = Output. 5 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver 160 . GND 159 . TEST 158 . TPIP0 157 . TPIN0 156 . GNDR 155 . TPOP0 154 . VCCT 153 . GNDT 152 . TPON0 151 . VCCR 150 . GNDR 149 . SD1/TP1 148 . TPON/FIBIP1 147 . VCCT 146 . GNDT 145 . TPOP/FIBIN1 144 . VCCR 143 . TPIN/FIBON1 142 . TPIP/FIBOP1 141 . GNDR 140 . RBIAS 139 . TPIP2 138 . TPIN2 137 . GNDR 136 . TPOP2 135 . VCCT 134 . GNDT 133 . TPON2 132 . VCCR 131 . GNDR 130 . SD3/TP3 129 . TPON/FIBIP3 128 . VCCT 127 . GNDT 126 . TPOP/FIBIN3 125 . VCCR 124 . TPIN/FIBON3 123 . TPIP/FIBOP3 122 . GNDR 121 . GNDR Figure 2: LXT975A LXT975A Pin Assignments (Date Code) (Part#) XXXX XXXX LXT975AHC LXT975AHC or LXT975QC LXT975QC (Lot#) XXXXXX 120 . N/C 119 . N/C 118 . CLK25M CLK25M 117 . FDE_FX 116 . CFG_0 115 . CFG_1 114 . CFG_2 113 . BYPSCR 112 . TEST 111 . AUTOENA 110 . FDE 109 . RESET 108 . GNDH 107 . VCCH 106 . TRSTE0 105 . TRSTE1 104 . TRSTE2 103 . TRSTE3 102 . PWRDN 101 . TEST 100 . MDDIS 99 . MDC 98 . MDINT 97 . MDIO 96 . VCC 95 . GND 94 . CRS3 93 . COL3 92 . TXD3_3 91 . TXD3_2 90 . TXD3_1 89 . TXD3_0 88 . TX_EN3 87 . TX_CLK3 86 . TX_ER3 85 . RX_ER3 84 . RX_CLK3 83 . RX_DV3 82 . RXD3_0 81 . RXD3_1 N/C.41 RXD1_3.42 RXD1_2.43 RXD1_1.44 RXD1_0.45 RX_DV1 .46 RX_CLK1.47 RX_ER1 .48 TX_ER1 .49 TX_CLK1.50 TX_EN1 .51 TXD1_0.52 TXD1_1.53 TXD1_2.54 TXD1_3.55 GND.56 COL1.57 CRS1 .58 GND.59 VCC.60 RXD2_3.61 RXD2_2.62 RXD2_1.63 RXD2_0.64 RX_DV2 .65 RX_CLK2.66 RX_ER2 .67 TX_ER2 .68 TX_CLK2.69 TX_EN2 .70 TXD2_0.71 TXD2_1.72 TXD2_2.73 TXD2_3.74 COL2.75 CRS2 .76 GND.77 VCCMII .78 RXD3_3.79 RXD3_2.80 LED3_0 . 1 LED3_1 . 2 LED3_2 . 3 LED2_0 . 4 LED2_1 . 5 LED2_2 . 6 GND . 7 LED1_0 . 8 LED1_1 . 9 LED1_2 . 10 LED0_0 . 11 LED0_1 . 12 LED0_2 . 13 GND . 14 LEDCLK . 15 LEDDAT . 16 LEDENA . 17 ADD2 . 18 ADD3 . 19 ADD4 . 20 GNDA . 21 VCC . 22 RXD0_3 . 23 RXD0_2 . 24 RXD0_1 . 25 RXD0_0 . 26 RX_DV0 . 27 RX_CLK0 . 28 RX_ER0 . 29 TX_ER0 . 30 TX_CLK0 . 31 TX_EN0 . 32 TXD0_0 . 33 TXD0_1 . 34 TXD0_2 . 35 TXD0_3 . 36 COL0 . 37 CRS0 . 38 GND . 39 VCCMII . 40 6 LXT974A/LXT975A LXT974A/LXT975A Pin Assignments and Signal Descriptions Table 4: LXT975A LXT975A Signal Detect/TP Select Signal Descriptions Pin#2 Symbol Type1 Signal Description 149 130 SD1/TP1 SD3/TP3 I Signal Detect - Ports 1 & 3. When SD/TPn pins are tied High or to a 5V PECL input, bit 19.2 = 1 and the operating mode of each respective port is forced to FX mode. In this mode, full-duplex is set via pin 117 (FDE_FX). When not using fiber mode, SD/TPn pins should be tied to GNDT. TP Select - Ports 1 & 3. When SD/TPn pins are tied Low, bit 19.2 = 0. The operating mode of each port can be set to 10BASE-T 10BASE-T, 100BASE-TX 100BASE-TX, or 100BASEFX 100BASEFX via the hardware control interface pins as shown in Table 8 on page 11. Note: Hardware control interface pins (CFG_0, CFG_1, CFG_2, FDE, BYPSCR, and AUTOENA) are global and set all ports simultaneously. In TP mode, network pins operate as described in Table 5. In FX mode, network pins are re-mapped and operate as described in Table 6. 1. Type Column Coding: I = Input, O = Output. 2. When not using fiber mode, SD/TPn pins should be tied to GNDT. Table 5: LXT975A LXT975A Twisted-Pair Interface Signal Descriptions Pin# Symbol Type1 155, 152 145, 148 136, 133 126, 129 TPOP0, TPON0 TPOP1, TPON1 TPOP2, TPON2 TPOP3, TPON3 O 158, 157 142, 143 139, 138 123, 124 TPIP0, TPIN0 TPIP1, TPIN1 TPIP2, TPIN2 TPIP3, TPIN3 I Signal Description Twisted-Pair Outputs, Positive & Negative - Ports 0-3. During 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T operation, TPO pins drive 802.3 compliant pulses onto the line. Twisted-Pair Inputs, Positive & Negative - Ports 0-3. During 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T operation, TPI pins receive differential 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T signals from the line. 1. Type Column Coding: I = Input, O = Output. Table 6: LXT975A LXT975A Fiber Interface Signal Descriptions Pin# Symbol Type1 145, 148 126, 129 FIBIN1, FIBIP1 FIBIN3, FIBIP3 I 142, 143 123, 124 FIBOP1, FIBON1 FIBOP3, FIBON3 O Signal Description Fiber Network Interface - Ports 1 and 3 During 100BASE-FX 100BASE-FX operation, FIBI pins receive differential PECL inputs from fiber transceivers. Fiber Network Interface - Ports 1 and 3 During 100BASE-FX 100BASE-FX operation, FIBO pins produce differential PECL outputs for fiber transceivers. 1. Type Column Coding: I = Input, O = Output. 7 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Table 7: LXT974A LXT974A and LXT975A LXT975A MII Signal Descriptions Pin#3 Symbol Type1 Signal Description2 MII Data Interface Pins 33 34 35 36 TXD0_0 TXD0_1 TXD0_2 TXD0_3 I Transmit Data - Port 0. Inputs containing NRZ data to be transmitted from port 0. 52 53 54 55 TXD1_0 TXD1_1 TXD1_2 TXD1_3 I Transmit Data - Port 1. Inputs containing NRZ data to be transmitted from port 1. 71 72 73 74 TXD2_0 TXD2_1 TXD2_2 TXD2_3 I Transmit Data - Port 2. Inputs containing NRZ data to be transmitted from port 2. 89 90 91 92 TXD3_0 TXD3_1 TXD3_2 TXD3_3 I Transmit Data - Port 3. Inputs containing NRZ data to be transmitted from port 3. 32 51 70 88 TX_EN0 TX_EN1 TX_EN2 TX_EN3 I Transmit Enable - Ports 0 - 3. Active High input enables respective port transmitter. This signal must be synchronous to the TX_CLK. 31 50 69 87 TX_CLK0 TX_CLK1 TX_CLK2 TX_CLK3 O Transmit Clock - Ports 0 - 3. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps operation. The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The LXT974A/975A LXT974A/975A normally samples these signals on the rising edge of TX_CLK. However, Advanced TX_CLK Mode is available by setting MII register bit 19.5=1. In this mode, the LXT974A/975A LXT974A/975A samples the transmit data and control signals on the falling edge of TX_CLK. 30 49 68 86 TX_ER0 TX_ER1 TX_ER2 TX_ER3 I Transmit Coding Error - Ports 0 - 3. This signal must be driven synchronously to TX_CLK. When High, forces the respective port to transmit Halt (H) code group. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT974A/975A LXT974A/975A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). 3. Unused pins should be tied Low. 8 LXT974A/LXT975A LXT974A/LXT975A Pin Assignments and Signal Descriptions Table 7: LXT974A LXT974A and LXT975A LXT975A MII Signal Descriptions ­ continued Pin#3 Symbol Type1 Signal Description2 26 25 24 23 RXD0_0 RXD0_1 RXD0_2 RXD0_3 O Receive Data - Port 0. Receive data signals (4-bit parallel nibbles) are driven synchronously to RX_CLK0. 45 44 43 42 RXD1_0 RXD1_1 RXD1_2 RXD1_3 O Receive Data - Port 1. Receive data signals (4-bit parallel nibbles) are driven synchronously to RX_CLK1. 64 63 62 61 RXD2_0 RXD2_1 RXD2_2 RXD2_3 O Receive Data - Port 2. Receive data signals (4-bit parallel nibbles) are driven synchronously to RX_CLK2. 82 81 80 79 RXD3_0 RXD3_1 RXD3_2 RXD3_3 O Receive Data - Port 3. Receive data signals (4-bit parallel nibbles) are driven synchronously to RX_CLK3. 27 46 65 83 RX_DV0 RX_DV1 RX_DV2 RX_DV3 O Receive Data Valid - Ports 0 - 3. These signals are synchronous to the respective RX_CLKn. Active High indication that received code group maps to valid data. 29 48 67 85 RX_ER0 RX_ER1 RX_ER2 RX_ER3 O Receive Error - Ports 0 - 3. These signals are synchronous to the respective RX_CLKn. Active High indicates that received code group is invalid, or that PLL is not locked. 28 47 66 84 RX_CLK0 RX_CLK1 RX_CLK2 RX_CLK3 O Receive Clock - Ports 0 - 3. 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps. 37 57 75 93 COL0 COL1 COL2 COL3 O Collision Detected - Ports 0 - 3. Active High outputs asserted upon detection of a collision. Remain High for the duration of the collision. These signals are generated asynchronously. Inactive during full-duplex operation. 38 58 76 94 CRS0 CRS1 CRS2 CRS3 O Carrier Sense - Ports 0 - 3. Active High signals. During half-duplex operation (bit 0.8 = 0), CRSn is asserted when either transmit or receive medium is non-idle. During full-duplex operation (bit 0.8 = 1), CRSn is asserted only when the receive medium is non-idle. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT974A/975A LXT974A/975A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). 3. Unused pins should be tied Low. 9 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Table 7: LXT974A LXT974A and LXT975A LXT975A MII Signal Descriptions ­ continued Pin#3 Symbol Type1 Signal Description2 MII Control Interface Pins 97 MDIO I/O Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. 98 MDINT OD Management Data Interrupt. An active Low output on this pin indicates status change. Interrupt is cleared by sequentially reading Register 1, then Register 18. 99 MDC I Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 2.5 MHz. 100 MDDIS I Management Disable. When MDDIS is High, the MDIO is restricted to Read Only and the Hardware Control Interface pins provide continual control of their respective bits. When MDDIS is Low at power up or Reset, the Hardware Control Interface pins control only the initial or "default" values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. 106 105 104 103 TRSTE0 TRSTE1 TRSTE2 TRSTE3 I Tristate - Ports 0 - 3. This bit controls bit 0.10 (Isolate bit). When TRSTEn is High, the respective port isolates itself from the MII Data Interface. When MDDIS is High, TRSTE provides continuous control over bit 0.10. When MDDIS is Low, TRSTE sets the initial (default) value of bit 0.10 at Reset and then bit control reverts back to the MDIO interface. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT974A/975A LXT974A/975A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). 3. Unused pins should be tied Low. 10 LXT974A/LXT975A LXT974A/LXT975A Pin Assignments and Signal Descriptions Table 8: LXT974A LXT974A and LXT975A LXT975A Hardware Control Interface Signal Descriptions Pin# 116 Symbol CFG_0 (Global) Type1 I Signal Description2 Configuration Control 0. When A/N is enabled, Low to High transition on CFG_0 causes auto-negotiate to restart on all ports and 0.9 = 1. When A/N is disabled, this input selects operating speed and directly affects bit 0.13. When CFG_0 is High, 100 Mbps is selected and bit 0.13 = 1. When CFG_0 is Low, 10 Mbps is selected and bit 0.13 = 0. 115 CFG_1 (Global) I Configuration Control 1. When A/N is enabled, CFG_1 determines operating speed advertisement capabilities in combination with CFG_2 and FDE on all ports. See Table 16 on page 19 for details. When A/N is disabled, CFG_1 enables 10 Mbps link test and directly affects bit 19.8. When CFG_1 is High, 10 Mbps link test is disabled and bit 19.8 = 1. When CFG_1 is Low, 10 Mbps link test is enabled and bit 19.8 = 0. 114 CFG_2 (Global) I Configuration Control 2. When A/N is enabled, CFG_2 determines operating speed advertisement capabilities in combination with CFG_1 on all ports. See Table 16 on page 19 for details. When A/N is disabled, this input selects either TP or FX interface. When FX interface is selected, the LXT974A/975A LXT974A/975A will automatically disable the scrambler. For correct FX operation, 100 Mbps operation must also be selected. Note: It is recommended to set the network interface for each port independently, via the SD/TPn pins. See Tables 1 and 4 for Signal Detect / TP Select signal descriptions and operation. When CFG_2 is Low, TP is enabled and bit 19.2 = 0. When CFG_2 is High, FX is enabled and bit 19.2 = 1. 110 FDE (Global) I Full-Duplex Enable - All Ports. When High, enables full-duplex operation on all ports. 117 FDE_FX I Full-Duplex Enable - FX Ports only. When High, enables full-duplex operation on all ports set for FX mode operation. This pin is ignored on ports set for TP mode. 113 BYPSCR (Global) I Bypass Scrambler. In TP mode, enables or bypasses Scrambler operation and directly affects MDIO register bit 19.3. When High, Scrambler is bypassed and bit 19.3 = 1. When Low, Scrambler is enabled and bit 19.3 = 0. In FX mode, the LXT974A/975A LXT974A/975A_ automatically bypasses the Scrambler. This pin has no effect selecting Scrambler bypass. 111 AUTOENA (Global) I Auto-Negotiation Enable. When High, enables auto-negotiation on all ports. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain. 2. The LXT974A/975A/975 LXT974A/975A/975_ supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). 11 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Table 9: LXT974A LXT974A and LXT975A LXT975A Miscellaneous Signal Descriptions Pin# 20 19 18 Symbol ADD4 ADD3 ADD2 Type1 I I I Signal Description2 Address . Set upper three bits of PHY address. ADD are set internally to match port number as shown at right. ADD1 ADD0 Port 0 0 0 0 1 1 1 0 2 1 1 3 101, 112, 159 TEST I Test. Must be tied Low. 140 RBIAS I Bias. This pin provides bias current for the internal circuitry. Must be tied to ground through a 22 k resistor. 118 CLK25M CLK25M I Clock Input. A 25 MHz clock input is required at this pin. Refer to Functional Description for detailed clock requirements. 109 RESET I Reset. This active Low input is OR'ed with the control register Reset bit (0.15). The LXT974A/975A LXT974A/975A reset cycle is extended 205 µs (nominal) after Reset is de-asserted. 102 PWRDN I Power Down. When High, forces LXT974A/975A LXT974A/975A into power down mode. This pin is OR'ed with the Power Down bit (0.11). Refer to Table 46 on page 57 for more information. N/C - No Connection. Leave open. 41, 119, 120 1. Type Column Coding: I = Input, O = Output, A = Analog. 2. The LXT974A/975A LXT974A/975A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). Table 10: LXT974A LXT974A and LXT975A LXT975A LED Indicator Signal Descriptions Pin#2 Symbol Type1 Signal Description3 11 8 4 1 LED0_0 LED1_0 LED2_0 LED3_0 OD LED0 - Ports 0 - 3. In default mode, active Low output indicates transmitter active. However, LED0 is programmable and may also be set to indicate receiver active, link status or duplex status. Refer to LED Configuration Register, Table 53 on page 63, for details on programming options. 12 9 5 2 LED0_1 LED1_1 LED2_1 LED3_1 OD LED1 - Ports 0 - 3. In default mode, active Low output indicates receiver active. However, LED1 is programmable and may also be set to indicate link status, duplex status, or operating speed. Refer to LED Configuration Register, Table 53 on page 63, for details on programming options. 13 10 6 3 LED0_2 LED1_2 LED2_2 LED3_2 OD LED2 - Ports 0 - 3. In default mode, active Low output indicates link up. However, LED2 is programmable and may also be set to indicate duplex status, operating speed or collision. Refer to LED Configuration Register, Table 53 on page 63, for details on programming options. 17 LEDENA O LED Enable. Active High output signals external device that LEDDAT is active. 15 LEDCLK O LED Clock. 25 MHz clock for LED serial data output. 16 LEDDAT O LED Data. Serial data output for 24 LEDs (6 x 4 ports) data. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain. 2. Unused pins should be tied Low. 3. The LXT974A/975A LXT974A/975A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). 12 LXT974A/LXT975A LXT974A/LXT975A Pin Assignments and Signal Descriptions Table 11: LXT974A LXT974A Power Supply Signal Descriptions Pin# Symbol Type Signal Description 22, 60, 96 VCC - Power Supply. +5V supply for all digital circuits. 40, 78 VCCMII - MII Supply. +3.3V or +5V supply for MII. A decoupling capacitor to digital ground should be supplied for these pins. 7, 14, 39, 56, 59, 77, 95, 160 GND - Digital Ground. Ground return for digital supply. 21 GNDA - Analog Ground. Ground return for analog supply. 108 GNDH - Ground. Ground return for core analog circuitry. 107 VCCH - Supply. +5V supply for core analog circuitry. 128, 137, 147, 156 VCCT - Transmit Power Supply. +5V supply for transmit circuits. 127, 136, 146, 155 GNDT - Transmit Ground. Ground return for transmit supply. 125, 134, 144, 153, VCCR - Receive Power Supply. +5V supply for all receive circuits. 121, 122, 131, 141, 150 GNDR - Receive Ground. Ground return for receive supply. Table 12: LXT975A LXT975A Power Supply Signal Descriptions Pin# Symbol Type Signal Description 22, 60, 96 VCC - Power Supply. +5V supply for all digital circuits. 40, 78 VCCMII - MII Supply. +3.3V or +5V supply for MII. A decoupling capacitor to digital ground should be supplied for these pins. 7, 14, 39, 56, 59, 77, 95, 160 GND - Digital Ground. Ground return for digital supply. 21 GNDA - Analog Ground. Ground return for analog supply. 108 GNDH - Ground. Ground return for core analog circuitry. 107 VCCH - Supply. +5V supply for core analog circuitry. 128, 135, 147, 154 VCCT - Transmit Power Supply. +5V supply for transmit circuits. 127, 134, 146, 153 GNDT - Transmit Ground. Ground return for transmit supply. 125, 132, 144, 151, VCCR - Receive Power Supply. +5V supply for all receive circuits. 121, 122, 131, 137, 141, 150, 156 GNDR - Receive Ground. Ground return for receive supply. 13 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver FUNCTIONAL DESCRIPTION Introduction The LXT974A LXT974A and LXT975A LXT975A are four-port Fast Ethernet 10/100 Transceivers that support 10 Mbps and 100 Mbps networks. They comply with all applicable requirements of IEEE 802.3. Each port can directly drive either a 100BASE-TX 100BASE-TX line (>130 meters) or a 10BASE-T 10BASE-T line (>185 meters). Figure 3 shows the LXT974A LXT974A in a typical switch application. Figure 3: LXT974A LXT974A Switch Application Backplane Fiber Module Fiber Module Fiber Module LXT974A LXT974A 10/100 Quad Transceiver Switch MAC ASIC The LXT974A/975A LXT974A/975A interfaces to four 10/100 Media Access Controllers (MAC)s through the MII interfaces. It performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X 100BASE-X specification. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX 100BASE-TX connections. The MII speeds are automatically set once port operating conditions have been determined. The LXT974A/975A LXT974A/975A provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps. It also offers standard Loopback Mode for switch applications. The LXT974A/ LXT974A/ 975A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). Memory Fiber Module LXT974A LXT974A 10/100 Quad Transceiver LXT974A LXT974A 10/100 Quad Transceiver QUAD Transformer QUAD Transformer Single RJ45 Selectable 10 or 100 Mbps The LXT975A LXT975A is pin compatible with the LXT974A LXT974A except for the network ports. Each port on the LXT974A LXT974A provides a combination twisted-pair or PECL interface for a 10/100BASE-TX 10/100BASE-TX or 100BASE-FX 100BASE-FX connection. The LXT975A LXT975A is optimized for stacked RJ45 modular applications as shown in Figure 4. Ports 1 and 3 support the PECL interface for fiber connections and all four ports support the twisted-pair interface for 10/100BASE-TX 10/100BASE-TX connections. Figure 4: LXT975A LXT975A Switch Application On power-up, the LXT974A/975A LXT974A/975A uses auto-negotiation/ parallel detection on each port to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT974A/ LXT974A/ 975A will auto-negotiate with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support autonegotiation, the LXT974A/975A LXT974A/975A will automatically detect the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions accordingly. 14 Backplane Fiber Module Fiber Module Fiber Module LXT974A LXT974A 10/100 Quad Transceiver Switch MAC ASIC Memory Fiber Module LXT975A LXT975A 10/100 Quad Transceiver QUAD Transformer LXT975A LXT975A 10/100 Quad Transceiver QUAD Transformer LXT975A LXT975A 10/100 Quad Transceiver QUAD Transformer LXT975A LXT975A 10/100 Quad Transceiver QUAD Transformer Stacked RJ45 10 or 100 Mbps LXT974A/LXT975A LXT974A/LXT975A Functional Description Network Media / Protocol Support The LXT974A/975A LXT974A/975A supports both 10BASE-T 10BASE-T and 100BASE-TX 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX 100BASE-FX). A Media Independent Interface (MII) is used for communication with the Media Access Controller (MAC). 10/100 Mbps Network Interface Each of the four network interface ports consists of four external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and fiber. Signal assignments (input or output, positive or negative) vary depending on whether the port is configured for TP or fiber media. Refer to Tables 1 through 6 for specific pin assignments. Fiber Interface The LXT974A/975A LXT974A/975A provides a PECL interface that complies with the ANSI X3.166 specification. This interface is suitable for driving a fiber-optic coupler. The twisted-pair pin assignments are remapped to support the PECL interface. The LXT974A LXT974A supports both the twisted-pair and fiber interface on all four ports. The LXT975A LXT975A, optimized for TP operation with dual-high RJ45 connectors, provides dual interfaces on ports 1 and 3. During 100BASE-FX 100BASE-FX operation, the FIBI pins receive differential PECL signals and the FIBO pins produce differential PECL output signals. Fiber ports cannot be enabled via auto-negotiation; they must be enabled via the Hardware Control Interface or MDIO registers. The LXT974A/975A LXT974A/975A output drivers generate either 100BASE-TX 100BASE-TX, 10BASE-T 10BASE-T, or 100BASE-FX 100BASE-FX output. When not transmitting data, the LXT974A/975A LXT974A/975A generates 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX 100BASE-TX, 100BASE-FX 100BASE-FX, or 10BASE-T 10BASE-T input, depending on the mode selected. Autonegotiation/parallel detection or manual control is used to determine the speed of this interface. Twisted-Pair Interface When operating at 100 Mbps, MLT3 symbols are continuously transmitted and received. When not transmitting data, the LXT974A/975A LXT974A/975A generates "IDLE" symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. In 100 Mbps mode, the LXT974A/975A LXT974A/975A is capable of driving a 100BASE-TX 100BASE-TX connection over 100, Category 5, Unshielded Twisted Pair (UTP). A 10BASE-T 10BASE-T connection can be supported using 100 Category 3, UTP. Only a transformer (1:1 on receive side, 2:1 on transmit side), load resistors, and bypass capacitors are needed to complete this interface. Using Level One's patented waveshaping technology, the transmitter predistorts the outgoing signal to reduce the need for external filters for EMI compliance. A 4k passive load is always present across the twisted-pair inputs. When enabled, the twisted-pair inputs are actively biased to approximately 2.8V. 15 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver MII Interface The LXT974A/975A LXT974A/975A supports four standard MIIs (one per port). This interface consists of a data interface and a management interface. The MII Data Interface passes data between the LXT974A/975A LXT974A/975A and one or more Media Access Controllers (MACs). Separate signals are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically, once the operating conditions of the network link have been determined. Nine signals are used to pass received data to the MAC: RXD, RX_CLK, RX_DV, RX_ER, COL and CRS. Seven signals are used to transmit data from the MAC: TXD, TX_CLK, TX_EN, and TX_ER. MII Data Interface Figure 5 shows the data portion of the MII interface. Separate channels are provided for transmitting data from the MAC to the LXT974A/975A LXT974A/975A (TXD), and for receiving data (RXD) from the line. Each channel has its own clock, data bus, and control signals. The LXT974A/975A LXT974A/975A supplies both clock signals as well as separate outputs for carrier sense and collision. Data transmission across the MII is implemented in 4-bit-wide nibbles. Tristating the MII The LXT974A/975A LXT974A/975A asserts RX_DV, RXD, RX_CLK and RX_ER as soon as it receives a packet from the network. When TRSTEn is High, the associated port output signals are tristated. Figure 5: MII Data Interface TX_EN n TXD n TX_ER n RX_CLK n RX_DV n RXD n RX_ER n CRS n COL n 16 However, Advanced TX_CLK Mode is available by setting MII register bit 19.5=1. In this mode, the LXT974A/975A LXT974A/975A samples the transmit data and control signals on the falling edge of TX_CLK. When operating under MDIO Control, the user can advance the transmit clock relative to TXD and TX_ER. When Advance TX_CLK Mode is selected, the LXT974A/975A LXT974A/975A clocks TXD data in on the falling edge of TX_CLK, instead of the rising edge. This mode provides an increase in timing margins of TXD, relative to TX_CLK. Advance TX_CLK Mode is enabled when bit 19.5 = 1. Transmit Enable The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN after the last bit of the packet. Receive Data Valid The LXT974A/975A LXT974A/975A asserts RX_DV when it receives a valid packet. Timing changes depend on line operating speed: · For 100TX 100TX and 100FX 100FX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the data packet. TX_CLK n LXT974A/975A LXT974A/975A Transmit Clock The LXT974A/975A LXT974A/975A is the master clock source for data transmission. The LXT974A/975A LXT974A/975A automatically sets the speed of TX_CLK to match port conditions. If the port is operating at 100 Mbps, TX_CLK will be set to 25 MHz. If the port is operating at 10 Mbps, TX_CLK will be set to 2.5 MHz. The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The LXT974A/975A LXT974A/975A normally samples these signals on the rising edge of TX_CLK. Media Access Controller MAC · For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the Start of Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet. Error Signals Whenever the LXT974A/975A LXT974A/975A receives an errored symbol from the network, it asserts RX_ER and drives "1110" on the RXD pins. When the MAC asserts TX_ER, the LXT974A/975A LXT974A/975A will drive "H" symbols out on the line. LXT974A/LXT975A LXT974A/LXT975A Functional Description Carrier Sense Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received from the line and in some modes when a packet is transmitted. On transmit, CRS is asserted on a 10 Mbps or 100 Mbps half-duplex link. Carrier sense is not generated on transmit when the link is operating in full-duplex mode. Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons: · De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to appear somewhat shorter to the MAC than it actually is on the wire. Table 13: Test Loopback Operation Bit Mode of Operation 19.2 0.13 10T Test Loopback 0 0 100TX 100TX Test Loopback 0 1 100FX 100FX Test Loopback 1 1 1. Bit 0.14 = 1, bit 0.8 = 1, and 0.12 = 0 must also be set to enable Test Loopback. Figure 6: Loopback Paths · CRS de-assertion is not aligned with TX_EN deassertion on transmit loopbacks in half-duplex mode. Operational Loopback Operational loopback is provided for 10 Mbps halfduplex links when bit 19.11 = 0. Data transmitted by the MAC will be looped back on the receive side of the MII. Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 19.11 = 1. Test Loopback A test loopback function is provided for diagnostic testing of the LXT974A/LXT975A LXT974A/LXT975A. During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT974A/975A LXT974A/975A and returned to the MAC. Test loopback is available for 100TX 100TX, 100FX 100FX, and 10T operation.Test loopback is enabled by setting bit 0.14 = 1, bit 0.8 = 1 (full-duplex), and bit 0.12 = 0 (disable auto-negotiation). The desired mode of operation for test loopback is set using bits 0.13 and 19.2 as shown in Table 13. Loopback paths for the three modes of operation are shown in Figure 6. 100FX 100FX Loopback 10T Loopback Digital Block MII FX Driver Analog Block TX Driver 100TX 100TX Loopback Collision The LXT974A/975A LXT974A/975A asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. Table 14 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. Table 14: Carrier Sense, Loopback, and Collision Conditions Speed & Duplex Condition Carrier Sense Loopback Collision Full-Duplex at 10 Mbps or 100 Mbps Receive Only None None 100 Mbps, Half-Duplex Transmit or Receive None Transmit and Receive 10 Mbps, Half-Duplex, 19.11 = 0 Transmit or Receive Yes Transmit and Receive 10 Mbps, Half-Duplex, 19.11 = 1 Transmit or Receive None Transmit and Receive 17 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver MII Management Interface The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO operates as a read-only interface. When MDDIS is Low, both read and write are enabled. The timing for the MDIO Interface is shown in Table 42 on page 54. The protocol is shown in Figures 7 and 8 (read and write). The protocol allows one controller to communicate with up to eight LXT974A/975A LXT974A/975A chips. Bits A4:2 of the 5-bit PHY address are assigned as the LXT974A/975A LXT974A/975A address. Bits A1:0 are assigned as port addresses 0 through 3. The LXT974A/975A LXT974A/975A supports 12 internal registers per port (48 total), each of which is 16 bits wide. The LXT974A/975A LXT974A/975A supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT974A/975A LXT974A/975A. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 specification. Additional registers are allowed for expanded functionality. The LXT974A/975A LXT974A/975A is configured with both sets of registers. Figure 7: Management Interface - Read Frame Structure MDC MDIO (Read) 32 "1"s 0 1 Preamble Idle 1 SFD A4 0 Op Code A3 A0 R4 R3 R0 Z D15 0 D15D14 D15D14 Turn Around Register Address PHY Address D14 D1 D1 D0 Data Write Idle Read Figure 8: Management Interface - Write Frame Structure MDC MDIO (Write) 32 "1"s Idle 0 Preamble 1 SFD 0 1 A4 Op Code A3 A0 R4 R3 R0 Register Address PHY Address 1 0 Turn Around D15 D14 D1 Data D0 Idle Write MII Interrupts The LXT974A/975A LXT974A/975A provides interrupt signals in two ways. The MDIO interrupt reflects the interrupt status of each port addressed by the read. Details are shown in Figure 9. Setting bit 17.1 = 1 on all four ports, enables global interrupts using the MDINT pin. An active Low on this pin indicates a status change on the LXT974A/975A LXT974A/975A. Interrupts may be caused by: · · · · Link status change Auto-negotiation complete Full-duplex status change Jabber detect Figure 9: MDIO Interrupt Signaling MDC INT MDIO Interrupt Z 0 Turn Around 18 MDIO FRAME Read Data Sourced by PHY Idle LXT974A/LXT975A LXT974A/LXT975A Functional Description Hardware Control Interface The Hardware Control Interface is used to configure operating characteristics of the LXT974A/975A LXT974A/975A. When MDDIS is Low, this interface provides initial values for the MDIO registers, and then passes control to the MDIO Interface. When MDDIS is High, this interface provides continuous control over the LXT974A/975A LXT974A/975A. Individual chip addressing allows multiple LXT974A/975A LXT974A/975A devices to share the MII in either mode. Tables 15 through 17 show how to set up the desired operating configurations using the Hardware Control Interface. Table 15: Configuring the LXT974A/975A LXT974A/975A via Hardware Control Desired Configuration Pin Name Input Value MDIO Registers AUTOENA High 0.12 = 1 SD/TPn Low 19.2 = 0 AUTOENA Low 0.12 = 0 Scrambler Bypassed on all ports BYPSCR High 19.3 = 1 Scrambler Enabled on all ports BYPSCR Low 19.3 = 0 Auto-Negotiation Enabled on all ports1, 2, 3 4 Auto-Negotiation Disabled on all ports 1. 2. 3. 4. SD/TPn must be set Low for Auto-Negotiation operation. Refer to Table 16 for Hardware Control Interface functions advertised when auto-negotiation is enabled. Fiber operation can be forced per port via SD/TPn pins when auto-negotiation is enabled. See Table 17 for details. Refer to Table 17 for Hardware Control Interface functions available when auto-negotiation is disabled. Table 16: Configuring LXT974A/975A LXT974A/975A Auto-Negotiation Advertisements Via Hardware Control Pin Settings Desired Configuration1,2 MDIO Registers SD/TPn (per port) FDE (global) CFG_2 (global) CFG_1 (global) CFG_03 (global) 4.5 4.6 4.7 4.8 Advertise All Low Ignore Low Low Ignore 1 1 1 1 Advertise 100 HD Low Low High Low Ignore 0 0 1 0 Advertise 100 HD/FD Low High High Low Ignore 0 0 1 1 Advertise 10 HD Low Low Low High Ignore 1 0 0 0 Advertise 10 HD/FD Low High Low High Ignore 1 1 0 0 Advertise 10/100 HD Low Low High High Ignore 1 0 1 0 1. Refer to Table 15 for basic configurations. 2. Refer to Table 17 for Hardware Control Interface functions available when auto-negotiation is disabled. 3. Auto-Negotiation is not affected by CFG_0. 19 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Table 17: Configuring the LXT974A/975A LXT974A/975A with Auto-Negotiation Disabled Pin Settings MDIO Registers 1,2 Desired Configuration SD/TPn per port CFG_2 global CFG_0 global FDE global FDE_FX 0.8 0.13 19.2 Per Port (Fiber) Configuration Fiber operation can be forced per port via SD/TPn pins when auto-negotiation is enabled. Per-port settings override the global pin settings. 100FX 100FX Full-Duplex Operation. High or PECL3 Ignored Ignored Ignored High 1 1 1 100FX 100FX Half-Duplex Operation. High or PECL3 Ignored Ignored Ignored Low 0 1 1 Global (Twisted-Pair) Configuration5 Force 100TX 100TX Full-Duplex Operation on all ports.4 Low Low High High Ignored 1 1 0 Force 100TX 100TX Half-Duplex Operation on all ports.4 Low Low High Low Ignored 0 1 0 Force 10T Full-Duplex Operation on all ports. Low Low Low High Ignored 1 0 0 Force 10T Half-Duplex Operation on all ports. Low Low Low Low Ignored 0 0 0 1. 2. 3. 4. 5. 20 Refer to Table 15 for basic configurations. Refer to Table 16 for Hardware Control Interface functions advertised when auto-negotiation is enabled. When SD/TPn is set High or to PECL levels, auto-negotiation is disabled and FDE_FX determines the duplex mode of the port. CFG_2, CFG_0, and SD/TPn must all be set for 100TX 100TX operation. Fiber configuration must be selected on a per-port basis. LXT974A/LXT975A LXT974A/LXT975A Functional Description Initialization At power-up or reset, the LXT974A/975A LXT974A/975A performs the initialization as shown in Figure 10. Control mode selection is provided via the MDDIS pin as shown in Table 18. When MDDIS (pin 100) is High, the LXT974A/975A LXT974A/975A operates in Manual Control Mode. When MDDIS is Low, the LXT974A/975A LXT974A/975A operates in MDIO Control Mode. The LXT974A/975A LXT974A/975A first checks the Hardware Control Interface pins and MDIO registers. Using these mechanisms, the user can command the LXT974A/975A LXT974A/975A to do one of the following: · Force network link to 100FX 100FX (Fiber). · Force network link operation to: 100TX 100TX, Full-Duplex 100TX 100TX, Half-Duplex 10BASE-T 10BASE-T, Full-Duplex 10BASE-T 10BASE-T, Half-Duplex · Allow auto-negotiation/parallel-detection. The Hardware Control Interface pins are used to set the state of the MDIO advertisement registers. MDIO Control Mode In the MDIO Control Mode, the LXT974A/975A LXT974A/975A uses the Hardware Control Interface to set up initial (default) values of the MDIO registers. The MDIO Register set for the LXT974A/975A LXT974A/975A is described in Tables 46 through 57. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). Once initial values are set, bit control reverts to the MDIO interface. Manual Control Mode In the Manual Control Mode, LXT974A/975A LXT974A/975A disables direct write operations to the MDIO registers via the MDIO interface. The Hardware Control Interface is continuously monitored and the MDIO registers are updated accordingly. When forcing the network link, the LXT974A/975A LXT974A/975A immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the autonegotiation / parallel-detection operation begins. Table 18: Mode Control Settings When the LXT974A/975A LXT974A/975A is first powered on, reset, or encounters a link failure state, it must determine the line speed and operating conditions to use for the network link. RESET Pin 109 PWR DWN Pin 102 MDIO Control Low High Low Manual Control Link Configuration MDDIS Pin 100 High High Low Reset - Low Low Power Down - - High Mode Figure 10: Hardware Interface Mode Selection Power-up or Reset MDIO Control Mode Low Check Value MDDIS High Manual Control Mode Read H/W Control Interface Disable MDIO Writes Initialize MDIO Registers Read H/W Control Interface Pass Control to MDIO Interface Update MDIO Registers Exit 21 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Auto-Negotiation communicate with devices that do not support autonegotiation. The LXT974A/975A LXT974A/975A attempts to auto-negotiate with its counterpart across the link by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 µs apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, which are referred to as a "page". All devices that support auto-negotiation must support a "Base Page" as defined in the IEEE 802.3 standard. Controlling Auto-Negotiation When auto-negotiation is controlled by software, the following steps are recommended: · After power-up, power-down, or reset, the powerdown recovery time, as specified in Table 43 on page 55, must be exhausted before proceeding. · Set the auto-negotiation advertisement register bits. · Enable auto-negotiation by setting MDIO bit 0.12 = 1. By exchanging Base Pages, the LXT974A/975A LXT974A/975A and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to proceed. Each side finds the highest common capabilities that both sides support. Both sides then exchange more pages, and finally agree on the operating state of the line. Monitoring Auto-Negotiation When auto-negotiation is being monitored, the following apply: · Bit 20.13 is set to 1 once the link is established. · Bits 20.12 and 20.11 can be used to determine the link operating conditions (speed and duplex). Parallel Detection In parallel with auto-negotiation, the LXT974A/975A LXT974A/975A also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. If either is detected, the device automatically reverts to the corresponding operating mode. Parallel detection allows the LXT974A/975A LXT974A/975A to Figure 11: LXT974A/975A LXT974A/975A Auto-Negotiation Operation Power-Up, Reset, Link Failure Start Disable Auto-Negotiation Go To Forced Settings Done 22 0.12 = 0 0.12 = 1 Check Value 0.12 Attempt AutoNegotiation YES Enable Auto-Neg/Parallel Detection Listen for 100TX 100TX Idle Symbols Link Set Listen for 10T Link Pulses NO LXT974A/LXT975A LXT974A/LXT975A Functional Description 100 Mbps Operation 100BASE-X 100BASE-X Network Operations 100BASE-X 100BASE-X MII Operations The LXT974A/975A LXT974A/975A encodes and scrambles the data sent by the MAC, and then transmits it using MLT3 signaling. The LXT974A/975A LXT974A/975A descrambles and decodes MLT3 data received from the network. When the MAC is not actively transmitting data, the LXT974A/975A LXT974A/975A sends out Idle symbols. The 100BASE-X 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However, data is normally transmitted across the MII interface in 4-bit nibbles. The LXT974A/975A LXT974A/975A incorporates a 4B/5B encoder/decoder circuit that translates 4-bit nibbles from the MII into 5-bit symbols for the 100BASE-X 100BASE-X connection, and translates 5-bit symbols from the 100BASE-X 100BASE-X connection into 4-bit nibbles for the MII. Figure 12 shows the data conversion flow from nibbles to symbols. Table 19 on page 24 shows 4B/5B symbol coding (not all symbols are valid). During 100BASE-X 100BASE-X operation, the LXT974A/975A LXT974A/975A transmits and receives 5-bit symbols across the network link. Figure 13 shows the structure of a standard frame packet. When the MAC is not actively transmitting data, the LXT974A/975A LXT974A/975A sends out Idle symbols on the line. In 100TX 100TX mode, the LXT974A/975A LXT974A/975A scrambles the data and transmits it to the network using MLT-3 line code. The MLT-3 signals received from the network are descrambled and decoded and sent across the MII to the MAC. In 100FX 100FX mode, the LXT974A/975A LXT974A/975A transmits and receives NRZI signals across the PECL interface. An external 100FX 100FX transceiver module is required to complete the fiber connection. As shown in Figure 13, the MAC starts each transmission with a preamble pattern. As soon as the LXT974A/975A LXT974A/975A detects the start of preamble, it transmits a J/K symbol (Start of Stream Delimiter, SSD) to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the Start of Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the LXT974A/975A LXT974A/975A transmits the T/R symbol End of Stream Delimiter (ESD) and then returns to transmitting Idle symbols. Figure 12: 100BASE-TX 100BASE-TX Data Flow Standard MII Mode Data Flow Parallel to Serial D0 D1 +1 D1 D2 D3 S0 S1 S2 S3 S4 5B/4B Serial to Parallel D3 Scramble 4B/5B D0 D2 0 DeScramble 0 0 -1 MLT3 Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1. 1. Four independent MII ports serve four independent Network ports. Network port configurations are independently selectable. MII port speed is set to match the associated Network port. 2. The Scrambler can be bypassed by setting 19.3 = 1. Figure 13: 100BASE-TX 100BASE-TX Frame Structure 64-Bit Preamble (8 Octets) P0 P1 Replaced by /J/K/ code-groups Start of Stream Delimiter (SSD) P6 Destination and Source Address (6 Octets each) SFD Start of Frame Delimiter (SFD) DA DA SA Packet Length (2 Octets) SA L1 L2 Data Field Frame Check Field (Pad to minimum packet size) (4 Octets) D0 D1 Dn CRC InterFrame Gap / Idle Code (> 12 Octets) I0 IFG Replaced by /T/R/ code-groups End of Stream Delimiter (ESD) 23 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Table 19: 4B/5B Coding 1 01001 Data 1 2 10100 Data 2 3 10101 Data 3 4 01010 Data 4 5 01011 Data 5 0110 6 01110 Data 6 0111 7 01111 Data 7 1000 8 10010 Data 8 1001 9 10011 Data 9 1010 A 10110 Data A 1011 B 10111 Data B 1100 C 11010 Data C 1101 D 11011 Data D 1110 E 11100 Data E 1111 F 11101 Data F undefined I1 1 1 1 11 Idle. Used as inter-stream fill code 0101 J2 11000 Start of Stream Delimiter (SSD), part 1 of 2 0101 K2 10001 Start of Stream Delimiter (SSD), part 2 of 2 undefined T3 01101 End of Stream Delimiter (ESD), part 1 of 2 undefined R3 00111 End of Stream Delimiter (ESD), part 2 of 2 undefined H4 00100 Transmit Error. Used to force signaling errors undefined Invalid 00000 Invalid undefined Invalid 00001 Invalid undefined Invalid 00010 Invalid undefined Invalid 00011 Invalid undefined Invalid 00101 Invalid undefined Invalid 00110 Invalid undefined Invalid 01000 Invalid undefined Invalid 01100 Invalid undefined Invalid 10000 Invalid undefined 24 Data 0 0101 1. 2. 3. 4. 11110 0100 INVALID 0 0011 CONTROL 5B Code 43210 0010 IDLE Name 0001 DATA 4B Code 3210 0000 Code Type Invalid 11001 Invalid Interpretation The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition. LXT974A/LXT975A LXT974A/LXT975A Functional Description 100BASE-X 100BASE-X Protocol Sublayer Operations Preamble Handling With respect to the 7-layer communications model, the LXT974A/975A LXT974A/975A is a Physical Layer 1 (PHY) device. The LXT974A/975A LXT974A/975A implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u specification. The following paragraphs discuss LXT974A/975A LXT974A/975A operation from the reference model point of view. When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start of Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues to encode the remaining MII data, following Table 19 on page 24, until TX_EN is de-asserted. It then returns to supplying IDLE symbols to the line driver. In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD. PCS Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/decoding function. For 100TX 100TX and 100FX 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. For 10T operation, the PCS layer merely provides a bus interface and serialization/de-serialization function. 10T operation does not use the 4B/5B encoder. Figure 14: LXT974A/975A LXT974A/975A Protocol Sublayers MII Interface PCS Sublayer PMA Sublayer LXT974A LXT974A Encoder/Decoder Serializer/De-serializer Link/Carrier Detect PECL Interface PMD Sublayer Scrambler/ De-scrambler 100BASE-TX 100BASE-TX Fiber Transceiver 100BASE-FX 100BASE-FX 25 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Data Errors Collision Indication Figure 15 shows normal reception. When the LXT974A/975A LXT974A/975A receives invalid symbols from the line, it asserts RX_ER, as shown in Figure 16. Figure 15: Figure 17 shows normal transmission. The LXT974A/ LXT974A/ 975A detects a collision if transmit and receive are active at the same time. As shown in Figure 18, upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision. 100BASE-TX 100BASE-TX Reception with No Errors R X _C LK R X _D V R X D p re am b le S FD S F D DA DA DA CRC DA CRC CRC CRC R X _E R Figure 16: 100BASE-TX 100BASE-TX Reception with Invalid Symbol R X _C LK R X _D V R X D pre am ble S F D S F D DA DA DA XX XX XX XX XX XX XX XX XX R X _E R Figure 17: 100BASE-TX 100BASE-TX Transmission with No Errors TX_CLK TX_EN TXD P R E A M B L DA E DA DA DA DA DA DA DA DA CRS COL Figure 18: 100BASE-TX 100BASE-TX Transmission with Collision TX _C LK TX _E N TX D P R E A M B L E JA M JA M JA M JA M CRS COL 26 LXT974A/LXT975A LXT974A/LXT975A Functional Description PMA Sublayer Link The LXT974A/975A LXT974A/975A supports a Standard link algorithm or Enhanced link algorithm, which can be set via bit 16.1. Link is established when the symbol error rate is less than 64 errors out of 1024 symbols received. Once the link is established: When standard link algorithm is selected (default, bit 16.1 = 0), the link will go down when the symbol error rate becomes greater than 64 out of 1024. When enhanced link algorithm is selected (bit 16.1 = 1), the link will go down if twelve idle symbols in a row are not received within 1 to 2 ms. This mode makes it more difficult to bring the link down. In either mode, the LXT974A/975A LXT974A/975A reports link failure via the MII status bits (1.2, 18.15, and 20.13) and interrupt functions. If auto-negotiate is enabled, link failure causes the LXT974A/975A LXT974A/975A to re-negotiate. Link Failure Override The LXT974A/975A LXT974A/975A will normally transmit 100 Mbps data packets or Idle symbols only if it detects the link is up, and transmits only FLP bursts if the link is not up. Setting bit 19.14 = 1 overrides this function, allowing the LXT974A/975A LXT974A/975A to transmit data packets even when the link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the LXT974A/975A LXT974A/975A will automatically begin transmitting FLP bursts if the link goes down. Carrier Sense (CRS) For 100TX 100TX and 100FX 100FX links, a start of stream delimiter or /J/K symbol pair causes assertion of carrier sense (CRS). An end of stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS if IDLE symbols are received without /T/R; however, in this case RX_ER will be asserted for one clock cycle when CRS is de-asserted. For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end of frame (EOF) marker. Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100TX 100TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions. Scrambler/Descrambler (100TX 100TX Only) The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. The scrambler/descrambler can be bypassed by either setting bit 19.3 = 1 or setting pin (BYPSCR) High. The scrambler is automatically bypassed when the fiber port is enabled. Scramber bypass is provided for diagnostic and test support. Baseline Wander Correction The LXT974A/975A LXT974A/975A provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX 100BASE-TX is by definition "unbalanced". This means that the DC average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander can cause receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact characteristics of the wander are completely data dependent. The LXT974A/975A LXT974A/975A baseline wander correction characteristics allow the LXT974A/975A LXT974A/975A to recover errorfree data while receiving worst-case "killer" packets over a variety of cable distances. Polarity Correction The LXT974A/975A LXT974A/975A automatically detects and corrects for the condition where the receive signal (TPIP/ N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end of frame (EOF) markers, are received consecutively. If link pulses or data are not received by the maximum receive time-out period, the polarity state is reset to a non-inverted state. Fiber PMD Sublayer The LXT974A/975A LXT974A/975A provides a PECL interface for connection to an external fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The LXT974A/975A LXT974A/975A uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps and does not support 10FL applications. 27 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver 10 Mbps Operation The LXT974A/975A LXT974A/975A will operate as a standard 10BASE-T 10BASE-T transceiver. Data transmitted by the MAC as 4-bit nibbles is serialized, Manchester-encoded, and transmitted on the TPOP/N outputs. Received data is decoded and de-serialized into 4-bit nibbles. The LXT974A/975A LXT974A/975A supports all the standard 10 Mbps functions. 10BASE-T 10BASE-T MII Operation The MAC transmits data to the LXT974A/975A LXT974A/975A via the MII interface. The LXT974A/975A LXT974A/975A converts the digital data from the MAC into an analog waveform that is transmitted to the network via the copper interface. The LXT974A/975A LXT974A/975A converts analog signals received from the network into a digital format suitable for the MAC. The LXT974A/975A LXT974A/975A sends the received data to the MAC via the MII. 10BASE-T 10BASE-T Network Operations During 10BASE-T 10BASE-T operation, the LXT974A/975A LXT974A/975A transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT974A/975A LXT974A/975A sends out link pulses on the line. In 10BASE-T 10BASE-T mode, the polynomial scrambler/ descrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT974A/ LXT974A/ 975A and sent across the MII to the MAC. The LXT974A/975A LXT974A/975A does not support fiber connections at 10 Mbps. Preamble Handling In 10BASE-T 10BASE-T Mode, the LXT974A/975A LXT974A/975A strips the entire preamble off of received packets. CRS is asserted a few bit times after carrier is detected. RX_DV is held Low for the duration of the preamble. Link Test In 10 Mbps mode, the LXT974A/975A LXT974A/975A always transmit link pulses. If the link test function is enabled, it monitors the connection for link pulses. Once link pulses are detected, data transmission will be enabled and will remain enabled as long as either the link pulses or data transmission continue. If the link pulses stop, the data transmission will be disabled. If the link test function is disabled, the LXT974A/ LXT974A/ 975A will transmit to the connection regardless of detected link pulses. The link test function can be disabled by setting bit 19.8 = 1 or by setting AUTOENA to disable auto-negotiation and setting CFG_1 input High. Link Failure Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT974A/975A LXT974A/975A returns to the autonegotiation phase if auto-negotiation is enabled. SQE (Heartbeat) By default, the SQE (heartbeat) function is disabled on the LXT974A/975A LXT974A/975A. To enable this function, set bit 19.10 =1. When this function is enabled, the LXT974A/975A LXT974A/975A will assert its COL output after each transmit packet. See Figure 31 on page 52 for SQE timing parameters. Jabber If MAC transmission exceeds the jabber timer, the LXT974A/975A LXT974A/975A will disable the transmit and loopback functions and enable the COL pin. See Figure 32 on page 52 for jabber timing parameters. The LXT974A/975A LXT974A/975A automatically exits jabber mode after the unjab time has expired. This function can be disabled by setting bit 19.9 = 1. When RX_DV is asserted, the very first two nibbles driven by the LXT974A/975A LXT974A/975A are the SFD "5D" hex followed by the body of the packet. In 10T loopback, the LXT974A/975A LXT974A/975A loops back whatever the MAC transmits to it, including the preamble. 28 LXT974A/LXT975A LXT974A/LXT975A Functional Description LED Functions Per Port LEDs The LXT974A/975A LXT974A/975A provides three programmable LEDs per port. Refer to Table 53 on page 63 for LED programming details. The LXT974A/975A LXT974A/975A also provides a serial LED output. The LXT974A/975A LXT974A/975A provides three LED outputs for each port (LEDn_0, LEDn_1 and LEDn_2, where n = port number). These outputs can directly drive LEDs to indicate activity and collision status. The active Low "on" times are normally extended for improved LED visibility. The ontime extension can be disabled by setting bit 16.0 = 1. Serial LED Output The LXT974A/975A LXT974A/975A provides a serial LED interface which should be attached to an external shift register. This interface provides 24 status bits (6 x 4 ports). Each port reports the following conditions: · Transmit (T) 0 = Transmit active 1 = Receive inactive · Link (L) 0 = Link active 1 = Link inactive · Duplex (D) 0 = Half-Duplex 1 = Full-Duplex · Speed (S) 0 = 100 Mbps In default mode, LED_0 indicates transmitter active. However, LEDn_0 is programmable and may also be set to indicate receiver active, link, or full-duplex status. Refer to LED Configuration Register, Table 53 on page 63, for details on programming options. 1 = Transmit inactive · Receive (R) 0 = Receive active LEDn_0 1 = 10 Mbps LEDn_1 In default mode, LED_1 indicates receiver active. However, LEDn_1 is programmable and may also be set to indicate link status, full-duplex status or operating speed. Refer to LED Configuration Register, Table 53 on page 63, for details on programming options. LEDn_2 · Collision (C) 0 = Collision active In default mode, active Low output indicates link up. However, LEDn_2 is programmable and may also be set to indicate full-duplex status, operating speed or collision. Refer to LED Configuration Register, Table 53 on page 63, for details on programming options. 1 = Collision inactive LED Data is output on LEDDAT in sets of 24 bits. The serial burst is repeated every 1 ms. A status change in any bit also triggers an immediate serial burst (following the minimum inter-burst gap of 10 µs). LEDENA is driven High for the duration of the LEDDAT output. Table 20: LED-DAT Serial Port Bit Assignments Port 0 Port 1 Port 3 Port 2 231 22 21 20 19 18 17 16 15 14 13 12 11 : 6 5 4 3 2 1 0 T R L D S C T R L D S C TRLDSC T R L D S C 1. Bit 23 is shifted out first. 29 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Operating Requirements Power Requirements The LXT974A/975A LXT974A/975A requires four +5V supply inputs (VCC, VCCR, VCCT, and VCCH). These inputs may be supplied from a single source although decoupling is required to each respective ground. As a matter of good practice, these supplies should be as clean as possible. Typical filtering and decoupling are shown in Figure 21 on page 38. MII Power Requirements An additional supply may be used for the MII (VCCMII). The supply may be either +5V or +3.3V. When the MII supply is 3.3V, MII inputs may not be driven with 5V levels. VCCMII should be supplied from the same power source used to supply the controller on the other side of the MII interface. Refer to Table 27 on page 43 for MII I/O characteristics. Power Down Mode The LXT974A/975A LXT974A/975A goes into Power Down Mode when PWRDWN is asserted. In this mode, all functions are disabled except the MDIO. The power supply current is significantly reduced. This mode can be used for energy-efficient applications or for redundant applications where there are two devices and one is left as a standby. When the LXT974A/975A LXT974A/975A is returned to normal operation, configuration settings of the MDIO registers are maintained. Refer to Table 25 on page 42 for power down specifications. Clock Requirements The LXT974A/975A LXT974A/975A requires a constant 25 MHz clock (CLK25M CLK25M) that must be enabled at all times. Refer to Test Specifications, Table 28 on page 43, for clock timing requirements. Low-Voltage Fault Detect The LXT974A/975A LXT974A/975A has a low-voltage fault detection function that prevents transmission of invalid symbols when VCC goes below normal operating levels. This function disables the transmit outputs when a lowvoltage fault on VCC occurs. If this condition happens, bit 20.2 is set High. Operation is automatically restored when VCC returns to normal. Table 29 on page 44 indicates voltage levels used to detect and clear the low-voltage fault condition. 30 LXT974A/LXT975A LXT974A/LXT975A Application Information APPLICATION INFORMATION Design Recommendations Power Supply Filtering The LXT974A/975A LXT974A/975A is designed to comply with IEEE requirements and to provide outstanding receive Bit Error Rate (BER) and long-line-length performance. Lab testing has shown that the LXT974A/975A LXT974A/975A can perform well beyond the required distance of 100 meters. To achieve maximum performance from the LXT974A/975A LXT974A/975A, attention to detail and good design practices are required. Refer to the LXT974A/975A LXT974A/975A Design and Layout Guide for detailed design and layout information. Power supply ripple and digital switching noise on the VCC plane can cause EMI problems and degrade line performance. It is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having these problems: · Poorly-regulated or over-burdened power supplies. · Wide data busses (>32-bits) running at a high clock rate. · DC-to-DC converters. General Design Guidelines Adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. Up to 50 mV of noise is considered acceptable. 50 to 80 mV of noise is considered marginal. High-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: · Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC or ground plane that is not located adjacent to the signal layer. · Use ample bulk and decoupling capacitors throughout the design (a value of .01 µF is recommended for decoupling caps). · Provide ample power and ground planes. · Provide termination on all high-speed switching signals and clock lines. · Provide impedance matching on long traces to prevent reflections. · Route high-speed signals next to a continuous, unbroken ground plane. · Filter and shield DC-DC converters, oscillators, etc. · Do not route any digital signals between the LXT974A/975A LXT974A/975A and the RJ45 connectors at the edge of the board. · Do not extend any circuit power and ground plane past the center of the magnetics or to the edge of the board. Use this area for chassis ground, or leave it void. Many of these issues can be improved just by following good general design guidelines. In addition, Level One also recommends filtering between the power supply and the analog VCC pins of the LXT974A/975A LXT974A/975A. Filtering has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT974A/975A LXT974A/975A, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI problems. The recommended implementation is to divide the VCC plane into two sections. The digital section supplies power to the digital VCC pin, MII VCC pin, and to the external components. The analog section supplies power to VCCH, VCCT, and VCCR pins of the LXT974A/975A LXT974A/975A. The break between the two planes should run under the device. In designs with more than one LXT974A/975A LXT974A/975A, a single continuous analog VCC plane can be used to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 impedance at 100 MHz. The beads should be placed so that current flow is evenly distributed. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. Each LXT974A/975A LXT974A/975A draws a maximum of 500 mA from the analog supply so beads rated at 750 mA should be used. A bulk cap (2.2 -10 µF) should be placed on each side of each ferrite bead to stop switching noise from traveling through the ferrite. In addition, a high-frequency bypass cap (.01µf) should be placed near each analog VCC pin. 31 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Ground Noise The best approach to minimize ground noise is strict use of good general design guidelines and by filtering the VCC plane. Power and Ground Plane Layout Considerations Great care needs to be taken when laying out the power and ground planes. The following guidelines are recommended: · Follow the guidelines in the LXT974A/975A LXT974A/975A Layout Guide for locating the split between the digital and analog VCC planes. MII Terminations Series termination resistors are not required on the MII signals driven by the LXT974A/975A LXT974A/975A. The RBIAS Pin The LXT974A/975A LXT974A/975A requires a 22 k, 1% resistor directly connected between the RBIAS pin and ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, and sink the other side of the resistor to a filtered ground. Surround the RBIAS trace with a filtered ground; do not run high-speed signals next to RBIAS. · Keep the digital VCC plane away from the TPOP/N and TPIP/N signals, away from the magnetics, and away from the RJ45 connectors. · Place the layers so that the TPOP/N and TPIP/N signals can be routed near or next to the ground plane. For EMI reasons, it is more important to shield TPOP/ N and TPIP/N. Chassis Ground For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. Chassis ground should extend from the RJ45 connectors to the magnetics, and can be used to terminate unused signal pairs (`Bob Smith' termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kV isolation capacitor. In multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kV isolation to the Bob Smith termination. 32 LXT974A/LXT975A LXT974A/LXT975A Application Information The Twisted-Pair Interface The Fiber Interface Because the LXT974A/975A LXT974A/975A transmitter uses 2:1 magnetics, system designers must take extra precautions to minimize parasitic shunt capacitance in order to meet return loss specifications. These steps include: The fiber interface consists of a PECL transmit and receive pair to an external fiber-optic transceiver. The transmit pair should be AC-coupled to the transceiver, and biased to 3.7V with a 50 equivalent impedance. The receive pair can be DC-coupled, and should be biased to 3.0V with a 50 equivalent impedance. Figure 23 on page 40 shows the correct bias networks to achieve these requirements. · Use compensating inductor in the output stage (see Figure 22 on page 39). · Place the magnetics as close as possible to the LXT974A/975A LXT974A/975A. · Keep transmit pair traces short. · Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the transmit traces two to three layers from the ground plane, with no intervening signals. · Some magnetic vendors are producing magnetics with improved return loss performance. Use of these improved magnetics increases the return loss budget available to the system designer. · Improve EMI performance by filtering the output centertap. A single ferrite bead may be used to supply centertap current to all 4 ports. All four ports draw a combined total of 270 mA so the bead should be rated at 400 mA. In addition, follow all the standard guidelines for a twistedpair interface: · Route the signal pairs differentially, close together. Allow nothing to come between them. · Keep distances as short as possible; both traces should have the same length. · Avoid vias and layer changes as much as possible. · Keep the transmit and receive pairs apart to avoid cross-talk. · Put all the components for the transmit network on the front side of the board (same side as the LXT974A/ LXT974A/ 975A). · Put entire receive termination network on the back side of the board. · Bypass common-mode noise to ground on the inboard side of the magnetics using 0.01 µF capacitors. · Keep termination circuits close together and on the same side of the board. · Always put termination circuits close to the source end of any circuit. 33 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Magnetics Information Magnetics With Improved Return Loss Performance The LXT974A/975A LXT974A/975A requires a 1:1 ratio for the receive transformers and a 2:1 ratio for the transmit transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from static voltages across the connectors and cables. Refer to Table 21 for transformer requirements. Level One is working with magnetic vendors to develop magnetic modules with improved return loss characteristics. These improved magnetics simplify the design requirements for meeting ANSI X3.263 return loss specifications. Based on a limited evaluation, Tables 22 and 23 lists transformers by manufacturer and part number. For additional magnetic information refer to www.level1.com for the Magnetic Manufacturers Cross Reference Guide. Magnetic information is provided as a reference only. Before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for a specific application. Table 21: Magnetics Requirements Parameter Min Nom Max Units Rx turns ratio ­ 1:1 ­ ­ Tx turns ratio ­ 2:1 ­ ­ Insertion loss 0.0 ­ 1.1 dB Primary inductance 350 ­ ­ µH Transformer isolation ­ 2 ­ kV Differential to common mode rejection 40 ­ ­ dB .1 to 60 MHz 35 ­ ­ dB 60 to 100 MHz ­ ­ -16 dB 30 MHz ­ ­ -10 dB 80 MHz ­ ­ -20 dB 30 MHz ­ ­ -15 dB 80 MHz Return Loss - Standard Return Loss - Improved 34 Test Condition 80 MHz LXT974A/LXT975A LXT974A/LXT975A Application Information Table 22: LXT974A LXT974A Magnetic Manufacturers Manufacturer2 Dual Port Single-High Quad Port Dual-High3 Quad Port Single-High Belfuse 5558-5999-F5 5558-5999-F5 S558-5999-E4 S558-5999-E4 S558-5999-F4 S558-5999-F4 Delta LF8254 LF8254 LF8251A LF8251A LF8251D1 LF8251D1 ­ HALO TG110-S220NX TG110-S220NX TG110-S222NX TG110-S222NX TG110-S420NX TG110-S420NX TG110-S460NX TG110-S460NX TG110-S465NX TG110-S465NX ­ Nanopulse 6872-30 6888-30 6889-30 6922-30 6932-30 H1069 H1069 H1074 H1074 H1068 H1068 ST6180T1 ST6180T1 ST6402T1 ST6402T1 ST6186T1 ST6186T1 Pulse ­ VALOR ST6174T ST6174T YCL PH406002 PH406002 S558-5999-D9 S558-5999-D9 S558-5999-J0 S558-5999-J0 ­ ­ 1. Magnetic with improved return loss performance. 2. Device manufacturers may have additional magnetics with varying pinouts. 3. The LXT975A LXT975A is preferred for dual-high applications. Each design must be evaluated for cross-talk and return loss performance. Table 23: LXT975A LXT975A Magnetic Manufacturers Dual Port Single-High Quad Port Single-High Belfuse ­ ­ S558-5999-F6 S558-5999-F6 Delta ­ ­ LF8713 LF8713 LF8701 LF8701 HALO ­ ­ TG110-S422NX TG110-S422NX TG110-S462NX TG110-S462NX Pulse ­ ­ H1076 H1076 VALOR ­ ­ ST6417T1 ST6417T1 Manufacturer2 Quad Port Dual-High 1. Magnetic with improved return loss performance. 2. Device manufacturers may have additional magnetics with varying pinouts. 35 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Twisted-Pair/ RJ45 Interface Figure 19 shows layout of the LXT974A LXT974A twisted-pair interface in a single-high RJ45 modular application. Figure 20 shows layout of the LXT975A LXT975A twisted-pair interface in a dual-high (stacked) RJ45 application. Figure 19: Typical LXT974A LXT974A Twisted-Pair Single RJ45 Modular Application LXT974A LXT974A Port 3 Port 2 Port 1 Port 0 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 GND TEST TP0 TPON0 VCCT GNDT TPOP0 VCCR TPIN0 TPIP0 GNDR TP1 TPON1 VCCT GNDT TPOP1 VCCR TPIN1 TPIP1 GNDR R BIAS TP2 TPON2 VCCT GNDT TPOP2 VCCR TPIN2 TPIP2 GNDR TP3 TPON3 VCCT GNDT TPOP3 VCCR TPIN3 TPIP3 GNDR GNDR 20 19 18 17 16 15 Rx Tx 21 14 13 12 11 10 25 26 23 24 Tx Rx 28 29 9 8 7 6 Rx Tx 33 34 30 31 5 4 3 2 1 Rx 35 36 Termination resistors and common mode bypass capacitors are not shown. See "Layout Requirements" section for recommended application circuit. Tx 38 39 40 RJ45 Footprint 2 1 4 3 6 5 8 7 2 1 4 3 6 5 8 7 2 1 4 6 3 5 8 7 2 1 4 3 6 5 8 7 Edge of PCB 1 Single RJ45 36 Port 3 8 1 Port 2 8 1 Port 1 8 1 Port 0 8 Amphenol 557571-1 1X4 Port Single Modular Jack LXT974A/LXT975A LXT974A/LXT975A Application Information Figure 20: Typical LXT975A LXT975A Twisted-Pair Stacked RJ45 Modular Application LXT975A LXT975A Port 3 Port 2 Port 1 Port 0 130 129 128 127 126 125 124 123 122 121 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 160 159 158 157 156 155 154 153 152 151 150 TP3 TPON3 VCCT GNDT TPOP3 VCCR TPIN3 TPIP3 GNDR GNDR TP1 TPON1 VCCT GNDT TPOP1 VCCR TPIN1 TPIP1 GNDR RBIAS TPIP2 TPIN2 GNDR TPOP2 VCCT GNDT TPON2 VCCR GNDR GND TEST TPIP0 TPIN0 GNDR TPOP0 VCCT GNDT TPON0 VCCR GNDR 20 19 18 17 16 15 14 13 12 Rx 21 Tx Rx 22 23 24 25 26 27 28 29 7 RJ45 Footprint Tx 11 10 8 5 6 2 1 3 4 4 3 6 5 30 31 Port 2 Port 3 6 5 4 3 2 Tx 1 Rx 32 33 34 35 36 37 38 39 8 5 6 2 1 3 4 4 3 40 1 2 6 Port 0 8 5 7 Port 1 Edge of PCB Port 0 Port 2 8 7 Tx 7 8 7 8 Rx 1 2 9 Termination resistors and common mode bypass capacitors are not shown. See "Layout Requirements" section for recommended application circuit. 1 8 1 Amphenol 2X2 Port Stacked Modular Jack Stacked RJ-45s 1 Port 3 8 1 8 Port 1 37 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Figure 21: LXT974A/975A LXT974A/975A Power and Ground Connections LXT974A/975A LXT974A/975A VCCH .01µF GNDH VCCT .01µF GNDT 22k 1% RBIAS GNDA VCCR .01µF GNDR 10µF Analog Supply Plane + Ferrite Bead Digital Supply Plane 10µF VCC +5V .01µF GND .01µF VCCMII 38 3.3V or +5V LXT974A/LXT975A LXT974A/LXT975A Application Information Figure 22: Typical Twisted-Pair Interface and Supply Filtering Output Stage with Compensating Inductor 0.1µF 1 GNDR TPIP 1:1 1 2 50 1% 3 75 TPIN 50 50 4 TPOP LXT974A/975A LXT974A/975A 200 1% 5 6 50 320 nH TPON 200 1% 50 2:1 To Twisted-Pair Network RJ45 50 1% 7 75 2 50 50 8 0.001µF/2kV VCCT 0.1µF .01µF GNDT 1. Receiver common mode bypass cap may improve BER performance in systems with noisy power supplies. 2. A single ferrite bead (rated at 400 mA) may be used to supply center tap current to all 4 ports. 39 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver Figure 23: Typical Fiber Interface V C C T +5 V 69 0.1 µF 69 GNDA 0.01µF TD F I B O P n 0.01µF TD +5 V LXT974A/975A LXT974A/975A 191 Fiber Txcvr 191 80 SD/TPn SD VCCR +5 V 130 GNDA 80 1 0.1 µF 80 To Fiber Network FIBONn GNDA FIBIN n RD FIBIP n RD 130 130 1. Refer to fiber transceiver manufacturers recommendations for termination circuitry. Suitable fiber transceivers include the HFBR-5103 HFBR-5103 and HFBR-5105 HFBR-5105. 40 LXT974A/LXT975A LXT974A/LXT975A Application Information Figure 24: Typical MII Interface TX_EN n TXD n TX_ER n TX_CLK n COLn MII Data I/F RX_DV n RX_ER n Twisted-Pair Interface RX_CLK n R X D n CRSn TRSTEn LXT974A/ LXT974A/ 975A MDIO MII Control I/F MDINT MDC MDDIS CFG0 CFG1 CFG2 BYPSCR FDE FDE_FX AUTOENA H/W Control I/F +5 V 330 Port LEDs (4 Ports) L E D n _0 330 L E D n _1 330 L E D n _2 LEDENA LEDCLK LEDDAT Serial LED Interface +3.3V or +5V VCCMII + 0.1 µF 10µF +5 V VCC GND TEST 0.1 µF 41 LXT974A/LXT975A LXT974A/LXT975A Fast Ethernet 10/100 Quad Transceiver TEST SPECIFICATIONS NOTE Tables 24 through 44 and Figures 25 through 38 represent the target specifications of the LXT974A/975A LXT974A/975A. Table 24: Absolute Maximum Ratings Parameter Sym Min Max Units VCC -0.3 6 V Ambient TOPA -15 +85 ºC Case TOPC ­ +120 ºC TST -65 +150 ºC Supply voltage Operating temperature Storage temperature CAUTION Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 25: Operating Conditions Sym Min Typ1 Max Units VCC 4.75 5.0 5.25 V VCCMII 3.125