LXT973 100BASE-TX 10BASE-T 100BASE-FX LXT973QC LXT973QE 100BASE-X 100BASE-T - Datasheet Archive

 

10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Datasheet The LXT973 is an IEEE-compliant, 2-port, Fast Ethernet PHY

 

LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Datasheet The LXT973 LXT973 is an IEEE-compliant, 2-port, Fast Ethernet PHY transceiver that directly supports both 100BASE-TX 100BASE-TX and 10BASE-T 10BASE-T applications. Each port provides a Media Independent Interface (MII) for easy attachment to 10 and 100 Mbps Media Access Controllers (MACs). The device also provides a pseudo-ECL interface per port for use with 100BASE-FX 100BASE-FX fiber networks. The LXT973 LXT973 incorporates the auto MDIX feature, allowing it to automatically switch twistedpair inputs and outputs. The LXT973 LXT973 is an ideal building block for systems that require two Ethernet ports, such as Internet Protocol (IP) Telephones, Twisted-Pair (TX)-to-Fiber (FX) converter modules, and for telecom applications, such as Telecom Central Office (TCO) and Customer Premise Equipment (CPE) devices. The LXT973 LXT973 supports full-duplex operation at both 10 and 100 Mbps. Its operating modes can be set using auto-negotiation, parallel detection, or manual control. Applications VoIP Telephone Handsets Media Converter - Fiber-to-Twisted-Pair Internet Access Devices - Cable Modem, ADSL Modem Ethernet Backplane Connections Product Features Dual-port Fast Ethernet PHY 2.5V operation 3.3V operation I/O compatibility Low power consumption; 250 mW per port typical Full 2-port MII interface with extended registers Auto MDI/MDIX switch over capability Signal Quality Error (SQE) enable/disable 100BASE-FX 100BASE-FX fiber-optic capability on both ports Integrated transmit and receive termination resistors Supports both auto-negotiation systems and legacy systems without autonegotiation capability Support for Next Page 20 MHz Register Access Configurable via MDIO port or external control pins Integrated termination resistors 100-pin Plastic Quad Flat Package (PQFP) - LXT973QC LXT973QC - Commercial (0° to 70°C ambient). - LXT973QE LXT973QE - Extended (-40° to +85°C ambient). For technical assistance on this product, please call 1-800-628-8686, or send an e-mail tosupport@mailbox.intel.com. Order Number: 249426-002 March 2002 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT973 LXT973 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2002 *Third-party brands and names are the property of their respective owners. 2 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 Contents Contents 1.0 Pin Assignments and Signal Descriptions .12 2.0 Signal Descriptions .16 3.0 Functional Description.22 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 Introduction.22 3.1.1 Comprehensive Functionality .22 Interface Descriptions.22 3.2.1 10/100 Mbps Network Interface .22 3.2.1.1 Twisted-Pair Interface .23 3.2.1.2 MDI Crossover (MDIX) .23 3.2.1.3 Fiber Interface .24 MII Operation.24 3.3.1 MII Clocks.24 3.3.2 Transmit Enable .24 3.3.3 Receive Data Valid.24 3.3.4 Carrier Sense .25 3.3.5 Error Signals.25 3.3.6 Collision.25 3.3.7 Loopback.25 3.3.7.1 Operational Loopback .25 3.3.7.2 Test Loopback .25 3.3.8 Configuration Management Interface .26 3.3.8.1 MII Management Interface .26 3.3.8.2 MII Addressing .27 3.3.8.3 Hardware Control Interface .28 Operating Requirements .28 3.4.1 Power Requirements.28 3.4.2 Clock Requirements .28 3.4.2.1 Reference Clock / External Oscillator.28 3.4.2.2 MDIO Clock .29 Initialization.29 3.5.1 MDIO Control Mode .29 3.5.2 Hardware Control Mode .29 3.5.3 Power-Down Mode.29 3.5.3.1 Hardware Power-Down .30 3.5.3.2 Software Power-Down.30 3.5.4 Reset .30 3.5.5 Hardware Configuration Settings .31 Link Establishment .31 3.6.1 Auto-Negotiation.31 3.6.1.1 Base Page Exchange.32 3.6.1.2 Next Page Exchange.32 3.6.1.3 Controlling Auto-Negotiation .32 3.6.1.4 Link Criteria .32 3.6.1.5 Parallel Detection .32 Network Media/Protocol Support.33 3.7.1 10/100 Mbps Network Interface .33 3 Contents 3.8 3.9 3.10 4.0 3.7.2 Twisted-Pair Interface . 33 3.7.3 Fiber Interface . 34 3.7.4 Fault Detection and Reporting . 34 3.7.5 Remote Fault. 34 3.7.6 Far End Fault . 34 100 Mbps Operation. 35 3.8.1 100BASE-X 100BASE-X Network Operations . 35 3.8.2 100BASE-X 100BASE-X Protocol Sublayer Operations . 36 3.8.3 PCS Sublayer. 36 3.8.3.1 Preamble Handling. 36 3.8.3.2 Dribble Bits . 36 3.8.4 PMA Sublayer . 37 3.8.4.1 Link Failure Override . 37 3.8.4.2 Carrier Sense . 37 3.8.4.3 Twisted-Pair PMD Sublayer . 37 3.8.4.4 Scrambler/Descrambler. 37 3.8.4.5 Baseline Wander Correction . 37 3.8.5 Fiber PMD Sublayer . 38 3.8.5.1 Far End Fault Indications . 38 10 Mbps Operation. 38 3.9.1 Polarity Correction. 38 3.9.2 Dribble Bits. 39 3.9.3 Link Test. 39 3.9.4 Link Failure. 39 3.9.5 Jabber . 39 Monitoring Operations. 39 3.10.1 Monitoring Auto-Negotiation. 39 3.10.2 Per-Port LED Driver Functions. 39 Application Information . 41 4.1 4.2 4.3 4.4 4.5 Design Recommendations . 41 4.1.1 General Design Guidelines . 41 4.1.2 Power Supply Filtering . 41 4.1.3 Power and Ground Plane Layout Considerations . 42 4.1.3.1 Chassis Ground. 42 4.1.4 MII Terminations . 42 4.1.5 The Fiber Interface. 42 4.1.6 Twisted-Pair Interface . 43 4.1.6.1 Magnetics Information . 43 Typical Application Circuits . 44 Initialization . 47 MDIO Control Mode . 47 Manual Control Mode. 47 5.0 Configuration . 49 6.0 Auto Negotiation . 51 7.0 Auto MDI/MDIX . 52 8.0 100 Mbps Operation . 53 8.1 4 Displaying Symbol Errors. 53 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 Contents 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 Scrambler Seeding.54 Scrambler Bypass .54 100BASE-T 100BASE-T Link Failure Criteria and Override .54 Baseline Wander Correction .54 Programmable Tx Slew Rate .54 9.0 Fiber Interface.56 10.0 10 Mbps Operation .57 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 11.0 Link Test.57 10Base-T Link Failure Criteria and Override.57 SQE (Heartbeat).57 Jabber .57 Polarity Correction.57 Dribble Bits .58 Transmit Polarity Control.58 PHY Address.58 Clock Generation.59 11.1 External Oscillator .59 12.0 Register Definitions.61 13.0 Magnetics Information .71 14.0 Test Specifications .72 15.0 Timing Diagrams .77 16.0 Mechanical Specifications.87 A Product Ordering Information .88 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 Block Diagram .11 LXT973 LXT973 Pin Assignments .12 LXT973 LXT973 Interfaces .23 Loopback Paths .26 Management Interface Read Frame Structure .27 Management Interface Write Frame Structure .27 Port Address Scheme .28 Auto-Negotiation Operation .33 100BASE-X 100BASE-X Frame Format .35 Protocol Sublayers .36 Typical LED Implementation .40 Power and Ground Supply Connections .44 Typical Twisted-Pair Interface .45 Typical Fiber Interface .46 Typical MII Interface .46 LXT973 LXT973 Initialization Sequence.47 100BASE-TX 100BASE-TX Frame Format .53 100BASE-TX 100BASE-TX Data Path .53 100BASE-TX 100BASE-TX Reception with no Errors.54 100BASE-TX 100BASE-TX Reception with Invalid Symbol .55 5 Contents 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 6 100BASE-TX 100BASE-TX Transmission with no Errors . 55 100BASE-TX 100BASE-TX Transmission with Collision . 55 MII 10BASE-T 10BASE-T DTE Mode Auto-Negotiation . 59 100BASE-T 100BASE-T DTE Mode Auto-Negotiation . 59 Link Down Clock Transition. 60 PHY Identifier Bit Mapping . 64 100BASE-TX 100BASE-TX Transmit Timing - 4B Mode . 77 100BASE-TX 100BASE-TX Receive Timing - 4B Mode . 78 100BASE-FX 100BASE-FX Transmit Timing . 79 100BASE-FX 100BASE-FX Receive Timing . 80 10BASE-T 10BASE-T Transmit Timing (Parallel Mode) . 81 10BASE-T 10BASE-T Receive Timing (Parallel Mode) . 82 10BASE-T 10BASE-T SQE (Heartbeat) Timing. 83 10BASE-T 10BASE-T Jab and Unjab Timing . 83 Fast Link Pulse Timing. 84 FLP Burst Timing . 84 MDIO Input Timing . 85 MDIO Output Timing . 85 Power-Up Timing . 86 RESET Pulse Width and Recovery Timing . 86 LXT973 LXT973 Mechanical Specifications . 87 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 Contents Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 PQFP Pin List .13 LXT973 LXT973 Port 0 Signal Descriptions .16 LXT973 LXT973 Port 1 Signal Descriptions .17 LXT973 LXT973 Network Interface Signal Descriptions.18 LXT973 LXT973 Global Control & Configuration Signal Descriptions .19 LXT973 LXT973 Power Supply Signal Descriptions.20 LXT973 LXT973 Per Port LED and Configuration Signal Descriptions .20 Carrier Sense, Loopback, and Collision Conditions .26 Configuration Settings (Hardware Control Interface) .31 LED Configurations .40 Magnetics Requirements.43 Mode Control Settings.48 Configuration Settings (Hardware Control Interface) .49 Next Page Code Word Definitions.51 Common Register Set .61 Register Bit Descriptions .61 Control Register (Address 0).62 Status Register (Address 1) .63 PHY Identification Register 1 (Address 2).64 PHY Identification Register 2 (Address 3).64 Auto-Negotiation Advertisement Register (Address 4).65 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) .66 Auto-Negotiation Expansion Register (Address 6).67 Auto-Negotiation Next Page Transmit Register (Address 7).67 Auto-Negotiation Link Partner Next Page Ability Register (Address 8).68 Port Configuration Register (Address 16) .68 Special Function Register (Address 27).70 Magnetics Requirements.71 Absolute Maximum Ratings.72 Operating Conditions.72 Digital Input/Output Characteristics2.73 Digital Input/Output Characteristics - MII Pins.73 REFCLK Characteristics .74 LED Pin Characteristics .74 100BASE-TX 100BASE-TX Transceiver Characteristics .74 10BASE-T 10BASE-T Transceiver Characteristics.75 100BASE-FX 100BASE-FX Transceiver Characteristics .75 10BASE-T 10BASE-T Link Integrity Timing Characteristics .75 Twisted-Pair Pins .76 MII - 100BASE-TX 100BASE-TX Transmit Timing Parameters - 4B Mode.77 MII - 100BASE-TX 100BASE-TX Receive Timing Parameters - 4B Mode.78 100BASE-FX 100BASE-FX Transmit Timing Parameters.79 100BASE-FX 100BASE-FX Receive Timing Parameters.80 MII - 10BASE-T 10BASE-T Transmit Timing Parameters (Parallel Mode) .81 MII - 10BASE-T 10BASE-T Receive Timing Parameters (Parallel Mode) .82 10BASE-T 10BASE-T SQE (Heartbeat) Timing Parameters .83 10BASE-T 10BASE-T Jab and Unjab Timing Parameters.83 Fast Link Pulse Timing Parameters .84 MDIO Timing Parameters.85 7 Contents 50 51 8 Power-Up Timing Parameters. 86 RESET Pulse Width and Recovery Timing Parameters . 86 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 Contents Revision History Date Revision Page Description 11 37 Section 3.10.1, "Monitoring Auto-Negotiation": Removed paragraphs 3 and 4, and Figure 11. 53 Under Section 8.1, "Displaying Symbol Errors": Removed Table 16: 4B/5B Coding. 61 Section 12.0, "Register Definitions" Removed "multiple 11-bit registers, with" from first sentence. 64 Table 20 "PHY Identification Register 2 (Address 3)": Changed default for Register bits 3.9:4 from "001110" to "100001". 72 Table 29 "Absolute Maximum Ratings" Modified Power Supply: added VCCA, VCC, VCCPECL, VCCIO information. Added three table notes. 73 Table 40 "Digital Input/Output Characteristics" Modified table note 2. 73 Table 32 "Digital Input/Output Characteristics - MII Pins" Removed "Driver Output Impedance." 74 Table 34 "LED Pin Characteristics" Added MAX value to Output High Current. 74 Table 35 "100BASE-TX 100BASE-TX Transceiver Characteristics" Added Typ values. 75 Table 36 "10BASE-T 10BASE-T Transceiver Characteristics" Added/replaced Typ values. Removed "Receiver Input Impedance." 75 Table 37 "100BASE-FX 100BASE-FX Transceiver Characteristics" Added Typ values 75 Table 38 "10BASE-T 10BASE-T Link Integrity Timing Characteristics" Added Typ value for Link Pulse Width 76 002 Under Section 3.8.4, "PMA Sublayer": Removed Table 10: 4B/5B Coding. 39 March 1, 2001 Figure 1 "LXT973 LXT973 Block Diagram": Added note to diagram. Added Table 39 "Twisted-Pair Pins". 77-85 Modified Table 40 on page 77 through Table 49 on page 85. 86 Added Figure 39 "Power-Up Timing" and Table 50 "Power-Up Timing Parameters". 86 Added Figure 40 "RESET Pulse Width and Recovery Timing" and Table 51 "RESET Pulse Width and Recovery Timing Parameters" 88 Section A, "Product Ordering Information": Added product ordering information table and diagram. 001 Initial Release (Preliminary datasheet) April 2001 0.2 Advance Datasheet (See Specification Update for Detail) February 2001 0.1 Advance Datasheet May 2001 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 9 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 1. LXT973 LXT973 Block Diagram 2 Port Global Functions RESET Management / Mode Select Logic & LED Drivers PWRDN MDIO Clock Generator REFCLK MDC Register Set Manchester Encoder TX PCS TXDn TXENn TXERn TXCLKn Parallel/Serial Converter Scrambler & Encoder Auto Negotiation Mgmt Counters 10 100 Pulse Shaper TP Driver ECL Driver CIM + TP/ Fiber Out + - Media Select Clock Generator RXDn RXDVn RXERn RXCLKn COLn CRSn Port LED Drivers + Adaptive EQ with BL Wander Cancellation 100TX 100TX + RX PCS LED Serial to Parallel Converter Carrier Sense Data Valid Error Detect DPBN_1 DPBP_1 Fiber_TPn Register Set 3 DPAN_0 DPAP_0 10 100 Manchester Decoder 100FX 100FX Slicer - Decoder & Descrambler + TP/ Fiber In DPBN_0 DPBP_0 DPAN_1 DPAP_1 10BT Per-Port Functions PORT 0 - PORT 1 Please see Table 4, "LXT973 LXT973 Network Interface Signal Descriptions" on page 18 and Table 5, "LXT973 LXT973 Global Control & Configuration Signal Descriptions" on page 19 for complete network interface signal Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 11 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1.0 Pin Assignments and Signal Descriptions 100 . 99 . 98 . 97 . 96 . 95 . 94 . 93 . 92 . 91 . 90 . 89 . 88 . 87 . 86 . 85 . 84 . 83 . 82 . 81 . TXD1_1 TXD1_0 TXEN1 TXCLK1 VCCIO GNDIO TXE R1 RXER1 RXCLK1 VC CD GNDD RXDV 1 RXD1_ 0 RXD1_ 1 RXD1_ 2 RXD1_ 3 VCCIO GNDIO LED1_ 1 LED1_ 2 Figure 2. LXT973 LXT973 Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Part # Lot # FPO # LXT973QE LXT973QE XX XXXXXX Rev # XXXXXXXX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LED1_3 TXSLEW1 TXSLEW0 GNDPECL SD0 SD1 VCCPECL VCCR DPAN_1 DPAP_1 GNDT GNDR DPBN_1 DPBP_1 VCCT VCCT DPBN_0 DPBP_0 GNDR GNDT DPAN_0 DPAP_0 VCCR TEST_1 TEST_0 ADDR1 ADDR2 ADDR3 ADDR4 LED0_3 RXD0_1 RXD0_0 RXDV 0 RXCLK0 RXER0 TXER0 TXCLK0 TXEN0 TXD0_0 VCCD GNDD TXD0_1 TXD0_2 TXD0_3 COL0 CRS0 VCCIO GND IO LED0_1 LED0_2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TXD1_2 TXD1_3 COL1 CRS1 AUTO_NEG1 AUTO_NEG0 SD_2P5V/SPEED1 SD_2P5V/SPEED0 DUPLEX1 DUPLEX0 LED_CGF0 LED_CGF1 RESET SGND REFCLK GNDD FIBER_TP1 FIBER_TP0 MDDIS1 MDDIS0 PWRDWN1 MDC1 MDIO1 PWRDWN0 MDIO0 MDC0 VCCIO GNDIO RXD0_3 RXD0_2 Package Topside Markings Marking Definition Part # LXT973 LXT973 is the unique identifier for this product family. Rev # Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping information.) Lot # Identifies the batch. FPO # Identifies the Finish Process Order. 12 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 1. LXT973 LXT973 PQFP Pin List Pin Signal Names Type1 Reference for Full Description 1 TXD1_2 I Table 3 on page 17 2 TXD1_3 3 COL1 I Table 3 on page 17 O, TS Table 3 on page 17 4 CRS1 O, TS Table 3 on page 17 5 AUTO_NEG1 I Table 7 on page 20 6 AUTO_NEG0 I Table 7 on page 20 7 SD_2P5V/SPEED1 I Table 7 on page 20 8 SD_2P5V/SPEED0 I Table 7 on page 20 9 DUPLEX1 I Table 7 on page 20 10 DUPLEX0 I Table 7 on page 20 11 LED_CGF0 I Table 5 on page 19 12 LED_CGF1 I Table 5 on page 19 13 RESET I Table 5 on page 19 14 SGND ­ Table 6 on page 20 15 REFCLK I Table 5 on page 19 16 GNDD ­ Table 6 on page 20 17 FIBER_TP1 I Table 7 on page 20 18 FIBER_TP0 I Table 7 on page 20 19 MDDIS1 I Table 3 on page 17 20 MDDIS0 I Table 2 on page 16 21 PWRDWN1 I Table 7 on page 20 22 MDC1 I Table 3 on page 17 23 MDIO1 I/O Table 3 on page 17 24 PWRDWN0 I Table 7 on page 20 25 MDIO0 I/O Table 2 on page 16 26 MDC0 I Table 2 on page 16 27 VCCIO ­ Table 6 on page 20 28 GNDIO ­ Table 6 on page 20 29 RXD0_3 O, TS Table 2 on page 16 30 RXD0_2 O, TS Table 2 on page 16 31 RXD0_1 O, TS Table 2 on page 16 32 RXD0_0 O, TS Table 2 on page 16 33 RXDV0 O, TS Table 2 on page 16 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-down. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 13 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 1. LXT973 LXT973 PQFP Pin List (Continued) Pin Signal Names Type1 Reference for Full Description 34 RXCLK0 O, TS Table 2 on page 16 35 RXER0 O, TS Table 2 on page 16 36 TXER0 I Table 2 on page 16 37 TXCLK0 O, TS Table 2 on page 16 38 TXEN0 I Table 2 on page 16 39 TXD0_0 I Table 2 on page 16 40 VCCD ­ Table 6 on page 20 41 GNDD ­ Table 6 on page 20 42 TXD0_1 I Table 2 on page 16 43 TXD0_2 I Table 2 on page 16 44 TXD0_3 I Table 2 on page 16 45 COL0 O, TS Table 2 on page 16 46 CRS0 O, TS Table 2 on page 16 47 VCCIO ­ Table 6 on page 20 48 GNDIO ­ Table 6 on page 20 49 LED0_1 O, OD Table 7 on page 20 50 LED0_2 O, OD Table 7 on page 20 51 LED0_3 O, OD Table 7 on page 20 52 ADDR4 I Table 5 on page 19 53 ADDR3 I Table 5 on page 19 54 ADDR2 I Table 5 on page 19 55 ADDR1 I Table 5 on page 19 56 TEST_0 I Table 5 on page 19 57 TEST_1 I Table 5 on page 19 58 VCCR ­ Table 6 on page 20 59 DPAP_0 AI/AO, SL Table 4 on page 18 60 DPAN_0 AI/AO, SL Table 4 on page 18 61 GNDT ­ Table 6 on page 20 62 GNDR ­ Table 6 on page 20 63 DPBP_0 AI/AO, SL Table 4 on page 18 64 DPBN_0 AI/AO, SL Table 4 on page 18 65 VCCT ­ Table 6 on page 20 66 VCCT ­ Table 6 on page 20 67 DPBP_1 AI/AO, SL Table 4 on page 18 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-down. 14 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 1. LXT973 LXT973 PQFP Pin List (Continued) Pin Signal Names 68 DPBN_1 69 70 71 Type1 Reference for Full Description AI/AO, SL Table 4 on page 18 GNDR ­ Table 6 on page 20 GNDT ­ Table 6 on page 20 DPAP_1 AI/AO, SL Table 4 on page 18 72 DPAN_1 AI/AO, SL Table 4 on page 18 73 VCCR ­ Table 6 on page 20 74 VCCPECL ­ Table 6 on page 20 75 SD1 I Table 4 on page 18 76 SD0 I Table 4 on page 18 77 GNDPECL ­ Table 6 on page 20 78 TxSLEW0 I Table 5 on page 19 79 TxSLEW1 I Table 5 on page 19 80 LED1_3 O. OD Table 7 on page 20 81 LED1_2 O, OD Table 7 on page 20 82 LED1_1 O, OD Table 7 on page 20 83 GNDIO ­ Table 6 on page 20 84 VCCIO ­ Table 6 on page 20 85 RXD1_3 O, TS Table 3 on page 17 86 RXD1_2 O, TS Table 3 on page 17 87 RXD1_1 O, TS Table 3 on page 17 88 RXD1_0 O, TS Table 3 on page 17 89 RXDV1 O, TS Table 3 on page 17 90 GNDD ­ Table 6 on page 20 91 VCCD ­ Table 3 on page 17 92 RXCLK1 O, TS Table 3 on page 17 93 RXER1 O, TS Table 3 on page 17 94 TXER1 I Table 6 on page 20 95 GNDIO ­ Table 6 on page 20 96 VCCIO ­ Table 3 on page 17 97 TXCLK1 O, TS Table 3 on page 17 98 TXEN1 I Table 3 on page 17 99 TXD1_0 I Table 3 on page 17 100 TXD1_1 I Table 3 on page 17 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-down. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 15 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 2.0 Table 2. Signal Descriptions LXT973 LXT973 Port 0 Signal Descriptions Pin # Signal Names 44 TXD0_2 42 TXD0_1 39 TXEN0 I Transmit Data. TXD0_n is a bundle of parallel data signals driven by the MAC controller, which TXD0 transition synchronously with respect to the TXCLK0. TXD0 is the least significant bit. TXD0 are monitored in normal mode only. I Transmit Enable. The MAC asserts TXEN0 when it drives data on TXD0n. This signal must be synchronized to TXCLK0. Transmit Error. TXER0 is a 100 Mbps only signal. The MAC asserts this input when an error has occurred in the transmit data stream. When operating at 100 Mbps, the LXT973 LXT973 responds by sending "H symbols" on the line. In Symbol mode, this pin acts as TXD0_4. TXD0_0 38 Signal Description TXD0_3 43 Type1 36 TXER0 I 37 TXCLK0 O, TS Transmit Clock. TXCLK0 is sourced by the LXT973 LXT973 in both 10 Mbps and 100 Mbps modes. 2.5 MHz for 10 Mbps operation 25 MHz for 100 Mbps operation. 29 RXD0_3 30 RXD0_2 31 RXD0_1 O, TS Receive Data.The LXT973 LXT973 drives received data on these outputs, synchronous to RXCLK0. 32 RXD0_0 33 RXDV0 O, TS Receive Data Valid. The LXT973 LXT973 asserts this signal when it drives valid data on RXD0n. This output is synchronous to RXCLK0. 35 RXER0 O, TS Receive Error. The LXT973 LXT973 asserts this output when it receives invalid symbols from the network. RXER0 is synchronous to RXCLK0. In Symbol mode, this pin acts as RXD0_4. 34 RXCLK0 O, TS Receive Clock. RXCLK0 is sourced by the LXT973 LXT973 in both 10 Mbps and 100 Mbps modes. 2.5 MHz for 10 Mbps operation 25 MHz for 100 Mbps operation. 45 COL0 O, TS Collision Detected. The LXT973 LXT973 asserts this output when a collision is detected. This output remains High for the duration of the collision. COL0 is asynchronous and is inactive during full-duplex operation. 46 CRS0 O, TS Carrier Sense. During half-duplex operation, the LXT973 LXT973 asserts this output when either the transmit or receive medium is non-idle. During full-duplex operation, CRS0 is asserted only when receive medium is non-idle. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-down. 16 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 2. LXT973 LXT973 Port 0 Signal Descriptions (Continued) Pin # Signal Names Type1 Signal Description Management Disable. When MDDIS0 is tied High, the MDIO port is completely disabled and the Hardware Control Interface pins set their respective bits at power-up and reset. When MDDIS0 is pulled Low at power-up or reset via the internal pulldown resistor or by tying it to ground, the Hardware Control Interface Pins control only the initial or "default" values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. 20 MDDIS0 I 26 MDC0 I Management Data Clock. Clock for MDIO0 serial channel. Maximum frequency is 20 MHz. 25 MDIO0 I/O Management Data Input/Output. Bi-directional serial data channel for PHY/STA communication. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-down. Table 3. LXT973 LXT973 Port 1 Signal Descriptions Pin # Signal Names Type1 Signal Description I Transmit Data. TXD1_n is a bundle of parallel data signals driven by the MAC controller. TXD1 transition synchronously with respect to the TXCLK1. TXD1 is the least significant bit. In normal mode, only TXD1 are monitored. 2 TXD1_3 1 TXD1_2 100 TXD1_1 99 TXD1_0 98 TXEN1 I Transmit Enable. The MAC asserts TXEN1 when it drives data on TXD0n. This signal must be synchronized to TXCLK1. 94 TXER1 I Transmit Error. (TXER1 is a 100 Mbps only signal.) The MAC asserts this input when an error has occurred in the transmit data stream. When operating at 100 Mbps, the LXT973 LXT973 responds by sending "H Symbols" on the line. In Symbol mode, this pin acts as TXD1_4. 97 TXCLK1 O, TS Transmit Clock. TXCLK1 is sourced by the LXT973 LXT973 in both 10 Mbps and 100 Mbps modes. 2.5 MHz for 10 Mbps operation 25 MHz for 100 Mbps operation. 85 RXD1_3 86 RXD1_2 87 RXD1_1 O, TS Receive Data.The LXT973 LXT973 drives received data on these outputs, synchronous to RXCLK1. 88 RXD1_0 89 RXDV1 O, TS Receive Data Valid. The LXT973 LXT973 asserts this signal when it drives valid data on RXD0n. This output is synchronous to RXCLK1. 93 RXER1 O, TS Receive Error. The LXT973 LXT973 asserts this output when it receives invalid symbols from the network. RXER1 is synchronous to RXCLK1. In Symbol mode, this pin acts as RXD1_4. 92 RXCLK1 O, TS Receive Clock. RXCLK1 is sourced by the LXT973 LXT973 in both 10 Mbps and 100 Mbps modes. 2.5 MHz for 10 Mbps operation 25 MHz for 100 Mbps operation. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 17 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 3. LXT973 LXT973 Port 1 Signal Descriptions (Continued) Signal Names Type1 Signal Description 3 COL1 O, TS Collision Detected. The LXT973 LXT973 asserts this output when a collision is detected. This output remains High for the duration of the collision. COL is asynchronous and is inactive during full-duplex operation. 4 CRS1 O, TS Carrier Sense. During half-duplex operation, the LXT973 LXT973 asserts this output when either the transmit or receive medium is non-idle. During full-duplex operation, CRS1 is asserted only when receive medium is non-idle. Pin # Management Disable. When MDDIS is tied High, the MDIO port is completely disabled and the Hardware Control Interface pins set their respective bits at power-up and reset. 19 MDDIS1 I 22 MDC1 I When MDDIS is pulled Low at power-up or reset via the internal pulldown resistor or by tieing it to ground, the Hardware Control Interface Pins control only the initial or "default" values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. Management Data Clock. Clock for MDIO1 serial channel. Maximum frequency is 20 MHz. (Note: 20 MHz value to be verified prior to final production release of product.) 23 MDIO1 I/O Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down Table 4. LXT973 LXT973 Network Interface Signal Descriptions Pin # Signal Names TP Op Fiber Op Port Pair Type 59 DPAP_0 TX+ RX+ 0 A 60 DPAN_0 TX- RX- 0 A Type1 AI/AO, SL Signal Description Twisted-Pair/Fiber Pair A, Positive & Negative - Port 0. Differential pair produces or receives IEEE 802.3-compliant pulses for either 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T. Also acts as receiver in Fiber mode. 63 DPBP_0 RX+ TX+ 0 B 64 DPBN_0 RX- TX- 0 B AI/AO, SL Twisted-Pair/Fiber Pair B, Positive & Negative - Port 0. Differential pair produces or receives IEEE 802.3-compliant pulses for either 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T. Also acts as transmitter in Fiber mode. 76 SD0 - - - - I Signal Detect. This signal is used for signal quality indication in Fiber mode. In twistedpair mode, this pin should be tied Low. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down 18 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 4. LXT973 LXT973 Network Interface Signal Descriptions (Continued) Pin # Signal Names TP Op 67 DPBP_1 TX+ 68 DPBN_1 TX- Fiber Op Port 1 B 1 TXTX+ Pair Type B Type1 Signal Description AI/AO, SL Twisted-Pair/Fiber Pair B, Positive & Negative - Port 1. Differential pair produces or receives IEEE 802.3-compliant pulses for either 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T. Also acts as transmitter in Fiber mode. 71 DPAP_1 RX+ RX- 1 A 72 DPAN_1 RX- RX+ 1 A AI/AO, SL Twisted-Pair/Fiber Pair A, Positive & Negative - Port 1. Differential pair produces or receives IEEE 802.3-compliant pulses for either 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T. Also acts as receiver in Fiber mode. 75 SD1 - - - - I Signal Detect. This signal is used for signal quality indication in Fiber mode. In twistedpair mode, this pin should be tied Low. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down Table 5. LXT973 LXT973 Global Control & Configuration Signal Descriptions Pin # Signal Names 78 TxSLEW0 79 TxSLEW1 13 RESET 52 ADDR3 54 ADDR2 55 TEST_0 57 TEST_1 15 REFCLK Tx Output Slew Controls 0 & 1. These pins select the TX output slew rate (rise and fall time) for both cores in the LXT973 LXT973 device. The various options are defined in Register bits 27.11:10. The TxSLEW pins set the power-on value of these register bits. I Reset. This active Low input is OR'd with Control Register bit 0.15. I Address . Sets device Port 0 PHY address. Note that ADDR0 is set internally so that Port 1 is always "1" address higher than Port 0. I Test Pins. Tie Low for normal operation. I Master Clock Input. A 25 MHz, 50 ppm clock is input here to act as the master clock. Full clock requirements are detailed in the Clock Requirements section of the Functional Description. See Section 3.4.2, "Clock Requirements" on page 28. ADDR1 56 I Signal Description ADDR4 53 Type1 LED Configuration 0 & 1. These pins are used to select one of four LED modes. The decode or each mode is shown below: LED_CFG0 LED_CFG1 I 0 0 Speed Link Duplex 0 Speed Link/Activity Duplex/Collision 1 Link Receive Transmit 1 12 LEDn_1 0 LED_CFG0 LED_CFG1 1 11 LEDn_2 LEDn_3 1 Speed Link/MII Isolate Duplex/Collision 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 19 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 6. LXT973 LXT973 Power Supply Signal Descriptions Pin # Signal Names 40, 91 VCCD Type1 Signal Description _ Digital Power Supply - Core. +2.5V supply for core digital circuits. 27, 47, 84, 96 VCCIO _ Digital Power Supply - I/O Ring. +2.5/3.3V supply for digital I/O circuits. The digital input circuits running off this rail, having a TTLlevel threshold and over-voltage protection, may be interfaced with 3.3/5.0V when the I/O supply is 3.3V, and 2.5/3.3/5.0V when the I/O supply is 2.5V. 74 VCCPECL _ Digital Power Supply - PECL Signal Detect Inputs. +2.5/3.3V supply for PECL Signal Detect input circuits. If Fiber Mode is not used, tie these pins to GNDPECL to save power. 58, 73 VCCR _ Analog Power Supply - Receive. +2.5V supply for all analog receive circuits. 65, 66 VCCT _ Analog Power Supply - Transmit. +2.5V supply for all analog transmit circuits. 16, 41, 90, GNDD _ Digital Ground. Ground return for core digital supplies (VCCD). All ground pins can be tied together using a single ground plane. 28, 48, 83, 95 GNDIO _ Digital GND - I/O Ring. Ground return for digital I/O circuits (VCCIO). 77 GNDPECL _ Digital GND - PECL Signal Detect Inputs. Ground return for PECL Signal Detect input circuits. 69, 62 GNDR _ Analog Ground - Receive. Ground return for receive analog supply. All ground pins can be tied together using a single ground plane. 61, 70 GNDT _ Analog Ground - Transmit. Ground return for transmit analog supply. All ground pins can be tied together using a single ground plane. 14 SGND _ Substrate Ground. Ground for chip substrate. All ground pins can be tied together using a single ground plane. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down Table 7. LXT973 LXT973 Per Port LED and Configuration Signal Descriptions Pin # Signal Names Type1 Signal Description OD, TS, SL, IP Port 0 LED Drivers 1-3. These pins drive LED indicators for Port 0. Each LED can display one of several available status conditions as selected by the LED Configuration Register. OD, TS, SL, IP Port 1 LED Drivers 1-3. These pins drive LED indicators for Port 1. Each LED can display one of several available status conditions as selected by the LED Configuration Register. 49 LED0_1 50 LED0_2 51 LED0_3 82 LED1_1 81 LED1_2 80 LED1_3 6 AUTO_NEG0 I 5 AUTO_NEG1 I Auto Negotiation Enable. When this pin is High, auto-negotiation is enabled on the relevant port. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down 20 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 7. LXT973 LXT973 Per Port LED and Configuration Signal Descriptions (Continued) Signal Names Type1 Signal Description 8 SD_2P5V/SPEED0 I SD_2P5V. In fiber mode, these pins select between a 2.5V or 3.3V fiber transceiver. High is for 2.5V and low is for 3.3V. 7 SD_2P5V/SPEED1 I Speed. Set the default speed of the port in Hardware mode. High is 100 Mbps and Low is 10 Mbps. 10 DUPLEX0 I 9 DUPLEX1 I Duplex. Sets the duplex setting of the port in Hardware mode. High is full-duplex and Low is half-duplex. 18 FIBER_TP0 I 17 FIBER_TP1 I 24 PWRDWN0 21 PWRDWN1 Pin # I Fiber/Twisted-Pair. Sets the operating state of the port in Hardware mode. High is twisted-pair and Low is fiber. Power-Down. When set High, this pin puts the relevant PHY into power-down mode. 1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output, IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 21 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.0 Functional Description 3.1 Introduction The LXT973 LXT973 is an IEEE-compliant, dual-port, Fast Ethernet PHY transceiver that directly supports both 100BASE-TX 100BASE-TX and 10BASE-T 10BASE-T applications. The device incorporates full Media Independent Interface (MII), enabling each individual network port to connect with 10/100 Mbps MACs. Each port directly drives either a 100BASE-TX 100BASE-TX line or a 10BASE-T 10BASE-T line (up to 160 meters). The LXT973 LXT973 also supports 100BASE-FX 100BASE-FX operation via a Pseudo-ECL (PECL) interface. The device uses a 100-pin QFP package. 3.1.1 Comprehensive Functionality The LXT973 LXT973 performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X 100BASE-X specification. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX 100BASE-TX connections. On power-up, the LXT973 LXT973 reads its configuration inputs to check for forced operation settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the link partner supports auto-negotiation, the LXT973 LXT973 auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT973 LXT973 automatically detects (parallel detection) the presence of either link pulses (10 Mbps PHY) or IDLE symbols (100 Mbps PHY) and sets its operating conditions accordingly. When parallel detection is used to establish link, the resulting link is at half-duplex. The LXT973 LXT973 provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps. 3.2 Interface Descriptions 3.2.1 10/100 Mbps Network Interface The LXT973 LXT973 supports both 10BASE-T 10BASE-T and 100BASE-TX 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX 100BASE-FX). Each network interface port consists of four external pins (two differential signal pairs). The pins are shared between twisted-pair and fiber. The LXT973 LXT973 output drivers generate either 100BASE-TX 100BASE-TX, 10BASE-T 10BASE-T, or 100BASE-FX 100BASE-FX output. When not transmitting data, the device generates IEEE 802.3-compliant link pulses or IDLE code. Input signals are decoded either as a 100BASE-TX 100BASE-TX, 100BASE-FX 100BASE-FX, or 10BASE-T 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. Polarity is determined by the MDI crossover function. 22 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 3. LXT973 LXT973 Interfaces TXENn TXDn TXERn DATA Interface TXCLKn DPAP/N_0 RXDn DPBP/N_0 DPBP/N_1 RXDVn DPAP/N_1 RXCLKn Twisted-Pair Network Interface RXERn CRSn COLn MDIO Management Interface MDIOn MDCn MDDISn Direct Drive LEDn_1 Port LED's LEDn_2 LEDn_3 Address / Control VCCIO Fiber_TPn ADDR VCCD +3.3V OR +2.5V +2.5V GNDD .01uF 3.2.1.1 Twisted-Pair Interface The LXT973 LXT973 supports either 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T connections over 100, Category 5, Unshielded Twisted-Pair (UTP). Only a transformer, RJ-45 RJ-45, and bypass capacitors are required to complete this interface. Using Intel's patented waveshaping technology, the transmitter shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings allow the designer to match the output waveform to the magnetic characteristics. Both transmit and receive terminations are built into the LXT973 LXT973. Therefore, no external components are required between the LXT973 LXT973 and the external transformer. The transmitter uses a transformer with a center tap to help reduce power consumption. When operating at 100 Mbps, MLT3 symbols are continuously transmitted and received. When not transmitting data, the LXT973 LXT973 generates "IDLE" symbols. During 10 Mbps operation, LXT973 LXT973 encoded data is exchanged. When no data is exchanged, the line transmits normal link pulses to maintain link. 3.2.1.2 MDI Crossover (MDIX) The LXT973 LXT973 crossover function, which is compliant to the IEEE 802.3, clause 23 standard, connects the transmit output of the device to the far-end receiver in a link segment. This function can be configured via Register bits 27.9:8. Please refer to Section 7.0, "Auto MDI/MDIX" on page 52. Default mode is auto-MDIX enabled. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 23 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.2.1.3 Fiber Interface The LXT973 LXT973 provides a PECL interface that complies with the ANSI X3.166 specification. This interface is suitable for driving a fiber-optic coupler (see Figure 14 on page 46). Fiber ports cannot be enabled via auto-negotiation and must be enabled via the Global Hardware Control Interface pins or MDIO registers. Using external circuitry, the LXT973 LXT973 can interface the fiber transceiver with 2.5V or 3.3V supply voltages. Fiber mode per port may be selected using Register bit 16.0. Please refer to Table 4 on page 18 for correct pin assignments. 3.3 MII Operation The LXT973 LXT973 device implements the Media Independent Interface (MII) as defined in the IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT973 LXT973 (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. Nine signals are used to pass received data to the MAC: RXD, RXCLK, RXDV, RXER, COL and CRS. Seven signals are used to transmit data from the MAC: TXD, TXCLK, TXEN, and TXER. The LXT973 LXT973 supplies both clock signals as well as separate outputs for carrier sense and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles. 3.3.1 MII Clocks The LXT973 LXT973 is the master clock source for data transmission and supplies both MII clocks (RXCLK and TXCLK). It automatically sets the clock speeds to match link conditions. When the link is operating at 100 Mbps, the clocks are set to 25 MHz. When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz. The transmit data and control signals must always be synchronized to TXCLK by the MAC. The LXT973 LXT973 samples these signals on the rising edge of TXCLK. 3.3.2 Transmit Enable The MAC must assert TXEN at the same time as the first nibble of preamble, and de-assert TXEN after the last bit of the packet. 3.3.3 Receive Data Valid The LXT973 LXT973 asserts RXDV when it receives a valid packet. Timing changes depend on line operating speed: · For 100BASE-TX 100BASE-TX links, RXDV is asserted from the first nibble of preamble to the last nibble of the data packet. · For 10BASE-T 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the Start-of-Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet. 24 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.3.4 Carrier Sense Carrier Sense (CRS) is an asynchronous output. CRS is generated when a packet is received from the line regardless of duplex mode, and for a transmission to the line in half-duplex mode. Table 8 on page 26 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. Carrier sense is not generated when a packet is transmitted in full-duplex mode. For 100BASE-TX 100BASE-TX and 100BASE-FX 100BASE-FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R/. In this event, the RXER bit in the RX Status Frame is asserted for one clock cycle when CRS is de-asserted. For 10BASE-T 10BASE-T links, CRS assertion is based on receipt of a valid preamble, and de-assertion is based on receipt of an End-of-Frame (EOF) marker. 3.3.5 Error Signals When the LXT973 LXT973 is in 100 Mbps mode and receives an invalid symbol from the network, it asserts RXER and drives "1110" on the RXD pins. When the MAC asserts TXER, the LXT973 LXT973 drives "H" symbols out on the DPAP/N_0 or DPAP/N_1 pins. 3.3.6 Collision The LXT973 LXT973 asserts its collision signal, asynchronously to any clock, when the line state is halfduplex and the transmitter and receiver are active at the same time. Table 8 on page 26 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. 3.3.7 Loopback The LXT973 LXT973 provides two loopback functions, operational and test (see Table 8 on page 26). Loopback paths are shown in Figure 4 on page 26. 3.3.7.1 Operational Loopback Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0. Data transmitted by the MAC (TXD) is looped back on the receive side of the MII (RXD). Operational loopback is not provided for 100 Mbps links, full-duplex links, or when Register bit 16.8 = 1. 3.3.7.2 Test Loopback A test loopback function is provided for diagnostic testing of the LXT973 LXT973. During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT973 LXT973 and returned to the MAC. Test loopback is available for both 100BASE-TX 100BASE-TX and 10BASE-T 10BASE-T operation. Test loopback is enabled by setting the register bits as follows: · Register bit 0.14 = 1 (loopback mode) Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 25 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver · Register bit 0.8 = 1 (full-duplex) · Register bit 0.12 = 0 (disable auto-negotiation). Figure 4. Loopback Paths LXT973 LXT973 FX Driver MII 10T Loopback Digital Block 100X Loopback Analog Block TX Driver Table 8. Carrier Sense, Loopback, and Collision Conditions Speed Duplex Condition Carrier Sense Test1 Loopback Operational Loopback Collision Full-Duplex No None No No None Transmit or Receive No No Transmit and Receive Full-Duplex Receive Only Yes No None Full-Duplex Receive Only No No None Half-Duplex, Register bit 16.8 = 0 Transmit or Receive Yes Yes Transmit and Receive Half-Duplex, Register bit 16.8 = 1 10 Mbps Yes Receive Only Half-Duplex 100 Mbps Receive Only Full-Duplex Transmit or Receive No No Transmit and Receive 1. Test Loopback is enabled when Register bits 0.14 = 1, 0.8 = 1, and 0.12 = 0. 3.3.8 Configuration Management Interface The LXT973 LXT973 provides an MDIO Management Interface and a Hardware Control Interface for device configuration and management. 3.3.8.1 MII Management Interface The LXT973 LXT973 supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT973 LXT973. The MDIO interface consists of a physical connection, a specific protocol which runs across the connection, and an internal set of addressable registers. The physical interface consists of a data line (MDIO) and clock line (MDC), and a control line (MDDIS). The maximum speed of MDC is 20 MHz. 26 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Operation of this interface is controlled by the MDDISn input pin. When MDDISn is High, the MDIO is completely disabled. When MDDISn is Low, read and write are enabled. The timing for the MDIO Interface is shown in Table 49 on page 85. See Figure 5 for read operations, and Figure 6 for write operations. The protocol allows one controller to communicate with multiple LXT973 LXT973 devices. Each LXT973 LXT973 port is assigned an address between 0 and 31, as described in Table 5 on page 19 (ADDR). The LXT973 LXT973 supports the core 16-bit MDIO registers. Registers 0-10 and 15 are required and their functions are specified by the IEEE 802.3 specification. Additional registers are included for expanded functionality. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-31) and Y is the bit number (0-15) Figure 5. Management Interface Read Frame Structure MDC MDIO (Read) High Z 0 32 "1"s 1 Preamble 1 ST A4 0 Op Code A3 A0 R4 R3 R0 Register Address PHY Address Z D15 D15 D14 D14D1 D14D1 D1 D0 0 Turn Around Data Write Idle Read Figure 6. Management Interface Write Frame Structure MDC MDIO (Write) 32 "1"s Idle 0 Preamble 1 ST 0 1 Op Code A4 A3 A0 R4 PHY Address R3 R0 Register Address 1 0 Turn Around D15 D14 D1 Data D0 Idle Write 3.3.8.2 MII Addressing The MDIO management protocol allows one controller to communicate with multiple LXT973 LXT973 chips. Pins ADDR_ determine the base address. Each port adds its port number to the base address to obtain its port address as shown in Figure 7 on page 28. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 27 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 7. Port Address Scheme BASE ADDR Example ADDR = 0001 Port 0 = 2 Port 1 = 3 LXT973 LXT973 Port 0 Port 1 3.3.8.3 PHY ADDR (BASE+0) ex. 2 PHY ADDR (BASE+1) ex. 3 Hardware Control Interface The LXT973 LXT973 provides a Hardware Control Interface for applications where the MDIO is not desired. Refer to Figure 16, "LXT973 LXT973 Initialization Sequence" on page 47 for additional details. 3.4 Operating Requirements 3.4.1 Power Requirements The LXT973 LXT973 requires five power supply inputs: VCCD, VCCR, VCCT, VCCPECL, and VCCIO. The digital and analog circuits require 2.5V supplies (VCCD, VCCR, and VCCT). These inputs may be supplied from a single source although decoupling is required to each respective ground. The fiber VCCPECL supply can be connected to either 2.5V or 3.3V. A separate power supply may be used for MII and MDIO (VCCIO) interfaces. The power supply may be either +2.5V or +3.3V. VCCIO should be supplied from the same power source used to supply the controller on the other side of the interface. As a matter of good practice, these supplies should be as clean as possible. 3.4.2 Clock Requirements 3.4.2.1 Reference Clock / External Oscillator The LXT973 LXT973 requires a constant enabled reference clock (REFCLK). REFCLK's frequency must be 25 MHz. Considering overall system performance first, the clock is best derived by providing a crystal-based oscillator. PLL-based oscillators with known stability may also be used. In general, an oscillator-based clock source is recommended over a derived clock due to frequency stability 28 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver and overall signal integrity. Regardless of clock source, careful consideration should be given to physical placement, board layout, and signal routing of the source to maintain the highest possible level of signal integrity. Refer to Table 33 on page 74 for clock timing requirements. 3.4.2.2 MDIO Clock The MII management channel (MDIO) also requires an external clock. The managed data clock (MDC) speed is a maximum of 20 MHz. Refer to Table 49 on page 85 for details. 3.5 Initialization When the LXT973 LXT973 is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Table 9 on page 31. 3.5.1 MDIO Control Mode In the MDIO Control mode, the LXT973 LXT973 reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface. 3.5.2 Hardware Control Mode In the Hardware Control Mode, the LXT973 LXT973 disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT973 LXT973 reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control: · Forced network link to 100BASE-FX 100BASE-FX (Fiber) · Forced network link operation to: 100BASE-TX 100BASE-TX, full-duplex 100BASE-TX 100BASE-TX, half-duplex 10BASE-T 10BASE-T, full-duplex 10BASE-T 10BASE-T, half-duplex · Allow auto-negotiation/parallel-detection When the network link is forced to a specific configuration, the LXT973 LXT973 immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT973 LXT973 begins the auto-negotiation/parallel-detection operation. 3.5.3 Power-Down Mode The LXT973 LXT973 incorporates numerous features to maintain the lowest power possible. The device can be put into a low-power state via Register 0 as well as a near-zero power state with the powerdown pin. When in power-down mode, the device is not capable of receiving or transmitting packets. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 29 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver The lowest power operation is achieved using the global power-down pin. This active High pin powers down every circuit in the device, including all clocks. All registers are unaltered and maintained when the global PWRDWN pin is released and the registers are reloaded with the value of the last hardware reset. Individual ports (software power-down) can be powered down using Control Register bit 0.11. This bit powers down a significant portion of the port, but clocks to the register section remain active. This allows the management interface to remain active during register power-down. The power-down bit is active High. 3.5.3.1 Hardware Power-Down The hardware power-down per port mode is controlled by the PWRDWN 0/1 pins. When PWRDWN 0/1 is High, the following conditions are true: · · · · 3.5.3.2 All LXT973 LXT973 ports and the clock are shut down. All outputs are tri-stated. The MDIO registers are not accessible. Configuration pins are not read upon release of the PWRDWN 0/1 pins, and registers are reloaded with the value of the last hardware reset. Software Power-Down Software port power-down control is provided by Register 11 in the respective port Control Registers (refer to Table 17 on page 62). During individual port power-down, the following conditions are true: · The individual port is shut down. · The MDIO registers remain accessible. · The register remains unchanged. 3.5.4 Reset The LXT973 LXT973 provides both hardware and software resets. Configuration control of autonegotiation, speed, and duplex mode selection is handled differently for each. During a hardware reset, settings for Register bits 0.13, 0.12, and 0.8 are read in from the pins (refer to Table 9 on page 31 for pin settings and Table 17 on page 62 for register bit definitions). During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the pins, and revert back to the values that were read in during the last hardware reset. Any changes to pin values from the last hardware reset are not detected during a software reset. Also, during a software reset (Register bit 0.15 = 1), the registers are available for reading. The reset bit is polled to see when the part has completed reset (Register bit 0.15 = 0). During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. All the MII interface pins are disabled during a hardware reset and released to the bus on deassertion of reset. 30 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.5.5 Hardware Configuration Settings The LXT973 LXT973 provides a hardware option to set the initial device configuration. The hardware option uses four per-port configuration pins that provide control (see Table 9 on page 31). Table 9. Configuration Settings (Hardware Control Interface) FIBER/TPx AUTO-NEGx SPEEDx DUPLEXx Low - - Low 100BASE-FX 100BASE-FX is enabled in half-duplex mode. Auto-negotiation is disabled. Low - - High 100BASE-FX 100BASE-FX is enabled in full-duplex mode. Auto-negotiation is disabled. High High High High AUTO_NEG is enabled. All capabilities are advertised. Register bits 4.8, 4.7, 4.6, and 4.5 are all set to 1. High High High Low High High Low High Mode AUTO_NEG is enabled. Only 100 Mbps capabilities are advertised. Register bits 4.8 and 4.7 are set 1. Register bits 4.6 and 4.5 are cleared to 0. AUTO_NEG is enabled. Only 10 Mbps capability is advertised. Register bits 4.8 and 4.7 are cleared to 0. Register bits 4.6 and 4.5 are set to 1. AUTO_NEG is enabled. Only half -duplex capability is advertised. High High Low Low High Low High High AUTO_NEG is disabled. LXT973 LXT973 port x is forced to 100 Mbps full-duplex operation. High Low High Low AUTO_NEG is disabled. LXT973 LXT973 port x is forced to 100 Mbps half-duplex operation. High Low Low High AUTO_NEG is disabled. LXT973 LXT973 port x is forced to 10 Mbps full-duplex operation. High Low Low Low AUTO_NEG is disabled. LXT973 LXT973 port x is forced to 10 Mbps half-duplex operation. Register bits 4.7 and 4.5 are set 1. Register bits 4.8 and 4.6 are cleared to 0. 1. These pins also set the default values for Registers 0 and 4 accordingly. 3.6 Link Establishment 3.6.1 Auto-Negotiation The LXT973 LXT973 attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 pulse positions spaced 62.5 µs apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may also be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, referred to as a "page." All devices that support auto-negotiation must implement the "Base Page", defined by IEEE 802.3 (Registers 4 and 5). The LXT973 LXT973 also supports the optional "Next Page" function (Registers 7 and 8). Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 31 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.6.1.1 Base Page Exchange By exchanging Base Pages, the LXT973 LXT973 and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to proceed. Each side finds their highest common capabilities, exchange more pages, and agree on the operating state of the line. 3.6.1.2 Next Page Exchange Additional information, exceeding that required by Base Page exchange, can also be sent via "Next Pages." The LXT973 LXT973 fully supports the IEEE 802.3 method of negotiation via Next Page exchange. The Next Page exchange uses Register 7 to send information and Register 8 to receive information, and occurs only if both ends of the link advertise their ability to exchange Next Pages. The LXT973 LXT973 is configured to make Next Page exchange easier for software. When a Base Page or Next Page is received, the Page Received Register bit 6.1 remains set until read. When Register bit 6.2 (Next Page Able) is received, it stays set until read. This bit should be cleared whenever a new negotiation occurs. This prevents the user from reading an old value in Register 6 and assuming there is valid information in Registers 5 and 8. Additionally, Register 6 contains a new bit (Register bit 6.5) that indicates when the current Received Page is the Base Page. This information is useful for recognizing when next pages must be re-sent due to the start of a new negotiation process. Register bit 16.1 and the Page Received bit (Register bit 6.1) are also cleared upon reading Register 6. 3.6.1.3 Controlling Auto-Negotiation When auto-negotiation is controlled by software, the following steps are recommended: 1. After power-up, power-down, or reset, the power-down recovery time (max = 300 µs) must be exhausted before proceeding. 2. Set the auto-negotiation advertisement register bits. 3. Enable auto-negotiation (set MDIO Register bit 0.12 = 1). 3.6.1.4 Link Criteria In 100 Mbps mode, link is established when the scrambler becomes locked and remains locked for approximately 50 ms. Link remains up unless the de-scrambler receives less than 12 consecutive IDLE symbols in any 2 ms period. This provides a very robust operation, filtering out any small noise hits that may disrupt the link. In 10 Mbps mode, link is established based on the link state machine found in the IEEE 802.3, Clause 14.X specification. Receiving 100 Mbps idle patterns does not bring up a 10 Mbps link. 3.6.1.5 Parallel Detection In parallel with auto-negotiation, the LXT973 LXT973 also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps IDLE symbols. If either is detected, the device automatically reverts to the corresponding operating mode. Parallel detection allows the LXT973 LXT973 to communicate with devices that do not support auto-negotiation. The established link is always set at half-duplex. 32 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 8. Auto-Negotiation Operation Power-Up, Reset, Link Failure Start Disable Auto-Negotiation 0.12 = 0 Go To Forced Settings 0.12 = 1 Check Value 0.12 Attempt AutoNegotiation Enable Auto-Neg/Parallel Detection Listen for 100TX 100TX Idle Symbols YES Done 3.7 Listen for 10T Link Pulses NO Link Set? Network Media/Protocol Support The LXT973 LXT973 supports both 10BASE-T 10BASE-T and 100BASE-TX 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX 100BASE-FX). 3.7.1 10/100 Mbps Network Interface The network interface port consists of five external pins (two differential signal pairs and a signal detect pin). The differential signal pins are shared between twisted-pair and fiber. Refer to Figure 3 on page 23 for specific pin assignments. The LXT973 LXT973 output drivers generate either 100BASE-TX 100BASE-TX, 10BASE-T 10BASE-T, or 100BASE-FX 100BASE-FX output. When not transmitting data, the LXT973 LXT973 generates IEEE 802.3-compliant link pulses or an IDLE code. Input signals are decoded either as a 100BASE-TX 100BASE-TX, 100BASE-FX 100BASE-FX, or 10BASE-T 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. 3.7.2 Twisted-Pair Interface When operating at 100 Mbps, the LXT973 LXT973 continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT973 LXT973 generates IDLE symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link up. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 33 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver The LXT973 LXT973 supports either 100BASE-TX 100BASE-TX or 10BASE-T 10BASE-T connections over 100, Category 5, Unshielded Twisted-Pair (UTP) cable. Only a transformer, RJ-45 RJ-45 connector, and bypass capacitors are required to complete this interface. On the transmit side, Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 5 on page 19) allow the designer to match the output waveform to the magnetic characteristics. 3.7.3 Fiber Interface The LXT973 LXT973 fiber port is designed to interface with common industry-standard fiber modules. It incorporates a PECL interface that complies with the ANSI X3.166 standard for seamless integration. Fiber mode is selected by putting a low level on the Fiber_TPn pin. This is only sensed upon completion of reset. 3.7.4 Fault Detection and Reporting The LXT973 LXT973 supports two fault detection and reporting mechanisms. "Remote Fault" refers to a MAC-to-MAC communication function that is essentially transparent to PHY layer devices, and is used only during auto-negotiation. Therefore, Remote Fault is applicable only to twisted-pair links. "Far End Fault" is an optional PMA-layer function that may be embedded within PHY devices. The LXT973 LXT973 supports both functions, which are explained in more detail in sections that follow. 3.7.5 Remote Fault Register bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault indications. This bit is typically used when restarting the auto-negotiation sequence, indicating to the link partner that link is down because the advertising device detected a fault. When the LXT973 LXT973 receives a Remote Fault indication from its partner during auto-negotiation it: · Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and · Sets the Remote Fault Register bit 1.4 in the MII Status Register to pass this information to the local controller. 3.7.6 Far End Fault In fiber mode, the SDn pin monitors signal quality. If signal quality degrades beyond the fault threshold, the fiber transceiver reports a signal quality fault condition via the SDn pin. Loss of signal quality blocks any fiber data from being received and causes a loss of link. 34 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver If the LXT973 LXT973 detects a signal fault condition, it transmits the Far End Fault Indication (FEFI) over the fiber link. The FEFI consists of 84 consecutive "1s" followed by a single "0." This pattern must be repeated at least three times. The LXT973 LXT973 transmits the Far-End Fault code a minimum of three times if all the following conditions are true: · · · · Fiber mode is selected. Far End Fault Code transmission is enabled (Register bit 16.2 = 1). Signal Detect indicates either no signal or the receive PLL cannot lock. Loopback is not enabled. 3.8 100 Mbps Operation 3.8.1 100BASE-X 100BASE-X Network Operations During 100BASE-X 100BASE-X operation, the LXT973 LXT973 transmits and receives 5-bit symbols across the network link. Figure 9 shows the structure of a standard frame packet. When the MAC is not actively transmitting data, the LXT973 LXT973 sends out IDLE symbols on the line. In 100BASE-TX 100BASE-TX mode, the device scrambles the data and transmits it to the network using MLT-3 line code. The MLT-3 signals received from the network are de-scrambled and decoded, and sent across the MII to the MAC. In 100BASE-FX 100BASE-FX mode, the LXT973 LXT973 transmits and receives NRZI signals across the PECL interface. An external 100BASE-FX 100BASE-FX transceiver module is required to complete the fiber connection. As shown in Figure 9, the MAC starts each transmission with a preamble pattern. As soon as the LXT973 LXT973 detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the LXT973 LXT973 transmits the T/R End-of-Stream Delimiter (ESD) symbol and returns to transmitting IDLE symbols. Figure 9. 100BASE-X 100BASE-X Frame Format 64-Bit Preamble (8 Octets) P0 P1 Replaced by /J/K/ code-groups Start-of-Stream Delimiter (SSD) Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 P6 Destination and Source Address (6 Octets each) SFD DA Start-of-Frame Delimiter (SFD) DA SA Packet Length (2 Octets) SA L1 L2 Data Field Frame Check Field InterFrame Gap / Idle Code (Pad to minimum packet size) (4 Octets) (> 12 Octets) D0 D1 Dn CRC I0 IFG Replaced by /T/R/ code-groups End-of-Stream Delimiter (ESD) 35 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.8.2 100BASE-X 100BASE-X Protocol Sublayer Operations In the 7-layer OSI communications model, the LXT973 LXT973 is a Physical Layer 1 (PHY) device. The LXT973 LXT973 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u specification. The following paragraphs discuss the LXT973 LXT973 operation from the reference model point of view. 3.8.3 PCS Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. For 100BASE-TX 100BASE-TX and 100BASE-FX 100BASE-FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TXEN is de-asserted. For 10BASE-T 10BASE-T operation, the PCS layer merely provides a bus interface and serialization/de-serialization function. 10BASE-T 10BASE-T operation does not use the 4B/5B encoder. 3.8.3.1 Preamble Handling When the MAC asserts TXEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-ofStream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues to encode the remaining MII data until TXEN is de-asserted. It then returns to supplying IDLE symbols to the line driver. The PCS layer performs the opposite function in the receive direction by substituting two preamble nibbles for the SSD. 3.8.3.2 Dribble Bits The LXT973 LXT973 handles dribble bits in all modes. If one through four dribble bits are received, the nibble is passed across the MII, and padded with ones if necessary. If five through seven dribble bits are received, the second nibble is not sent to the MII bus. Figure 10. Protocol Sublayers MII Interface PCS Sublayer PMA Sublayer LXT973 LXT973 Encoder/Decoder Serializer/De-serializer Link/Carrier Detect PECL Interface PMD Sublayer Scrambler/ De-scrambler 100BASE-TX 100BASE-TX 36 Fiber Transceiver 100BASE-FX 100BASE-FX Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.8.4 PMA Sublayer 3.8.4.1 Link Failure Override The LXT973 LXT973 normally transmits 100 Mbps data packets or IDLE symbols only if it detects that link is up, and transmits FLP bursts in auto-negotiation mode or IDLE symbols in forced mode. Setting Register bit 16.14 = 1 overrides this function, allowing the LXT973 LXT973 to transmit data packets even when link is down. This feature is provided as a diagnostic tool. Note: 3.8.4.2 Auto-negotiation must be disabled to transmit data packets in the absence of link. If autonegotiation is enabled, the LXT973 LXT973 automatically begins transmitting FLP bursts if the link goes down. Carrier Sense For 100BASE-TX 100BASE-TX and 100BASE-FX 100BASE-FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R/. In this event, the RXER bit in the RX Status Frame is asserted for one clock cycle when CRS is de-asserted. 3.8.4.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3), as well as receiving, polarity correction, and baseline wander correction functions. 3.8.4.4 Scrambler/Descrambler The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. The scrambler/de scrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic and test support. 3.8.4.5 Baseline Wander Correction The LXT973 LXT973 provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX 100BASE-TX is, by definition, "unbalanced." This means that the DC average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander may cause receiver errors, particularly in less robust designs, at long-line lengths (100 meters). The exact characteristics of the wander are completely data dependent. The LXT973 LXT973 baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case "killer" packets over all cable lengths. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 37 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.8.5 Fiber PMD Sublayer The LXT973 LXT973 provides a PECL interface for connection to an external fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The device uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps only and does not support 10 Mbps applications. 3.8.5.1 Far End Fault Indications The LXT973 LXT973 Signal Detect pins independently detect signal faults from the local fiber transceivers via the SD pins. The device also uses Register bit 1.4 to report Remote Fault indications received from its link partner. The device ORs both fault conditions to set Register bit 1.4. This bit is set once and cleared when read. Either fault condition causes the LXT973 LXT973 to drop the link unless Forced Link Pass is selected (Register bit 16.14 = 1). A link-down condition is then reported via status bits. In response to locally detected signal faults (SD activated by the local fiber transceiver), the affected port can transmit the Far End Fault code if a fault code transmission is enabled by Register bit 16.2. · When Register bit 16.2 = 1, transmission of the Far End Fault code is enabled. The LXT973 LXT973 transmits Far End Fault code if fault conditions are detected by the Signal Detect pins. · When Register bit 16.2 = 0, the LXT973 LXT973 does not transmit Far End Fault code. It continues to transmit IDLE code and may or may not drop link, depending on the setting for Register bit 16.14. The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer to stop and the Far End fault code to begin. The Far End Fault code consists of 84 "1s" followed by a single "0", and is repeated until the Far End Fault condition is removed. 3.9 10 Mbps Operation The LXT973 LXT973 operates as a standard 10BASE-T 10BASE-T transceiver and supports all the standard 10 Mbps functions. During 10BASE-T 10BASE-T operation, the LXT973 LXT973 transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the device sends out link pulses on the line. In 10BASE-T 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT973 LXT973 and sent across the MII to the MAC. 3.9.1 Polarity Correction The LXT973 LXT973 automatically detects and corrects for an inverted receive signal. Reversed polarity is detected if eight inverted link pulses or four inverted End-of-Frame (EOF) markers are received consecutively. If link pulses or data are not received by the maximum receive time-out period, the polarity state is reset to a non-inverted state. 38 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Note: 3.9.2 The LXT973 LXT973 does not support fiber connections at 10 Mbps. Dribble Bits The LXT973 LXT973 device handles dribble bits in all modes. If one through four dribble bits are received, the nibble is passed across the MII. If five through seven dribble bits are received, the second nibble is not sent to the MII bus. 3.9.3 Link Test The LXT973 LXT973 always transmits link pulses in 10BASE-T 10BASE-T mode. When enabled, the link test function monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continues. If link pulses stop, the data transmission is disabled. If the link test function is disabled, the LXT973 LXT973 transmits to the connection regardless of detected link pulses. The link test function is disabled by setting Register bit 16.14 = 1. 3.9.4 Link Failure Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT973 LXT973 returns to the auto-negotiation phase if auto-negotiation is enabled. 3.9.5 Jabber If a transmission exceeds the jabber timer, the LXT973 LXT973 disables the transmit and loopback functions. The LXT973 LXT973 automatically exits jabber mode after the unjab time has expired. This function is disabled by setting Register bit 16.10 = 1. 3.10 Monitoring Operations 3.10.1 Monitoring Auto-Negotiation Auto-negotiation may be monitored as follows: · Link Status Register bit 1.2 = 1 once the link is established. · Additional bits in Register 1 can be used to determine the link operating conditions and status (refer to Table 18 on page 63). 3.10.2 Per-Port LED Driver Functions The LXT973 LXT973 incorporates three direct drive LEDs per port (LEDn_1, LEDn_2, and LEDn_3). On power-up, all the LEDs light up for approximately one second after reset de-asserts. Each LED may be configured to one of several different display modes using the LED Configuration Pins, as shown in Table 10 on page 40. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 39 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver The LED driver pins are open drain circuits (10 mA maximum current rating). If an LEDx_n pin is unused, terminate with a 10K pull-up resistor. Figure 11 shows a typical LED implementation. When configured for modes 2 or 4, the LEDs blink at the rate of 100 ms to display multiple status. Table 10 provides LED configurations for the LXT973 LXT973. Table 10. LED Configurations LED_CFG0 LED_CFG1 LEDn_1 LEDn_2 LEDn_3 0 0 Speed Link Duplex 1 0 Speed Link/Activity Duplex/Collision 0 1 Link Receive Transmit 1 1 Speed Link/MII Isolate Duplex/Collision Figure 11. Typical LED Implementation VLED 220 LEDx_n pin 40 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 4.0 Application Information 4.1 Design Recommendations The LXT973 LXT973 is designed to comply with IEEE 802.3 requirements to provide outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from the LXT973 LXT973, attention to detail and good design practices are required. Refer to the LXT973 LXT973 Design and Layout Guide for detailed design and layout information. 4.1.1 General Design Guidelines Adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. Up to a maximum noise level of 50 mV is considered acceptable. Highfrequency switching noise can be reduced, and its effects eliminated, by following these simple guidelines throughout the design: · Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC or ground plane that is not located adjacent to the signal layer. · Use ample bulk and de-coupling capacitors throughout the design (a value of 0.01 µF is recommended for de-coupling caps). · · · · · · Provide ample power and ground planes. Provide termination on all high-speed switching signals and clock lines. Provide impedance matching on long traces to prevent reflections. Route high-speed signals next to a continuous, unbroken ground plane. Filter and shield DC-to-DC converters, oscillators, etc. Do not route any digital signals between the LXT973 LXT973 and the RJ-45 RJ-45 connectors at the edge of the board. · Do not extend any circuit power and ground planes past the center of the magnetics or to the edge of the board. Use this area for chassis ground, or leave it void. 4.1.2 Power Supply Filtering Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and degrade line performance. To minimize ground noise as much as