LXT325 LXT325PE LXT325NE LXT325QE

APRIL, 1996 DATA SHEET LXT325 T1/E1 Integrated Quad Receiver General Description 1 Features The LXT325 quad receiver is a

325_2.fm4 Page 111 Thursday, August 1, 1996 4:39 PM APRIL, 1996 DATA SHEET LXT325 LXT325 T1/E1 Integrated Quad Receiver General Description 1 Features The LXT325 LXT325 quad receiver is a fully-integrated, quadruple-PCM receiver for both 1.544 Mbps, and 2.048 Mbps applications. It incorporates four independent receivers in a single 28-pin DIP or PLCC, or a 44-pin QFP. Each LXT325 LXT325 receiver also incorporates a Loss Of Signal (LOS) detection circuit and output driver. The operating frequency is pin selectable. These receivers perform data and timing recovery, and use peak detection and a variable threshold to reduce impulsive noise. Receiver sensitivity down to 500 mV allows for up to 13.6 dB of attenuation. The LXT325 LXT325 quad receiver is an advanced, double-poly, double-metal CMOS device and requires only a single 5-volt power supply. 2 · Four independent 1.544/2.048 Mbps receivers · Loss Of Signal (LOS) output for each receiver · Circuit functions include data and clock recovery · Meets or exceeds AT&T PUB 62411 ITU-T G.703 and ITU G.823 requirements for jitter tolerance · High-density T1/E1 line cards · 5 · Minimum receive signal of 500 mV · Selectable slicer levels (DSX-1/E1) to provide improved SNR · CMOS technology requires only single 5 V power input M13, E13 line interfaces · Test equipment · Line monitoring · 4 · Unipolar RPOS and RNEG outputs · Available in 28-pin plastic DIP and PLCC and 44-pin QFP packages Applications 3 · Single Master Clock input Receive line interface · -40 °C to 85 °C operating temperature range 6 7 8 9 10 LXT325 LXT325 Block Diagram MCLK MODE DIVIDE BY X DATA SLICERS RTIP PEAK DETECTOR RRING 12 TIMING RECOVERY DATA LATCH LOS DETECT VCC POWER SUPPLY GND 11 CLOCK GENERATOR RCLK 13 RPOS RNEG 14 LOS RECEIVER #1 15 RECEIVER #2 RECEIVER #3 RECEIVER #4 L1 2-111 325_2.fm4 Page 112 Friday, June 21, 1996 11:46 AM LXT325 LXT325 T1/E1 Integrated Quad Receiver RNEG1 RPOS1 VCC RRING1 RTIP1 LOS1 4 3 2 1 28 27 26 RPOS2 5 25 RRING2 RNEG2 6 24 RTIP2 RCLK2 7 23 LOS2 LOS3 8 22 RRING3 RPOS3 9 21 RTIP3 RNEG3 10 20 LOS4 RCLK3 11 19 RRING4 12 13 14 15 16 17 18 RCLK4 GND MCLK MODE RTIP4 LXT325PE LXT325PE RNEG4 VCC RRING1 RTIP1 LOS1 RRING2 RTIP2 LOS2 RRING3 RTIP3 LOS4 RRING4 RTIP4 MODE MCLK RCLK1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RPOS4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n/c RTIP4 MODE MCLK n/c GND GND RCLK4 RNEG4 RPOS4 n/c RPOS1 RNEG1 RCLK1 RPOS2 RNEG2 RCLK2 LOS3 RPOS3 RNEG3 RCLK3 RPOS4 RNEG4 RCLK4 GND LXT325NE LXT325NE Figure 1: LXT325 LXT325 Pin Assignments 33 32 31 30 29 28 27 26 25 24 23 22 34 21 35 20 36 19 37 18 38 17 39 LXT325QE LXT325QE 16 40 15 41 14 42 13 43 44 12 1 2 3 4 5 6 7 8 9 10 11 n/c RCLK3 RNEG3 RPOS3 n/c n/c LOS3 RCLK2 RNEG2 RPOS2 n/c n/c LOS1 RTIP1 RRING1 VCC VCC n/c RPOS1 RNEG1 RCLK1 n/c n/c RRING4 LOS4 RTIP3 RRING3 n/c LOS2 RTIP2 RRING2 n/c n/c 2-112 L1 325_2.fm4 Page 113 Friday, June 21, 1996 11:46 AM LXT325 LXT325 T1/E1 Integrated Quad Receiver Table 1: Pin Assignments and Descriptions Pin # 1 DIP PLCC QFP1 Symbol I/O2 Description 1 2 2 3 8 9 RPOS1 RNEG1 DO Receiver 1 Positive and Negative Data outputs. A signal on RNEGx corresponds to receipt of a negative pulse on RTIPx and RRINGx. A signal on RPOSx corresponds to receipt of a positive pulse on RTIPx and RRINGx. RNEGx and RPOSx outputs are Non-Return-to-Zero (NRZ) signals. Both outputs are stable and valid on the rising edge of RCLKx. 3 4 10 RCLK1 DO Receiver 1 Recovered Clock. Clock recovered from the inputs to RTIP1 and RRING1. See RPOS1/RNEG1. 4 5 6 5 6 7 13 14 15 RPOS2 RNEG2 RCLK2 DO Receiver 2 Data and Clock outputs. Signals recovered from the inputs to RTIP2 and RRING2. See RPOS1/RNEG1/RCLK1. 7 8 16 LOS3 DO Receiver 3 Loss of Signal Detector. LOSx pins go high when the associated receiver detects 175 consecutive spaces. The LOS output returns low when a mark is received. 8 9 10 9 10 11 19 20 21 RPOS3 RNEG3 RCLK3 DO 11 12 13 12 13 14 24 25 26 RPOS4 RNEG4 RCLK4 DO 14 15 27 28 GND Ground. 15 16 30 MCLK DI Master Clock. A 1.544 MHz or 2.048 MHz clock input used to generate internal clocks. Upon loss of signal, MCLK serves as the source for all the RCLKx signals. 16 17 31 MODE DI Mode Selection. Set MODE high for 50% slicer level. This setting is mandatory for 2.048 Mbit/s operation and provides maximum sensitivity in 1.544 Mbit/s designs. Where undershoot will exceed 45% in 1.544 MHz applications, pull MODE low to set the slicer levels to 70%. 17 18 18 19 32 35 RTIP4 RRING4 AI Receiver 3 Data and Clock outputs. Signals recovered from the inputs to RTIP3 and RRING3. See RPOS1/RNEG1/RCLK1. Receiver 4 Data and Clock outputs. Signals recovered from the inputs to RTIP4 and RRING4. See RPOS1/RNEG1/RCLK1. Receiver 4 Tip and Ring. The AMI signal received from the 4th twisted-pair line is applied at these pins. A center-tapped, centergrounded transformer is required on these pins. Data and clock from the signal applied at these pins are recovered and output on the RPOSx/RNEGx, and RCLKx pins. 19 20 36 LOS4 DO Receiver 4 Loss of Signal Detector. See LOS3. 20 21 21 22 37 38 RTIP3 RRING3 AI Receiver 3 Tip and Ring Inputs. See RTIP4/RRING4. 22 23 40 LOS2 DO Receiver 2 Loss of Signal detector. See LOS3. 3 4 5 6 7 8 9 10 11 12 13 14 15 1. Pins 1, 7, 11, 12, 17, 18, 22, 23, 29, 33, 34, 39, 43 and 44 have no function in the 44-pin QFP package. All applications should leave them unconnected. 2. Entries in the I/O column are DI = Digital Input; DO = Digital Output; AI = Analog Input. L1 2 2-113 325_2.fm4 Page 114 Friday, June 21, 1996 11:46 AM LXT325 LXT325 T1/E1 Integrated Quad Receiver Table 1: Pin Assignments and Descriptions continued Pin # DIP PLCC QFP1 Symbol I/O2 23 24 24 25 41 42 RTIP2 RRING2 AI Receiver 2 Tip and Ring Inputs. See RTIP4/RRING4. 25 26 2 LOS1 DO Receiver 1 Loss of Signal Detector. See LOS3. 26 27 27 28 3 4 RTIP1 RRING1 AI Receiver 1 Tip and Ring Inputs. See RTIP4/RRING4. 28 1 5,6 VCC +5 VDC Power Supply Description 1. Pins 1, 7, 11, 12, 17, 18, 22, 23, 29, 33, 34, 39, 43 and 44 have no function in the 44-pin QFP package. All applications should leave them unconnected. 2. Entries in the I/O column are DI = Digital Input; DO = Digital Output; AI = Analog Input. 2-114 L1 325_2.fm4 Page 115 Friday, June 21, 1996 11:46 AM LXT325 LXT325 T1/E1 Integrated Quad Receiver FUNCTIONAL DESCRIPTION The slicer threshold is maintained through a capacitive storage arrangement and a combination of Refresh and Bleed-off circuitry. This design balance prevents the refresh circuitry from driving the threshold too high, while ensuring that it is maintained over long strings of successive zeros. NOTE This functional information is for design aid only. The LXT325 LXT325 quad receiver is a fully-integrated, PCM receiver for both 1.544 Mbit/s (DSX-1) and 2.048 Mbit/s (E1) applications. The MCLK frequency and the MODE pin input level set the mode of operation. The LXT325 LXT325 is a low-power CMOS device operating from a single +5 V power supply. The figure at the front of the Data Sheet shows a simplified block diagram of the LXT325 LXT325. The input signal is received from the twisted-pair line on each side of a centergrounded transformer. (Positive pulses are received at RTIP and negative pulses are received at RRING.) This differential signal is processed through the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received signal. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For E1 applications the threshold is set to 50% of the peak value (MODE set High). In 1.544 Mbit/s applications where undershoot does not exceed 45%, MODE may be set High (50% of the peak value) for the maximum sensitivity and noise margin. In applications where the undershoot exceeds 45% the MODE must be set Low. With MODE Low, the slicer threshold is set to 70% of the peak value. This threshold is maintained above 65% for up to 15 consecutive zeros over the range of specified operating conditions. These receivers are capable of accurately recovering signals with up to 13.6 dB of attenuation (from 2.4 V), corresponding to a received signal level of 500 mV. Maximum cable length is 1500 feet of ABAM cable (approximately 6 dB), with the additional attenuation being resistive flat loss. Regardless of received signal level, the peak detectors are held above a minimum level of 150 mV to provide immunity from impulsive noise. After processing through the data slicers, the received signal is routed to the data and clock recovery sections. Recovered clock signals are supplied to the data latch. The recovered data is synchronized with the recovered clock (RCLK), then output at RNEG and RPOS. RPOS and RNEG outputs are valid on the rising edge of RCLK. 2 3 4 5 6 LINE INTERFACE The LXT325 LXT325 quad receiver interfaces with four twistedpair lines (one twisted-pair for each receiver) through standard pulse transformers and appropriate resistors. Recommended transformer characteristics are listed in Table 2. 7 8 9 10 11 Table 2: Recommended Transformer Characteristics Parameter 1 1:1:1 1:2:2 Unit Primary 1.0 Maximum 1.0 Maximum Secondary 1.0 Maximum 1.0 Maximum Primary inductance (Line Side) 1.2 typical 0.5 Maximum mH Leakage inductance 0.5 Maximum 1.0 Maximum µH Interwinding capacitance 25 Maximum 40 Maximum 12 pF DC Resistance L1 13 14 15 2-115 325_2.fm4 Page 116 Friday, June 21, 1996 11:46 AM LXT325 LXT325 T1/E1 Integrated Quad Receiver APPLICATION INFORMATION difference in circuit design between these two applications is the input transformer. The typical DSX-1 pulse seen in test equipment requires a 1:1:1 transformer at the receiver input. The attenuated pulse seen in monitor applications may require a 1:2:2 transformer to boost the input signal. Figure 2 is a typical 1.544 Mbit/s DSX-1 application. The LXT325 LXT325 is shown tapped into the cross connect frame with 800 resistors across each leg of the center-tapped, centergrounded, 1:2:2 step-up transformer. NOTE This application information is for design aid only. The LXT325 LXT325 quad receiver is compatible with both DSX1 and E1 systems. Low, +5 V only, power consumption simplifies design considerations where multiple receivers are required. The LXT325 LXT325 is well-suited for use in both line interface equipment and monitor applications. The primary Figure 2: Typical T1 Test/Monitor Equipment Application TP CROSS-CONNECT Reference Point TP TP TP TP TP TP 432 9 432 9 432 9 TP 432 9 800 9 800 RTIP1 9 RPOS1 LXT 325 Q-RCVR RCLK1 RRING1 RNEG1 RTIP2 RPOS2 1:2:2 800 9 800 9 RCLK2 RRING2 RNEG2 RTIP3 RPOS3 1:2:2 800 9 800 9 1:2:2 800 800 1:2:2 9 9 RCLK3 RRING3 RNEG3 RTIP4 RPOS4 RCLK4 RRING4 RNEG4 MODE +5V 22 µF 2-116 MCLK VCC GND 0.1 µF L1 325_2.fm4 Page 117 Friday, June 21, 1996 11:46 AM LXT325 LXT325 T1/E1 Integrated Quad Receiver Figure 3: Typical DSX-1/E1 Receiver Application RTIP1 LXT 325 Q-RCVR 1 RPOS1 Rx 2 RCLK1 Rx RRING1 RNEG1 RTIP2 RPOS2 1:1:1 3 Rx 4 RCLK2 Rx RRING2 RNEG2 RTIP3 1:1:1 RPOS3 5 Rx 6 RCLK3 Rx RRING3 RNEG3 RTIP4 RPOS4 1:1:1 7 8 Rx RCLK4 Rx 1:1:1 RRING4 MODE +5V 9 RNEG4 MCLK VCC 1.544/2.048 MHz GND 10 11 12 NOTES: Rx = 200 for DSX-1 (100 , TP, T1) applications Rx = 240 for E1 (120 , TP, E1) applications Rx = 150 for E1 (75 , coax, E1) applications 13 14 15 L1 2-117 325_2.fm4 Page 118 Friday, June 21, 1996 11:46 AM LXT325 LXT325 T1/E1 Integrated Quad Receiver TEST SPECIFICATIONS NOTE The minimum and maximum values in Tables 3 through 6 and Figures 5 through 7 represent the performance specificatons of the LXT325 LXT325 and are guaranteed by test, except where noted by design. Table 3: Absolute Maximum Ratings Parameter Symbol Min Max Units Supply Voltage VCC -0.3 V 6V V Input Voltage, any I/O pin1 VI/O GND - 0.3 V VCC + 0.3 V V Input Current, any I/O pin2 II/O -10 10 mA Storage Temperature TST -65 150 °C CAUTION Exceeding these values may cause permanent damage to the device. Operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Excluding RTIP and RRING which must stay within -6 V to VCC +0.3 V 2. Transient currents of up to 100 mA will not cause SCR latch-up. Table 4: Recommended Operating Conditions Parameter Symbol Min Typ Max Units Supply Voltage1 VCC 4.75 5 5.25 V Power dissipation PD 1 1 W Operating Temperature TOP -40 85 °C 1. Voltages are with respect to ground unless otherwise stated. Table 5: DC Electrical Characteristics1 Parameter Sym Min Typ Max Units Supply current ICC 40 mA Input High voltage VIH 2.0 V Digital Inputs Input Low voltage VIL 0.8 V Digital Inputs Output High voltage VOH 2.4 V IO = 0.4 mA Output Low voltage VOL 0.4 V IO = 1.6 mA Input leakage current ILL ±10 µA Digital inputs Output current IH 1.6 mA VO = 0.4 V TRF 25 ns 15 pF load Output rise/fall time Test Conditions 1. Clocked operation over recommended temperature and power supply ranges. 2-118 L1 325_2.fm4 Page 119 Thursday, August 1, 1996 4:40 PM LXT325 LXT325 T1/E1 Integrated Quad Receiver Table 6: Receiver Characteristics Sym Min Typ1 Max Units Mode=Low SRD 63 70 77 % Mode=High SRC 43 50 57 % Dynamic Range DR 0.50 3.6 VPEAK Undershoot US 62 % Sensitivity below DSX (0 dB = 2.4 V) 13.6 dB 500 mV 2.048 MHz S/X 14 dB 1.544 MHz S/X 12 dB Parameter Slicer ratio Error-Free Signal-toCrosstalk ratio Test Conditions 1 2 maximum of 6 dB cable loss, with balance being resistive loss. Single frequency interference production test guarantees error-free operation as specified in G.703, 6.3.4 (Testing for 1.544 MHz systems uses a 1.544 Mbit/s QRSS interfering signal; MODE = 1.) 1. Typical figures are at 25 °C and are design aids only; not guaranteed and not subject to production testing. 3 4 5 6 t PW t PW 7 t SUR t HR 8 Figure 4: Clock Timing Diagram RCLK RPOS RNEG 9 Table 7: Master and Receive Clock Timing Characteristics (See Figure 4) Sym Min Typ1 Max Units DSX-1 MCLK 1.544 MHz E1 MCLK 2.048 MHz Master Clock Tolerance MCLKt ±100 ppm Master Clock duty cycle MCLKd 40 50 60 % Receive Clock duty cycle RCLKd 40 50 60 % 1.544 Mbit/s tPW 270 325 378 ns 2.048 Mbit/s tPW 203 244 285 ns 1.544 Mbit/s tSUR 50 270 ns 2.048 Mbit/s tSUR 50 203 ns 1.544 Mbit/s tHR 50 270 ns 2.048 Mbit/s tHR 50 203 ns TRF 25 ns Parameter Master Clock Frequency Receive Clock pulse width RPOS/RNEG to RCLK rising setup time RCLK rising to RPOS/RNEG hold time Rise/fall timeany digital output Test Conditions 10 11 12 13 14 15 1. Typical figures are at 25 °C and are design aids only; not guaranteed and not subject to production testing. L1 2-119