MC74LVX8053 LVX8053 HC4053A MC14053B MC74LVX8053DT MC74LVX8053DTR2 - Datasheet Archive

 

Analog Multiplexer / Demultiplexer High­Performance Silicon­Gate CMOS The MC74LVX8053 utilizes silicon­gate CMOS

 

MC74LVX8053 MC74LVX8053 Analog Multiplexer / Demultiplexer High­Performance Silicon­Gate CMOS The MC74LVX8053 MC74LVX8053 utilizes silicon­gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to GND). The LVX8053 LVX8053 is similar in pinout to the high­speed HC4053A HC4053A, and the metal­gate MC14053B MC14053B. The Channel­Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel­Select and Enable inputs are compatible with standard CMOS outputs; with pull­up resistors they are compatible with LSTTL outputs. This device has been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal­gate CMOS analog switches. · · · · · · · · · Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC ­ GND) = 2.0 to 6.0 V Digital (Control) Power Supply Range (VCC ­ GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance Than Metal­Gate Counterparts Low Noise In Compliance With the Requirements of JEDEC Standard No. 7A Chip Complexity: LVX8053 LVX8053 - 156 FETs or 39 Equivalent Gates LOGIC DIAGRAM Triple Single­Pole, Double­Position Plus Common Off 12 X0 13 X1 X SWITCH 2 ANALOG INPUTS/OUTPUTS Y0 1 Y1 Y SWITCH 14 15 X Y COMMON OUTPUTS/INPUTS http://onsemi.com 16­LEAD SOIC D SUFFIX CASE 751B 16­LEAD TSSOP DT SUFFIX CASE 948F PIN CONNECTION AND MARKING DIAGRAM (Top View) VCC 16 Y X X1 X0 A B C 15 14 13 12 11 10 9 8 GND 1 2 3 4 5 6 7 Y1 Y0 Z1 Z Z0 Enable NC For detailed package marking information, see the Marking Diagram section on page 11 of this data sheet. FUNCTION TABLE ­ MC74LVX8053 MC74LVX8053 Control Inputs Enable C L L L L L L L L H Select B A L L L L H H H H X L L H H L L H H X L H L H L H L H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X = Don't Care 5 Z0 3 Z1 Z SWITCH 4 Z ORDERING INFORMATION 11 A 10 B 9 C 6 ENABLE CHANNEL-SELECT INPUTS Device © Semiconductor Components Industries, LLC, 1999 March, 2000 ­ Rev. 2 SOIC 48 Units/Rail SOIC 2500 Units/Reel MC74LVX8053DT MC74LVX8053DT TSSOP 96 Units/Rail MC74LVX8053DTR2 MC74LVX8053DTR2 1 Shipping MC74LVX8053DR2 MC74LVX8053DR2 NOTE: This device allows independent control of each switch. Channel­Select Input A controls the X­Switch, Input B controls the Y­Switch and Input C controls the Z­Switch Package MC74LVX8053D MC74LVX8053D PIN 16 = VCC PIN 8 = GND TSSOP 2500 Units/Reel Publication Order Number: MC74LVX8053/D MC74LVX8053/D MC74LVX8053 MC74LVX8053 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎ Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎ ÎÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* Symbol Parameter Value Unit ­ 0.5 to + 7.0 V Analog Input Voltage ­ 0.5 to VCC + 0.5 V Digital Input Voltage (Referenced to GND) ­ 0.5 to VCC + 0.5 V ± 20 mA 500 450 mW ­ 65 to + 150 _C 260 _C VCC Positive DC Supply Voltage VIS Vin I (Referenced to GND) DC Current, Into or Out of Any Pin PD Power Dissipation in Still Air, Tstg Storage Temperature Range TL SOIC Package TSSOP Package Lead Temperature, 1 mm from Case for 10 Seconds *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating - SOIC Package: ­ 7 mW/_C from 65_ to 125_C TSSOP Package: ­ 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS ÎÎÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎ Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î Symbol Parameter Min VCC Positive DC Supply Voltage VIS Vin VIO* 6.0 V VCC V VCC V 1.2 Digital Input Voltage (Referenced to GND) 2.0 GND (Referenced to GND) Unit 0.0 Analog Input Voltage Max V + 85 _C Static or Dynamic Voltage Across Switch TA Operating Temperature Range, All Package Types ­ 55 tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V ns/V 0 0 100 20 *For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. v v MC74LVX8053 MC74LVX8053 DC CHARACTERISTICS - Digital Section (Voltages Referenced to GND) Symbol Parameter Guaranteed Limit VCC V Condition ­55 to 25°C 85°C 125°C Unit VIH Minimum High­Level Input Voltage, Channel­Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 5.5 1.50 2.10 3.15 3.85 1.50 2.10 3.15 3.85 1.50 2.10 3.15 3.85 V VIL Maximum Low­Level Input Voltage, Channel­Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 5.5 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 V Iin Maximum Input Leakage Current, Channel­Select or Enable Inputs Vin = VCC or GND, 5.5 ± 0.1 ± 1.0 ± 1.0 µA Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VIS = VCC or GND; VIO = 0 V 5.5 4 40 160 µA ICC DC ELECTRICAL CHARACTERISTICS Analog Section ÎÎÎ Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î ÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit ­ 55 to 25_C Vin = VIL or VIH VIS = VCC to GND |IS| 10.0 mA (Figures 1, 2) 3.0 4.5 5.5 40 30 25 45 32 28 50 37 30 Vin = VIL or VIH VIS = VCC or GND (Endpoints) |IS| 10.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = 1/2 (VCC ­ GND) |IS| 10.0 mA Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 3) 3.0 4.5 5.5 30 25 20 35 28 25 40 35 30 15 8.0 8.0 20 12 12 25 15 15 v 3.0 4.5 5.5 5.5 0.1 0.5 1.0 µA Maximum Off­Channel Leakage Current, Common Channel Ron VCC V v Symbol Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 4) 5.5 0.1 1.0 2.0 Maximum On­Channel Leakage Current, Channel­to­Channel Vin = VIL or VIH; Switch­to­Switch = VCC or GND; (Figure 5) 5.5 0.1 1.0 2.0 Parameter Maximum "ON" Resistance Test Conditions v Ron Ioff Ion Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum Off­Channel Leakage Current, Any One Channel http://onsemi.com 3 v 85_C v 125_C Unit µA MC74LVX8053 MC74LVX8053 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns) Guaranteed Limit VCC V ­55 to 25°C 85°C 125°C Unit Maximum Propagation Delay, Channel­Select to Analog Output (Figure 9) 2.0 3.0 4.5 5.5 30 20 15 15 35 25 18 18 40 30 22 20 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 3.0 4.5 5.5 4.0 3.0 1.0 1.0 6.0 5.0 2.0 2.0 8.0 6.0 2.0 2.0 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 5.5 30 20 15 15 35 25 18 18 40 30 22 20 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 5.5 20 12 8.0 8.0 25 14 10 10 30 15 12 12 ns Symbol Parameter tPLH, tPHL Cin Maximum Input Capacitance, Channel­Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF Common O/I 50 50 50 Feedthrough 1.0 1.0 1.0 (All Switches Off) CPD Typical @ 25°C, VCC = 5.0 V Power Dissipation Capacitance (Figure 13)* 45 * Used to determine the no­load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . http://onsemi.com 4 pF MC74LVX8053 MC74LVX8053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol BW - Parameter VCC V Condition fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm t 0dB at VOS; I Increase fin Frequency Until dB F U til Meter Reads ­3dB; RL = 50, CL = 10pF 3.0 4.5 5.5 Off­Channel Feedthrough Isolation (Figure 7) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF 3.0 4.5 5.5 ­50 ­50 ­50 3.0 4.5 5.5 ­37 ­37 ­37 3.0 4.5 5.5 25 105 135 3.0 4.5 5.5 35 145 190 3.0 4.5 5.5 ­50 ­50 ­50 3.0 4.5 5.5 ­60 ­60 ­60 Feedthrough Noise. Channel­Select Input to Common I/O (Figure 8) Vin 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600, CL = 50pF Crosstalk Between Any Two Switches (Figure 12) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF fin = 1.0MHz, RL = 50, CL = 10pF THD Unit 120 120 120 RL = 10k, CL = 10pF - 25°C Maximum On­Channel Bandwidth or Mi i Minimum Frequency Response F R (Figure 6) fin = 1.0MHz, RL = 50, CL = 10pF - Limit* Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10k, CL = 50pF THD = THDmeasured ­ THDsource VIS = 2.0VPP sine wave VIS = 4.0VPP sine wave VIS = 5.5VPP sine wave 3.0 4.5 5.5 45 Ron , ON RESISTANCE (OHMS) 40 35 125°C 85°C 25°C 25 20 ­ 55°C 15 10 5 00 1.0 2.0 3.0 VIN, INPUT VOLTAGE (VOLTS) Figure 1a. Typical On Resistance, VCC = 3.0 V http://onsemi.com 5 dB mVPP dB % *Limits not tested. Determined by design and verified by qualification. 30 MHz 4.0 0.10 0.08 0.05 MC74LVX8053 MC74LVX8053 30 25 125°C 85°C 20 25°C 15 ­ 55°C Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 30 10 5 0 25 125°C 85°C 20 25°C ­ 55°C 15 10 5 0 1.0 2.0 3.0 4.0 0 5.0 0 1.0 2.0 Figure 1b. Typical On Resistance, VCC = 4.5 V 4.0 5.0 Figure 1c. Typical On Resistance, VCC = 5.5 V PLOTTER PROGRAMMABLE POWER SUPPLY ­ 3.0 VIN, INPUT VOLTAGE (VOLTS) VIN, INPUT VOLTAGE (VOLTS) MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND GND Figure 2. On Resistance Test Set­Up http://onsemi.com 6 6.0 MC74LVX8053 MC74LVX8053 VCC VCC VCC 16 GND ANALOG I/O OFF A VCC VIH OFF VIH 6 8 Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set­Up VCC Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set­Up VCC 16 A VCC 16 0.1µF fin ON VOS dB METER ON N/C COMMON O/I OFF VCC COMMON O/I 6 8 GND OFF VCC COMMON O/I OFF NC VCC 16 GND RL CL* ANALOG I/O VIL 6 6 8 8 *Includes all probe and jig capacitance Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set­Up VCC 16 VIS 0.1µF fin VCC 16 VOS dB METER OFF RL Figure 6. Maximum On Channel Bandwidth, Test Set­Up CL* RL ON/OFF COMMON O/I ANALOG I/O RL OFF/ON RL RL 6 6 8 VIL or VIH VCC GND CHANNEL SELECT Vin 1 MHz tr = tf = 3 ns 8 TEST POINT CL* VCC 11 CHANNEL SELECT *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 7. Off Channel Feedthrough Isolation, Test Set­Up Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set­Up http://onsemi.com 7 MC74LVX8053 MC74LVX8053 VCC 16 VCC VCC CHANNEL SELECT ON/OFF 50% COMMON O/I ANALOG I/O OFF/ON GND tPLH TEST POINT CL* tPHL 6 ANALOG OUT 50% 8 CHANNEL SELECT *Includes all probe and jig capacitance Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set­Up Channel Select to Analog Out VCC 16 ANALOG IN COMMON O/I ANALOG I/O VCC ON 50% TEST POINT CL* GND tPHL tPLH ANALOG OUT 6 8 50% *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In to Analog Out tf tr 90% 50% 10% ENABLE tPZL ANALOG OUT Figure 10b. Propagation Delay, Test Set­Up Analog In to Analog Out tPLZ 1 VCC 2 GND 1 50% TEST POINT ON/OFF CL* VOL ENABLE 90% 1k ANALOG I/O 2 tPZH tPHZ ANALOG OUT VCC 16 VCC HIGH IMPEDANCE 10% POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL VOH 50% 6 8 HIGH IMPEDANCE Figure 11a. Propagation Delays, Enable to Analog Out Figure 11b. Propagation Delay, Test Set­Up Enable to Analog Out http://onsemi.com 8 MC74LVX8053 MC74LVX8053 VCC VIS A VCC 16 RL fin 16 VOS ON COMMON O/I ON/OFF NC ANALOG I/O 0.1µF OFF/ON OFF RL RL CL* RL CL* VCC 6 6 8 8 CHANNEL SELECT 11 *Includes all probe and jig capacitance Figure 12. Crosstalk Between Any Two Switches, Test Set­Up Figure 13. Power Dissipation Capacitance, Test Set­Up 0 VIS VCC 16 0.1µF fin ­ 10 VOS ON CL* TO DISTORTION METER ­ 30 ­ 40 dB RL FUNDAMENTAL FREQUENCY ­ 20 ­ 50 DEVICE ­ 60 6 SOURCE ­ 70 8 ­ 80 ­ 90 *Includes all probe and jig capacitance ­ 100 1.0 2.0 3.125 FREQUENCY (kHz) Figure 14a. Total Harmonic Distortion, Test Set­Up Figure 14b. Plot, Harmonic Distortion APPLICATIONS INFORMATION connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC ­ GND = 2 to 6 volts When voltage transients above VCC and/or below GND are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping. The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swing is determined by the supply voltages VCC. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In this example, the difference between VCC and GND is five volts. Therefore, using the configuration of Figure 15, a maximum analog signal of five volts peak­to­peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not http://onsemi.com 9 MC74LVX8053 MC74LVX8053 VCC +5V 16 +5V ANALOG SIGNAL 0V ON Dx +5V ANALOG SIGNAL VCC 16 VCC Dx ON/OFF 0V 8 Dx VEE 6 Dx VEE TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS 11 10 9 8 Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes +5V +5V 16 +5V ANALOG SIGNAL GND ON/OFF 6 8 ANALOG SIGNAL +5V * R R 11 10 9 +5V +5V GND GND 16 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL R GND +5V 6 LSTTL/NMOS CIRCUITRY 8 * 2K R 10K 11 10 9 LSTTL/NMOS CIRCUITRY VHC1GT50 VHC1GT50 BUFFERS a. Using Pull­Up Resistors b. Using HCT Interface Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs A 11 13 LEVEL SHIFTER 12 14 B 10 1 LEVEL SHIFTER 2 15 C 9 3 LEVEL SHIFTER 5 4 ENABLE 6 LEVEL SHIFTER Figure 18. Function Diagram, LVX8053 LVX8053 http://onsemi.com 10 X1 X0 X Y1 Y0 Y Z1 Z0 Z MC74LVX8053 MC74LVX8053 MARKING DIAGRAMS (Top View) 16 15 14 13 12 11 10 16 15 14 13 12 11 10 9 9 LVX LVX8053 LVX8053 8053 AWLYWW* 1 2 3 4 ALYW* 5 6 7 8 1 16­LEAD SOIC D SUFFIX CASE 751B 2 3 4 5 6 7 8 16­LEAD TSSOP DT SUFFIX CASE 948F *See Applications Note #AND8004/D AND8004/D for date code and traceability information. PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B­05 ISSUE J ­A ­ 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. ­B ­ P 8 PL 0.25 (0.010) M B M G K F R X 45° C ­T SEATING ­ PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 11 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0° 7° 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7° 0° 0.229 0.244 0.010 0.019 MC74LVX8053 MC74LVX8053 PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F­01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K K1 L/2 ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ ÇÇ 2X 16 9 J1 B ­U­ L SECTION N­N J PIN 1 IDENT. 8 1 N 0.25 (0.010) 0.15 (0.006) T U S A ­V­ NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE ­W­. M N F DETAIL E ­W­ C 0.10 (0.004) ­T­ SEATING PLANE H D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 ­­­ 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 ­­­ 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ G ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). 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