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Part : 74LVX273M Supplier : ON Semiconductor Manufacturer : Avnet Stock : - Best Price : €0.2567 Price Each : €0.3640
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Part : 74LVX273MTC Supplier : Fairchild Semiconductor Manufacturer : Bristol Electronics Stock : 434 Best Price : - Price Each : -
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LVX273

Catalog Datasheet MFG & Type PDF Document Tags

LVX273

Abstract: KFIR LVX273 S 3 National ÆÆ Semiconductor 74LVX273 Low Voltage Octal D Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-tlops with individual D inputs and Q outputs. The , 74LVX273SJ 74LVX273SJX M20D SSOP TYPE 1 74LVX273MSCX MSC20 8-52 LVX273 Mode Select-Function , operations and should not be used to estimate propagation delays. 8-53 LVX273 Absolute Maximum , 2.0 0.8 Note: Input tr = if = 3 ns 8-54 LVX273 AC Electrical Characteristics: Symbol
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KFIR

LVX273

Abstract: LCX08 , LVXU04, LVX05, LVX 14 LVX125, LVX 126, LVX240, LVX244, LVX541 LVX245 LVX74, LVX174, LVX273 LVX374, LVX574
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LCX08 LCX32 LCX04 LCX74 LVX123 lvx00 LCX02 LCX86 LCX240

74LVX 244 D

Abstract: , LVX174, LVX273 LVX374 LVX373, LVX573 LVX138 LVX157 GATE NAND NO R AND OR INVERTER, BUFFER EXCLUSIVE
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74LVX 244 D 74LVQ TC74LVQ 74LVX LVX02 LVX32 LVX86

LVX165

Abstract: lvx161284 HC Portfolio Comparison PART # LVX00 LVX02 LVX04 LVXU04 LVX05 LVX06 LVX07 LVX08 LVX10 LVX11 LVX14 LVX20 LVX21 LVX27 LVX32 LVX50 LVX74 LVX86 LVX107 LVX109 LVX112 LVX123 LVX125 LVX126 LVX132 LVX138 LVX139 LVX153 LVX154 LVX157 LVX158 LVX161 LVX163 LVX164 LVX165 LVX166 LVX174 LVX175 LVX221 LVX240 LVX241 LVX244 LVX245 LVX251 LVX257 LVX259 LVX273 LVX365 LVX367 LVX368 LVX373 LVX374 LVX377 LVX393 LVX540 LVX541 FUNCTION Quad 2-Input NAND Gate Quad 2
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MC74LVX3245 MC74LVXC4245 lvx161284 MC74LVX2 74lv139 applications MC74LVX573 MC74LVX574 74LV573 74LV574 MC74LVX595

74LVX273

Abstract: 74LVX273M Revised April 2005 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance The register
Fairchild Semiconductor
Original
MS-013 MTC20 M20D MO-153

74LVX273

Abstract: 74LVX273M Revised September 2003 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance The register
Fairchild Semiconductor
Original

lcx74

Abstract: 74LCX , LVX273 L V X374 3-STATE LCX374, LCX574, LCX16374A, LVQ 374 LATCH 3-STATE LCX373, LCX573
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74LCX 241FF lcx16373A TC74LCX 16-BIT 16-BI LCX125 LCX244

74LVX273

Abstract: 74LVX273M Revised March 1999 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be
Fairchild Semiconductor
Original

LVX273

Abstract: 74LVX273 co r-CM X > ^^ National Semiconductor 74LVX273 Low Voltage Octal D Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be
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TL/F/11614-1 SG1125

74LVX273

Abstract: 74LVX273M 74LVX273 Low Voltage Octal D Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop's Q output All outputs will be forced LOW independently of Clock or Data
National Semiconductor
Original

74LVX273

Abstract: 74LVX273M FAIRCHILD h1QQQ Revised March 1999 SEMiCONDUCTDRM 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q
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MD-153

74LVX273

Abstract: 74LVX273M 74LVX273 Low Voltage Octal D Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or
Fairchild Semiconductor
Original

LVX273

Abstract: 74LVX273 FAIRCHILD emicdnductor t February 1998 74LVX273 Low Voltage Octal D Flip-Flop General Description The LVX273 has eight edge-triggered D-lype flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be
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DIODE SJ 98

LVX273

Abstract: P013L IMMUNITY DESCRIPTION The LVX273 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated
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74LVX273T P013L SO-20 TSSOP20

LVX273

Abstract: 74LVX273 IMMUNITY DESCRIPTION The LVX273 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated
STMicroelectronics
Original
Abstract: A I R C H June 1993 I L D Revised March 1999 SEM [CONDUCTOR T M 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The -
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D-153

B5011A

Abstract: Box58090 tSüllEB 007flflSl ^a? NSC1 January 1994 74LVX273 L o w Voltage Octal D Flip-Flop gg National ÆÆ Semiconductor 74LVX273 Low Voltage Octal D Flip-Flop General Description The ' LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D in put, one setup time before the LOW-to-HIGH clock tran
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B5011A Box58090 MSC 5511 D-8060

HC165A

Abstract: TC9525F Series) * X 4 1 LVQ74 FLIP-FLOPS LVQ174 LVQ273, LVQ374 LVX74 LVX174 LVX273, LVX374 LATCHES
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HC137A HCT164A HC165A HC4520A TC9525F VHC165 HC4050A TC9534N TC5090AP TC5091AP TC5092AP TC5093AP TC35094P TC35095AP/AF
Abstract: 74LVX273 L o w Voltage Octal D Flip-Flop February 1998 FAIRCHILD S E M IC O N D U C T O R 74LVX273 Low Voltage Octal D Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-tlops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D in put, one setup time before the LOW-to-HIGH clock transi tion, is transferred to the -
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2314-006I

ic dg 211

Abstract: 74LVX273 FAIRCHILD SEMICONDUCTOR T M June 1993 Revised March 1999 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q o utp uts. The com m on buffered C lock (CP) and M aster R eset (MR) input load and reset (clear) all flip-flops sim ultaneously. The register is fu lly edge-triggered. The state of each D input, one setup tim e before th e LOW -to-H IG H clock tra n si tion, is transferred to the
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ic dg 211 S-013 O-153

74HC273

Abstract: 74HC273 Toshiba LVX273 S 3 National ÆÆ Semiconductor 74LVX273 Low Voltage Octal D Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-tlops with individual D inputs and Q outputs. The , 74LVX273SJ 74LVX273SJX M20D SSOP TYPE 1 74LVX273MSCX MSC20 8-52 LVX273 Mode Select-Function , operations and should not be used to estimate propagation delays. 8-53 LVX273 Absolute Maximum , 2.0 0.8 Note: Input tr = if = 3 ns 8-54 LVX273 AC Electrical Characteristics: Symbol
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74HC273 74HC273 Toshiba TC74LVX273F TC74LVX273FW TC74LVX273FT TC74LVX273 150MH TSSOP20-P-0044-0
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