EP2C70 PT-EP2C70-1 DQ1L10 DQ1L11 DQ1L12 DQ1L13 DQ1L16 DQ1L14 DQ1L15 DQ1L17 - Datasheet Archive

 

Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2

 

Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 GND_PLL3 VCCD_PLL3 GND_PLL3 GND IO IO IO IO IO IO VCCIO2 IO IO IO IO IO IO GND IO IO IO IO IO VCCIO2 IO IO IO IO IO IO IO GND IO IO IO IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) F672 F896 E4 H7 G7 K10 J9 J8 E3 D3 B2 B3 E5 F6 G7 K9 H7 H8 G5 G6 C2 C3 G5 G6 LVDS66p LVDS66n F3 F4 H5 H6 G3 G4 LVDS65p LVDS65n LVDS64p LVDS64n LVDS63p E3 E4 B2 C3 C1 ASDO nCSO LVDS68p LVDS68n PLL3_OUTp PLL3_OUTn LVDS67p LVDS67n VREFB2N0 Configuration Function ASDO nCSO CRC_ERROR CLKUSR F3 F4 D2 LVDS63n LVDS62p LVDS62n LVDS61p LVDS61n LVDS60p LVDS60n D1 F7 H6 J5 E2 E1 K6 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 C2 D2 D3 H3 H4 J7 J6 VREFB2N1 LVDS59p LVDS59n LVDS58p DQS for x8/x9 in F672 J5 K8 K7 L8 J8 J7 EP2C70 EP2C70 Pin List Page 1 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 IO VCCIO2 IO IO IO IO IO IO IO IO GND IO IO VCCIO2 IO IO IO IO IO IO GND IO GND IO IO IO VCCIO2 IO IO IO IO IO IO IO GND IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 LVDS58n K5 L7 LVDS57p LVDS57n LVDS56p LVDS56n LVDS55p LVDS55n LVDS54p LVDS54n G4 G3 J6 K8 K7 F2 F1 L10 L9 K6 K5 L6 L5 M9 M8 DQ2L0 DQ2L1 DQ2L2 DQ2L3 DQ2L4 DQ1L0 DQ1L1 DQ1L2 DQ1L3 DQ1L4 LVDS53p LVDS53n G1 G2 E1 E2 CDPCLK0/DQS2L CDPCLK0/DQS2L CDPCLK0/DQS2L LVDS52p LVDS52n LVDS51p LVDS51n LVDS50p LVDS50n H3 H4 J3 J4 H2 H1 F1 F2 G1 G2 H1 H2 DQ2L5 DQ2L6 DQ2L7 DQ1L5 DQ1L6 DQ1L7 DQ1L8 DM1L0/BWS#1L0 DQ2L0 DQ2L1 DQ2L2 DQ2L3 DQ2L4 DQ2L5 LVDS49p J2 K3 LVDS49n LVDS48p LVDS48n J1 K4 K3 K4 N10 M10 K1 K2 L4 M6 M7 J1 J2 M5 L3 L4 LVDS47p LVDS47n LVDS46p LVDS46n VREFB2N2 LVDS45p LVDS45n LVDS44p Configuration Function DM2L DQS for x16/x18 in F896 CDPCLK0/DQS2L DQ2L6 DQ0L0 DQ0L1 DQ0L2 DQ0L3 DQ0L4 DQ1L9 DQ1L10 DQ1L10 DQ1L11 DQ1L11 DQ1L12 DQ1L12 DQ1L13 DQ1L13 DQ2L7 DM2L DQ1L0 DQ1L1 DQ1L2 DQ1L3 DQ1L4 K1 EP2C70 EP2C70 Pin List Page 2 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 GND IO IO IO IO VCCIO2 IO IO IO IO IO IO GND IO IO IO IO VCCIO2 IO GND IO GND IO VCCIO2 IO IO IO TDI TCK TMS TDO DCLK DATA0 nCE CLK0 CLK1 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 LVDS44n LVDS43p LVDS43n LVDS42p F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 K2 N8 N7 L1 LVDS42n LVDS41p LVDS41n LVDS40p LVDS40n LVDS39p L7 L6 L2 L2 P9 N9 M1 M2 M3 LVDS39n LVDS38p LVDS38n L3 M4 P6 DQ0L5 DQ0L6 DQ0L7 DQ1L16 DQ1L16 DQ1L8 DM1L0/BWS#1L0 DQ1L14 DQ1L14 DQ1L15 DQ1L15 DQ0L0 DQ0L1 DQ1L9 DQ1L10 DQ1L10 DQ1L17 DQ1L17 DQ0L2 DQ0L3 DQ0L4 DQ1L11 DQ1L11 DQ1L12 DQ1L12 DQ1L13 DQ1L13 DM1L1/BWS#1L1 DQ0L5 DQ1L14 DQ1L14 DQ0L6 DQ1L15 DQ1L15 DQ0L7 DPCLK0/DQS0L DQ1L16 DQ1L16 DPCLK0/DQS0L N4 M5 DQ1L5 DQ1L6 DQ1L7 M4 N2 N3 P7 VREFB2N3 DQS for x16/x18 in F896 LVDS37p P3 LVDS37n LVDS36p LVDS36n DCLK DATA0 LVDSCLK0p/input(3) LVDSCLK0n/input(3) DM0L TDI TCK TMS TDO DCLK DATA0 nCE M3 M2 M8 M6 L8 M7 N6 N3 N4 N2 N1 P4 P1 P2 P8 P5 R7 R4 R9 R8 R6 R2 R3 DPCLK0/DQS0L EP2C70 EP2C70 Pin List DPCLK0/DQS0L Page 3 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B2 B2 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB2N3 VREFB2N3 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 GND nCONFIG CLK2 CLK3 VCCIO1 IO IO IO IO GND IO GND IO GND IO IO IO IO IO VCCIO1 IO IO IO GND IO GND IO IO IO IO VCCIO1 IO IO IO IO IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 F896 nCONFIG LVDSCLK1p/input(3) LVDSCLK1n/input(3) N7 P2 P1 R5 T2 T3 LVDS35p LVDS35n LVDS34p LVDS34n P3 P4 R2 R3 LVDS33p R4 LVDS33n DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 T6 T7 T4 T5 DPCLK1/DQS1L DPCLK1/DQS1L DPCLK1/DQS1L DPCLK1/DQS1L DQ1L0 DQ1L1 DQ3L0 DQ3L1 DM0L DQ1L17 DQ1L17 DM1L1/BWS#1L1 U1 DQ1L2 DQ3L2 DQ1L3 DQ1L4 DQ3L3 DQ3L4 DQ1L0 DQ1L1 DQ1L2 DQ3L0 DQ3L1 DQ3L2 DQ1L5 DQ1L6 DQ3L5 DQ3L6 DQ1L3 DQ1L4 DQ3L3 DQ3L4 DQ1L5 DQ3L5 DQ1L6 DQ1L7 DQ3L6 DQ3L7 DQ1L8 DM1L/BWS#1L DQ3L8 DM3L0/BWS#3L0 U2 VREFB1N0 LVDS32p LVDS32n LVDS31p LVDS31n R5 LVDS30p LVDS30n LVDS29p T2 T3 P7 P6 LVDS29n U5 T9 T8 U9 U8 U6 U7 U3 U4 LVDS28p LVDS28n LVDS27p LVDS27n R6 R7 V2 V3 W1 W2 VREFB1N1 LVDS26p LVDS26n LVDS25p LVDS25n T4 U2 U1 U3 U4 V4 W3 W4 Y1 Y2 DQ1L7 DQ1L8 DQ3L7 DQ3L8 DM1L/BWS#1L DM3L0/BWS#3L0 EP2C70 EP2C70 Pin List Page 4 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 IO GND IO IO IO IO IO VCCIO1 IO IO IO IO IO IO IO GND IO IO IO IO IO VCCIO1 IO IO IO IO IO IO GND IO GND IO IO IO IO VCCIO1 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. F672 F896 LVDS24p V1 Y3 LVDS24n LVDS23p LVDS23n LVDS22p LVDS22n V2 T7 T6 V4 V3 Y4 V10 V9 V8 V7 LVDS21p LVDS21n LVDS20p LVDS20n LVDS19p LVDS19n W2 W1 LVDS18p LVDS18n LVDS17p LVDS17n U6 U7 U5 W4 W3 W9 W10 W6 W8 W7 LVDS16p LVDS16n LVDS15p LVDS15n LVDS14p Y2 Y1 V5 V6 AA2 Y5 AC1 AC2 AC3 AC4 AD1 DQ3L5 DQ3L6 DQ3L7 DQ3L8 LVDS14n AA1 AD2 DM3L/BWS#3L LVDS13p LVDS13n LVDS12p LVDS12n Configuration Function W5 AA1 AA2 AA3 AA4 AB1 AB2 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQ3L0 DQ3L1 DQS for x16/x18 in F896 DQ3L9 DQ3L10 DQ3L10 DQ3L0 DQ3L1 DQ3L10 DQ3L10 DQ3L2 DQ3L3 DQ3L4 CDPCLK1/DQS3L DQ3L11 DQ3L11 DQ3L12 DQ3L12 DQ3L13 DQ3L13 CDPCLK1/DQS3L DQ3L5 DQ3L2 DQ3L3 DQ3L4 CDPCLK1/DQS3L DQ3L9 DQ3L14 DQ3L14 DQ3L14 DQ3L14 DQ3L15 DQ3L15 DQ3L16 DQ3L16 DQ3L17 DQ3L17 DQ3L6 DQ3L7 DQ3L15 DQ3L15 DQ3L16 DQ3L16 DQ3L8 DQ3L17 DQ3L17 DM3L1/BWS#3L1 DM3L/BWS#3L DM3L1/BWS#3L1 DQ3L11 DQ3L11 DQ3L12 DQ3L12 DQ3L13 DQ3L13 CDPCLK1/DQS3L AD3 AD4 AA5 AA6 EP2C70 EP2C70 Pin List Page 5 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 IO IO IO IO IO IO GND IO GND IO IO IO IO IO VCCIO1 IO IO IO IO IO IO GND IO IO IO IO IO VCCIO1 IO IO IO IO IO IO IO GND LVDS11p LVDS11n VREFB1N2 LVDS10p LVDS10n LVDS9p PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 Y3 Y4 W6 V7 Y9 Y10 Y6 Y7 Y8 AE1 LVDS9n DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 AE2 AA7 AB6 AB5 AC6 AC5 LVDS8p LVDS8n LVDS7p LVDS7n AB2 AB1 AA4 AA3 LVDS6p LVDS6n LVDS5p LVDS5n LVDS4p LVDS4n AC2 AC1 AF1 AF2 AG2 AG3 AH1 AH2 VREFB1N3 AA5 Y5 AD2 AD3 AE2 AD5 AA8 AE3 AE4 AF3 AE3 AB3 AB4 AF4 AA9 AA10 AB7 AC7 AD6 AD7 LVDS3p LVDS3n LVDS2p LVDS2n LVDS1p LVDS1n LVDS0p LVDS0n PLL1_OUTp PLL1_OUTn AC3 AA7 AA6 EP2C70 EP2C70 Pin List Page 6 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B1 B1 B1 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB1N3 VREFB1N3 VREFB1N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N3 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 GND_PLL1 VCCD_PLL1 GND_PLL1 VCCA_PLL1 GNDA_PLL1 GND IO IO IO IO IO IO VCCIO8 IO GND IO IO IO GND IO IO IO IO VCCIO8 IO GND IO IO IO GND IO IO IO VCCIO8 IO GND PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) F672 F896 W7 Y7 Y6 AA8 Y8 AB8 AB9 AC8 AC9 AC10 AE4 AF4 AC5 AC6 AD4 AD5 AE8 AE7 AG4 AG5 AJ2 AH3 DM1B DQ1B7 DQ1B6 DQ1B5 DQ1B4 LVDS253p AE5 AK3 CDPCLK2/DQS1B LVDS253n AF5 AD6 AD7 AJ3 AD8 AH5 DQ1B3 LVDS256n LVDS256p LVDS255p LVDS255n LVDS254p LVDS254n VREFB8N3 Configuration Function DEV_OE DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 DM1B DQ1B7 DQ1B6 CDPCLK2/DQS1B CDPCLK2/DQS1B LVDS252p LVDS252n LVDS251p LVDS251n AG6 AF7 AJ4 AH4 DQ1B5 DQ1B4 LVDS250p AK5 DQ1B2 LVDS250n LVDS249p LVDS249n AJ5 AG8 AF8 DQ1B1 LVDS248p LVDS248n VREFB8N2 CDPCLK2/DQS1B AH7 AG7 AF9 LVDS247p AC7 DQ1B3 DQ1B0 AK6 EP2C70 EP2C70 Pin List Page 7 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 IO GND IO IO IO IO VCCIO8 IO GND IO IO IO GND IO IO IO VCCIO8 IO GND IO IO GND IO IO IO IO VCCIO8 IO GND IO IO IO GND IO IO IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 LVDS247n Y10 AJ6 DQ1B2 LVDS246p LVDS246n LVDS245p AB8 AC8 AD8 AE6 AD9 AC11 AD10 AK7 DQ1B1 DQ1B0 DM3B/BWS#3B DQ3B8 DM3B1/BWS#3B1 DQ3B17 DQ3B17 DM3B/BWS#3B DM3B1/BWS#3B1 LVDS245n AF6 AJ7 DQ3B7 DQ3B16 DQ3B16 DQ3B8 DQ3B17 DQ3B17 LVDS244p LVDS244n AA9 AA10 AB10 AF10 DQ3B6 AC12 DQ3B5 AD11 DQ3B4 DQ3B15 DQ3B15 DQ3B14 DQ3B14 DQ3B13 DQ3B13 DQ3B7 DQ3B6 DQ3B5 DQ3B16 DQ3B16 DQ3B15 DQ3B15 DQ3B14 DQ3B14 LVDS243p LVDS243n LVDS242p AA11 Y11 AE7 AF11 AE11 AK8 DQ3B3 DQ3B2 DQ3B1 DQ3B12 DQ3B12 DQ3B11 DQ3B11 DQ3B10 DQ3B10 LVDS242n AF7 AJ8 DQ3B0 DQ3B9 DQ3B4 DQ3B13 DQ3B13 LVDS241p LVDS241n AH9 AG9 DQ3B3 DQ3B2 DQ3B12 DQ3B12 DQ3B11 DQ3B11 LVDS240p LVDS240n LVDS239p LVDS239n AE12 AD12 AH10 DPCLK2/DQS3B AG10 DQ3B1 DQ3B0 DPCLK2/DQS3B DQ3B10 DQ3B10 DQ3B9 DPCLK2/DQS3B AE8 AF8 LVDS238p LVDS238n LVDS237p LVDS237n VREFB8N1 LVDS236p DPCLK2/DQS3B AK9 AC9 AJ9 AK10 AJ10 AC10 AF12 AB12 AE9 AK11 DM3B0/BWS#3B0 DM5B/BWS#5B DM3B0/BWS#3B0 DQ3B8 DQ3B7 DQ5B8 DQ3B8 DQ3B6 EP2C70 EP2C70 Pin List Page 8 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 IO VCCIO8 GND IO IO IO GND IO IO IO VCCIO8 IO GND IO IO GND IO IO IO VCCIO8 IO GND IO IO GND IO IO VCCIO8 IO GND IO IO GND IO CLK15 CLK15 CLK14 CLK14 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 LVDS236n AF9 AJ11 DQ5B7 DQ3B7 DQ3B5 LVDS235p LVDS235n AD10 AE13 DQ5B6 AC11 AD13 DQ5B5 AC13 DQ3B6 DQ3B5 DQ3B4 DQ3B3 DQ3B2 LVDS234p LVDS234n AB12 AE10 AF10 DQ3B2 DQ3B4 DQ3B3 DQ3B1 DQ3B0 LVDS233p AD11 AK12 LVDS233n AE11 VREFB8N0 AB13 DQ5B2 AH12 DQ5B4 AG12 DQ5B3 DQ5B1 DQ3B1 DM5B/BWS#5B DM5B1/BWS#5B1 AJ12 DQ5B0 AD14 DQ3B0 DQ5B8 DQ5B17 DQ5B17 LVDS232p AC12 AG13 AC14 AG14 DQ5B7 DQ5B16 DQ5B16 LVDS232n AF14 DQ5B6 DQ5B15 DQ5B15 DM5B1/BWS#5B1 DQ5B17 DQ5B17 DQ5B5 DQ5B4 DQ5B14 DQ5B14 DQ5B13 DQ5B13 DQ5B16 DQ5B16 DQ5B15 DQ5B15 DQ5B3 DQ5B2 DQ5B12 DQ5B12 DQ5B11 DQ5B11 DQ5B1 DQ5B10 DQ5B10 DQ5B0 DPCLK3/DQS5B DQ5B9 DPCLK3/DQS5B LVDS231p LVDS231n AA12 Y12 LVDS230p LVDS230n AD12 AJ13 DQ4B7 AE12 AH13 DQ4B6 LVDS229p AF15 AE15 DM4B AK14 LVDS229n LVDS228p AE13 AJ14 AJ15 LVDS228n LVDSCLK7p/input(3) LVDSCLK7n/input(3) AF13 AH15 AC13 AG15 AD13 AH14 DPCLK3/DQS5B EP2C70 EP2C70 Pin List DPCLK3/DQS5B Page 9 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N3 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 CLK13 CLK13 CLK12 CLK12 IO VCCIO7 IO GND IO GND IO IO IO IO IO IO VCCIO7 IO GND IO GND IO IO IO IO VCCIO7 IO GND GND IO IO IO IO VCCIO7 IO GND IO GND PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 DQS for x8/x9 in F672 LVDSCLK6p/input(3) LVDSCLK6n/input(3) LVDS227p AF14 AE14 AE15 AD15 AC15 AJ16 DPCLK4/DQS4B LVDS227n DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 DPCLK4/DQS4B DPCLK4/DQS4B DPCLK4/DQS4B AD15 AH16 DM4B DM5B0/BWS#5B0 AC14 AE16 LVDS226p LVDS226n VREFB7N3 LVDS225p LVDS225n DQ4B5 DQ5B14 DQ5B14 AA13 Y13 AA14 Y14 Y15 AA15 DQ4B4 DQ4B3 DQ5B13 DQ5B13 DQ5B12 DQ5B12 DQ4B2 DQ4B1 DQ4B0 DQ5B11 DQ5B11 DQ5B10 DQ5B10 DQ5B9 AD16 AC16 AG16 AF16 AH17 AG17 DQ5B8 DQ4B7 DQ4B6 DQ5B7 DQ5B6 AE17 DQ4B5 DQ5B5 AK17 DQ4B4 DQ5B4 DQ4B3 DQ4B2 DQ4B1 DQ4B0 DQ5B3 DQ5B2 DQ5B1 DQ5B0 LVDS224p AB15 LVDS224n LVDS223p LVDS223n LVDS222p AC15 AJ17 DM2B AD17 AC17 AJ18 LVDS222n AH18 LVDS221p LVDS221n VREFB7N2 LVDS220p AE16 AD16 AC16 AF17 AK19 AJ19 AF17 AK20 LVDS220n AE17 AJ20 LVDS219p DM5B0/BWS#5B0 DQ2B7 DQ5B8 DQ5B7 DQ2B6 DQ5B6 DQ2B5 DQ5B5 AH19 EP2C70 EP2C70 Pin List DM2B DQ2B7 Page 10 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 IO IO IO IO IO VCCIO7 IO GND IO GND IO IO IO IO IO IO VCCIO7 GND GND IO IO IO IO IO IO VCCIO7 IO GND IO GND IO IO IO IO IO IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 LVDS219n LVDS218p LVDS218n LVDS217p LVDS217n AC17 AD17 AA16 Y16 AG19 AF18 AG18 AD18 AC18 DQ2B4 DQ2B3 DQ2B2 DQ2B1 DQ5B4 DQ5B3 DQ5B2 DQ5B1 LVDS216p AF18 AK21 DQ2B0 DQ5B0 LVDS216n AE18 AJ21 LVDS215p LVDS215n LVDS214p LVDS214n LVDS213p LVDS213n AG20 AF20 AF19 AK22 DPCLK5/DQS2B AE19 AJ22 AB18 AB18 AC18 AB19 LVDS212p LVDS212n VREFB7N1 AA17 LVDS211p LVDS211n AA18 DQS for x16/x18 in F896 DQ2B6 DQ2B5 DQ2B4 DQ2B3 DQ2B2 DQ2B1 DQ2B0 DPCLK5/DQS2B DPCLK5/DQS2B DPCLK5/DQS2B AD19 AC19 AH20 AE19 AK23 AJ23 LVDS210p AK24 LVDS210n AJ24 LVDS209p LVDS209n LVDS208p LVDS208n LVDS207p LVDS207n AD19 AC19 AF20 AE20 AB20 AC20 AF21 AE20 AH22 AG22 AC20 AD20 DM0B DQ0B7 DQ0B6 DQ0B5 DQ0B4 EP2C70 EP2C70 Pin List Page 11 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B6 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB6N3 VCCIO7 IO GND IO GND IO IO IO IO IO IO VCCIO7 IO GND GND IO IO IO IO IO VCCIO7 IO GND IO IO VCCIO7 IO IO IO IO IO IO GND GNDA_PLL4 VCCA_PLL4 GND_PLL4 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) F672 F896 DQS for x8/x9 in F672 LVDS206p AF21 AK25 DQ0B3 LVDS206n AE21 AJ25 Y18 AA20 AG23 AF22 AK26 AJ26 AD22 AH24 DQ0B2 LVDS205p LVDS205n LVDS204p LVDS204n VREFB7N0 LVDS203p Configuration Function DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 DM0B DQ0B7 DQ0B6 LVDS203n AG24 DQ0B5 LVDS202p LVDS202n LVDS201p LVDS201n LVDS200p DQ0B4 DQ0B3 AF22 AG25 AH26 AD21 AC21 AK28 DQ0B1 LVDS200n AE22 AJ28 DQ0B0 LVDS199p LVDS199n AC21 AF23 AD21 AF24 LVDS198p LVDS198n LVDS197p LVDS197n LVDS196p LVDS196n AD23 AD22 AC22 AB21 AF23 AE23 AJ27 AH27 AG27 AG26 AE23 AE24 Y19 AA19 AA21 AD23 AC22 AA21 DQ0B2 DQ0B1 DQ0B0 CDPCLK3/DQS0B EP2C70 EP2C70 Pin List CDPCLK3/DQS0B CDPCLK3/DQS0B CDPCLK3/DQS0B Page 12 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N3 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VCCD_PLL4 GND_PLL4 GND IO IO IO IO IO IO IO VCCIO6 IO IO IO IO IO GND IO IO IO IO VCCIO6 IO IO IO IO GND IO GND IO IO IO IO IO VCCIO6 IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) PLL4_OUTn PLL4_OUTp VREFB6N3 LVDS193n LVDS193p INIT_DONE nCEO F672 F896 Y20 W20 LVDS195n LVDS195p LVDS194n LVDS194p Configuration Function AB22 AA22 AC23 AE25 AE24 AD25 AD24 AC24 V20 AB23 AD24 AD25 AC23 AC24 AB24 AF27 V21 Y21 Y22 W21 AF28 AD26 AD27 AC25 AC26 LVDS192n LVDS192p LVDS191n LVDS191p AA24 AA23 AB24 AB23 AC25 AC26 V22 AD28 LVDS188n LVDS188p LVDS187n LVDS187p LVDS186n AB26 AB25 Y24 Y23 AA25 AA24 AA23 AB25 AB26 AF29 LVDS186p AA26 DQS for x16/x18 in F896 AH30 AJ29 AE27 AE28 VREFB6N2 DQS for x16/x18 in DQS for x8/x9 in F672 F896 AG29 AG28 AH29 AH28 LVDS190n LVDS190p LVDS189n LVDS189p DQS for x8/x9 in F672 AF30 EP2C70 EP2C70 Pin List Page 13 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N2 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 IO IO IO GND IO IO IO IO IO IO IO VCCIO6 IO IO IO IO IO GND IO IO IO GND IO IO IO IO VCCIO6 IO IO IO IO IO GND IO IO IO LVDS185n LVDS185p PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. LVDS184n LVDS184p LVDS183n LVDS183p LVDS182n LVDS182p LVDS181n LVDS181p LVDS180n LVDS180p LVDS179n LVDS179p Configuration Function F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 Y26 Y25 U22 Y24 Y23 AA25 DM3R/BWS#3R DQ3R8 DQ3R7 DM3R1/BWS#3R1 DQ3R17 DQ3R17 DQ3R16 DQ3R16 DM3R/BWS#3R DQ3R8 DM3R1/BWS#3R1 DQ3R17 DQ3R17 DQ3R7 DQ3R16 DQ3R16 DQ3R6 DQ3R15 DQ3R15 DQ3R5 DQ3R14 DQ3R14 CDPCLK4/DQS3R DQ3R4 DQ3R3 DQ3R2 DQ3R1 CDPCLK4/DQS3R DQ3R13 DQ3R13 DQ3R12 DQ3R12 DQ3R11 DQ3R11 DQ3R10 DQ3R10 DQ3R0 DQ3R9 DM1R/BWS#1R DM3R0/BWS#3R0 DQ1R8 DQ3R8 DQ1R7 DQ1R6 DQ3R7 DQ3R6 W25 Y22 Y21 AC27 DQ3R6 AC28 DQ3R5 AE29 AE30 AD29 W26 V23 V24 V25 V26 AD30 AA26 AA27 W23 W24 W24 W23 LVDS178n LVDS178p CDPCLK4/DQS3R DQ3R13 DQ3R13 DQ3R12 DQ3R12 DQ3R11 DQ3R11 DQ3R10 DQ3R10 Y26 Y25 W26 LVDS177n LVDS177p LVDS176n LVDS176p U21 U20 LVDS175n LVDS175p VREFB6N1 U24 U23 T21 LVDS174n U25 LVDS174p U26 T20 LVDS173n CDPCLK4/DQS3R DQ3R4 DQ3R3 DQ3R2 DQ3R1 DQ3R15 DQ3R15 DQ3R14 DQ3R14 W22 DQ3R0 W21 AC29 AC30 W25 V24 AA28 V22 AB29 AB30 V21 Y28 DQ3R9 DM1R/BWS#1R DM3R0/BWS#3R0 DQ1R8 DQ3R8 DQ1R7 DQ1R6 DQ3R7 DQ3R6 EP2C70 EP2C70 Pin List Page 14 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N1 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 IO IO VCCIO6 IO IO IO IO IO IO GND IO GND IO GND IO IO IO IO VCCIO6 IO IO IO IO nSTATUS GND CONF_DONE GND MSEL1 MSEL0 IO IO VCCIO6 IO IO CLK7 CLK6 LVDS173p LVDS172n Y27 AA29 LVDS172p LVDS171n LVDS171p LVDS170n LVDS170p AA30 W27 W28 Y29 Y30 V23 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 T25 T24 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 DQ1R5 DQ1R4 DQ1R5 DQ1R4 DQ3R5 DQ3R4 DQ3R5 DQ3R4 LVDS169n W29 LVDS169p W30 DQ1R3 DQ3R3 LVDS168n LVDS168p VREFB6N0 V28 V29 V27 U25 DQ1R2 DQ3R2 DQ1R1 DQ1R0 DQ3R1 DQ3R0 T23 LVDS167n LVDS167p LVDS166n LVDS166p nSTATUS R20 R22 U24 U23 U29 U30 U26 CONF_DONE R23 U27 MSEL1 MSEL0 LVDS165n LVDS165p P21 P20 R24 R25 U28 U22 T28 T29 LVDS164n LVDS164p LVDSCLK3n/input(3) LVDSCLK3p/input(3) P24 P23 P26 P25 T27 T26 T25 T24 T22 DQ1R3 DQ3R3 DQ1R2 DQ3R2 DQ1R1 DQ1R0 DQ3R1 DQ3R0 DM0R DM1R1/BWS#1R1 DQ1R17 DQ1R17 DPCLK6/DQS1R DPCLK6/DQS1R DPCLK6/DQS1R DPCLK6/DQS1R EP2C70 EP2C70 Pin List Page 15 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N3 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 CLK5 CLK4 IO IO IO GND IO VCCIO5 IO IO IO IO GND IO GND IO IO IO IO IO VCCIO5 IO IO IO GND IO GND IO IO IO IO IO IO IO VCCIO5 IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 LVDSCLK2n/input(3) LVDSCLK2p/input(3) LVDS163n LVDS163p N26 N25 N24 N23 N21 R28 R29 T23 T22 R24 LVDS162n M25 R26 LVDS162p LVDS161n LVDS161p VREFB5N3 M24 R27 R23 R22 R25 M21 LVDS160n DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 DPCLK7/DQS0R DPCLK7/DQS0R DPCLK7/DQS0R DPCLK7/DQS0R DM0R DM1R1/BWS#1R1 DQ0R7 DQ1R16 DQ1R16 DQ1R17 DQ1R17 DQ0R6 DQ0R5 DQ1R15 DQ1R15 DQ1R14 DQ1R14 DQ0R4 DQ1R13 DQ1R13 P29 LVDS160p LVDS159n LVDS159p LVDS158n LVDS158p N20 DQ0R7 DQ1R16 DQ1R16 DQ0R3 DQ1R12 DQ1R12 M20 M19 P30 P28 P27 P26 P25 DQ0R6 DQ0R5 DQ1R15 DQ1R15 DQ1R14 DQ1R14 DQ0R2 DQ0R1 DQ0R0 DQ1R11 DQ1R11 DQ1R10 DQ1R10 DQ1R9 LVDS157n LVDS157p LVDS156n M23 M22 K26 P24 P23 N28 DQ0R4 DQ0R3 DQ0R2 DQ1R13 DQ1R13 DQ1R12 DQ1R12 DQ1R11 DQ1R11 LVDS156p K25 N29 DQ0R1 DQ1R10 DQ1R10 L19 L25 L24 DQ0R0 DQ1R9 LVDS153n LVDS153p N25 N24 M29 M30 P22 N22 N21 VREFB5N2 L23 M28 LVDS155n LVDS155p LVDS154n LVDS154p EP2C70 EP2C70 Pin List DM1R0/BWS#1R0 DQ1R8 DQ1R7 Page 16 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N2 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 IO GND IO GND IO IO IO IO IO IO IO VCCIO5 IO IO IO GND IO IO IO IO IO IO IO VCCIO5 IO IO IO GND IO GND IO IO IO IO IO IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 DQS for x8/x9 in F672 LVDS152n J26 L29 LVDS152p J25 L30 DQ1R6 LVDS151n LVDS151p LVDS150n LVDS150p L20 L21 K24 K23 K21 K19 H26 K29 K30 L28 L27 M26 M27 J29 DQ1R5 LVDS149p LVDS148n LVDS148p H25 LVDS147n LVDS147p LVDS146n LVDS146p LVDS145n LVDS145p DM2R DQ2R7 DQ2R6 DQ2R5 DM1R0/BWS#1R0 DQ1R8 DQ1R7 DQ1R6 DQ1R5 J30 M21 M22 DQ2R4 DQ1R4 J24 J23 H24 H23 G26 G25 K22 M23 N23 K27 K28 M25 M24 L26 DQ2R3 DQ2R2 DQ2R1 DQ2R0 DQ1R3 DQ1R2 DQ1R1 DQ1R0 DQ2R3 DQ2R2 DQ2R1 DQ2R0 CDPCLK5/DQS2R CDPCLK5/DQS2R CDPCLK5/DQS2R LVDS144n LVDS144p G24 G23 L22 L21 K26 LVDS143n F26 H29 LVDS143p F25 LVDS142n LVDS142p LVDS141n LVDS141p J20 J21 F23 F24 DQS for x16/x18 in F896 DQ2R4 H30 K23 L24 L25 G29 G30 LVDS149n DM2R DQS for x16/x18 in DQS for x8/x9 in F672 F896 EP2C70 EP2C70 Pin List DQ2R7 DQ2R6 DQ2R5 DQ1R4 DQ1R3 DQ1R2 DQ1R1 DQ1R0 CDPCLK5/DQS2R Page 17 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N1 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VCCIO5 IO IO IO IO IO GND IO IO IO IO IO IO IO VCCIO5 IO IO IO IO IO GND IO IO IO IO IO VCCIO5 IO IO IO IO IO IO GND GND_PLL2 VCCD_PLL2 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) F672 F896 VREFB5N1 LVDS140n LVDS140p LVDS139n LVDS139p J22 J26 K24 K25 F29 F30 LVDS138n LVDS138p LVDS137n LVDS137p LVDS136n LVDS136p D25 D26 LVDS135n LVDS135p LVDS134n LVDS134p Configuration Function E25 E26 C24 C25 B25 B24 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 H26 H27 H28 G27 G28 E29 E30 C30 C29 D29 D28 F27 LVDS133n LVDS133p LVDS132n LVDS132p VREFB5N0 E24 E23 H21 E28 E27 J25 J24 F28 LVDS131n LVDS131p LVDS130n LVDS130p PLL2_OUTp PLL2_OUTn G22 G21 D23 E22 F21 F20 G25 G26 H25 H24 G24 H23 G20 H20 K22 J22 EP2C70 EP2C70 Pin List Page 18 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B5 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB5N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 GND_PLL2 VCCA_PLL2 GNDA_PLL2 GND IO IO IO IO IO IO VCCIO4 IO IO GND IO VCCIO4 IO IO IO IO IO GND GND IO VCCIO4 IO IO IO IO IO IO GND IO GND IO VCCIO4 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 E21 G19 F19 K21 H22 G23 LVDS129n LVDS129p LVDS128n LVDS128p LVDS127n LVDS127p C23 C22 C21 D21 B23 A23 F23 G22 E24 F24 C28 B29 LVDS126n LVDS126p A22 B22 D26 D27 CDPCLK6/DQS0T CDPCLK6/DQS0T CDPCLK6/DQS0T LVDS125n B21 B28 DQ0T0 DQ0T0 LVDS125p LVDS124n LVDS124p LVDS123n LVDS123p A21 A28 C27 B27 G21 H21 DQ0T1 DQ0T1 DQ0T2 DQ0T3 DQ0T4 DQ0T5 LVDS122n B26 LVDS122p VREFB4N0 LVDS121n LVDS121p LVDS120n LVDS120p D20 E20 A26 C26 E23 E22 D25 D24 LVDS119n B20 A20 A25 DQ0T6 B25 LVDS119p CDPCLK6/DQS0T DQ0T2 DQ0T7 DM0T DQ0T3 EP2C70 EP2C70 Pin List Page 19 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 IO IO IO IO IO IO GND IO GND IO VCCIO4 IO IO IO IO IO IO GND GND VCCIO4 IO IO IO IO IO IO GND IO GND IO VCCIO4 IO IO IO IO IO LVDS118n LVDS118p LVDS117n LVDS117p LVDS116n LVDS116p PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 DQS for x8/x9 in F672 C19 D19 B19 A19 E18 D18 G20 H20 B24 A24 D23 C24 DQ0T4 DQ0T5 DQ0T6 DQ0T7 LVDS115n DQS for x16/x18 in F896 DPCLK8/DQS2T DPCLK8/DQS2T DM0T B23 LVDS115p DQS for x16/x18 in DQS for x8/x9 in F672 F896 A23 LVDS114n LVDS114p G18 D22 C22 G19 C21 J19 H19 VREFB4N1 LVDS113n LVDS113p F18 LVDS112n LVDS112p LVDS111n LVDS111p LVDS110n LVDS110p F17 G17 D17 C17 LVDS109n B18 B21 LVDS109p A18 A21 DQ2T0 DQ5T0 DQ2T2 LVDS108n LVDS108p LVDS107n LVDS107p LVDS106n G16 F16 F15 G15 F19 E19 H18 J18 D19 DQ2T1 DQ2T2 DQ2T3 DQ2T4 DQ5T1 DQ5T2 DQ5T3 DQ5T4 DQ2T3 DQ2T4 E21 D21 B22 A22 F20 E20 DPCLK8/DQS2T DPCLK8/DQS2T DQ2T0 DQ2T1 EP2C70 EP2C70 Pin List DQ2T5 DQ2T6 Page 20 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 VREFB4N3 GND IO GND IO VCCIO4 IO IO IO IO GND GND IO VCCIO4 IO IO IO IO GND IO GND IO VCCIO4 IO IO IO IO IO IO GND IO GND IO VCCIO4 IO CLK8 CLK9 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 LVDS106p F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 C19 DQS for x16/x18 in F896 DQ2T7 LVDS105n B17 B20 DQ2T5 DQ5T5 LVDS105p VREFB4N2 LVDS104n LVDS104p A17 D16 E15 D15 A20 D18 G18 F18 DQ2T6 DQ5T6 DQ2T7 DQ5T7 DQ5T8 LVDS103n B19 LVDS103p LVDS102n LVDS102p LVDS101n C16 A19 C18 B18 B17 DM2T LVDS101p B16 A17 DQ4T0 DM2T DM5T0/BWS#5T0 DQ4T0 DQ4T1 DQ4T2 DQ4T3 DQ5T0 DQ5T1 DQ5T2 DQ5T3 DQ5T9 DQ4T4 DQ5T4 DQ4T5 DQ5T5 DQ4T6 DQ4T7 DQ5T6 DQ5T7 E17 LVDS100n LVDS100p B15 C15 G13 F13 G14 F14 G17 H17 D17 C17 G16 F16 DQ4T1 DQ4T2 DQ4T3 DQ5T10 DQ5T10 DQ5T11 DQ5T11 DQ5T12 DQ5T12 DQ4T4 DQ4T5 DQ5T13 DQ5T13 DQ5T14 DQ5T14 D14 H16 DQ4T6 DQ5T15 DQ5T15 DM4T DM5T0/BWS#5T0 LVDS98n A14 C16 LVDS98p LVDSCLK4n/input(3) LVDSCLK4p/input(3) B14 B13 A13 B16 E16 D16 DPCLK9/DQS4T DPCLK9/DQS4T DPCLK9/DQS4T DPCLK9/DQS4T VREFB4N3 LVDS99n LVDS99p EP2C70 EP2C70 Pin List DQ5T8 Page 21 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 CLK10 CLK10 CLK11 CLK11 IO GND IO IO GND IO VCCIO3 IO IO GND IO IO GND IO VCCIO3 IO IO IO GND IO IO GND IO VCCIO3 IO IO IO GND IO IO IO GND VCCIO3 IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 LVDSCLK5n/input(3) LVDSCLK5p/input(3) LVDS97n C13 D13 B12 G15 H15 C15 LVDS97p LVDS96n C12 B15 E15 LVDS96p DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 DPCLK10/DQS5T DPCLK10/DQS5T DPCLK10/DQS5T DPCLK10/DQS5T DPCLK10/DQS5T DPCLK10/DQS5T DQ5T0 DPCLK10/DQS5T DPCLK10/DQS5T DQ5T9 DQ5T1 DQ5T10 DQ5T10 D15 LVDS95n LVDS95p B11 C11 B14 A14 DQ4T7 DQ5T16 DQ5T16 DQ5T17 DQ5T17 DQ5T2 DQ5T3 DQ5T11 DQ5T11 DQ5T12 DQ5T12 LVDS94n LVDS94p G12 F12 E14 D14 DM4T DQ5T0 DM5T1/BWS#5T1 DQ3T0 DQ5T4 DQ5T5 DQ5T13 DQ5T13 DQ5T14 DQ5T14 LVDS93n C13 DQ5T6 DQ5T15 DQ5T15 LVDS93p DQ5T7 DQ5T8 DQ5T16 DQ5T16 DQ5T17 DQ5T17 DM5T/BWS#5T DM5T1/BWS#5T1 VREFB3N0 D11 B13 H14 C14 LVDS92n D12 G14 B12 DQ5T1 DQ3T1 LVDS92p E12 A12 DQ5T2 DQ3T2 LVDS91n LVDS91p A10 B10 G11 E13 F13 J13 DQ5T4 DQ5T5 DQ5T3 DQ3T4 DQ3T5 DQ3T3 LVDS90n LVDS90p D10 C10 G13 D12 C12 DQ5T6 DQ5T7 DQ3T6 DQ3T7 DQ3T2 DQ3T3 DQ3T4 LVDS89n A9 B11 DQ5T8 DQ3T8 DQ3T5 EP2C70 EP2C70 Pin List DQ3T0 DQ3T1 Page 22 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 IO IO IO GND IO IO IO GND IO VCCIO3 IO IO IO IO GND IO IO GND IO VCCIO3 IO IO IO GND IO IO IO GND IO VCCIO3 IO IO IO IO GND IO PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Configuration Function F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 LVDS89p B9 DM5T/BWS#5T DM3T0/BWS#3T0 DQ3T6 VREFB3N1 E10 A11 H13 D13 LVDS88n LVDS88p LVDS87n F11 DQ3T0 DQ3T9 DQ3T7 DQ3T8 LVDS87p LVDS86n LVDS86p LVDS85n LVDS85p E12 F12 B10 A10 A8 B8 LVDS84n LVDS84p B9 A9 F11 E11 DM3T0/BWS#3T0 DPCLK11/DQS3T DPCLK11/DQS3T DPCLK11/DQS3T DPCLK11/DQS3T DPCLK11/DQS3T DPCLK11/DQS3T DQ3T0 DQ3T9 DQ3T1 DQ3T2 G12 H12 DPCLK11/DQS3T DPCLK11/DQS3T DQ3T10 DQ3T10 DQ3T11 DQ3T11 LVDS83n C9 D10 DQ3T1 DQ3T10 DQ3T10 DQ3T3 DQ3T12 DQ3T12 LVDS83p LVDS82n LVDS82p D9 G10 F10 C10 J12 H11 DQ3T2 DQ3T3 DQ3T4 DQ3T11 DQ3T11 DQ3T12 DQ3T12 DQ3T13 DQ3T13 DQ3T4 DQ3T5 DQ3T6 DQ3T13 DQ3T13 DQ3T14 DQ3T14 DQ3T15 DQ3T15 LVDS81n LVDS81p LVDS80n C8 D8 A7 C9 D9 B8 DQ3T5 DQ3T6 DQ3T7 DQ3T14 DQ3T14 DQ3T15 DQ3T15 DQ3T16 DQ3T16 DQ3T7 DQ3T8 DQ3T16 DQ3T16 DQ3T17 DQ3T17 LVDS80p B7 A8 DQ3T8 DQ3T17 DQ3T17 DM3T/BWS#3T DM3T1/BWS#3T1 D6 C7 D7 F9 E10 D8 E9 G11 DM3T/BWS#3T DQ1T0 DQ1T1 DQ1T2 DM3T1/BWS#3T1 LVDS79n LVDS79p LVDS78n G9 B7 DQ1T3 EP2C70 EP2C70 Pin List Page 23 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 VREFB3N3 GND IO VCCIO3 IO IO IO GND IO IO IO GND IO VCCIO3 IO IO IO IO GND IO IO IO GND IO VCCIO3 IO IO IO IO IO IO GND GNDA_PLL3 VCCA_PLL3 VCCINT VCCINT VCCINT PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 LVDS78p F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 A7 VREFB3N2 LVDS77n LVDS77p E8 C7 B6 A6 LVDS76n LVDS76p LVDS75n D7 D6 B5 DQ1T0 DQ1T1 LVDS75p A5 DQ1T2 LVDS74n LVDS74p LVDS73n LVDS73p C4 B4 H10 G10 DQ1T3 DQ1T4 DQ1T5 VREFB3N3 C5 G9 B3 DQ1T4 LVDS72n D5 C4 A6 LVDS72p B6 A3 CDPCLK7/DQS1T LVDS71n LVDS71p LVDS70n LVDS70p LVDS69p LVDS69n B5 A5 B4 A4 C6 C5 E8 F8 E7 F7 D5 D4 DQ1T5 DQ1T6 DQ1T7 DM1T F8 G8 H10 H11 H15 G8 H9 AA13 AA14 AA17 DEV_CLRn EP2C70 EP2C70 Pin List CDPCLK7/DQS1T CDPCLK7/DQS1T CDPCLK7/DQS1T DQ1T6 DQ1T7 DM1T Page 24 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 F896 H16 H17 H19 J9 J18 K9 K10 K11 K12 K13 K14 K15 K18 L9 L11 L16 L17 L18 M10 M11 M16 M17 N10 N17 P10 P17 R8 R10 R11 R16 R19 T8 T9 T11 T16 T18 DQS for x8/x9 in F672 AA18 K13 K14 K17 K18 L13 L14 L15 L16 L17 L18 L19 M12 M13 M14 M15 M17 M18 M19 N11 N12 N19 N20 P11 P12 P19 P20 R12 R19 T12 T19 U11 U12 U19 U20 V11 EP2C70 EP2C70 Pin List DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 Page 25 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO8 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 F896 T19 U9 U11 U13 U14 U15 U16 U18 V9 V10 V16 V18 W10 W11 W15 W16 W17 C1 F5 L1 M9 V12 V19 V20 W12 W13 W14 W16 W17 W18 W19 Y12 Y13 Y14 Y15 Y16 Y17 Y18 D1 F5 J3 L11 N5 R1 R10 AB3 AE5 AG1 T1 T10 V5 Y11 AB11 AB15 AE10 AF6 AF13 N5 AB5 AD1 P5 R9 T1 V8 AB6 AB9 AB13 AF3 DQS for x8/x9 in F672 EP2C70 EP2C70 Pin List DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 Page 26 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 AH8 AH11 AK4 AK15 AB16 AB20 AE21 AF19 AF25 AH21 AH23 AK16 W18 AK27 AA22 AB28 AD26 AE26 AG30 P22 T21 R18 T30 T26 V26 V19 Y20 C26 D30 F26 F22 J23 J19 J28 L26 L20 M18 N27 R21 N22 R30 A16 A16 A27 A24 C20 C20 C23 D22 E18 E14 E25 E17 F21 H18 J16 AF11 V12 W9 AB14 AB17 AB22 AD20 AF16 AF24 V15 EP2C70 EP2C70 Pin List Page 27 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 F896 J15 A3 A11 E6 J20 A4 A15 C8 C11 E6 F10 F15 J11 J15 AA11 AA12 AA15 AA16 AA19 AA20 K11 K12 K15 K16 K19 K20 L12 M16 N13 N14 N15 N16 N17 N18 P13 P14 P15 P16 P17 P18 E9 E13 H9 J12 H8 H12 J10 J11 J13 J14 J16 J17 K16 K17 L10 L12 L13 L14 L15 M12 M13 M14 M15 N9 N11 N12 N13 N14 N15 N16 DQS for x8/x9 in F672 EP2C70 EP2C70 Pin List DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 Page 28 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 F896 N18 P9 P11 P12 P13 P14 P15 P16 P18 R12 R13 R14 R15 R17 T10 T12 T13 T14 T15 T17 U10 U12 U17 V11 V13 V14 V17 W8 W12 W19 A2 A12 A15 A25 R11 R13 R14 R15 R16 R17 R18 R20 T11 T13 T14 T15 T16 T17 T18 T20 U13 U14 U15 U16 U17 U18 V13 V14 V15 V16 V17 V18 W15 Y19 A2 A13 A18 A29 AB4 AB10 AB7 DQS for x8/x9 in F672 EP2C70 EP2C70 Pin List DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 Page 29 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional Function(s) Configuration Function F672 F896 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 AB14 AB17 AB21 AB27 AE6 AE9 AD9 AE14 AD14 AE18 AD18 AE22 AE1 AE25 AF5 AE26 AF26 AF2 AG11 AG21 AF12 AH6 AF15 AH25 AF25 AJ1 B1 AJ30 B26 AK2 C14 AK13 C18 AK18 D4 AK29 D24 B1 E7 B30 C6 E11 C25 E16 D11 E19 D20 H5 E5 H13 E26 F6 H14 F9 H22 F14 K20 F17 F22 L5 F25 AB11 AB16 AB19 AC4 EP2C70 EP2C70 Pin List Page 30 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Note (1), (2) Bank Number VREFB Group Pin Name / Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function F672 F896 L22 M1 J4 J10 J14 J17 J21 J27 L23 M11 M20 N1 N6 N26 N30 P10 P21 U10 U21 V1 V6 V25 V30 W11 W20 M26 N8 N19 P8 P19 R1 R21 R26 T5 U8 U19 W5 W13 W14 W22 Y9 Y17 DQS for x8/x9 in F672 DQS for x16/x18 in DQS for x8/x9 in F672 F896 DQS for x16/x18 in F896 Notes: (1) Optional Functions (LVDS, DDR, etc) are not available for some pins in certain packages. E.g. for EP2C8, LVDS70 LVDS70 pair is available for Q208 and F256 but not for T144. (2) DQS0T, DQS1T, DQS0B and DQS1B pin functions are only available in F672 and F896 packages. (3) If the dedicated CLK pins are not used to feed the global clock networks, they can be used as general-purpose input pins to feed core logic. They do not have support for an I/O register. PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. EP2C70 EP2C70 Pin List Page 31 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Pin Type (1st, 2nd, & 3rd Function) Pin Description Power Supply and Reference Pins These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVPECL, LVDS(regular I/O and CLK pins) ,differential HSTL and differential SSTL I/O standards. All VCCINT pins must be connected to 1.2 V. VCCIO[1.8] Power These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5 V, 1.8 V, 2.5 V, 3.3-V PCI, and 3.3-V PCIX,differential SSTL, differential HSTL, and LVDS (regular I/O) I/O standards. GND Ground VREFB[1.8]N[0.3] I/O Device ground pins. All GND pins should be connected to the board GND plane. Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. VCCA_PLL[1.4] Power Analog power for PLLs[1.4]. The designer must connect these pins to 1.2 V, even if the PLL is not used. Designer is advised to keep isolated from other VCC for better jitter performance. VCCD_PLL[1.4] Power Digital power for PLLs[1.4]. The designer must connect these pins to 1.2 V, even if the PLL is not used. GNDA_PLL[1.4] Ground Analog ground for PLLs[1.4]. The designer can connect this pin to the GND plane on the board. GND_PLL[1.4] Ground Ground for PLLs[1.4]. The designer can connect this pin to the GND plane on the board. NC No Connect Pin Name VCCINT DCLK Input (PS) Output (AS) DATA0 Input MSEL[0.1] Input PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Do not drive signals into these pins. Dedicated Configuration/JTAG Pins Dedicated configuration clock pin. In PS configuration, DCLK is used to clock configuration data from an external source into the Cyclone II device. In AS mode, DCLK is an output from the Cyclone II device that provides timing for the configuration interface. DCLK should not be left floating. Designer should drive it high or low, whichever is more convenient on the board. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. Dedicated configuration data input pin. In serial configuration modes, bit-wide configuration data is received through this pin. In AS mode, DATA0 has an internal pull-up resistor that is always active. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. Configuration input pins that set the Cyclone II device configuration scheme. These pins must be hardwired to VCCPD or GND. The designer should connect MSEL[0.1] to 00 for AS, 10 for PS, 01 for Fast AS and 00 for JTAG-based Configuration. Pin Definitions Page 32 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Pin Name nCE nCONFIG CONF_DONE Pin Type (1st, 2nd, & 3rd Function) Pin Description Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. In multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the chain. In single device configuration, nCE is tied low. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. Input Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state & tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. If the configuration scheme uses an enhanced configuration device or EPC2, nCONFIG can be tied directly to the configuration device's nINIT_CONF pin. If JTAG configuration is used, nCONFIG can be tied to VCC. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. Bidirectional (open-drain) This is a dedicated configuration status pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin. CONF_DONE should be pulled high by an external 10-k pull-up resistor. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. nSTATUS Bidirectional (open-drain) TCK Input TMS Input TDI Input This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after powerup and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin. nSTATUS should be pulled high by an external 10-k pull-up resistor. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TCK to GND. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TMS to VCC. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TDI to VCC. The input buffer on this pin supports hysteresis using Schmitt or (Schmidt) trigger circuitry. TDO Output Dedicated JTAG output pin. The JTAG circuitry can be disabled by leaving TDO unconnected. CLK[0,2,4,6,8,10,12,14], LVDSCLK[0.7]p Clock, Input CLK[1,3,5,7,9,11,13,15], LVDSCLK[0.7]n Clock, Input PLL[1.4]_OUTp I/O, Output PLL[1.4]_OUTn I/O, Output PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Clockgand PLL Pins p p p p global clock input or user input pins. Dedicated global clock input pins that can also be used for the negative terminal inputs for differential global clock input or user input pins. Optional positive terminal for external clock outputs from PLL [1.4]. These pins can only use the differential I/O standard if it is being fed by a PLL output Optional negative terminal for external clock outputs from PLL[1.4]. These pins can only use the differential I/O standard if it is being fed by a PLL output Pin Definitions Page 33 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Pin Name nCEO Pin Type (1st, 2nd, & 3rd Function) Pin Description Optional/Dual-Purpose Configuration Pins I/O, Output Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device's nCE pin and must be pulled high to Vccio by an external 10k pull-up resistor. During single device configuration and for the last device in multi-device configuration, this pin can be used as an user I/O after configuration. nCSO I/O, Output ASDO I/O, Output Output control signal from the Cyclone II FPGA to the nCS pin of the serial configuration device in AS mode that enables the configuration device by driving it low. In AS mode, the nCSO has internal weak pull-up resistor, which is always active. Output control signal from the Cyclone II FPGA to the serial configuration device in AS mode used to read out configuration data. In AS mode, the ASDO has internal weak pull-up resistor, which is always active. CRC_ERROR I/O, Output Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. I/O (when option off), Input (when option on) Optional chip-wide reset pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. The DEV_CLRn pin does not affect JTAG boundary-scan or programming operations. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Quartus II software. I/O (when option off), Input (when option on) Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. This pin is enabled by turning on the Enable device-wide output enable (DEV_OE) option in the Quartus II software. I/O, Output (open-drain) This is a dual-purpose status pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. This pin is enabled by turning on the Enable INIT_DONE output option in the Quartus II software. DEV_CLRn DEV_OE INIT_DONE CLKUSR LVDS[0-256][p,n] PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software. I/O, Input Dual-Purpose Differential & External Memory Interface Pins I/O, TX/RX channel Dual-purpose differential transmitter/receiver channels 0 to 256. These channels can be used for transmitting/receiving LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. Pin Definitions Page 34 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Pin Name DPCLK[0.11]/ DQS[[0,1]L,[3,5,4,2]B,[1,0]R,[2,4,5,3]T] CDPCLK[0.7]/ DQS[[2,3]L,[1,0]B,[3,2]R,[0,1]T] DQ[[[1,3][L,R]],[[3,5][B,T]]][0.17] DQ[[[0.3][L,R]],[[0.5][B,T]]][0.8] DM[[[0.3][L,R]],[[0.5][B,T]]] Pin Type (1st, 2nd, & 3rd Function) Pin Description I/O, DPCLK/DQS Dual-purpose DPCLK/DQS pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets and clock enables. It can also be used as optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry, which allows fine tune of the phase shift for input clocks or strobes to properly align clock edges needed to capture data. I/O, CDPCLK/DQS I/O, DQ I/O, DQ Dual-purpose CDPCLK/DQS pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets and clock enables. Only one of the two CDPCLK in each corner can feed the clock control block at a time. The other pin can be used as general-purpose I/O pin. The CDPCLK signals incur more delay to the clock block control because they are multiplexed before driving into the clock block control. It can also be used as optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry, which allows fine tune of the phase shift for input clocks or strobes to properly align clock edges needed to capture data. Optional data signal for use in external memory interfacing in the x16 or x18 modes. Optional data signal for use in external memory interfacing in the x8 or x9 modes. I/O, DM Optional data mask pins for x8/x9 modes are required when writing to DDR SDRAM and DDR2 SDRAM devices. A low signal indicates that the write is valid. If the DM signal is high, the memory masks the DQ signals. Each group of DQ & DQS signals requires a DM pin. DM[[[1,3][L,R]],[[3,5][B,T]]][0,1] I/O, DM DM[[[0.3][L,R]],[[0.5][B,T]]] I/O, BWS DM[[[1,3][L,R]],[[3,5][B,T]]][0,1] I/O, BWS PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Optional data mask pins for x16/x18 modes are required when writing to DDR SDRAM and DDR2 SDRAM devices. A low signal indicates that the write is valid. If the DM signal is high, the memory masks the DQ signals. Each group of DQ & DQS signals requires a DM pin. Byte Write Select is an active LOW pin. When asserted active, BWS will select which byte is written into the device during write operation. Bytes not written remain unchange. Deselecting BWS will cause write data to be ignored and not written into device. Byte Write Select is an active LOW pin. When asserted active, BWS will select which byte is written into the device during write operation. Bytes not written remain unchange. Deselecting BWS will cause write data to be ignored and not written into device. Pin Definitions Page 35 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device, ver 1.6 VREFB4N3 VREFB4N2 VREFB4N1 B4 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. VREFB4N0 PLL2 B6 B2 B3 VREFB3N0 B1 FB1N3 VREFB1N2 VREFB1N1 VREFB1N0 VREFB2N3 VREFB2N2 VREFB2N1 VREFB2N0 PLL3 VREFB3N1 Bank & PLL Diagram FB6N3 VREFB6N2 VREFB6N1 VREFB6N0 VREFB5N3 VREFB5N2 VREFB5N1 VREFB5N0 VREFB3N2 B5 VREFB3N3 Page 36 of 38 VREF VREF B8 PLL1 VREFB8N3 VREFB8N2 VREFB8N1 B7 VREFB8N0 VREFB7N3 VREFB7N2 VREFB7N1 VREFB7N0 PLL4 Notes: 1. This is a top view of the silicon die. 2.This is a pictoral representation only to get an idea of placement on the device. Refer to the pin list and the Quartus II software for exact locations. PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Bank & PLL Diagram Page 37 of 38 Pin Information for the CycloneTM II EP2C70 EP2C70 Device Version 1.6 Version Number 1.0 1.1 1.2 Date 10/5/2004 2/24/2005 3/18/2005 1.3 1.4 6/2/2005 2/10/2006 1.5 1.6 3/1/2006 6/16/2006 PT-EP2C70-1 PT-EP2C70-1.6 Copyright © 2006 Altera Corp. Changes Made Initial revision Modified Pin Definitions for DATA0 pin Added CRC_ERROR pin in Pin List and Pin Definition Changed pin name from GNDD_PLL and GNDG_PLL to GND_PLL Finalize Modified Pin Type column in Pin Definitions for VREFB[1.8]N[0.1] pins Added footnote for pins that do not support Optional Functions (LVDS, DDR, etc) Added footnote for DQS0T, DQS1T, DQS0B and DQS1B pins Modified pin definition for NC pins Modified Pin Description of VREFB[1.8]N[0.3] pins Modified Pin Description of VCCA_PLL[1.4] and VCCD_PLL[1.4] pins Added Pin Description for BWS pins Added comment for PLL_OUT pins in Pin Definitions Added "I/O" to pin type of pin nCEO, nCSO and ASDO Modified Pin Description of VCCIO and VCCINT. Modified Pin Description for NCONFIG, NCE, DATA0, TMS, TCK, TDI, NSTATUS, CONDONE and DCLK pins Moved nCEO Discription from section "Dedicated Configuration/JTAG Pins" to section "Optional/Dual-Purpose Configuration Pins" Revision History Page 38 of 38