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Part Manufacturer Description Datasheet BUY
LVDS001EVK Texas Instruments 3.3V LVDS-LVDS Buffer visit Texas Instruments
SN65LVDS100DGKR Texas Instruments 2 Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator 8-VSSOP -40 to 85 visit Texas Instruments
SN65LVDS100DGK Texas Instruments 2 Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator 8-VSSOP -40 to 85 visit Texas Instruments
SN65LVDS100DGKG4 Texas Instruments 2 Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator 8-VSSOP -40 to 85 visit Texas Instruments
SN65LVDS100DGKRG4 Texas Instruments 2 Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator 8-VSSOP -40 to 85 visit Texas Instruments

LVDS+20+pin+hirose+connector+LVDS

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: / (200Mbps ) / (200Mbps ) 0.26 1.5 ns 0.26 tui 30% ns IIN 20 VIN , Bus LVDS 5.2.2 Bus LVDS · · · · 20 FR4 155Mbps 10 FR4 400Mbps 66MHz , - min 40 20 0 0 NESA 0.5 1 1.5 2 2.5 Bus LVDS LVDS-031 5.7 , 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 () 20 TDR Raw impedance , 40 35 30 25 20 15 0 20 40 60 (ns) 80 LVDS-043 1 1.5 TDR 5.9. 300ps 0.5 National Semiconductor
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tektronix 463 LVDS-008 ROGERS4350 GETEK FR4 10G BERT AN-81 national
Abstract: National Semiconductor's LVDS Group 7.1.4 (PRBS) ( TP' ) (L) 20% NRZ 2 2 0V , ) 7.1.6 7.1. 0V 20% ( ) (m) (Mbps) (ns) (ns) 1 400 2.500 0.490 2 , 5.550 1.160 0V 20% 1m 400Mbps ( 0.490ns) 10m 180Mbps ( 1.160ns) 7.2. ±100mV 20 , 170 5.882 1.176 5 155.5 6.431 1.286 10 100 10.000 2.000 ±100mV 20 , 20% ±100mV 100 20% CAT3 10 1 (DS90C031) 1 2 3 5 (m) 10 LVDS -
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AN-808 LVDS-047 CAT3105 DS90C032 Multi-BERT-100 an8082 MultiBERT-100 49251 PRBS LVDS-065 LVDS-069
Abstract: SPREAD 2% SPREAD 4% SPREAD -20 -30 -40 -50 -60 -70 200ps/div 200ps/div MAX9247 40 , RxCLKOUT MAX9244 Spread spectrum reduces EMI OUTPUT POWER SPECTRUM vs. FREQUENCY 20 10 Non-DC-Balanced Clock (MHz) MAX9242 16 to 34 20 to 40 Rising strobe edge, input oversampling MAX9244 16 to 34 20 to 40 Falling strobe edge, input oversampling MAX9246 6 to 18 8 to 20 Falling strobe edge Features POWER SPECTRUM (dBm) DC-Balanced Clock (MHz) Part Maxim Integrated Products
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max9263 MAX9259 MAX9234 DS90CR216 MAX9268 MAX9257 max9234
Abstract: 78.6 59 79 CMOS TSSOP-28 ADC10D020 2 20 150 59 75 CMOS TQFP , LQFP-32 ADC12010 1 10 160 70 83 CMOS LQFP-32 ADC12020 1 20 185 , ADC12QS065 8 ADC12EU050 50 350 70 78 LVDS/ SLVDS 20 150 74 93 CMOS , TQFP-64 10 80 3 78.6 79 -75 9.5 59 TSSOP-28 ADC10D020 10 20 3 , -6 ADC081S101 8 1 500 - 1000 2.7 - 5.25 2.0 ±0.05 7.9 49.7 SPI -40 - 85 SOT National Semiconductor
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IEEE-1588 LMH6550 LMH6551 LMH6555 LMH6515 CLC5903 1LQ1 LM201 LM5035 DS15CP154 LMH7332 picocell CDMA2000TD-SCDMA ADC14155/105C/080C
Abstract: can drive lines with fanouts of 20 to 1, making Virtex-E LVDS I/Os suitable for a broad variety of high-load applications. Figure 3 illustrates a Virtex-E LVDS driver driving 20 LVDS receivers in a , transmission lines and stubs to all 20 LVDS receivers. Each LVDS receiver is connected to the main multi-drop , + Up to 20 Virtex-E or other LVDS Receivers DATA IN 20 x231_04_092099 Figure 3: Virtex-E 20-load Multi-Drop LVDS Schematic The two 29 single-ended transmission lines can be Xilinx
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ANSI/TIA/EIA-644 IEEE1596 XAPP230 XAPP231 XAPP232 XAPP233 receiver ANSI/TIA/EIA-644 lvds standard 20 pin EIA-644
Abstract: THC63LVD1027_Rev.2.0_E THC63LVD1027 85MHz 10Bits Dual LVDS Repeater General Description , THine Electronics,Inc. THC63LVD1027_Rev.2.0_E Pin Out RS 1 64 GND CAP 2 63 , Exposed PAD 18 RB2â'" 19 RB2+ 20 Top View 65 GND (Exposed PAD) RC2â'" 21 44 , . THC63LVD1027_Rev.2.0_E Pin Description Pin Name Direction Type Description RA1+/â'" LVDS data , is 0.1uF 3/22 THine Electronics,Inc. THC63LVD1027_Rev.2.0_E Mode Setting MODE1 (Input THine Electronics
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Abstract: -20 to 70 -20 to 70 -20 to 70 -15 to 60 -10 to 60 -10 to 60 -10 to 60 -20 to 70 -20 to 70 -20 to 70 -20 to 70 -20 to 70 -20 to 70 -20 to 70 -10 to 70 -20 to 70 0 to 50 0 to 50 -20 to 70 -20 to 70 -10 to 65 0 to 50 0 to 50 -20 to 70 -20 to 70 -20 to 70 -20 to 70 0 to 50 -20 to 70 -20 to 70 -20 to 70 -20 to 70 -20 to 70 0 to 50 -20 to 70 0 to 50 0 to 50 0 to 50 0 to 50 0 Toshiba
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LTA065B0D2F LT070AC46100 LTM08C351S LTD104EA5R LTA121C280F wacom digitizer 800x600 wacom wacom toshiba LT056DET2S00 LTA057A343F LTA065B0D4F LTM08C351L
Abstract: 5.2.2 Bus LVDS · · · · 20 FR4 155Mbps 10 FR4 400Mbps 66MHz 800Mbps ECL ECL , 20 0 0 NESA 0.5 1 1.5 2 2.5 Bus LVDS LVDS-031 5.7. 5-6 National , 75 70 65 60 55 50 45 40 35 30 25 () 20 TDR Raw impedance Case A A= B= C = IC , LVDS 100 95 90 0.5 85 80 1 75 70 1.5 65 60 55 50 45 40 35 30 25 20 15 0 20 40 60 (ns) 80 LVDS-043 1 1.5 TDR 5.9. 300ps 0.5 National Semiconductor
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LVDS-052 LVDS-060 LVDS049 AN-1123 LVDS-055 LVDS TIA/EIA-644 LVDS-041 LVDS-046 LVDS-042
Abstract: ) . 2.0 V Operating Case Temperature (TCASE)(3) . 0°C to 80°C Storage Ambient Temperature (TSTG ). ­20°C to 100°C Operating Moisture . 20% to 85% Storage Moisture . 20% to 85 , laser safety. VLVDSI 2.0 VCC VEE 0.8 VLVCMOSIH LVCMOS Input Low Voltage VLVCMOSIL LVCMOS Input Rise/Fall Time(7) tR , tF 50 20 ps V ns Caution Do not stare into beam Siemens
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V23814-K1306-M130 V23815-K1306-M130 k1306 datasheet DIODE 1334 smd M130 50-pin lvds V23814/15-K1306-M130 D-13623
Abstract: operating temperature range ·5mm x 5mm, 20-pin TQFN package www.maxim-ic.com/timing *Contact the , NO SPREAD 2% SPREAD 4% SPREAD -20 -30 -40 -50 -60 -70 200ps/div 200ps/div 39 40 , MAX9244 Spread spectrum reduces EMI OUTPUT POWER SPECTRUM vs. FREQUENCY 20 10 POWER SPECTRUM (dBm , -20 -30 -40 -50 RESOLUTION BW = 100kHz VIDEO BW = 100kHz RxCLKIN_ = 33MHz ATTENUATION = 50dB , Clock (MHz) Non-DC-Balanced Clock (MHz) Features 16 to 34 16 to 34 6 to 18 20 to 40 20 Maxim Integrated Products
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HDMI to vga pinout MAX9374 MAX9180 lvds 26 pin SK4401 MAX9384 MAX9390/MAX9391 MAX9491/MAX9471
Abstract: THC63LVD1027_Rev.2.0_E THC63LVD1027 85MHz 10Bits Dual LVDS Repeater General Description , THine Electronics,Inc. THC63LVD1027_Rev.2.0_E Pin Out RS 1 64 GND CAP 2 63 , Exposed PAD 18 RB2â'" 19 RB2+ 20 Top View 65 GND (Exposed PAD) RC2â'" 21 44 , . THC63LVD1027_Rev.2.0_E Pin Description Pin Name Direction Type Description RA1+/â'" LVDS data , is 0.1uF 3/22 THine Electronics,Inc. THC63LVD1027_Rev.2.0_E Mode Setting MODE1 (Input THine Electronics
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Abstract: documentation. The VESA SPWG 2.0 Specification (Standard Panel Working Group) defines standard mechanical and , Converter Datasheet Compliant to Industry Standard Panel 2.0 Specification Style A, XGA with two exceptions , LVDS Converter does also not support the Display Data Channel (DDC) on pins 17, 19 and 20 of the , LVDS Interface Connector: Hirose DF19G-20P-1H or equivalent Compliant to Industry Standard Panel 2.0 , (DDC) on pins 17, 19 and 20 of the connector. 4. Installation For the installation of the LVDS Toradex
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lcd LVDS display 30 pin connector xga LVDS 30 pin hirose connector LVDS LVDS connector 26 pins LCD LVDS connector 30 PIN header LVDS 40 pin hirose connector LVDS lvds 40 pin pinout A1715 DF14-20S-1 DF19-20S-1C
Abstract: Mux (MHz) (Gbps) 21 DS90CR213MTD 21:3 20 66 1.38 5 - 10 70°C TSSOP-48 Note 1 DS90CR214MTD 21:3 20 66 1.38 5 - 10 70°C TSSOP-48 Note 1 DS90CR215MTD 21:3 20 66 1.38 3.3 - 40 85°C TSSOP-48 Note 1 DS90CR216AMTD 21:3 20 66 1.38 3.3 - 40 85°C TSSOP-48 Note 1 DS90CR217MTD 21:3 20 85 1.78 3.3 - 10 70°C TSSOP-48 Note 1 DS90CR218AMTD 21:3 National Semiconductor
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DS90UR801 TSSOP56 DS92LV18 DS90CR48x AN-1084 80000B DS90CR2 DS90CR4 DS90CR485/486 DS90CR481/482 DS90CR481/486 DS90CR485/6
Abstract: ] RX_DATA_P4_IN[3] RX_DATA_P4_INN[2] RX_DATA_P4_IN[2] B23 E20 D22 D21 C23 .20 E22 E21 C22 D20 AB21 AC21 AA19 , -A10 Corner 1 23 D -B- A E AC 45 Degrees (4 PLCS) e TOP VIEW 23 22 21 20 19 , Input High Current Input Low Current Min 2.0 0.8 20 100 -0.2 Typ Max Min 2.0 0.8 20 100 -0.2 TA = +25oC Typ Max Min 2.0 TA = +85oC Typ Max Unit V 0.8 20 100 -0.2 V uA uA mA VIN = 2.7V VIN = VCC VIN , ) 727-8994 Revision 1/.ebruary 2, 2001 20 www.semtech.com Semtech Semtech
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SK2020 G4 ASIC OC-48 OC-192 304-L 304-TBGA
Abstract: in APEX 20KE Devices 2.4 V +1 V 2.0 V 1.4 V 1.0 V 0.4 V -1 V 0.0 V LVDS , W Y AA AB AC AD AF 26 25 24 23 22 21 20 19 18 17 16 15 , D1 D1PLL 20 21 15 Altera Corporation Using LVDS in APEX 20KE Devices 20 PLL 2 PLL PLL PLL 16 FIFO 20 I/O Altera
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15LVDS 13LVDS EP20K200E EP20K300E EP20K400E EP20K600E SCI-LVDSANSI/TIA/EIA-644 M-WP-LVDSAPEX-01/J LVDSRX01 LVDS32 LVCMOS256
Abstract: V, with respect to ground. When there is a +1-V ground shift, the voltage swing ranges from 2.0 V , . Common-Mode Voltage Range 2.4 V +1 V 2.0 V 1.4 V 1.0 V 0.4 V Driver Output -1 V 0.0 V , 11.43 33 ns ×4 mode fLVDSCLK ×8 mode ×7 mode tC 5.71 20 6.88 20 6.88 20 ns ×8 mode 30 105 30 87.5 30 78.125 MHz ×7 mode 30 105 30 , 12.80 33 ns ×7 mode 9.52 33 11.43 33 11.43 33 ns ×4 mode 5.71 20 Altera
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10226-1A10VE altlvds_tx EP20K1000E ldvs connector vhdl code for lvds driver 800-EPLD
Abstract: +100 mV Input Current IIN, I IN VIN, V IN = VCC or 0V -20 +20 -20 +20 -20 +20 uA Input Common-Mode Voltage VCM Figure 1 0.05 VCC 0.05 0.05 VCC 0.05 , | Figure 2 1.0 20 VOS Figure 2 |VOS| Figure 2 1.0 20 1.0 20 VID = ±100mV , 250 352 450 1.0 710 20 mV 250 339 450 mV 1.0 20 mV 1.375 V 1.0 20 mV 18 24 mA LVDS OUTPUTS (OUT2, OUT2 ) Differential Output Voltage Maxim Integrated Products
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MAX9376 630ps JESD51-7 MAX9376EUB EIA/TIA-644
Abstract: differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SIA_1+ SIA_1- 19 20 I, LVDS , (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n) VIH High Level Input Voltage 2.0 VDD V , Capacitance Any Digital Input Pin to VSS 2.0 pF COUT1 Output Capacitance Any Digital Output , 35 mV -40 mA 0 100 0 mV mV 2400 3.55 2.0 mV V pF LVDS OUTPUT DC , Transition Use an alternating 1 and 0 pattern at Time 200 Mb/s, measure between 20% and Differential High National Semiconductor
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DS15MB200 AN-1187 AN-1194 DS15MB200TSQ DS15MB200TSQX lvds buffer DS201573 CSP-9-111C2 CSP-9-111S2
Abstract: MIL-STD-883, Method 3015) Q2 kV Quiescent Supply Current 0.8 2.0 V V 100 -5 mV +5 , 2.0 2.5 20 16 12 0 0 3.0 0.5 IL(OFF) 1.0 1.5 2.0 2.5 3.0 -40 , CURRENT (uA) 0.5 24 4 0 0 28 8 2 0 MAX14979E toc03 TA = +85°C 20 40 , 24 23 22 21 20 19 TOP VIEW 26 MAX14979E Pin Configuration NO0- 28 , Differential Terminal for Switch 3 19 NO2- Normally Open LVDS Differential Terminal for Switch 2 20 Maxim Integrated Products
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laptop lcd LVDS 26 pin no3a 650MH 100MH
Abstract: their documentation. - The VESA SPWG 2.0 Specification (Standard Panel Working Group) defines , Panel 2.0 Specification Style A, XGA with two exceptions: First of all a 1.25mm pitch connector , Display Data Channel (DDC) on pins 17, 19 and 20 of the connector. Most Industry Panels do not feature , - Connector: Hirose DF19G-20P-1H or equivalent - Compliant to Industry Standard Panel 2.0 , (DDC) on pins 17, 19 and 20 of the connector. 4. Installation For the installation of the LVDS Toradex
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