TN1057 LUT14-1 LFECP20E-5 LFEC20E-5 52MAC2 34MAC2 TN1057J 18SRISRO14-3 MAC14-4 - Datasheet Archive

 

Oct. 2005 LatticeECP/EC sysDSP LatticeECP/ECLatticeECP-DSP sysDSP( )sysDSP LUT14-1 14-1 sysDSPLUT LatticeECP LFECP20E-5 DSP

 

TN1057 TN1057_01.2J Oct. 2005 LatticeECP/EC sysDSP LatticeECP/ECLatticeECP-DSP sysDSP( )sysDSP LUT14-1 LUT14-1 14-1 sysDSPLUT LatticeECP LFECP20E-5 LFECP20E-5 DSP LatticeEC LFEC20E-5 LFEC20E-5 LUT fMAX LUT fMAX LUT 9x9 235 0 76 174 18x18 211 0 50 608 36x36 177 0 35 2225 sysDSP sysDSPLatticeECP-DSPsysDSP14-1 14-1 LatticeECP-DSP sysDSP LatticeECP 14-1 sysDSP TN1057 TN1057_01.2J LatticeECP Oct. 2005 14-2 sysDSP TN1057 TN1057_01.2J Oct. 2005 sysDSP3 36x36 · 36×361 18x18 · · · · 4 52MAC2 52MAC2 18×182 18×1841 9x9 · 8 · 34MAC2 34MAC2 · 9×924 · 9×942 sysDSP LatticeECP-DSPsysDSP · ispLEVERIPexpresssysDSP HDL · HDLsysDSP · MathworksSimulink ispLEVERispLEVER sysDSPHDL · sysDSP IPexpresssysDSP IPexpresssysDSPHDL IPexpress sysDSP IPexpressispLEVEREXAMPLES (Project Navigator)File->Open Example IPexpress4 · · · · MULT () MAC () MULTADDSUB (/) MULTADDSUBSUM (/) LatticeECP 14-3 sysDSP TN1057J TN1057J (sysDSP UG) Oct. 2004 MULT MULTsysDSP14-2 () sysDSP 18SRISRO14-3 18SRISRO14-3 14-2 MULT 14-3 MULT LatticeECP 14-4 (ispLEVER5.1) TN1057J TN1057J (sysDSP UG) Oct. 2004 MAC MAC14-4 MAC14-4 ()1 18SRISROAccumsload () 14-5 14-4 MAC 14-5 MAC LatticeECP 14-5 (ispLEVER5.1) TN1057J TN1057J (sysDSP UG) Oct. 2004 MULTADDSUB MULTADDSUB GUIMULT18X18ADDSUBMULT9X9ADDSUB GUIMULT18X18ADDSUBMULT9X9ADDSUB 14-6() 1MULTADDSUB sysDSP18 SRISRO14-7 SRISRO14-7 14-6 MULTADDSUB 14-7 MULTADDSUB LatticeECP 14-6 (ispLEVER5.1) TN1057J TN1057J (sysDSP UG) Oct. 2004 MULTADDSUBSUM MULTADDSUBSUM GUIMULT18X18ADDSUBSUMMULT9X9ADDSUBSUM GUIMULT18X18ADDSUBSUMMULT9X9ADDSUBSUM 14-814-9 14-8 MULTADDSUBSUM 14-9 MULTADDSUM LatticeECP 14-7 (ispLEVER5.1) TN1057J TN1057J (sysDSP UG) Oct. 2004 ()1 MULTADDSUMsysDSP 18SRISRO14-9 18SRISRO14-9 sysDSP HDLsysDSP sysDSP VerilogVHDL // This Verilog example will be mapped into single MULT9X9MAC with the output register // enabled // This will be mapped into single MULT9X9MAC with the output register enabled module mult_acc (dataout, dataax, dataay, clk); output [16:0] dataout; input [7:0] dataax, dataay; input clk; reg [16:0] dataout; wire [15:0] multa = dataax * dataay; // 9x9 Multiplier wire [16:0] adder_out; assign adder_out = multa + dataout; // Accumulator always @(posedge clk) begin dataout