LTC3880/LTC3880-1 3880/LTC3880-1 LTC3880 LTC3880-1 VDD33 VDD25 40-LEAD - Datasheet Archive

 

Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management DESCRIPTION FEATURES PMBus/I2C Compliant

 

LTC3880/LTC3880-1 LTC3880/LTC3880-1 Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management DESCRIPTION FEATURES PMBus/I2C Compliant Serial Interface ­ elemetry Read Back includes VIN, IIN, VOUT, IOUT, T Temperature and Faults ­ Programmable Voltage, Current Limit, Digital Soft-Start/Stop, Sequencing, Margining, OV/UV and Frequency Synchronization (250kHz to 1MHz) n ±0.5% Output Voltage Accuracy over Temperature n Integrated 16-Bit ADC n Internal EEPROM and Fault Logging n Integrated Powerful N-Channel MOSFET Gate Drivers Power Conversion n Wide V Range: 4.5V to 24V IN nV OUT Range: 0.5V to 5.5V n Analog Current Mode Control Loop n Supports Power-Up Into Pre-Biased Load n Accurate PolyPhase® Current Sharing for Up to 6 Phases n Available in a 40-Pin (6mm × 6mm) QFN Package The LTC®3880/LTC3880-1 3880/LTC3880-1 are dual, PolyPhase DC/DC synchronous step-down switching regulator controllers with an I2C-based PMBus compliant serial interface. The controllers use a constant frequency, current mode architecture that is supported by LTpowerPlayTM software development tool with graphical user interface (GUI). n Switching frequency, output voltage, and device address can be programmed using external configuration resistors. Additionally, parameters can be set via the digital interface or stored in EEPROM. Voltage, current, internal/external temperature and fault status can be read back through the bus interface. The LTC3880/LTC3880-1 LTC3880/LTC3880-1 can be configured for Burst Mode® operation, discontinuous (pulse-skipping) mode or continuous inductor current mode. The LTC3880 LTC3880 incorporates a 5V linear regulator while the LTC3880-1 LTC3880-1 uses an external 5V supply for minimum power loss. APPLICATIONS L, LT, LTC, LTM, PolyPhase, Burst Mode, µModule, Linear Technology and the Linear logo are registered trademarks and No RSENSE and LTpowerPlay are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150. High Current Distributed Power Systems Telecom, Datacom and Storage Systems n Intelligent Energy Efficient Power Regulation n n TYPICAL APPLICATION VIN INTVCC VIN LTC3880 LTC3880* BOOST0 1.0µH TG1 SW0 100 0.56µH BG1 1.74k 0.2µF PGND + + ISENSEO ISENSE1 ISENSEO­ ISENSE1­ VSENSEO+ VSENSE1 VSENSEO­ TSNS0 TSNS1 + 10nF 2200pF 6.04k *SOME DETAILS OMITTED FOR CLARITY PMBus INTERFACE TO/FROM OTHER LTC DEVICES WRITE PROTECT 2200pF ITHO SDA SCL ALERT RUN0 RUN1 SHARE_CLK WP ITH1 GPIO0 GPIO1 VDD33 VDD33 VDD25 VDD25 10nF 90 VOUT1 1.8V 20A SW1 BG0 2.15k 0.2µF 0.1µF BOOST1 + 530µF 4.99k 5 80 70 4 60 50 3 40 2 30 20 1 10 0 0.01 FAULT MANAGEMENT 6 VIN = 12V VOUT = 1.8V POWER LOSS (W) 530µF TG0 EFFICIENCY (%) 0.1µF VOUT0 3.3V 15A Efficiency and Power Loss vs Load Current 1µF 10µF 1 0.1 10 LOAD CURRENT (A) 0 100 3880 TA01b 1µF 1µF SGND 3880 TA01a 3880f 1 LTC3880/LTC3880-1 LTC3880/LTC3880-1 TABLE OF CONTENTS Features. 1 Applications. 1 Typical Application. 1 Description. 1 Table of Contents. 2 Absolute Maximum Ratings. 4 Pin Configuration. 4 Order Information. 4 Electrical Characteristics. 5 Typical Performance Characteristics. 9 Pin Functions. 12 Block Diagram. 14 Operation. 15 Overview. 15 Main Control Loop. 15 EEPROM. 16 Power Up and Initialization. 16 Soft-Start. 17 Sequencing. 18 Voltage-Based Sequencing. 18 Shutdown. 18 Light Load Current Operation. 19 Switching Frequency and Phase. 19 Output Voltage Sensing.20 Current Sensing.20 Load Sharing. 21 External/Internal Temperature Sense. 21 RCONFIG (Resistor Configuration) Pins.22 Fault Detection and Handling.22 CRC Failure .23 Serial Interface. 24 Communication Failure . 24 Device Addressing. 24 Responses to VOUT and IOUT Faults. 24 Output Overvoltage Fault Response.25 Output Undervoltage Response .25 Peak Output Overcurrent Fault Response.25 Responses to Timing Faults.25 Responses to VIN OV Faults.26 Responses to OT/UT Faults.26 Overtemperature Fault Response-Internal .26 Overtemperature and Undertemperature Fault Response-Externals .26 Responses to External Faults .26 Fault Logging.26 Bus Timeout Failure. 27 Similarity Between PMBus, SMBus and I2C 2-Wire Interface. 27 PMBus Serial Digital Interface. 27 PMBus Command Summary. 31 PMBus Commands. 31 *Data Format.36 Applications Information. 37 Current Limit Programming. 37 ISENSE+ and ISENSE­ Pins. 37 Low Value Resistor Current Sensing.38 Inductor DCR Current Sensing. 39 Slope Compensation and Inductor Peak Current.40 Inductor Value Calculation.40 Inductor Core Selection. 41 Power MOSFET and Schottky Diode (Optional) Selection. 41 Variable Delay Time, Soft-Start and Output Voltage Ramping. 42 Digital Servo Mode.43 Soft Off (Sequenced Off).43 INTVCC Regulator.44 Topside MOSFET Driver Supply (CB, DB).45 Undervoltage Lockout.45 CIN and COUT Selection.45 Fault Conditions.46 Open-Drain Pins. 47 Phase-Locked Loop and Frequency Synchronization. 47 3880f 2 LTC3880/LTC3880-1 LTC3880/LTC3880-1 TABLE OF CONTENTS Minimum On-Time Considerations.48 RCONFIG (External Resistor Configuration Pins).48 Voltage Selection.48 Frequency and Phase Selection Using RCONFIG. 49 Address Selection Using RCONFIG.50 Efficiency Considerations. 51 Checking Transient Response. 52 PC Board Layout Checklist.53 PC Board Layout Debugging.55 Design Example.56 Connecting the USB to the I2C/SMBus/PMBus Controller to the LTC3880 LTC3880 In System.58 LTpowerPlay: An Interactive GUI for Digital Power. 59 PMBus Command Details. 61 Addressing and Write Protect. 61 General Configuration Registers.63 On/Off/Margin.64 PWM Config.66 Voltage.68 Input Voltage and Limits.68 Output Voltage and Limits.69 Current.72 Input Current Calibration . 72 Output Current Calibration . 72 Input Current.72 Output Current.73 Temperature. 74 External Temperature Calibration. 74 External Temperature Limits. 75 Timing. 76 Timing-On Sequence/Ramp. 76 Timing-Off Sequence/Ramp.77 Precondition for Restart. 78 Fault Response. 78 Fault Responses All Faults. 78 Fault Responses Input Voltage. 78 Fault Responses Output Voltage. 79 Fault Responses Output Current.82 Fault Responses IC Temperature.83 Fault Responses External Temperature.84 Fault Sharing.85 Fault Sharing Propagation.85 Fault Sharing Response. 87 Scratchpad. 87 Identification.88 Fault Warning and Status.90 Telemetry.95 NVM Memory Commands.98 Store/Restore.98 Fault Logging.99 Block Memory Write/Read. 104 Typical Applications. 105 Package Description. 111 Typical Application. 112 Related Parts. 112 3880f 3 LTC3880/LTC3880-1 LTC3880/LTC3880-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN Voltage. ­0.3V to 28V Topside Driver Voltages BOOST1, BOOST0. ­0.3V to 34V Switch Voltage (SW1, SW0). ­5V to 28V EXTVCC, INTVCC, (BOOST1 ­ SW1), (BOOST0 ­ SW0). ­0.3V to 6V VSENSE0+, VSENSE1, ISENSE0n, ISENSE1n. ­0.3V to 6V RUN0, RUN1, SDA, SCL, ALERT. ­0.3V to 5.5V FREQ_CFG, VOUTn_CFG, V TRIMn_CFG, ASEL, VDD25 VDD25. ­0.3V to 2.75V VDD33 VDD33, GPIO0, GPIO1, TSNS0, TSNS1, VSENSE0 ­, SHARE_CLK, WP, SYNC, ITHn . ­0.3V to 3.6V INTVCC Peak Output Current.100mA Operating Junction Temperature Range (Note 2). ­40°C to 125°C Storage Temperature Range. ­40°C to 125°C PIN CONFIGURATION LTC3880-1 LTC3880-1 VSENSE0­ 2 BOOST1 BG1 EXTVCC PGND VIN BG0 BOOST0 TSNS0 40 39 38 37 36 35 34 33 32 31 VSENSE0+ 1 TG0 TOP VIEW BOOST1 BG1 INTVCC PGND VIN BG0 BOOST0 TG0 SW0 TSNS0 TOP VIEW SW0 LTC3880 LTC3880 40 39 38 37 36 35 34 33 32 31 30 TG1 VSENSE0+ 1 30 TG1 29 SW1 VSENSE0­ 2 29 SW1 ISENSE1+ 3 28 TSNS1 ISENSE1+ 3 28 TSNS1 ISENSE1­ 4 27 VSENSE1 ISENSE1­ 4 ITH0 5 26 ITH1 41 SGND ISENSE0+ 6 25 VDD33 VDD33 SYNC 8 26 ITH1 41 SGND ISENSE0+ 6 24 SHARE_CLK ISENSE0­ 7 27 VSENSE1 ITH0 5 ISENSE0­ 7 23 WP 25 VDD33 VDD33 24 SHARE_CLK SYNC 8 23 WP SCL 9 22 VDD25 VDD25 SCL 9 22 VDD25 VDD25 SDA 10 21 VTRIM1_CFG SDA 10 21 VTRIM1_CFG VTRIM0_CFG VOUT1_CFG VOUT0_CFG FREQ_CFG ASEL RUN1 RUN0 GPIO1 GPIO0 ALERT 11 12 13 14 15 16 17 18 19 20 VTRIM0_CFG VOUT1_CFG VOUT0_CFG FREQ_CFG ASEL RUN1 RUN0 GPIO1 GPIO0 ALERT 11 12 13 14 15 16 17 18 19 20 UJ PACKAGE 40-LEAD 40-LEAD (6mm × 6mm) PLASTIC QFN UJ PACKAGE 40-LEAD 40-LEAD (6mm × 6mm) PLASTIC QFN TJMAX = 125°C, JA = 33°C/W EXPOSED PAD (PIN 41) IS SGND, MUST BE SOLDERED TO PCB TJMAX = 125°C, JA = 33°C/W EXPOSED PAD (PIN 41) IS SGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE LTC3880EUJ LTC3880EUJ#PBF LTC3880EUJ LTC3880EUJ#TRPBF LTC3880UJ LTC3880UJ 40-Lead (6mm × 6mm) Plastic QFN ­40°C to 105°C LTC3880EUJ-1 LTC3880EUJ-1#PBF LTC3880EUJ-1 LTC3880EUJ-1#TRPBF LTC3880UJ-1 LTC3880UJ-1 40-Lead (6mm × 6mm) Plastic QFN ­40°C to 105°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3880f 4 LTC3880/LTC3880-1 LTC3880/LTC3880-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER Input Voltage Input Voltage Range VIN Input Voltage Supply Current IQ Normal Operation VUVLO Undervoltage Lockout Threshold when VIN > 4.3V Control Loop Full-Scale Voltage Range 0 VOUT1R0 Set Point Accuracy (0.6V to 5V) Resolution LSB Step Size VOUT1R1 Full-Scale Voltage Range 1 Set Point Accuracy (0.6V to 2.5V) Resolution LSB Step Size Full-Scale Voltage Range 0 VOUT0R0 Set Point Accuracy (0.6V to 4.096V) Resolution LSB Step Size Full-Scale Voltage Range 1 VOUT0R1 Set Point Accuracy (0.6V to 2.5V) Resolution LSB Step Size Line Regulation VLINEREG Load Regulation VLOADREG Error Amplifier gm gm0,1 Input Current IISENSE0,1 VSENSE Input Resistance to Ground VSENSERIN0 VSENSE Input Resistance to Ground VSENSERIN1 Resolution VIlLIMIT VILIMMAX VILMMIN Gate Drivers TG Transition Time: TG0,1 Rise Time tr Fall Time tf BG Transition Time: BG0,1 Rise Time tr Fall Time tf Top Gate Off to Bottom Gate On Delay Time TG/BG t1D Bottom Gate Off to Top Gate On Delay Time BG/TG t2D Minimum On-Time tON(MIN) OV/UV Output Voltage Supervisor Channel 0 N Resolution Voltage Monitoring Range V0RANGE0 Voltage Monitoring Range V0RANGE1 Threshold Programming Step V0OUSTP0 Threshold Programming Step V0OUSTP1 CONDITIONS MIN (Note 12) (Note 14) VRUN0,1 = 3.3V, No Caps on TG and BG VRUN0,1 = 0V VINTVCC/VEXTVCC Falling VINTVCC/VEXTVCC Rising l VOUT_COMMAND(1) = 5.500V (Note 9) l l VOUT_COMMAND(1) = 2.75V (Note 9) VOUT_COMMAND(0) = 4.095V (Note 9) VOUT_COMMAND(0) = 2.75V (Note 9) TYP 4.5 MAX 24 25 20 3.7 3.95 l l l l l l 6V < VIN < 24V 0.7V < VITH < 2.0V ITH0,1 =1.22V VISENSE = 5.5V 0V VPIN 5.5V 0V VPIN 5.5V l l 2.7 ­0.5 4.0 ­0.5 2.7 ­0.5 12 1.375 12 0.6875 12 1.375 12 0.6875 l Hi Range Lo Range Hi Range Lo Range 5.4 ­0.5 l 68 44 (Note 4) CLOAD = 3300pF CLOAD = 3300pF (Note 4) CLOAD = 3300pF CLOAD = 3300pF (Note 4) CLOAD = 3300pF Each Driver (Note 4) CLOAD = 3300pF Each Driver 3 ±2 41 37 3 75 50 37.5 25 5.6 0.5 2.8 0.5 4.2 0.5 2.8 0.5 ±10 82 56 V % Bits mV V % Bits mV V % Bits mV V % Bits mV %/V % mmho µA k k bits mV mV mV mV 30 30 ns ns 30 30 30 30 90 ns ns ns ns ns 8 Range Value = 0 Range Value = 1 Range Value = 0 Range Value = 1 V mA mA V V ±0.02 ±0.2 l UNITS 1 0.5 4.096 2.7 22 11 Bits V V mV mV 3880f 5 LTC3880/LTC3880-1 LTC3880/LTC3880-1 The l denotes the specifications which apply over the full operating ELECTRICAL CHARACTERISTICS junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER Threshold Accuracy 2V < VOUT0 < 4V V0THACC0 Threshold Accuracy 1V < VOUT0 < 2.5V V0THACC1 OV Comparator Response Time tPROPOV0 UV Comparator Response Time tPROPUV0 OV/UV Output Voltage Supervisor Channel 1 N Resolution Voltage Range V1RANGE0 Voltage Range V1RANGE1 Step Size V1OUSTP0 Step Size V1OUSTP1 Threshold Accuracy 2V < VOUT1 < 5V V1THACC0 Threshold Accuracy 1V < VOUT1 < 2.5V V1THACC1 OV Comparator Response Time tPROPOV1 UV Comparator Response Time tPROPUV1 VIN Voltage Supervisor N Resolution Full-Scale Voltage VINRANGE Step Size VINSTP Threshold Accuracy 9.0V < VIN < 20V VINTHACC Threshold Accuracy 4.5V < VIN < 9V VINTHACC\M Comparator Response Time tPROPVIN (VIN_ON and VIN_OFF) Output Voltage Readback N Resolution LSB Step Size Full-Scale Voltage VOFS VOUT_TUE Zero-Code Offset Voltage VOS Conversion Time tCONVERT VIN Voltage Readback N Resolution Full-Scale Voltage VIFS Total Unadjusted Error VIN_TUE CONDITIONS Range Value = 0 Range Value = 1 VOD = 10% of Threshold VOD = 10% of Threshold MIN TYP l l 8 Range Value = 0 Range Value = 1 Range Value = 0 Range Value = 1 Range Value = 0 Range Value = 1 VOD = 10% of Threshold VOD = 10% of Threshold 1 0.5 5.5 2.7 22 11 ±2 ±2 35 350 l l 8 4.5 20 82 ±2.5 ±5 100 l l VOD = 10% of Threshold (Note 10) VRUNn = 0V (Note 8) (Note 8) VOUTn > 0.6V 16 244 8 0.5 ±500 l l (Note 6) 120 (Note 5) (Note 11) VVIN > 4.5V 10 38.91 0.5 2 l Conversion Time tCONVERT Output Current Readback N Resolution LSB Step Size Full-Scale Current IFS Total Unadjusted Error IOUT_TUE Zero-Code Offset Voltage VOS Conversion Time tCONVERT Input Current and Duty Cycle Readback D_RES Resolution D_TUE Total Unadjusted Error Update Rate tCONVERT MAX ±2 ±2 35 350 (Note 6) (Note 5) 0V |VISENSE+ ­ VISENSE­| 15.625mV 16mV |VISENSE+ ­ VISENSE­| 31.25mV 32mV |VISENSE+ ­ VISENSE­| 62.5mV 64mV |VISENSE+ ­ VISENSE­| 125mV (Note 7) RISENSE = 1m (Note 8) VISENSE > 6mV (Note 15) 120 10 V15.26 30.52 61 122 ±128 ±1 ±28 l l (Note 6) 120 10 16.3% Duty Cycle (Note 6) ­3 3 120 UNITS % % µs µs bits V V mV mV % % µs µs bits V mV % % µs Bits µV V % µV ms Bits V % % ms Bits µV µV µV µV A % µV ms Bits % ms 3880f 6 LTC3880/LTC3880-1 LTC3880/LTC3880-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER Temperature Readback (T0, T1, T2) Resolution TRES_T T0,1_TUE External TSNS TUE T2_TUE Internal TSNS TUE Update Rate tCONVERT_T INTVCC Regulator Internal VCC Voltage No Load (LTC3380 LTC3380) VINTVCC INTVCC Load Regulation (LTC3380 LTC3380) VLDO_INT VDD33 VDD33 Regulator Internal VDD33 VDD33 Voltage VDD33 VDD33 VDD33 VDD33 Current Limit ILIM(VDD33 VDD33) VDD33 VDD33 Overvoltage Threshold VDD33 VDD33_OV VDD33 VDD33 Undervoltage Threshold VDD33 VDD33_UV VDD25 VDD25 Regulator Internal VDD25 VDD25 Voltage VDD25 VDD25 VDD25 VDD25 Current Limit ILIM(VDD25 VDD25) Oscillator and Phase-Locked Loop Oscillator Frequency Accuracy fOSC VTH,SYNC SYNC Input Threshold VOL,SYNC ILEAKSYNC SYNC-0 SYNC Low Output Voltage SYNC Leakage Current in Slave Mode SYNC to Ch0 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG0 SYNC-1 SYNC to Ch1 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG1 EEPROM Characteristics Endurance (Note 13) Retention Mass_Write (Note 13) Mass Write Operation Time CONDITIONS MIN TYP MAX 0.25 ±3 UNITS °C °C °C ms VTSNS = 72mV (Note 8) VRUN0,1 = 0.0V, fSYNC = 0kHz (Note 8) (Note 6) l 6V < VIN < 24V ICC = 0mA to 50mA l 4.8 5 0.5 5.2 ±2 V % 4.5V < VINTVCC/VEXTVCC VDD33 VDD33 = GND l 3.2 3.3 70 3.5 3.1 3.40 V mA V V l 2.25 2.5 50 2.75 V mA ±7.5 % ±1 120 VDD25 VDD25 = GND 250kHz < fSYNC < 1MHz Measured Falling Edge-to-Falling Edge of SYNC with SWITCH_FREQUENCY = 250.0.and 1000.0 VCLKIN Falling VCLKIN Rising ILOAD = 3mA 0V VPIN 3.6V MFR_PWM_CONFIG[2:0] = 0, 2, 3 MFR_PWM_CONFIG[2:0] = 5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0] = 4, 6 MFR_PWM_CONFIG[2:0] = 3 MFR_PWM_CONFIG[2:0] = 0 MFR_PWM_CONFIG[2:0] = 2, 4, 5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0] = 6 l 0°C < TJ < 85°C During EEPROM Write Operations TJ < 125°C STORE_USER_ALL, 0°C < TJ < 85°C During EEPROM Write Operations l 10,000 l 10 Digital Inputs SCL, SDA, RUN0, RUN1, GPIO0, GPIO1 VIH Input High Threshold Voltage SCL, SDA, RUN0, RUN1, GPIO0, GPIO1 Input Low Threshold Voltage SCL, SDA, RUN0, RUN1, GPIO0, GPIO1 VIL Input Hysteresis SCL, SDA VHYST Input Capacitance CPIN Digital Input WP Input Pull-Up Current WP IPUWP Open-Drain Outputs SCL, SDA, GPIO0, GPIO1, ALERT, RUN0, RUN1, SHARE_CLK Output Low Voltage ISINK = 3mA VOL 1 1.5 0.2 l 0.4 ±5 0 60 90 120 120 180 240 270 300 Cycles 440 l 4100 2.0 l l 1.4 0.08 10 10 l V V V µA Deg Deg Deg Deg Deg Deg Deg Deg Deg Years ms V V V pF µA 0.4 V 3880f 7 LTC3880/LTC3880-1 LTC3880/LTC3880-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER Digital Inputs SHARE_CLK, WP Input High Threshold Voltage VIH Input Low Threshold Voltage VIL Leakage Current SDA, SCL, ALERT, RUN0, RUN1 Input Leakage Current IOL Leakage Current GPIO0, GPIO1 Input Leakage Current IGL Digital Filtering of GPIO0, GPIO1 Input Digital Filtering GPIO IFLTG Digital Filtering of RUN0, RUN1 Input Digital Filtering RUN IFLTG PMBus Interface Timing Characteristics Serial Bus Operating Frequency fSMB Bus Free Time Between Stop and Start tBUF Hold time After Repeated Start Condition. tHD,STA After this Period, the First Clock is Generated Repeated Start Condition Setup Time tSU,STA Stop Condition Setup Time tSU,STO Data Hold Time tHD,DAT Receiving Data Transmitting Data Data Setup Time tSU,DAT Receiving Data tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads Stuck PMBus Timer Block Reads Serial Clock Low Period tLOW Serial Clock High Period tHIGH CONDITIONS MIN TYP MAX 1.5 1 1.8 0.6 V V l l UNITS 0V VPIN 5.5V l ±5 µA 0V VPIN 3.3 V 0V VPIN < 3.6V l ±1 ±1 µA µA 3 10 l l l µs 10 1.3 0.6 l l l 0 0.3 l 400 0.6 0.6 0.1 l Measured from the Last PMBus Start Event Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3880/LTC3880-1 LTC3880/LTC3880-1 are tested under pulsed load conditions such that TJ TA. The LTC3880E/LTC3880E-1 LTC3880E/LTC3880E-1 are guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the ­40°C to 105°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD · JA) The maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. µs µs µs 0.9 32 150 l l 1.3 0.6 kHz µs µs 10000 µs µs µs ms ms µs µs Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits mantissa (signed). This limits the output resolution to 10 bits though the internal ADC is 16 bits and the calculations use 32-bit words. Note 6: The data conversion is done in round robin fashion. All inputs signals are continuously converted for a typical latency of 120ms. Note 7: The IOUT_CAL_GAIN = 1.0m and MFR_IOUT_CAL_GAIN_TC = 0.0. Value as read from READ_IOUT in amperes. Note 8: Part tested with PWM disabled. Evaluation in application demonstrates capability. Note 9: All VOUT commands assume the ADC is used to auto-zero the output to achieve the stated accuracy. LTC3880 LTC3880 is tested in a feedback loop that servos VOUT to a specified value. Note 10: The maximum VOUT voltage is 5.5V. Note 11: The maximum VIN voltage is 28V. Note 12: When VIN < 6V, INTVCC must be tied to VIN. Note 13: EEPROM endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification. The RESTORE_USER_ALL command (NVM read) is valid over the entire operating temperature range. 3880f 8 LTC3880/LTC3880-1 LTC3880/LTC3880-1 ELECTRICAL CHARACTERISTICS Note 14: The LTC3880-1 LTC3880-1 quiescent current (IQ) equals the IQ of VIN plus the IQ of EXTVCC. Note 15: Guaranteed with a common mode voltage (VOUT) between 0V and 3.6V. TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current, VOUT = 3.3V (LTC3880 LTC3880) Efficiency vs Load Current, VOUT = 1.8V (LTC3880 LTC3880) 90 80 70 70 60 50 VIN = 12V fSW = 364kHz L = 0.56µH DCR = 1.8m CCM DCM BM 40 30 20 10 0 10 1000 10000 100 LOAD CURRENT (mA) 91.0 60 50 VIN = 12V fSW = 370kHz L = 0.56µH DCR = 1.8m CCM DCM BM 40 30 20 10 0 100000 VOUT = 1.8V IOUT = 10A 90.5 10 1000 10000 100 LOAD CURRENT (mA) EFFICIENCY (%) 80 EFFICIENCY (%) 90 EFFICIENCY (%) 100 2200 89.5 2100 89.0 2000 88.0 1900 7 5 9 11 INPUT VOLTAGE (V) 13 3880 G02 3880 G01 Load Step (Burst Mode Operation) 2400 2300 90.0 88.5 100000 2500 POWER LOSS (mW) 100 Efficiency and Power Loss vs Input Voltage (LTC3880 LTC3880) 15 1800 3880 G03 Load Step (Forced Continuous Mode) Load Step (Pulse-Skipping Mode) ILOAD 10A/DIV ILOAD 10A/DIV ILOAD 10A/DIV ITH 1V/DIV ITH 1V/DIV ITH 1V/DIV VOUT 200mV/DIV AC-COUPLED VOUT 200mV/DIV AC-COUPLED VOUT 200mV/DIV AC-COUPLED VIN = 12V 500µs/DIV VOUT = 1.8V 0A TO 18A STEP 3880 G04 VIN = 12V 500µs/DIV VOUT = 1.8V 0A TO 18A STEP Inductor Current at Light Load 3880 G05 VIN = 12V 500µs/DIV VOUT = 1.8V 0A TO 18A STEP Start-Up into a Pre-Biased Load FORCED CONTINUOUS MODE 2A/DIV Soft-Start Ramp RUN 2V/DIV PULSE-SKIPPING MODE 2A/DIV RUN 2V/DIV VOUT 1V/DIV Burst Mode OPERATION 2A/DIV VOUT 1V/DIV tRISE = 10ms tDELAY = 5ms VIN = 12V VOUT = 1.8V ILOAD = 100µA 1µs/DIV 3880 G06 5ms/DIV 3880 G08 tRISE = 10ms tDELAY = 5ms 5ms/DIV 3880 G09 3880 G07 3880f 9 LTC3880/LTC3880-1 LTC3880/LTC3880-1 RUN 2V/DIV VOUT 1V/DIV tFALL = 5ms tDELAY = 10ms 5ms/DIV 3880 G10 Current Sense Threshold vs ITH Voltage (Low Range) 60 50 40 30 20 10 0 ­10 ­20 VSENSE 50mV VSENSE 25mV 0 0.5 1 1.5 VITH (V) 2 MAXIMUM CURRENT SENSE THRESHOLD (mV) Soft-Off Ramp CURRENT LIMIT (A) WITH 1m SENSE RESISTOR TYPICAL PERFORMANCE CHARACTERISTICS 2.5 55 Maximum Current Sense Threshold vs Duty Cycle, VOUT = 0V 50mV SENSE CONDITION 54 53 52 51 50 49 48 47 46 45 30 0 70 50 DUTY CYCLE (%) 90 3880 G12 3880 G11 55 Regulated Output vs Temperature 110 0.5020 0.5015 52 0.5010 51 0.5005 50 49 SHARE_CLK FREQUENCY (kHz) 53 0.5000 0.4995 48 0.4990 47 0.4985 46 105 100 0.4980 45 0 1 3 4 5 2 COMMON MODE VOLTAGE (V) 6 0.4975 ­50 ­30 ­10 10 30 50 70 TEMPERATURE (°C) 3880 G13 90 95 90 ­50 ­30 ­10 10 30 50 70 TEMPERATURE (°C) 110 3880 G14 SHARE-CLK Frequency vs VIN 90 110 3880 G15 Quiescent Current vs Temperature VOUT Measurement vs VOUT 0.40 30 101.0 100.5 100.0 99.5 MEASSURED ERROR (mV) 0.30 QUIESCENT CURRENT (mA) SHARE_CLOCK FREQUENCY (kHz) SHARE_CLK Frequency vs Temperature 0.5025 50mV SENSE CONDITION 54 VOUT (V) MAXIMUM CURRENT SENSE THRESHOLD (mV) Maximum Current Sense Threshold vs Common Mode Voltage 25 20 0.20 0.10 0 ­0.10 ­0.20 ­0.30 99.0 6 8 10 12 14 16 18 20 22 24 26 28 VIN (V) 3880 G16 15 ­50 ­30 ­10 10 30 50 70 TEMPERATURE (°C) 90 110 3880 G17 ­0.40 0.5 1 1.5 2 2.5 3 3.5 VOUT (V) 4 4.5 5 5.5 3880 G18 3880f 10 LTC3880/LTC3880-1 LTC3880/LTC3880-1 TYPICAL PERFORMANCE CHARACTERISTICS VOUT Command INL VOUT Command DNL INTVCC Line Regulation 5.25 0.2 5.00 1.0 0.1 0.5 4.75 INTVCC (V) DNL (LSBs) 0.3 1.5 INL (LSBs) 2.0 0 0 ­0.1 ­0.5 ­0.2 ­1.0 0.5 1 1.5 2 2.5 3 3.5 VOUT (V) 4 4.5 5 ­0.3 5.5 3.75 0.5 1 1.5 2 2.5 3 3.5 VOUT (V) 4 4.5 5 3.50 5.5 1.010 VOUT OV Threshold vs Temperature (4V Target) 4.04 4.03 4V OV THRESHOLD (V) 2V OV THRESHOLD (V) 1V OV THRESHOLD (V) 2.02 0.995 2.01 2.00 1.99 1.98 90 4.02 4.01 4.00 3.99 3.98 3.97 1.97 ­50 ­25 110 0 3.96 ­50 ­25 25 50 75 100 125 150 TEMPERATURE (°C) 3880 G22 1.0 6 0.8 MEASUREMENT ERROR (mA) 0 ­0.2 ­0.4 ­0.6 2 4 2 0 ­2 ­4 ­0.8 ­6 ­1.0 ­45 ­25 ­5 15 35 55 75 95 115 ACTUAL TEMPERATURE (°C) ­8 3880 G25 IIN Measurement Error vs IIN 0 IIN MEASUREMENT ERROR (mA) 8 0.2 25 50 75 100 125 150 TEMPERATURE (°C) 3880 G24 IOUT Error vs IOUT Room Temperature 0.4 0 3880 G23 Temperature Error vs Temperature 0.6 25 20 3880 G21 2.03 1.000 15 VIN (V) VOUT OV Threshold vs Temperature (2V Target) 1.005 10 5 3880 G20 VOUT OV Threshold vs Temperature (1V Target) MEASUREMENT ERROR (°C) 4.25 4.00 3880 G19 0.990 ­50 ­30 ­10 10 30 50 70 TEMPERATURE (°C) 4.50 0 10 5 15 OUTPUT CURRENT (A) 20 ­2 ­4 ­6 ­8 ­10 ­12 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 IIN (A) 3880 G26 3880 G27 3880f 11 LTC3880/LTC3880-1 LTC3880/LTC3880-1 TYPICAL PERFORMANCE CHARACTERISTICS DC Output Current Matching in a 2-Phase System (LTC3880 LTC3880) Dynamic Current Sharing During a Load Transient in a 4-Phase System Dynamic Current Sharing During a Load Transient in a 4-Phase System 25 CHANNEL CURRENT (A) 20 CURRENT 10 5A/DIV CURRENT 10 5A/DIV 0 15 0 10 5µs/DIV 3880 G29 5µs/DIV 3880 G29 5 0 CHAN 0 CHAN 1 0 5 25 30 10 15 20 TOTAL CURRENT (A) 35 40 3880 G28 PIN FUNCTIONS VSENSE0+ (Pin 1): Channel 0 Positive Voltage Sense Input. VSENSE0­ (Pin 2): Channel 0 Negative Voltage Sense Input. ITH0/ITH1 (Pin 5/Pin 26 ): Current Control Threshold and Error Amplifier Compensation Nodes. Each associated channel's current comparator tripping threshold increases with its ITH voltage. ISENSE0+/ISENSE1+ (Pins 6/Pin 3): Current Sense Comparator Inputs. The (+) inputs to the current comparators are normally connected to DCR sensing networks or current sensing resistors. ISENSE0­/ISENSE1­ (Pin 7/Pin 4): Current Sense Comparator Inputs. The (­) inputs are connected to the low side of the current sense element. SYNC (Pin 8): External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. If clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse to ground. A resistor pull up to 3.3V is required in the application if the LTC3880 LTC3880 is the master. SCL (Pin 9): Serial Bus Clock Input. Open-drain output, can hold the output low if clock stretching is enabled. A pull-up resistor to 3.3V is required in the application. SDA (Pin 10): Serial Bus Data Input and Output. A pull-up resistor to 3.3V is required in the application. ALERT (Pin 11): Open-Drain Digital Output. Connect the SMBALERT signal to this pin. A pull-up resistor to 3.3V is required in the application. GPIO0/GPIO1 (Pin 12/Pin 13): Digital Programmable General Purpose Inputs and Outputs. Open-drain output. A pull-up resistor to 3.3V is required in the application. RUN0/RUN1 (Pin 14/Pin 15): Enable Run Input. Logic high on these pins enables the controller. Open-drain output holds the pin low until the LTC3880 LTC3880 is out of reset. A pullup resistor to 3.3V is required in the application. ASEL (Pin 16): Serial Bus Address Configuration Input. Connect a ±1% resistor divider between the chip VDD25 VDD25 ASEL and SGND in order to select the 4LSBs of the serial bus interface address. A resistor divider on ASEL is recommended if there are more than 1 LTC3880 LTC3880 on the same board to assure the user can independently program each IC. If the pin is left open, the IC will use the value programmed in the NVM. Minimize capacitance when the pin is open to assure accurate detection of the pin state. 3880f 12 LTC3880/LTC3880-1 LTC3880/LTC3880-1 PIN FUNCTIONS FREQ_CFG (Pin 17): Frequency or Phase Set/Select Pin. Connect a ±1% resistor divider between the chip VDD25 VDD25 FREQ_CFG and SGND in order to select switching frequency or phase. If the pin is left open, the IC will use the value programmed in the NVM. Minimize capacitance when the pin is open to assure accurate detection of the pin state. VSENSE1 (Pin 27): Channel 1 Voltage Sense Input. This input voltage is referenced to the SGND pin. VOUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Output Voltage Select Pin. Connect a ±1% resistor divider between the chip VDD25 VDD25 VOUTn_CFG and SGND in order to select output voltage. This voltage can be adjusted with the VTRIMn_CFG pins. If the pin is left open, the IC will use the value programmed in the NVM. Minimize capacitance when the pin is open to assure accurate detection of the pin state. EXTVCC (Pin 33) LTC3880-1 LTC3880-1: External Regulator 5V input. The control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. VTRIM0_CFG/VTRIM1_CFG (Pin 20/Pin 21): Voltage Trim Select Pin. Connect a ±1% resistor divider between the chip VDD25 VDD25 VTRIMn_CFG and SGND in order to adjust the output voltage set point. The VTRIMn_CFG settings in conjunction with the VOUTn_CFG setting adjusts the voltage set point. If the pin is left open, the IC will either not modify the VOUTn_CFG setting or use NVM. Minimize capacitance when the pin is open to assure accurate detection of the pin state. VDD25 VDD25 (Pin 22): Internally Generated 2.5V power Supply Output Pin. Bypass this pin to SGND with a low ESR 1µF capacitor. Do not load this pin with external current except for the ±1% resistor dividers required for the configuration pins. INTVCC (Pin 33) LTC3880 LTC3880: Internal Regulator 5V Output. The control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. PGND (Pin 34): Power Ground Pin. Connect this pin closely to the sources of the bottom N-channel MOSFETs, the (­) terminal of CVCC and the (­) terminal of CIN. VIN (Pin 35): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1µF to 1µF). BG0/BG1 (Pin 36/Pin 32): Bottom Gate Driver Outputs. These pins drive the gates of the bottom N-Channel MOSFETs between PGND and INTVCC. BOOST0/BOOST1 (Pin 37/Pin 31): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. TG0/TG1 (Pin 38/Pin 30): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch node voltages. WP (Pin 23): Write Protect Pin Active High. An internal 10µA current source pulls the pin to VDD33 VDD33. If WP is high, the PMBus writes are restricted. SW0/ SW1 (Pin 39/Pin 29): Switch Node Connections to Inductors. Voltage swings at the pins are from a Schottky diode (external) voltage drop below ground to VIN. SHARE_CLK (Pin 24): Share Clock, Bidirectional OpenDrain Clock Sharing Pin. Nominally 100kHz. Used to synchronize the timing between multiple LTC3880s. Tie all SHARE_CLK pins together. All LTC3880s will synchronize to the fastest clock. A pull-up resistor to 3.3V is required. TSNS0/TSNS1 (Pin 40/Pin 28): Channel 0,1 External Diode Temperature Sense. Connect to the anode of a diode connected PNP transistor and star connect the cathode to SGND in order to sense remote temperature. If external temperature sense elements are not installed, short pin to ground and set the UT_FAULT_LIMIT to ­275°C and the UT_FAULT_RESPONSE to ignore. VDD33 VDD33 (Pin 25): Internally Generated 3.3V Power Supply Output Pin. Bypass this pin to SGND with a low ESR 1µF capacitor. Do not load this pin with external current except for the pull-up resistors required for GPIOn, SCLK, SYNC and possibly RUNn, SDA and SCL. SGND (Exposed Pad Pin 41): Signal Ground. All smallsignal and compensation components should connect to this ground, which in turn connects to PGND at one point. 3880f 13 LTC3880/LTC3880-1 LTC3880/LTC3880-1 BLOCK DIAGRAM (One of two channels (CH0) shown) VIN 35 VIN ON/OFF 19R + ­ R 8-BIT VIN DAC 38R R 5V REG LTC3880 LTC3880 ONLY 3k + ­ + ­ ICMP CIN INTVCC/EXTVCC (LTC3880-1 LTC3880-1) INTVCC /EXTVCC 33 SGND VDD33 VDD33 3.3V SUBREG VDD33 VDD33 25 BOOST0 S R Q PWM_CLOCK VIN + 37 TG0 IREV M1 SW0 ON 39 SWITCH LOGIC AND ANTISHOOTTHROUGH UV REV UVLO SS ILIM RANGE SELECT HI: 1:1 LO: 1:1.5 CB 38 FCNT ISENSE0+ DB 6 ISENSE0­ + 7 RUN BG0 OV VOUT0 COUT M2 36 CVCC 34 SLOPE COMPENSATION INTVCC ITH0 UVLO ACTIVE CLAMP 1 71.1k 16-BIT 16-BIT ADC ILIM DAC (3 BITS) 5 + ­ 2µA RC CC1 SLEEP + EA 30µA + ­ ­ + + ­ + 8:1 ­ + MUX ­ + ­ + ­ + ­ PGND NO DIFF AMP ON CH1 R R ­ AO + ISENSE1+ ISENSE1­ VSENSE1 R R PWM0 PWM1 ­ + ­ + ­ + SGND ­ + 1.22V REF 40 9R 0.56V SGND 2R 12-BIT 12-BIT SET POINT DAC 8-BIT UV DAC 8-BIT OV DAC SGND 8 SYNC PHASE DET M3 VCO PHASE SELECTOR VDD33 VDD33 WP 23 SCL 9 SDA 10 PMBus INTERFACE (400kHz COMPATIBLE) VDD33 VDD33 COMPARE MAIN CONTROL ALERT 11 RUN1 15 GPIO1 13 SHARE_CLK 24 PWM CLOCK SGND VDD33 VDD33 VDD25 VDD25 CLOCK DIVIDER 2.5V SUBREG SLAVE MISO CLK MOSI MASTER SINC3 RUN0 14 GPIO0 12 2 TSNS0 TMUX VSTBY VSENSE0+ 41 SGND OV UV 1 VSENSE0­ UVLO 22 VDD25 VDD25 18 VOUT0_CFG OSC (32MHz) 19 VOUT1_CFG CONFIG DETECT CHANNEL TIMING MANAGEMENT PROGRAM ROM RAM 20 VTRIM0_CFG 21 VTRIM1_CFG 17 FREQ_CFG EEPROM 16 ASEL 3880 F01 Figure 1. Block Diagram 3880f 14 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION OVERVIEW The LTC3880 LTC3880 is a dual channel/dual phase, constant frequency, analog current mode controller for DC/DC step-down applications with a digital interface. A typical application circuit is shown on the first page of this data sheet. Major features include: Programmable Output Voltage n Programmable Input Voltage Comparator n Programmable Current Limit n Programmable Switching Frequency n Programmable OV and UV Comparators n Programmable On and Off Delay Times n Programmable Output Rise/Fall Times n Phase-Locked Loop for Synchronous, Polyphase Operation (2, 3, 4 or 6 Phases) n Input and Output Voltage/Current, Temperature and Duty Cycle Telemetry n Average Output Current n Average PWM Duty Cycle n Average Output Voltage n Average Input Voltage n Average Input Current n Configurable, Latched and Unlatched Individual Fault and Warning Status n Individual channels are accessed through the PMBus using the PAGE command, i.e., PAGE 0 or 1. Fault reporting and shutdown behavior are fully configurable. Two individual GPIO outputs are provided (GPIO0, GPIO1), both of which can be masked independently. A dedicated pin for ALERT is provided. The shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes. Individual status commands enable fault reporting over the serial bus to identify the specific fault event. Fault or warning detection includes the following: Output Undervoltage/Overvoltage n Fully Differential Load Sense n Integrated Gate Drivers n Non-Volatile Configuration Memory n n n n Optional External Configuration Resistors for Key Operating Parameters n Optional Time-Base Interconnect for Synchronization Between Multiple Controllers Input Undervoltage/Overvoltage Input and Output Overcurrent Internal Overtemperature External Overtemperature n Communication, Memory or Logic (CML) Fault n n Fault Logging n WP Pin to Protect Internal Configuration n Standalone Operation After User Factory Configuration n PMBus, 400kHz Compliant Interface n The PMBus interface provides access to important power management data during system operation including: Internal Controller Temperature n External System Temperature via Optional Diode Sense Elements n MAIN CONTROL LOOP The LTC3880 LTC3880 is a constant frequency, current mode stepdown controller containing two channels operating with various user-defined relative phasing. During normal operation each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin which is the output of each error amplifier, EA. The EA negative terminal is equal to the VSENSE voltage divided by 5.5 (2.75 if range = 1). The positive terminal of the EA is 3880f 15 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION connected to the output of a 12-bit DAC with values ranging from 0V to 1.024V. The output voltage, through feedback of the EA, will be regulated to 5.5 times the DAC output (2.75 times if range = 1). The DAC value is calculated by the part to synthesize the users desired output voltage. The output voltage is programmed by the user either with the resistor configuration pins detailed in Tables12 and 13 or by the VOUT command (either from NVM or by PMBus command). Refer to the PMBus command section of the data sheet or the PMBus specification for more details. The output voltage can be modified by the user at any time with a PMBus VOUT_COMMAND. This command will typically have a latency less than 10ms. The user is encouraged to reference the PMBus Power System Management Protocol Specification to understand how to program the LTC3880 LTC3880. This specification can be found at http://www.pmbus.org/specs.html. Continuing the basic operation description, the current mode controller will turn off the top gate when the peak current is reached. If the load current increases, VSENSE will slightly droop with respect to the DAC reference. This causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on. In continuous conduction mode, the bottom MOSFET stays on until the end of the switching cycle. EEPROM The LTC3880 LTC3880 contains internal EEPROM (nonvolatile memory) to store configuration settings and fault log information. EEPROM endurance retention and mass write operation time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations above TJ = 85°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures between 85°C and 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. The fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log EEPROM locations. If occasional writes to these registers occur above 85°C, the slight degradation in the data retention characteristics of the fault log will not take away from the usefulness of the function. It is recommended that the EEPROM not be written when the die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTC3880 LTC3880 will disable the write until the die temperature drops below 120°C. (The controller will also disable when the die temperature exceeds the internal overtemperature fault limit.) The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimensionless acceleration factor using the following equation: Ea 1 1 ­ · k TUSE +273 TSTRESS +273 AF = e where: AF = acceleration factor Ea = activation energy = 1.4eV K = 8.617 · 10­5 eV/°K TUSE = 125°C specified junction temperature TSTRESS = actual junction temperature in °C Example: Calculate the effect on retention when operating at a junction temperature of 135°C for 10 hours. TSTRESS = 130°C TUSE = 125°C AF= e[(1.4/8.617 · 10 ­5) · (1/398 ­ 1/403)] = 1.66 The equivalent operating time at 125°C = 16.6 hours. Thus the overall retention of the EEPROM was degraded by 16.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM retention rating of 87,480 hours at a maximum junction temperature of 125°C. POWER UP AND INITIALIZATION The LTC3880 LTC3880 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. It operates from a single input supply (4.5V to 24V) while three on-chip linear regulators generate internal 3880f 16 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION 2.5V, 3.3V and 5V. If VIN is below 6V, the INTVCC and VIN pins must be tied together. The controller configuration is initialized by an internal threshold based UVLO where VIN must be approximately 4V and the 5V, 3.3V and 2.5V linear regulators must be within approximately 20% of the regulated values. The LTC3880-1 LTC3880-1 does not have an internal 5V linear regulators. The EXTVCC pin is driven by an external regulator to improve efficiency of the circuit and minimize power on the LTC3880 LTC3880. The EXTVCC pin must exceed approximately 4V before the internal UVLO is exceeded. To minimize application power, the EXTVCC pin can be supplied by a switching regulator. During initialization, the external configuration resistors are identified and/or contents of the NVM are read into the controller's commands and all PWM outputs are in high impedance (Hi-Z) mode. The RUNn and GPIOn pins are held low. The LTC3880 LTC3880 will use the contents of Tables 12 to 15 to determine the resistor defined parameters. See the Resistor Configuration section for more detail. The resistor configuration pins only control some of the preset values of the controller. The remaining values are programmed in NVM either at the factory or by the user. If the configuration resistors are not inserted or if the ignore RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_ALL configuration command), the LTC3880 LTC3880 will use only the contents of NVM to determine the DC/DC characteristics. The ASEL value read at power-up or reset is always respected unless the pin is open. The ASEL will use the MSB from NVM and the LSB from the detected threshold. See the Applications Information section for more detail. After the part has initialized, an additional comparator monitors VIN. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After VIN is initially applied, the part will typically require 80ms to initialize and begin the TON_DELAY timer. Status is available after approximately 120ms. SOFT-START The part must enter the run state prior to soft-start. The run pins are released by the LTC3880 LTC3880 after the part initializes and VIN is greater than the VIN_ON threshold. If multiple LTC3880s are used in an application, they all hold their respective run pins low until all devices initialize and VIN exceeds the VIN_ON threshold for every device. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. The SHARE_CLK pin is held low until the part has initialized after VIN is applied. The LTC3880 LTC3880 can be set to turn off (or remain off) if SHARE_CLK is low (set bit 2 of MFR_CHAN_CONFIG to a 1). This allows the user to assure synchronization across numerous LTC ICs even if the RUN pins can not be connected together due to board constraints. In general, if the user cares about synchronization between chips it is best to connect all the respective RUN pins together and to connect all the respective SHARE_CLK pins together. This assures all chips begin sequencing at the same time and use the same time base. After the RUN pin releases and prior to entering a constant output voltage regulation state, the LTC3880 LTC3880 performs a monotonic initial ramp or "soft-start". Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set-point. Once the LTC3880 LTC3880 is commanded to turn on, (after power up and initialization) the controller waits for the user specified turn-on delay (TON_DELAY) prior to initiating this output voltage ramp. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting the value of TON_RISE to any value less than 0.25ms. The LTC3880 LTC3880 PWM always uses discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. This will allow the regulator to start up into a pre-biased load. When the TON_MAX_FAULT_LIMIT is reached, the part transitions to continuous mode or burst, if so programmed. If TON_MAX_FAULT_LIMIT is set to zero, there is no time limit and the part transitions to the desired conduction mode after TON_RISE completes and VOUT has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present. Setting TON_MAX_FAULT_LIMIT to a value of 0 is not recommended. This described method of start-up sequencing is time based. 3880f 17 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION SEQUENCING The default mode for sequencing the outputs on and off is time based. Each output is enabled after waiting TON_DELAY amount of time following either a RUN pin going high, a PMBus command to turn on or the VIN rising above a preprogrammed voltage. Off sequencing is handled in a similar way. To assure proper sequencing, make sure all ICs connect the SHARE_CLK pin together and RUN pins together. If the RUN pins can not be connected together for some reason, set bit 2 of MFR_CHAN_CONFIG to a 1. This bit requires the SHARE_CLK pin to be clocking before the power supply output can start. When the RUN pin is pulled low, the LTC3880 LTC3880 will hold the pin low for the MFR_ RESTART_DELAY. The minimum MFR_RESTART_DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures proper sequencing of all rails. The LTC3880 LTC3880 calculates this delay internally and will not process a shorter delay. However, a longer commanded MFR_RESTART_DELAY will be used by the part. The maximum allowed value is 16.38 seconds. VOLTAGE-BASED SEQUENCING The GPIOn pins can be asserted when the UV threshold is exceeded for each output. It is possible to feed the GPIO pin from one output into the RUN pin of the next output in the sequence. To use the GPIOn pin for voltage based sequencing, set bit 12 of the MFR_GPIOn_PROPAGATE command = 1. Bit 12 is the VOUT_UVUF which is the unfiltered VOUT_UV comparator. Using the unfiltered VOUT_UV fault limit is recommended because there is little appreciable time delay between the comparator crossing Voltage Based Sequencing by Cascading GPIOs into RUN Pins START GPIO0 = VOUT0_UVUF RUN 0 LTC3880 LTC3880 RUN 1 GPIO1 = VOUT1_UVUF RUN 0 GPIO0 = VOUT0_UVUF LTC3880 LTC3880 RUN 1 GPIO1 = VOUT1_UVUF 3880 F02 TO NEXT CHANNEL IN THE SEQUENCE Figure 2. Event (Voltage) Based Sequencing the UV threshold and the GPIO pin releasing This can be implemented across multiple LTC3880s. The VOUT_UVUF has a 250µs filter. If the VOUT voltage bounces around the UV threshold for a long period of time it is possible for the GPIO output to toggle more than once. To minimize this problem, set the TON_RISE time under 100ms. If a fault in the string of rails is detected, only the faulted rail and downstream rails will fault off. The rails in the string of devices in front of the faulted rail will remain on unless commanded off. SHUTDOWN The LTC3880 LTC3880 supports two shutdown modes. The first mode is closed-loop shutdown response, with userdefined turn-off delay (TOFF_DELAY) and ramp down rate (TOFF_FALL). The controller will maintain the mode of operation for TOFF_FALL. In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. The other shutdown mode occurs in response to a fault condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG is set to a 1) or VIN falling below the VIN_OFF threshold or GPIO pulled low externally (if the MFR_GPIO_ RESPONSE is set to inhibit). Under these conditions the power stage is disabled in order to stop the transfer of energy to the load as quickly as possible. The shutdown state can be entered from the soft-start or active regulation states either through user intervention (deasserting RUNn or the PMBus OPERATION command) or in response to a detected fault or an external fault via the bidirectional GPIOn pins, or loss of SHARE_CLK (if bit 2 of MFR_CHAN_CONFIG is set to a 1) or VIN falling below the VIN_OFF threshold. In hiccup mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time (MFR_RETRY_DELAY). This delay minimizes the duty cycle associated with autonomous retries if the fault that caused the shutdown disappears once the output is disabled. The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If multiple outputs are controlled by the same GPIO pin, the longest 3880f 18 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION decay time of all the controlled outputs determines the retry delay. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit0 of MFR_CHAN_CONFIG. Alternatively, the controller can be configured so that it remains latched-off following a fault and clearing requires user intervention such as toggling RUNn or commanding the part OFF then ON. LIGHT LOAD CURRENT OPERATION The LTC3880 LTC3880 has three modes of operation including high efficiency Burst Mode operation, discontinuous conduction mode or forced continuous conduction mode. Mode selection is done using the MFR_PWM_MODE command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode). In Burst Mode operation the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below approximately 0.5V, the internal sleep mode asserts and both external MOSFETS are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA output begins to rise. When the output voltage drops sufficiently, sleep mode is deasserted, and the controller resumes normal operation by turning on the top external MOSFET on the next PWM cycle. If a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator, IREV, turns off the bottom gate external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller can operate in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the ITH pin. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry. Forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this and turn off the offending channel. However, this fault is based on an ADC read and can take up to 120ms to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction or Burst Mode operation. If the part is set to Burst Mode operation, as the inductor average current increases, the controller will automatically modify the operation from Burst Mode operation, to discontinuous mode to continuous mode. SWITCHING FREQUENCY AND PHASE The switching frequency of the LTC3880 LTC3880's controller can be established with internal clock references or with an external time-base. The LTC3880 LTC3880 can be configured for an external clock input through the programmed value in NVM, a PMBus command or setting the RBOTTOM resistor of the FREQ_CFG pin to 0 and the RTOP to open. The PMBus command FREQUENCY_SWITCH is set to external clock. The MFR_PWM_CONFIG command determines the relative phasing. Using the RCONFIG input, channel 0 and channel1 have a relative phasing of 0° and 180° with respect to the falling edge of SYNC. The master should be selected to be out of phase with the slave. Both RUN pins must be low or both channels commanded off before the FREQUENCY and MFR_PWM_CONFIG commands can be written to the LTC3880 LTC3880. The relative phasing of all devices in a PolyPhase rail should be optimally phased. The relative phasing of each rail is 360/n where n is the number of phases in the rail. If the LTC3880 LTC3880 is configured as the oscillator output on SYNC, the switching frequency source can be selected with either external configuration resistors or through serial bus programming. The FREQ_CFG configuration resistor pin can be used to select the FREQUENCY_ SWITCH and MFR_PWM_CONFIG values as outlined in Table14. Otherwise, the FREQUENCY_SWITCH and MFR_PWM_CONFIG PMBus commands can be used to select PWM switching frequency and the PWM channel phase relationship. The phase and frequency relationships are completely independent of each other providing the numerous application options for the user. If the LTC3880 LTC3880 is configured to drive the SYNC pin using the 3880f 19 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION programmed FREQUENCY_SWITCH command value, the SYNC pin will pull low at the desired clock rate with 500ns low pulse. Care must be taken in the application to assure the capacitance on SYNC is minimized to assure the pull-up resistor versus the capacitor load has a low enough time constant for the application. In addition, a phase-locked loop (PLL) is available to synchronize the internal oscillator to an external clock source that is connected to the SYNC pin. All phase relationships are between the falling edge of SYNC and the rising edge of the LTC3880 LTC3880 TG outputs. Multiple LTC3880s can be synchronized in order to realize PolyPhase arrays. OUTPUT VOLTAGE SENSING The channel 0 differential amplifier allows remote, differential sensing of the load voltage with VSENSE0n pins. The channel 1 sense pin (VSENSE1) is referenced to SGND. The telemetry ADC is fully differential and makes measurements of channels 0 and 1 output voltages at the VSENSE0n and VSENSE1/SGND pins, respectively. Due to head room limitations of the internal amplifier for VSENSE0, the maximum allowed differential sense voltage is 4.096V. 10k 4.99k 10k 10k 10k RUN ALERT GPIO SYNC SHARE_CLK 1µF CURRENT SENSING For DCR current sense applications, a resistor in series with a capacitor is placed across the inductor. In this configuration, the resistor is tied to the FET side of the inductor while the capacitor is tied to the load side of the inductor as shown in Figure 3. If the RC values are chosen such that the RC time constant matches the inductor time constant (L/DCR, where DCR is the inductor series resistance), the resultant voltage (VDCR) appearing across the capacitor will equal the voltage across the inductor series resistance and thus represent the current flowing through the inductor. The RC calculations are based on the room temperature DCR of the inductor. The RC time constant should remain constant, as a function of temperature. This assures the transient response of the circuit is the same regardless of the temperature. The DCR of the inductor has a large temperature coefficient, approximately 3900ppm/°C. The temperature coefficient of the inductor must be written to the MFR_IOUT_CAL_ GAIN_TC register. The external temperature is sensed near the inductor and used to modify the internal current limit circuit to maintain an essentially constant current LTC3880 LTC3880 + POWER STAGE ITH0 ITH1 ISENSE0+ GPIO0 ISENSE0­ VSENSE0+ RUN0 RUN1 VSENSE0­ ALERT GPIO1 SYNC ISENSE1+ SHARE_CLK VDD33 VDD33 ISENSE1­ VSENSE1 SGND 1µF NOTE: SOME CONNECTORS AND COMPONENTS OMITTED FOR CLARITY PGND 1/2 LTC3880 LTC3880 + POWER STAGE ITH0 VDD33 VDD33 RUN0 ALERT GPIO1 SYNC SHARE_CLK SGND ISENSE0+ ISENSE0­ VSENSE0+ VSENSE0­ PGND LOAD 3880 F03 Figure 3. Load Sharing Connections for 3-Phase Operation 3880f 20 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION limit with temperature. In this application, the ISENSEn+ pin is connected to the FET side of the capacitor while the ISENSEn­ pin is placed on the load side of the capacitor. The current sensed from the input is then given by the expression VDCR/DCR. VDCR is digitized by the LTC3880 LTC3880's telemetry ADC with an input range of ±128mV, a noise floor of 7µVRMS, and a peak-peak noise of approximately 46.5µV. The LTC3880 LTC3880 computes the inductor current using the DCR value stored in the IOUT_CAL_GAIN command and the temperature coefficient stored in command MFR_IOUT_CAL_GAIN_TC. The resulting current value is returned by the READ_IOUT command. LOAD SHARING Multiple LTC3880 LTC3880's can be arrayed in order to provide a balanced load-share solution by bussing the necessary pins. Figure 3 illustrates the shared connections required for load sharing. The frequency must only be programmed on one of the LTC3880s. The other(s) must be programmed to External Clock. EXTERNAL/INTERNAL TEMPERATURE SENSE External temperature can be best measured using a remote diode-connected PNP transistor such as the MMBT3906 MMBT3906. The emitter should be connected to the TSNSn pin while the base and collector terminals of the PNP transistor should be returned to the LTC3880 LTC3880's SGND pin, preferably using a star connection. It is possible to connect the collector of the PNP to the source of the bottom MOSFET. This may optimize board layout allowing the PNP closer proximity to the power FETs. The base of the PNP must still be tied to signal ground. For best noise immunity, the connections should be routed differentially and a 10nF capacitor should be placed in parallel with the diode connected PNP Two different currents . are applied to the diode (nominally 2µA and 32µA) and the temperature is calculated from the VBE measurement. The external transistor temperature is digitized by the telemetry ADC, and the value is returned by the PMBus READ_TEMPERATURE_1 (Chn) command. The READ_TEMPERATURE_2 command returns the junction temperature of the LTC3880 LTC3880 using an on-chip diode. The slope of the external temperature sensor can be modified with the temperature slope coefficient stored in MFR_TEMP_1_GAIN. Typical PNPs require temperature slope adjustments slightly less than 1. The MMBT3906 MMBT3906 has a recommended value in this command of approximately MFR_TEMP_1_GAIN = 0.991 based on the ideality factor of 1.01. Simply invert the ideality factor to calculate the MFR_TEMP_1_GAIN. Different manufacturers and different lots may have different ideality factors. Consult with the manufacturer to set this value. The offset of the external temperature sense can be adjusted by MFR_TEMP_1_OFFSET. A value of 0 in this register sets the temperature offset to ­273.15°C. If the PNP cannot be placed in direct contact with the inductor, the slope or offset can be increased to account for temperature mismatches. If the user is adjusting the slope, the intercept point is at absolute zero, ­273.15°C, so small adjustments in slope can change the apparent measured temperature significantly. Another way to artificially increase the slope of the temperature term is to increase the MFR_IOUT_CAL_GAIN_TC term. This will modify the temperature slope with respect to room temperature. TSNS LTC3880 LTC3880 SGND SGND 10nF MMBT3906 MMBT3906 3880 F04 Figure 4. Temperature Sense Circuit 3880f 21 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION RCONFIG (RESISTOR CONFIGURATION) PINS There are six input pins utilizing 1% resistor dividers between VDD25 VDD25 and SGND to select key operating parameters. The pins are ASEL, FREQ_CFG, VOUT0_CFG, VOUT1_CFG, VTRIM0_CFG and VTRIM1_CFG. If pins are floated, the value stored in the corresponding NVM command is used. If bit 6 of the MFR_CONFIG_ALL configuration command is asserted in NVM, the resistor inputs are ignored upon power-up except for ASEL which is always respected. The resistor configuration pins are only measured during a power-up reset or after an MFR_RESET command is executed. The VOUTn_CFG and VTRIMn pin settings are described in Tables 12 and 13. These pins select the output voltages for the LTC3880 LTC3880's analog PWM controllers. If both pins are open, the VOUT_COMMAND command is loaded from NVM to determine the output voltage. The following parameters are set as a percentage of the output voltage if the RCONFIG pins are used to determined output voltage: VOUT_OV_FAULT_LIMIT. +10% VOUT_OV_WARN. +7.5% nVOUT_MAX. +7.5% nVOUT_MARGIN_HI.+5% nPOWER_GOOD_ON.­7% nPOWER_GOOD_OFF.­8% nVOUT_MARGIN_LO.­5% nVOUT_UV_WARN.­6.5% nVOUT_UV_FAULT_LIMIT.­7% n n The FREQ_CFG pin settings are described in Table 14. This pin selects the switching frequency and phase relationships between the two channels and SYNC pin. To synchronize to an external clock, the part must be put into external clock mode (FREQ_CFG pin shorted to ground). If no external clock is supplied, the part will clock at the lowest freerunning frequency of the internal PWM oscillator. This low clock rate will increase the ripple current of the inductor possibly producing undesirable operation. If the external SYNC signal is missing or misbehaving, a "PLL Lock Status" fault will be indicated in the STATUS_MFR_SPECIFIC command. If the user does not wish to see the PLL_FAULT even if there is not a valid synchronization signal at power up, bit 3 of the MFR_CONFIG_ALL command must be asserted. If the SYNC pin is connected between multiple ICs only one of the ICs can be the oscillator, all other ICs must be configured to external clock. The ASEL pin settings are described in Table 15. This pin selects the bottom 4 bits of the slave address for the LTC3880 LTC3880. The 3 most significant bits are retrieved from the NVM MFR_ADDRESS command. If the pin is floating, the 7-bit value stored in NVM MFR_ADDRESS command is used to determine the slave address. For more detail, refer to Table 15a. Note: Per the PMBus specification, pin programmed parameters can be overridden by commands from the digital interface with the exception of ASEL which is always honored. Do not set any part address to 0x5A or 0x5B because these are global addresses and all parts will respond to them. FAULT DETECTION AND HANDLING A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include: Input OV/FAULT Protection and UV Warning n Average Input OC Warn n Output OV/UV Fault and Warn Protection n Output OC Fault and Warn Protection n Internal and External Overtemperature Fault and Warn Protection n External Undertemperature Fault and Warn Protection n CML Fault (Communication, Memory or Logic) n External Fault Detection via the Bidirectional GPIOn Pins. n In addition, the LTC3880 LTC3880 can map any combination of fault indicators to their respective GPIOn pin using the propagate GPIOn response commands, MFR_GPIO_PROPAGATE. Typical usage of a GPIO pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the GPIOn pins can be used as 3880f 22 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION inputs to detect external faults downstream of the controller that require an immediate response. The GPIO0 and/or GPIO1 pins can also be configured as power good outputs. Power good indicates the controller output is above the power good threshold. At power-up the pin will initially be three-state. If it is necessary to have the desired polarity on the pin at power-up in this configuration, attach a Schottky diode between the RUN pin of the propagated power good signal and the GPIO pin. The Cathode must be attached to RUN and the Anode to the GPIO pin. If the GPIO pin is set to a power good status, the MFR_GPIO_RESPONSE must be ignore otherwise there is a latched off condition with the controller. As described in the Soft-Start section, it is possible to control start-up through concatenated events. If GPIOn is used to drive the RUN pin of another controller, the unfiltered VOUT_UV fault limit should be mapped to the GPIO pin. Any fault or warning event will cause the ALERT pin to assert low. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1 or bias power is cycled or a MFR_RESET command is issued, or the RUN pins are toggled OFF/ON or the part is commanded OFF/ON via PMBus or an ARA command operation is performed. The MFR_GPIO_PROPAGATE command determines if the GPIO pins are pulled low when a fault is detected; however, the ALERT pin is always pulled low if a fault or warning is detected and the status bits are updated. Output and input fault event handling is controlled by the corresponding fault response byte as specified in Tables5 to 9. Shutdown recovery from these types of faults can either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault condition is not present after the retry interval has elapsed, a new soft-start is attempted. If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. The MFR_RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds. Channel-to-channel fault dependencies can be created by connecting GPIOn pins together. In the event of an internal fault, one or more of the channels is configured to pull the bussed GPIOn pins low. The other channels are then configured to shut down when the GPIOn pins are pulled low. For autonomous group retry, the faulted channel is configured to let go of the GPIOn pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF the GPIO pin remains asserted , low until either the RUN pin is toggled OFF/ON or the part is commanded OFF/ON or the ARA command operation is performed. The toggling of the RUN either by the pin or OFF/ON command will clear faults associated with the channel. If it is desired to have all faults cleared when either RUN pin is toggled, set bit 0 of MFR_CONFIG_ALL to a 1. The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands. Additional fault detection and handling capabilities are: CRC Failure The integrity of the NVM memory is checked after a poweron reset. A CRC failure will prevent the controller from leaving the inactive state. If a CRC failure occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin will be pulled low. NVM repair can be attempted by writing the desired configuration to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command. The LTC3880 LTC3880 manufacturing section of the NVM is mirrored. The NVM has the ability to perform limited repair if either one of the two sections of the manufacturing section of the NVM configuration becomes corrupted. If a discrepancy is detected, the "NVM CRC Fault" in the STATUS_MFR_SPECIFIC command is set. If this bit remains set after being cleared by issuing a CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable internal fault has occurred. The user is cautioned to disable both output power supply rails associated with this specific part. There are no provisions for field repairing unrecoverable NVM faults in the manufacturing section. 3880f 23 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION SERIAL INTERFACE The LTC3880 LTC3880 serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the NVM or an external resistor divider. In addition the LTC3880 LTC3880 always responds to the global broadcast address of 0x5A (7 bit) or 0x5B (7 bit). Address 0x5A is not paged and is performed on both channels. 0x5B respects the page command. Because address 0x5A does not support page, it can not be used for any paged reading commands. The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTC3880 LTC3880. Communication Failure PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low. DEVICE ADDRESSING The LTC3880 LTC3880 offers five different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) channel, 4) rail addressing and 5) alert response address (ARA). of an LTC3880 LTC3880. The value of the device address is set by a combination of the ASEL configuration pin and the MFR_ADDRESS command. When this addressing means is used, the PAGE command determines the channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS. Channel addressing provides a means of the PMBus master addressing a single channel of the LTC3880 LTC3880 without using the PAGE command. The value assigned to the paged MFR_CHANNEL_ADDRESS determines the specific channel the user wishes to act upon. Example: If MFR_CHANNEL_ADDRESS for page 0 is set to 0x57 and the MFR_CHANNEL_ADDRESS for page 1 is set to 0x54, the user can address channel 0 of the device by performing PMBus device commands using address 0x57 (7 bit). The user can address channel 1 of the device by performing PMBus device commands using address 0x54 (7 bit). This eliminates the user from first assigning the PAGE command and then the command to be acted upon. Rail addressing provides a means of the PMBus master addressing a set of channels connected to the same output rail, simultaneously. This is similar to global addressing, however, the PMBus address can be dynamically assigned by using the MFR_RAIL_ADDRESS command. The MFR_RAIL_ADDRESS is paged, so channels can be independently assigned to a specific rail. It is recommended that rail addressing should be limited to command write operations. All five means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. RESPONSES TO VOUT AND IOUT FAULTS Global addressing provides a means of the PMBus master to address all LTC3880 LTC3880 devices on the bus. The LTC3880 LTC3880 global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF Commands sent are . written to both channels simultaneously. Global command 0x5B (7 bit) or 0xB6 (8 bit) is paged and allows channel specific command of all LTC3880 LTC3880 devices on the bus. VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways. Device addressing provides the standard means of the PMBus master communicating with a single instance The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus these values are As a Percentage of the VOUT if Using the Resistor Configuration Pins n In NVM if Either Programmed at the Factory or Through the GUI n By PMBus Command n 3880f 24 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION based on average currents and can have a time latency of up to 120ms. The IOUT calculation accounts for the sense resistor and the temperature coefficient of the resistor. The input current is equal to the sum of output current times the respective channel duty cycle plus the input offset current for each channel. If this calculated input current exceed the IN_OC_WARN_LIMIT the ALERT pin is pulled low and the IIN_OC_WARN bit is asserted in the STATUS_INPUT register. The digital processor within the LTC3880 LTC3880 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). The retry interval is set in MFR_RETRY_DELAY and can be from 120ms to 83.88 seconds in 1ms increments. The shutdown for OV/UV and OC can be done immediately or after a user selectable deglitch time. Output Overvoltage Fault Response A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term overvoltages at the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared regardless of the PMBus VOUT_OV_FAULT_RESPONSE command byte value. Using the VOUT_OV_FAULT_RESPONSE command, the user can select any of the following behaviors: OV Pull-Down Only (OV cannot be ignored) n Shut Down (Stop Switching) Immediately-Latch Off n Shut Down Immediately-Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY n Either the Latch Off or Retry fault responses can be deglitched in increments of (0-7) · 10µs. See Table 5. Output Undervoltage Response The response to an undervoltage comparator output can be either: Ignore n Shut Down Immediately-Latch Off n Peak Output Overcurrent Fault Response Due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle by cycle basis. The value of the peak current limit is specified in sense voltage in the EC table. The current limit circuit operates by limiting the ITH maximum voltage. If DCR sensing is used, the ITH maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor. The LTC3880 LTC3880 automatically monitors the external temperature sensors and modifies the maximum allowed ITH to compensate for this term. The overcurrent fault processing circuitry can execute the following behaviors: Current Limit Indefinitely n Shut Down Immediately-Latch Off n Shut Down Immediately-Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY n The overcurrent responses can be deglitched in increments of (0-7) · 16ms. See Table 7 RESPONSES TO TIMING FAULTS TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT condition is predicated upon detection of the VOUT_UV_ FAULT_LIMIT as the output is undergoing a SOFT_START sequence. The TON_MAX_FAULT_LIMIT time is started after TON_DELAY has been reached and a SOFT_START sequence is started. The resolution of the TON_MAX_ FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT_LIMIT is not reached within the TON_MAX_FAULT_LIMIT time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE command value. This response may be one of the following: Ignore n Shut Down (Stop Switching) Immediately-Latch Off n Shut Down Immediately-Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY n Shut Down Immediately-Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY n The UV responses can be deglitched. See Table 6. 3880f 25 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT means the fault is ignored. The TON_MAX_FAULT_LIMIT should be set longer than the TON_RISE time. It is recommended TON_MAX_FAULT_ LIMIT always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user. The fault responses are: See Table 9. See Table 9. RESPONSES TO VIN OV FAULTS RESPONSES TO EXTERNAL FAULTS VIN overvoltage is measured with the MUX'd ADC; therefore, the response is naturally deglitched by the 120ms typical response time of the ADC. The fault responses are: When either GPIOn pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFC command, and the ALERT pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its GPIOn pin going low by modifying the MFR_GPIO_RESPONSE command. To avoid the ALERT pin asserting low when GPIO is pulled low, assert bit 1 of MFR_CHAN_CONFIG. Ignore n Shut Down Immediately-Latch Off n Shut Down Immediately-Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY n See Table 9. Ignore n Shut Down Immediately-Latch Off n Shut Down Immediately-Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY n FAULT LOGGING RESPONSES TO OT/UT FAULTS Overtemperature Fault Response-Internal An internal temperature sensor protects against NVM damage. Above 85°C, no writes to NVM are recommended. Above 130°C, the part disables the NVM and does not re-enable until the temperature has dropped to 120°C. Temperature is measured by the ADC. Internal temperature faults cannot be ignored. Internal temperature limits cannot be adjusted by the user. See Table 9. Overtemperature and Undertemperature Fault Response-Externals Two external temperature sensors can be used to sense critical circuit elements like inductors and power MOSFETs. The OT_FAULT_RESPONSE and UT_FAULT_RESPOSE commands are used to determine the appropriate response to an overtemperature and undertemperature condition, respectively. If no external sense elements are used (not recommended) set the UT_FAULT_RESPONSE to ignore and set the UT_FAULT_LIMIT to ­275°C. The LTC3880 LTC3880 has fault logging capability. Data is logged into memory in the order shown in Table 11. The data to be stored in the fault log is being continuously stored in internal volatile memory. When a fault event occurs, the recording into internal volatile memory is halted, the fault log information is available from the MFR_FAULT_LOG command, and the contents of the internal memory are copied into NVM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is not guaranteed. When the die temperature exceeds 130°C the fault logging is delayed until the die temperature drops below 120°C. After the fault condition that created the fault log event has been removed, clear the fault before the fault log data is erased, or else the part will immediately issue another fault log. When the LTC3880 LTC3880 powers-up, it checks the NVM for a valid fault log. If a valid fault log exists in NVM, the "Valid Fault Log" bit in the STATUS_MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault logging will be blocked until the LTC3880 LTC3880 has received a MFR_FAULT_LOG_CLEAR command before fault logging will be re-enabled. 3880f 26 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION The information is stored in EEPROM in the event of any fault that disables the controller on either channel. An external GPIOn pulling low will not trigger a fault logging event. BUS TIMEOUT FAILURE The LTC3880 LTC3880 implements a timeout feature to avoid hanging the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 25ms or the LTC3880 LTC3880 will three-state the bus and ignore the given data packet. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable. The LTC3880 LTC3880 allows longer PMBus timeouts for block read data packets. This timeout is proportional to the length of the block read. The additional block read timeout applies primarily to the MFR_FAULT_LOG command. In no circumstances will the timeout period be less than the tTIMEOUT_SMB specification of 32ms (typical). supported by all I2C controllers but is required for SMBus/ PMBus reads. If a general purpose I2C controller is used, check that repeat start is supported. For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1 Revision 1.1: Paragraph 5: Transport. For a description of the differences between SMBus and I2C, refer to System Management Bus (SMBus) Specification Version 2.0: Appendix B-Differences Between SMBus and I2C. PMBUS SERIAL DIGITAL INTERFACE The LTC3880 LTC3880 communicates with a host (master) using the standard PMBus serial bus interface. The Timing Diagram, Figure 5, shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTC3880 LTC3880 is a slave device. The master can communicate with the LTC3880 LTC3880 using the following formats: Master transmitter, slave receiver The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTC3880 LTC3880 supports the full PMBus frequency range from 10kHz to 400kHz. n SIMILARITY BETWEEN PMBUS, SMBUS AND I2C 2-WIRE INTERFACE n The PMBus 2-wire interface is an incremental extension of the SMBus. SMBus is built upon I2C with some minor differences in timing, DC parameters and protocol. The PMBus/SMBus protocols are more robust than simple I2C byte commands because PMBus/SMBus provide time-outs to prevent bus hangs and optional packet error checking (PEC) to ensure data integrity. In general, a master device that can be configured for I2C communication can be used for PMBus communication with little or no change to hardware or firmware. Repeat start (restart) is not Master receiver, slave transmitter n The following PMBus protocols are supported: Write Byte, Write Word, Send Byte n Read Byte, Read Word, Block Read Alert Response Address n Figures 7-16 illustrate the aforementioned PMBus protocols. All transactions support PEC (parity error check) and GCP (group command protocol). The Block Read supports 255 bytes of returned data. For this reason, the PMBus timeout may be extended when reading the fault log. Figure 6 is a key to the protocol diagrams in this section. PEC is optional. A value shown below a field in the following figures is a mandatory value for that field. 3880f 27 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION SDA tf tr tLOW tSU(DAT) tHD(SDA) tf tSP tr tBUF SCL tHD(STA) tHD(DAT) tSU(STA) tHIGH tSU(STO) 3880 F05 START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 5. Timing Diagram 1 S 7 1 1 SLAVE ADDRESS Wr A 8 1 1 DATA BYTE A P x x S START CONDITION Sr REPEATED START CONDITION Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) x SHOWN UNDER A FIELD INDICATES THAT THAT FIELD IS REQUIRED TO HAVE THE VALUE OF x A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0 FOR AN ACK OR 1 FOR A NACK) P STOP CONDITION Master reads slave immediately after the first byte. At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. Combined format. During a change of direction within a transfer, the master repeats both a start condition and the slave address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition. n MASTER TO SLAVE SLAVE TO MASTER CONTINUATION OF PROTOCOL Master transmitter transmits to slave receiver. The transfer direction in this case is not changed. n n PEC PACKET ERROR CODE . The data formats implemented by PMBus are: 3880 F06 Figure 6. PMBus Packet Protocol Diagram Element Key Examples of these formats are shown in Figures 7-16. 3880f 28 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION Table 1. Data Format Terminology PMBus TERMINOLOGY MEANING Linear Linear Linear_5s_11s L11 Page 35 Linear (for Voltage Related Commands) Linear Linear_16u L16 Page 35 Direct-Manufacturer Customized DirectMfr CF Page 35 Direct Hex ABBREVIATIONS FOR SUMMARY COMMAND TABLE FOR MORE DETAIL REFER TO THE DATA FORMAT SECTION OF TABLE 2 TERMINOLOGY FOR: SPECS, GUI, APPLICATION NOTES Hex 1 S 7 1 1 ASC Reg Register Fields I16 ASCII ASCII Reg 8 1 8 1 1 DATA BYTE SLAVE ADDRESS Wr A COMMAND CODE A A P 3880 F07 Figure 7. Write Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A P 3880 F08 Figure 8. Write Word Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE A PEC A P 3880 F09 Figure 9. Write Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A PEC A P 3880 F10 Figure 10. Write Word Protocol with PEC 3880f 29 LTC3880/LTC3880-1 LTC3880/LTC3880-1 OPERATION 1 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 8 P 3880 F11 Figure 11. Send Byte Protocol 1 S 7 1 1 8 1 8 1 1 PEC SLAVE ADDRESS Wr A COMMAND CODE A A P 3880 F12 Figure 12. Send Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 1 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 1 1 DATA BYTE HIGH A 8 P 1 3880 F13 Figure 13. Read Word Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 8 1 8 1 1 PEC DATA BYTE HIGH A A P 3880 F14 Figure 14. Read Word Protocol with PEC 1 S 7 1 1 8 1 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 1 DATA BYTE A P 1 3880 F15 Figure 15. Read Byte Protocol 1 S 7 1 1 8 1 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE A 1 PEC 1 A P 3880 F16 Figure 16. Read Byte Protocol with PEC Refer to Figure 6 for a legend. 3880f 30 LTC3880/LTC3880-1 LTC3880/LTC3880-1 PMBus COMMAND SUMMARY PMBUS COMMANDS The following tables list supported PMBus commands and manufacturer specific commands. A complete description of these commands can be found in the "PMBus Power System Mgt Protocol Specification ­ Part II ­ Revision 1.1". Users are encouraged to reference this specification. Exceptions or manufacturer specific implementations are listed below in Table 2. Floating point values listed in the "DEFAULT VALUE" column are either Linear 16-bit Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus Section7.1) format, whichever is appropriate for the command. All commands from 0xD0 through 0xFF not listed in this table are implicitly reserved by the manufacturer. Users should avoid blind writes within this range of commands to avoid undesired operation of the part. All commands from 0x00 through 0xCF not listed in this table are implicitly not supported by the manufacturer. Attempting to access non-supported or reserved commands may result in a CML command fault event. All output voltage settings and measurements are based on the VOUT_MODE setting of 0x14. This translates to an exponent of 2­12. Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.) COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE PAGE 0x00 61 Y 0x80 65 Y 0x1E 64 NA 90 0x00 61 N NA 98 N NA 98 Reg 0xB0 88 Y Reg 2­12 0x14 69 R/W Word Y L16 V Y 1.0 0x1000 70 0x24 Upper limit on the output voltage the unit can command regardless of any other commands. R/W Word Y L16 V Y 4.096 ch0 0x4189 5.5 ch1 0x5800 69 VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. R/W Word Y L16 V Y 1.05 0x10CD 70 VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. R/W Word Y L16 V Y 0.95 0x0F33 70 VOUT_TRANSITION_RATE 0X27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.25 AA00 76 FREQUENCY_SWITCH 0x33 Switching frequency of the controller. R/W Word N L11 kHz Y 350 0xFABC 67 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 6.5 0xCB40 68 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 6.0 0xCB00 68 PAGE 0x00 Channel or page currently selected for any command that supports paging. R/W Byte N Reg OPERATION 0x01 Operating mode control. On/off, margin high and margin low. R/W Byte Y Reg ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y Reg CLEAR_