LTC2208 25VP-P LTC2208-14 16-BIT /DA15 /DA14 /DA13 /DA12 /DA11 /DA10 /DB15 - Datasheet Archive

 

16-Bit, 130Msps ADC U FEATURES DESCRIPTIO The LTC®2208 is a 130Msps, sampling 16-bit A/D converter designed for digitizing

 

LTC2208 LTC2208 16-Bit, 130Msps ADC U FEATURES DESCRIPTIO The LTC®2208 is a 130Msps, sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end. Sample Rate: 130Msps 78dBFS Noise Floor 100dB SFDR SFDR >83dB at 250MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P 25VP-P or 1.5VP-P Input Range) 700MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer LVDS or CMOS Outputs Single 3.3V Supply Power Dissipation: 1.25W Clock Duty Cycle Stabilizer Pin Compatible 14-Bit Version 130Msps: LTC2208 LTC2208 (16-Bit), LTC2208-14 LTC2208-14 (14-Bit) 64-Pin (9mm × 9mm) QFN Package U APPLICATIO S Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE The LTC2208 LTC2208 is perfect for demanding communications applications, with AC performance that includes 78dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 70fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4LSB INL, ±1LSB DNL (no missing codes). The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC­ inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U TYPICAL APPLICATIO 3.3V SENSE 2.2µF AIN+ 1.25V COMMON MODE BIAS VOLTAGE + ANALOG INPUT AIN­ INTERNAL ADC REFERENCE GENERATOR 16-BIT 16-BIT PIPELINED ADC CORE S/H AMP ­ 64k Point FFT, FIN = 15.1MHz, ­1dB, PGA = 0 0.5V TO 3.6V 1µF OF CLKOUT D15 · · · D0 OUTPUT DRIVERS CORRECTION LOGIC AND SHIFT REGISTER AMPLITUDE (dBFS) VCM OVDD CMOS OR LVDS OGND CLOCK/DUTY CYCLE CONTROL 3.3V VDD GND 1µF 1µF 1µF 2208 TA01 ENC + ENC ­ PGA SHDN DITH MODE LVDS RAND 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 0 10 50 20 40 30 FREQUENCY (MHz) 60 2208 G03 ADC CONTROL INPUTS 2208fb 1 LTC2208 LTC2208 W U U W W W AXI U RATI GS U ABSOLUTE PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1 and 2) 64 PGA 63 RAND 62 MODE 61 LVDS 60 OF+/OFA 59 OF­/DA15 /DA15 58 D15+/DA14 /DA14 57 D15­/DA13 /DA13 56 D14+/DA12 /DA12 55 D14­/DA11 /DA11 54 D13+/DA10 /DA10 53 D13­/DA9 52 D12+/DA8 51 D12­/DA7 50 OGND 49 OVDD TOP VIEW SENSE 1 GND 2 VCM 3 GND 4 VDD 5 VDD 6 GND 7 AIN+ 8 AIN­ 9 GND 10 GND 11 ENC+ 12 ENC­ 13 GND 14 VDD 15 VDD 16 48 D11+/DA6 47 D11­/DA5 46 D10+/DA4 45 D10­/DA3 44 D9+/DA2 43 D9­/DA1 42 D8+/DA0 41 D8­/CLKOUTA 40 CLKOUT+/CLKOUTB 39 CLKOUT ­/OFB 38 D7+/DB15 /DB15 37 D7­/DB14 /DB14 36 D6+/DB13 /DB13 35 D6­/DB12 /DB12 34 D5+/DB11 /DB11 33 D5­/DB10 /DB10 65 VDD 17 GND 18 SHDN 19 DITH 20 ­/DB0 21 D0 DO+/DB1 22 D1­/DB2 23 D1+/DB3 24 D2­/DB4 25 D2+/DB5 26 D3­/DB6 27 D3+/DB7 28 D4­/DB8 29 D4+/DB9 30 OGND 31 OVDD 32 Supply Voltage (VDD) . ­0.3V to 4V Digital Output Ground Voltage (OGND). ­0.3V to 1V Analog Input Voltage (Note 3) . ­0.3V to (VDD + 0.3V) Digital Input Voltage . ­0.3V to (VDD + 0.3V) Digital Output Voltage .­0.3V to (OVDD + 0.3V) Power Dissipation. 2000mW Operating Temperature Range LTC2208C LTC2208C . 0°C to 70°C LTC2208I LTC2208I .­40°C to 85°C Storage Temperature Range .­65°C to 150°C Digital Output Supply Voltage (OVDD) . ­0.3V to 4V EXPOSED PAD IS GND (PIN 65) MUST BE SOLDERED TO PCB BOARD TJMAX = 125°C, JA = 20°C/W* ORDER PART NUMBER UP PART MARKING* LTC2208CUP LTC2208CUP LTC2208IUP LTC2208IUP LTC2208UP LTC2208UP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. *TJMAX = 150°C, option available, consult factory. U CO VERTER CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS Integral Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Offset Drift Gain Error Full-Scale Drift Differential Analog Input (Note 5) TA = 25°C Differential Analog Input (Note 5) Differential Analog Input (Note 6) Transition Noise External Reference Internal Reference External Reference External Reference MIN TYP MAX UNITS ±1.2 ±1.5 ±0.3 ±2 ±10 ±0.2 ±30 ±15 2.9 ±4.0 ±4.5 ±1 ±8.5 LSB LSB LSB mV V/°C %FS ±1.5 ppm/°C ppm/°C LSBRMS 2208fb 2 LTC2208 LTC2208 U U A ALOG I PUT The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VIN VIN, CM IIN ISENSE IMODE ILVDS CIN PARAMETER Analog Input Range (AIN+ ­ AIN­) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage Current MODE Pin Pull-Down Current to GND LVDS Pin Pull-Down Current to GND Analog Input Capacitance tAP Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth tJITTER CMRR BW-3dB CONDITIONS 3.135V VDD 3.465V Differential Input (Note 7) 0V AIN+, AIN­ VDD 0V SENSE VDD MIN 10 10 6.5 1.8 1 UNITS VP-P V µA µA µA µA pF pF ns 70 fs RMS 1V < (AIN+ = AIN­) ENC­ TYP 1.5 or 2.25 1.25 MAX 1.5 1 3 W U DY A IC ACCURACY The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = ­1dBFS. (Note 4) SYMBOL SNR SFDR PARAMETER Signal-to-Noise Ratio Spurious Free Dynamic Range 2nd or 3rd Harmonic CONDITIONS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 30MHz Input (2.25V Range, PGA = 0) TA = 25°C 30MHz Input (2.25V Range, PGA = 0) 30MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) TA = 25°C 140MHz Input (1.5V Range, PGA = 1) 250MHz Input (2.25V Range, PGA = 0) 250MHz Input (1.5V Range, PGA =1 ) 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 30MHz Input (2.25V Range, PGA = 0) TA = 25°C 30MHz Input (2.25V Range, PGA = 0) 30MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) TA = 25°C 140MHz Input (1.5V Range, PGA = 1) 250MHz Input (2.25V Range, PGA = 0) 250MHz Input (1.5V Range, PGA = 1) MIN 76.5 76.1 73.8 73.4 88 87 86 84 TYP 77.7 75.3 77.6 77.3 75.2 77.5 75.1 76.9 74.8 74.5 75.4 73.8 100 100 95 94 100 90 95 85 90 89 78 83 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 2208fb 3 LTC2208 LTC2208 W U DY A IC ACCURACY The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = ­1dBFS unless otherwise noted. (Note 4) SYMBOL SFDR S/(N+D) PARAMETER Spurious Free Dynamic Range 4th Harmonic or Higher Signal-to-Noise Plus Distortion Ratio CONDITIONS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 30MHz Input (2.25V Range, PGA = 0) 30MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 250MHz Input (2.25V Range, PGA = 0) 250MHz Input (1.5V Range, PGA = 1) 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 30MHz Input (2.25V Range, PGA = 0) TA = 25°C 30MHz Input (2.25V Range, PGA = 0) 30MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) TA = 25°C 140MHz Input (1.5V Range, PGA = 1) MIN 90 88 76.3 75.9 73.6 73.2 100 250MHz Input (2.25V Range, PGA = 0) 250MHz Input (1.5V Range, PGA = 1) SFDR Spurious Free Dynamic Range at ­25dBFS Dither "OFF" 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 30MHz Input (2.25V Range, PGA = 0) 30MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 250MHz Input (2.25V Range, PGA = 0) 250MHz Input (1.5V Range, PGA = 1) SFDR Spurious Free Dynamic Range at ­25dBFS Dither "ON" 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 30MHz Input (2.25V Range, PGA = 0) 30MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 250MHz Input (2.25V Range, PGA = 0) 250MHz Input (1.5V Range, PGA = 1) TYP 100 100 100 100 100 100 95 95 90 90 77.7 75.3 MAX UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS 77.5 77.5 75.2 77.4 75 76.4 74.5 74.5 73.6 72.9 105 105 105 105 105 105 100 100 100 100 115 115 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 115 115 115 115 110 110 105 105 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 2208fb 4 LTC2208 LTC2208 W U WW CO O ODE BIAS CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation CONDITIONS IOUT = 0 IOUT = 0 3.135V VDD 3.465V VCM Output Resistance MIN 1.15 1mA | IOUT | 1mA TYP 1.25 +40 1 MAX 1.35 UNITS V ppm/°C mV/ V 2 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC­) VID Differential Input Voltage Common Mode Input Voltage VICM RIN Input Resistance CIN Input Capacitance LOGIC INPUTS (DITH, PGA, SHDN, RAND) VIH High Level Input Voltage VIL Low Level Input Voltage IIN Digital Input Current CIN Digital Input Capacitance LOGIC OUTPUTS (CMOS MODE) OVDD = 3.3V VOH High Level Output Voltage VOL Low Level Output Voltage ISOURCE Output Source Current ISINK Output Sink Current OVDD = 2.5V VOH High Level Output Voltage Low Level Output Voltage VOL OVDD = 1.8V VOH High Level Output Voltage VOL Low Level Output Voltage LOGIC OUTPUTS (LVDS MODE) STANDARD LVDS VOD Differential Output Voltage VOS Output Common Mode Voltage LOW POWER LVDS VOD Differential Ouptut Voltage VOS Output Common Mode Voltage CONDITIONS MIN (Note 7) Internally Set Externally Set (Note 7) 1.6 1.2 3.0 UNITS V V V k pF 6 3 VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) VDD = 3.3V MAX 0.2 (See Figure 2) (Note 7) VDD = 3.3V TYP 2 0.8 ±10 1.5 V V µA pF 3.299 3.29 0.01 0.10 ­50 50 0.4 V V V V mA mA IO = ­10µA IO = ­200µA IO = 160µA IO = 1.6mA 3.1 VOUT = 0V VOUT = 3.3V VDD = 3.3V VDD = 3.3V IO = ­200µA IO = 1.60mA 2.49 0.1 V V VDD = 3.3V VDD = 3.3V IO = ­200µA IO = 1.60mA 1.79 0.1 V V 100 Differential Load 100 Differential Load 100 Differential Load 100 Differential Load 247 1.125 350 1.2 454 1.375 mV V 125 1.125 175 1.2 250 1.375 mV V 2208fb 5 LTC2208 LTC2208 U W POWER REQUIRE E TS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = ­1dBFS. (Note 4) SYMBOL PARAMETER VDD Analog Supply Voltage PSHDN Shutdown Power STANDARD LVDS OUTPUT MODE OVDD Output Supply Voltage IVDD Analog Supply Current IOVDD Output Supply Current PDIS Power Dissipation LOW POWER LVDS OUTPUT MODE OVDD Output Supply Voltage IVDD Analog Supply Current IOVDD Output Supply Current PDIS Power Dissipation CMOS OUTPUT MODE OVDD Output Supply Voltage IVDD Analog Supply Current PDIS Power Dissipation CONDITIONS (Note 8) SHDN = VDD MIN 3.135 TYP 3.3 0.2 MAX 3.465 UNITS V mW (Note 8) 3 3.3 380 74 1498 3.6 450 90 1782 V mA mA mW 3 3.3 380 31 1356 3.6 450 50 1650 V mA mA mW 380 1250 3.6 450 1485 V mA mW (Note 8) (Note 8) 0.5 UW TI I G CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fS tL PARAMETER Sampling Frequency ENC Low Time CONDITIONS (Note 8) Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) tH ENC High Time Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) MIN 1 3.65 2.6 3.65 2.6 TYP 3.846 3.846 3.846 3.846 ­1 MAX 130 1000 1000 1000 1000 UNITS MHz ns ns ns ns ns tAP Sample-and-Hold Aperture Delay LVDS OUTPUT MODE (STANDARD and LOW POWER) tD ENC to DATA Delay tC ENC to CLKOUT Delay (Note 7) 1.3 2.5 3.8 ns (Note 7) 1.3 2.5 3.8 ns tSKEW (tC-tD) (Note 7) ­0.6 0 0.5 0.5 7 0.6 ns ns ns Cycles (Note 7) (Note 7) (tC-tD) (Note 7) Full Rate CMOS Demuxed 1.3 1.3 ­0.6 2.7 2.7 0 7 7 4.0 4.0 0.6 ns ns ns Cycles Cycles DATA to CLKOUT Skew tRISE Output Rise Time tFALL Output Fall Time Data Latency Data Latency CMOS OUTPUT MODE tD ENC to DATA Delay tC ENC to CLKOUT Delay tSKEW DATA to CLKOUT Skew Data Latency Data Latency 2208fb 6 LTC2208 LTC2208 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 130MHz, LVDS outputs, differential ENC+/ ENC­ = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P 25VP-P with differential drive (PGA = 0), unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a "best fit straight line" to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from ­1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2's complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. W UW TI I G DIAGRA LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels tAP ANALOG INPUT N+1 N+4 N N+3 N+2 tH tL ENC­ ENC+ tD N­7 D0-D15 D0-D15, OF CLKOUT+ CLKOUT ­ N­6 N­5 N­4 N­3 tC 2208 TD01 2208fb 7 LTC2208 LTC2208 W UW TI I G DIAGRA S Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N+4 N N+3 N+2 tH tL ENC­ ENC+ tD N­7 DA0-DA15 DA0-DA15, OFA N­6 N­5 N­4 N­3 tC CLKOUTA CLKOUTB HIGH IMPEDANCE DB0-DB15 DB0-DB15, OFB 2208 TD02 Demultiplexed CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N N+4 N+2 N+3 tH tL ENC­ ENC+ tD N­8 N­6 N­4 N­7 DA0-DA15 DA0-DA15, OFA N­5 N­3 tD DB0-DB15 DB0-DB15, OFB tC CLKOUTA CLKOUTB 2208 TD03 2208fb 8 LTC2208 LTC2208 U W TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (INL) vs Output Code Differential Nonlinearity (DNL) vs Output Code AC Grounded Input Histogram 0.8 DNL ERROR (LSB) INL ERROR (LSB) 1 0.5 0 ­0.5 9000 0.6 1.5 10000 8000 0.4 7000 0.2 6000 COUNT 1 2 0 0.2 5000 4000 0.4 3000 0.6 2000 ­1.5 0.8 1000 ­2 1 ­1 16384 32768 OUTPUT CODE 0 65536 49152 & / 0 10 40 30 20 50 FREQUENCY (MHz) 0 32736 32740 32744 32748 32752 32756 OUTPUT CODE 2208 G14 65536 2208 G02 64k Point FFT, 15.1MHz, ­20dBFS, PGA = 0, Internal Dither "Off" 60 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 0 10 2208 G15 50 20 40 30 FREQUENCY (MHz) 60 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 0 0 0 ­20 ­30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) ­20 ­40 ­50 ­60 ­70 ­80 ­40 ­50 ­60 ­70 ­80 ­90 ­90 ­100 ­100 ­110 50 20 40 30 FREQUENCY (MHz) 60 2208 G05 ­110 ­120 10 60 2208 G04 ­10 ­30 0 50 20 40 30 FREQUENCY (MHz) 32k Point 2-Tone FFT, fIN = 20.14 MHz and 14.25MHz, ­25dBFS, PGA = 0 ­10 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 10 2208 G03 32k Point 2-Tone FFT, fIN = 21.14 MHz and 14.25MHz, ­7dBFS, PGA = 0 64k Point FFT, 15.1MHz, ­20dBFS, PGA = 0, Internal Dither "On" AMPLITUDE (dBFS) 49152 32768 OUTPUT CODE 64k Point FFT, fIN = 15.1MHz, ­1dBFS, PGA = 0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 128K Point FFT, fIN = 4.93MHz, ­1dBFS, PGA = 0 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 16384 AMPLITUDE (dBFS) 0 ­120 0 10 50 20 40 30 FREQUENCY (MHz) 60 2208 G06 0 10 50 20 40 30 FREQUENCY (MHz) 60 2208 G07 2208fb 9 LTC2208 LTC2208 U W TYPICAL PERFOR A CE CHARACTERISTICS 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 ­80 ­70 ­60 ­50 ­40 ­30 ­20 ­10 0 INPUT LEVEL (dBFS) 2208 G09 0 10 40 30 20 50 FREQUENCY (MHz) 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 0 60 10 40 30 20 50 FREQUENCY (MHz) 10 40 30 20 50 FREQUENCY (MHz) 60 2208 G20 40 30 20 50 FREQUENCY (MHz) 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 0 60 10 40 30 20 50 FREQUENCY (MHz) 0 10 40 30 20 50 FREQUENCY (MHz) 60 2208 G21 60 2208 G19 64K Point FFT, fIN = 70.1 MHz, ­1dBFS, PGA = 1 AMPLITUDE (dBFS) 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 60 2208 G16 64K Point FFT, fIN = 70.1 MHz, ­10dBFS, PGA = 0 128K Point FFT, fIN = 70.1 MHz, ­25dBFS, PGA = 0, Dither "On" AMPLITUDE (dBFS) AMPLITUDE (dBFS) 64K Point FFT, fIN = 70.1 MHz, ­20dBFS, PGA = 0 0 10 2208 G18 2208 G17 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 0 AMPLITUDE (dBFS) 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 64K Point FFT, fIN = 70.1 MHz, ­1dBFS, PGA = 0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 128K Point FFT, fIN = 30.1 MHz, ­25dBFS, PGA = 0, Dither "On" AMPLITUDE (dBFS) 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 ­80 ­70 ­60 ­50 ­40 ­30 ­20 ­10 0 INPUT LEVEL (dBFS) 2208 G08 64K Point FFT, fIN = 30.1 MHz, ­1dBFS, PGA = 0 SFDR vs Input Level, fIN = 15MHz, PGA = 0, Dither "On" SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) SFDR vs Input Level, fIN = 15MHz, PGA = 0, Dither "Off" 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 0 10 40 30 20 50 FREQUENCY (MHz) 60 2208 G22 2208fb 10 LTC2208 LTC2208 U W TYPICAL PERFOR A CE CHARACTERISTICS SFDR vs Input Level, fIN = 70.2MHz, PGA = 0, Dither "Off" SFDR vs Input Level, fIN = 70.2MHz, PGA = 0, Dither "On" 110 100 90 80 70 60 100 AMPLITUDE (dBFS) SFDR (dBc AND dBFS) 130 120 110 SFDR (dBc AND dBFS) 130 120 64K Point FFT, fIN = 67.2 MHz and 74.4 MHz, ­7dBFS, PGA = 0 90 80 70 60 50 50 40 40 30 ­80 ­70 ­60 ­50 ­40 ­30 ­20 ­10 INPUT LEVEL (dBFS) 30 ­80 ­70 ­60 ­50 ­40 ­30 ­20 ­10 INPUT LEVEL (dBFS) 0 0 0 64K Point FFT, fIN = 67.2 MHz and 74.4 MHz, ­15dBFS, PGA = 0 64K Point FFT, fIN = 140.1 MHz, ­1dBFS, PGA = 0 ­30 AMPLITUDE (dBFS) ­20 ­30 AMPLITUDE (dBFS) 0 ­10 ­20 ­40 ­50 ­60 ­70 ­80 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 40 30 20 50 FREQUENCY (MHz) ­90 ­100 10 ­110 ­120 60 ­120 0 10 40 30 20 50 FREQUENCY (MHz) 60 0 10 40 30 20 50 FREQUENCY (MHz) SFDR vs Input Level, fIN = 140.2MHz, PGA = 1, Dither "On" SFDR vs Input Level, fIN = 140.2MHz, PGA = 1, Dither "Off" 60 2208 G26 2208 G27 2208 G25 64K Point FFT, fIN = 170.1 MHz, ­1dBFS, PGA = 1 130 0 120 ­10 110 110 100 90 80 70 60 ­20 ­30 100 AMPLITUDE (dBFS) SFDR (dBc AND dBFS) 130 120 SFDR (dBc AND dBFS) 60 64K Point FFT, fIN = 140.1 MHz, ­1dBFS, PGA = 1 0 0 40 30 20 50 FREQUENCY (MHz) 2208 G24 ­10 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 10 2208 G29 2208 G28 AMPLITUDE (dBFS) 0 ­10 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­90 ­100 ­110 ­120 ­130 90 80 70 60 50 40 40 30 ­80 ­70 ­60 ­50 ­40 ­30 ­20 ­10 INPUT LEVEL (dBFS) 30 ­80 ­70 ­60 ­50 ­40 ­30 ­20 ­10 INPUT LEVEL (dBFS) 2208 G30 ­50 ­60 ­70 ­80 ­90 50 0 ­40 ­100 ­110 ­120 0 2208 G31 0 10 40 30 20 50 FREQUENCY (MHz) 60 2208 G34 2208fb 11 LTC2208 LTC2208 U W TYPICAL PERFOR A CE CHARACTERISTICS 64K Point FFT, fIN = 250.1MHz, ­10dBFS, PGA = 1 64K Point FFT, fIN = 250.1MHz, ­1dBFS, PGA = 1 64K Point FFT, fIN = 380MHz, ­1dBFS, PGA = 1 ­20 ­20 ­30 ­30 ­30 ­40 ­50 ­60 ­70 ­80 AMPLITUDE (dBFS) 0 ­10 AMPLITUDE (dBFS) 0 ­10 ­20 AMPLITUDE (dBFS) 0 ­10 ­40 ­50 ­60 ­70 ­80 ­40 ­50 ­60 ­70 ­80 ­90 ­90 ­90 ­100 ­100 ­100 ­110 ­110 ­110 ­120 ­120 0 10 40 30 20 50 FREQUENCY (MHz) 60 0 10 40 30 20 50 FREQUENCY (MHz) 2208 G36 ­120 60 SFDR (HD2 and HD3) vs Input Frequency 0 78 100 77 95 ­30 60 SNR vs Input Frequency 105 ­20 76 90 75 ­50 ­60 ­70 ­80 SNR (dBFS) PGA = 0 ­40 SFDR (dBc) PGA = 1 85 80 PGA = 0 74 PGA = 1 73 75 ­100 ­110 0 10 40 30 20 50 FREQUENCY (MHz) 72 70 ­90 71 65 60 70 0 100 200 400 300 INPUT FREQUENCY (MHz) 2208 G39 500 100 200 400 300 INPUT FREQUENCY (MHz) IVDD vs Sample Rate, 5MHz Sine Wave, ­1dBFS 420 110 110 500 2208 G40 SNR and SFDR vs Supply Voltage (VDD), fIN = 5MHz SNR and SFDR vs Sample Rate, fIN = 5MHz LOWER LIMIT LIMIT 105 105 400 SFDR SFDR SNR AND SFDR (dBFS) 100 95 90 85 80 0 2208 G23 SNR 100 380 95 IVDD (mA) AMPLITUDE (dBFS) 40 30 20 50 FREQUENCY (MHz) 2208 G38 ­10 SNR AND SFDR (dBFS) 10 2208 G37 64K Point FFT, fIN = 380MHz, ­10dBFS, PGA = 1 ­120 0 UPPER LIMIT 90 85 360 340 80 SNR 320 75 75 70 0 25 50 75 100 125 150 175 200 SAMPLE RATE (Msps) 2208 G32 70 2.8 300 3 3.2 3.4 SUPPLY VOLTAGE (V) 3.6 & /!! 0 50 100 SAMPLE RATE (Msps) 150 2208 G13 2208fb 12 LTC2208 LTC2208 U W TYPICAL PERFOR A CE CHARACTERISTICS Normalized Full Scale vs Temperature, Internal Reference, 5 Units SNR and SFDR vs Duty Cycle 110 1.01 NORMALIZED FULL SCALE SFDR AND SNR (dBFS) 100 90 80 SNR DCS OFF SNR DCS ON SFDR DCS OFF SFDR DCS ON 70 60 40 30 50 60 1.005 1 0.995 0.99 ­40 70 DUTY CYCLE (%) 60 0 20 40 TEMPERATURE (°C) 80 2208 G11 & / SFDR vs Analog Input Common Mode Voltage, 10MHz and 70 MHz, ­1dBFS, PGA = 0 Input Offset Voltage vs Temperature, 5 Units 5 110 4 105 3 100 2 95 1 SFDR (dBc) OFFSET VOLTAGE (mV) ­20 0 ­1 ­2 10MHz 90 85 80 70MHz 75 ­3 70 ­4 65 ­5 ­40 ­20 0 20 40 60 TEMPERATURE (°C) 60 80 1.75 0.5 0.75 1.25 1.5 2 1 ANALOG INPUT COMMON MODE VOLTAGE (V) 2208 G12 2208 G41 Full-Scale Settling After Wake Up from Shutdown or Starting Encode Clock Mid-Scale Settling After Wake Up from Shutdown or Starting Encode Clock 4 0.6 3 FULL-SCALE ERROR (%) 5 0.8 FULL-SCALE ERROR (%) 1.0 0.4 0.2 0 ­0.2 ­0.4 2 1 0 ­1 ­2 ­0.6 ­3 ­0.8 ­4 ­1.0 0 50 100 150 200 250 300 350 400 450 500 TIME AFTER WAKE-UP OR CLOCK START (µs) 2208 G42 ­5 0 100 200 300 400 500 600 700 800 900 1000 TIME FROM WAKE-UP OR CLOCK START (s) 2208 G43 2208fb 13 LTC2208 LTC2208 U U U PI FU CTIO S For CMOS Mode. Full Rate or Demultiplexed SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. VCM (Pin 3): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2µF. Ceramic chip capacitors are recommended. VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1µF ceramic chip capacitors. AIN+ (Pin 8): Positive Differential Analog Input. AIN­ (Pin 9): Negative Differential Analog Input. ENC+ (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the rising edge of ENC+. ENC­ (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC ­. Internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1µF capacitor for a single-ended Encode signal. SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. DB0-DB15 DB0-DB15 (Pins 21-30 and 33-38): Digital Outputs, B Bus. DB15 is the MSB. Active in demultiplexed mode. The B bus is in high impedance state in full rate CMOS. OGND (Pins 31 and 50): Output Driver Ground. OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 1µF capacitor. OFB (Pin 39): Over/Under Flow Digital Output for the B Bus. OFB is high when an over or under flow has occurred on the B bus. At high impedance state in full rate CMOS mode. CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the falling edge of CLKOUTB. CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA. DA0-DA15 DA0-DA15 (Pins 42-48 and 51-59): Digital Outputs, A Bus. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode. OFA (Pin 60): Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under flow has occurred on the A bus. LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2's complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2's complement output format and disables the clock duty cycle stabilizer. RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. PGA (Pin 64): Programmable Gain Amplifier Control Pin. Low selects a front-end gain of 1, input range of 2.25VP-P 25VP-P. High selects a front-end gain of 1.5, input range of 1.5VP-P. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 2208fb 14 LTC2208 LTC2208 U U U PI FU CTIO S For LVDS Mode. STANDARD or LOW POWER OGND (Pins 31 and 50): Output Driver Ground. SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF capacitor. GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. VCM (Pin 3): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2µF. Ceramic chip capacitors are recommended. VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1µF ceramic chip capacitors. AIN + (Pin 8): Positive Differential Analog Input. AIN ­ (Pin 9): Negative Differential Analog Input. ENC + (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the rising edge of ENC+. ENC ­ (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC ­. Internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1µF capacitor for a single-ended Encode signal. SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are set in high impedance state. DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of the data sheet for details on dither operation. D0­/D0+ to D15­/D15+ (Pins 21-30, 33-38, 41-48 and 51-58): LVDS Digital Outputs. All LVDS outputs require differential 100 termination resistors at the LVDS receiver. D15+/D15­ is the MSB. CLKOUT­/CLKOUT + (Pins 39 and 40): LVDS Data Valid 0utput. Latch data on the rising edge of CLKOUT +, falling edge of CLKOUT ­. OF­/OF+ (Pins 59 and 60): Over/Under Flow Digital Output OF is high when an over or under flow has occurred. LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2's complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2's complement output format and disables the clock duty cycle stabilizer. RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. The mode of operation reduces the effects of digital output interference. PGA (Pin 64): Programmable Gain Amplifier Control Pin. Low selects a front-end gain of 1, input range of 2.25VP-P 25VP-P. High selects a front-end gain of 1.5, input range of 1.5VP-P. GND (Exposed Pad Pin 65): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 2208fb 15 LTC2208 LTC2208 W BLOCK DIAGRA AIN+ AIN­ VDD INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER ADC CLOCKS RANGE SELECT OVDD SENSE PGA VCM BUFFER ADC REFERENCE DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS · · · VOLTAGE REFERENCE OGND ENC+ ENC­ SHDN PGA RAND M0DE LVDS CLKOUT+ CLKOUT­ OF+ OF­ D15+ D15­ D0+ D0­ 2208 F01 DITH Figure 1. Functional Block Diagram 2208fb 16 LTC2208 LTC2208 U OPERATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: ( V22 + V32 + V42 + . VN2 )/V1) THD = ­20Log where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ration of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Full Power Bandwidth The Full Power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC + equals the ENC­ voltage to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from convertion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = ­20log (2 · fIN · tJITTER) 2208fb 17 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO CONVERTER OPERATION The LTC2208 LTC2208 is a CMOS pipelined multistep converter with a front-end PGA. As shown in Figure 1, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC2208 LTC2208 has two phases of operation, determined by the state of the differential ENC+/ENC ­ input pins. For brevity, the text will refer to ENC+ greater than ENC ­ as ENC high and ENC+ less than ENC ­ as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "input S/H" shown in the block diagram. At the instant that ENC transitions from low to high, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. 18 SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2208 LTC2208 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transitors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the LTC2208 LTC2208 VDD CSAMPLE 4.9pF AIN+ CPARASITIC 1.8pF VDD CSAMPLE 4.9pF AIN­ CPARASITIC 1.8pF VDD 1.6V 6k ENC+ ENC­ 6k 1.6V 2208 F02 Figure 2. Equivalent Input Circuit 2208fb LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V for the 1.5V range (PGA = 1), around a common mode voltage of 1.25V. The VCM output pin (Pin 3) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2µF or greater. Input Drive Impedence As with all high performance, high speed ADCs the dynamic performance of the LTC2208 LTC2208 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC the sample and hold circuit will connect the 4.9pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2F encode); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance it is recommended to have a source impedence of 100 or less for each input. The source impedence should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. provide isolation from ADC S/H switching. The LTC2208 LTC2208 has a very broadband S/H circuit, DC to 700MHz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended RC filter. Figures 3, 4a and 4b show three examples of input RC filtering at three ranges of input frequencies. In general it is desirable to make the capacitors as large as can be tolerated-this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2208 LTC2208 does not require any input filter to achieve data sheet specifications; however, no filtering will put more stringent noise requirements on the input drive circuitry. Transformer Coupled Circuits Figure 3 shows the LTC2208 LTC2208 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50 can reduce the input bandwidth and increase high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. VCM 2.2µF 5 Input Filtering A first order RC low pass filter at the input of the ADC can serve two functions: limit the noise from input circuitry and LTC2208 LTC2208 8.2pF 35 8.2pF 0.1µF 10 INPUT DRIVE CIRCUITS 5 AIN+ 10 T1 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2µF 35 5 AIN­ 8.2pF 2208 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 100MHz 2208fb 19 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high frequency response and balance than flux coupled center tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25V. Figure 4b shows the same circuit with components suitable for higher input frequencies. VCM 0.1µF 25 0.1µF 0.1µF T1 = MA/COM ETC1-1-13 ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2µF 5 AIN­ 4.7pF 25 0.1µF T1 1:1 0.1µF 25 2208 F04a T1 = MA/COM ETC1-1-13 ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2µF AIN+ LTC2208 LTC2208 2.2pF 5 2.2pF AIN+ LTC2208 LTC2208 + ­ AIN­ 12pF 2208 F05 Figure 5. DC Coupled Input with Differential Amplifier 2.2µF 5 2.2µF 12pF AMPLIFIER = LTC6600-20 LTC6600-20, LTC1993 LTC1993, ETC. VCM ANALOG INPUT + ­ Figure 4a. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 100MHz to 250MHz 0.1µF HIGH SPEED DIFFERENTIAL AMPLIFIER LTC2208 LTC2208 4.7pF 4.7pF 25 VCM CM 5 AIN+ T1 1:1 Figure 6 shows the LTC2208 LTC2208 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2208 LTC2208 has three modes of ANALOG INPUT 2.2µF ANALOG INPUT Reference Operation AIN­ reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full scale range of 2.25VP-P 25VP-P (PGA = 0). A 1.25V output, VCM is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; it will not be stable without this capacitor. The minimum value required for stability is 2.2µF. 2208 F04b Figure 4b. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 250MHz to 500MHz Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifiers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input. TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE RANGE SELECT AND GAIN CONTROL INTERNAL ADC REFERENCE SENSE PGA 2.5V BANDGAP REFERENCE VCM BUFFER 1.25V 2.2µF 2208 F06 Figure 6. Reference Circuit 2208fb 20 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has very stringent settling requirements and is not accessible for external use. The SENSE pin can be driven ±5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1µF ceramic capacitor. VCM 1.25V 2.2µF 2 3.3V 1µF LTC1461-2 LTC1461-2.5 4 6 SENSE LTC2208 LTC2208 In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a fixed frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive. 2.2µF VDD LTC2208 LTC2208 2208 F07 TO INTERNAL ADC CLOCK DRIVERS Figure 7. A 2.25V Range ADC with an External 2.5V Reference VDD PGA Pin 1.6V 6k + The PGA pin selects between two gain settings for the ADC front-end. PGA = 0 selects an input range of 2.25VP-P 25VP-P; PGA = 1 selects an input range of 1.5VP-P. The 2.25V input range has the best SNR; however, the distortion will be higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range will have improved distortion; however, the SNR will be 1.8dB worse. See the typical performance curves section. ENC VDD 1.6V 6k ENC­ 2208 F08a Figure 8a. Equivalent Encode Input Circuit Driving the Encode Inputs The noise performance of the LTC2208 LTC2208 can depend on the encode signal quality as much as for the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. 0.1µF ENC+ T1 LTC2208 LTC2208 50 100 8.2pF 0.1µF 50 0.1µF ENC­ 2208 F08b T1 = MA/COM ETC1-1-13 ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 8b. Transformer Driven Encode 2208fb 21 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO ENC+ VTHRESHOLD = 1.6V 1.6V ENC­ LTC2208 LTC2208 0.1µF 2208 F09 Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter DIGITAL OUTPUTS Digital Output Modes 3.3V MC100LVELT22 MC100LVELT22 3.3V Q0 ENC+ D0 Q0 The lower limit of the LTC2208 LTC2208 sample rate is determined by droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2208 LTC2208 is 1Msps. ENC­ LTC2208 LTC2208 2208 F10 Figure 10. ENC Drive Using a CMOS to PECL Translator Maximum and Minimum Encode Rates The maximum encode rate for the LTC2208 LTC2208 is 130Msps. For the ADC to operate properly the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 3.65ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended ENCODE signal asymmetric rise and fall times can result in duty cycles that are far from 50%. An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC pin to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The LTC2208 LTC2208 can operate in four digital output modes: standard LVDS, low power LVDS, full rate CMOS, and demultiplexed CMOS. The LVDS pin selects the mode of operation. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the LVDS pin. Table 1. LVDS Pin Function LVDS 0V(GND) 1/3VDD 2/3VDD VDD Digital Output Mode Full-Rate CMOS Demultiplexed CMOS Low Power LVDS LVDS Digital Output Buffers (CMOS Modes) Figure 11 shows an equivalent circuit for a single output buffer in CMOS Mode, Full-Rate or Demultiplexed. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external circuitry and eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2208 LTC2208 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as a ALVCH16373 ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the 2208fb 22 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO output may be used but is not required since the ADC has a series resistor of 43 on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. LTC2208 LTC2208 OVDD VDD 0.5V TO 3.6V VDD 0.1µF OVDD DATA FROM LATCH PREDRIVER LOGIC TYPICAL DATA OUTPUT resistor, even if the signal is not used (such as OF+/OF­ or CLKOUT+/CLKOUT­). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. In Low Power LVDS Mode 1.75mA is steered between the differential outputs, resulting in ±175mV at the LVDS receiver's 100 termination resistor. The output common mode voltage is 1.20V, the same as standard LVDS Mode. Data Format The LTC2208 LTC2208 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 2 shows the logic states for the MODE pin. OGND 2208 F11 Figure 11. Equivalent Circuit for a Digital Output Buffer Digital Output Buffers (LVDS Modes) Figure 12 shows an equivalent circuit for an LVDS output pair. A 3.5mA current is steered from OUT+ to OUT­ or vice versa, which creates a ±350mV differential voltage across the 100 termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.20V. For proper operation each LVDS output pair must be terminated with an external 100 termination Table 2. MODE Pin Function Output Format 1/3VDD 2/3VDD VDD LTC2208 LTC2208 Clock Duty Cycle Stabilizer Offset Binary Offset Binary 2's Complement 2's Complement MODE 0(GND) Off On On Off OVDD 3.3V 3.5mA 0.1µF VDD VDD OVDD 43 DATA FROM LATCH PREDRIVER LOGIC 10k 10k OVDD 100 LVDS RECEIVER 43 1.20V + ­ OGND 2208 F12 Figure 12. Equivalent Output Buffer in LVDS Mode 2208fb 23 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow on the B data bus. In LVDS mode, a differential logic high on OF+/OF­ pins indicates an overflow or underflow. LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high. CLKOUT CLKOUT OF OF Output Clock The ADC has a delayed version of the encode input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In both CMOS modes, A bus data will be updated as CLKOUTA falls and CLKOUTB rises. In demultiplexed CMOS mode the B bus data will be updated as CLKOUTA falls and CLKOUTB rises. D15 In Full Rate CMOS Mode, only the A data bus is active; data may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. D1 In demultiplexed CMOS mode CLKOUTA and CLKOUTB will toggle at 1/2 the frequency of the encode signal. Both the A bus and the B bus may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. D15/D0 D15/D0 D14 D2 RAND = HIGH, SCRAMBLE ENABLED D14/D0 D14/D0 · · · D2/D0 D1/D0 RAND D0 D0 2208 F13 Figure 13. Functional Equivalent of Digital Output Randomizer Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is "Randomized" by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to the 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In LVDS Mode, OVDD should be connected to a 3.3V supply and OGND should be connected to GND. 2208fb 24 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO Internal Dither PC BOARD FPGA The LTC2208 LTC2208 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. CLKOUT OF D15/D0 D15/D0 D15 LTC2208 LTC2208 D14/D0 D14/D0 As shown in Figure 15, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off. D14 · · · D2/D0 D2 D1/D0 D1 D0 D0 2208 F14 Figure 14. Descrambling a Scrambled Digital Output LTC2208 LTC2208 AIN+ ANALOG INPUT AIN­ 16-BIT 16-BIT PIPELINED ADC CORE S/H AMP CLOCK/DUTY CYCLE CONTROL PRECISION DAC DIGITAL SUMMATION CLKOUT OF D15 · · · D0 OUTPUT DRIVERS MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR 2208 F15 ENC + ENC ­ DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit 2208fb 25 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO Grounding and Bypassing The LTC2208 LTC2208 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2208 LTC2208 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2208 LTC2208 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2208 LTC2208 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible. 2208fb 26 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO Layer 1 Component Side Layer 2 GND Plane 2208fb 27 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO Layer 3 GND Layer 4 GND 2208fb 28 LTC2208 LTC2208 U W U U APPLICATIO S I FOR ATIO Layer 5 GND Layer 6 Bottom Side 2208fb 29 TP2 PWR GND TP5 3.3V LTC2208IUP LTC2208IUP LTC2208IUP-14 LTC2208IUP-14 LTC2208IUP-14 LTC2208IUP-14 DC996B-C DC996B-C DC996B-D DC996B-D DC996B-A DC996B-A DC996B-B DC996B-B LTC2208IUP LTC2208IUP ASSEMBLY 14 14 16 16 BITS 5 3 1 C1 0.01µF U2 * VERSION TABLE C10 8.2pF R36 R44 86.6 86.6 L1 56nH 1.8pF 4.7pF 1.8pF 4.7pF C8 182 86.6 182 86.6 43.2 86.6 43.2 L1 6 4 86.6 R36, 44 VCC C4 8.2pF R4 5.1 R5 5.1 TP1 EXT REF C12 0.1µF 56nH 18nH 56nH 18nH 8.2pF 3.9pF 8.2pF 3.9pF OFF RUN T2 R8 1000 GND VDD J2 MODE R6 1000 ON DITHER SHDN WBC1-1LB MABAES0060 MABAES0060 WBC1-1LB MABAES0060 MABAES0060 5 3 1 5 3 J3 R13 100 C17 2.2µF 6 4 2 6 4 2 R27 10 C8 4.7pF R28 10 R14 1000 R12 33.2 R11 33.2 C13 2.2µF VCC R10 10 1 R15 100 R45 2 VCC R1 49.9 R2 49.9 C5 0.01µF C7 0.01µF T1 MABA-007159- MABA-007159- T2 000000 · · C9-10 C9-10 J9 AUX PWR CONNECTOR C3 0.01µF · · J7 ENCODE C2 T3 CLOCK 0.01µF ETC1-1-13 ETC1-1-13 C8 8.2pF C6 J5 AIN 0.01µF · · R45 86.6 R7 1000 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VDD16 VDD16 VDD15 VDD15 GND14 GND14 ENCN ENCP GND11 GND11 GND10 GND10 AINN AINP GND7 VDD6 VDD5 GND VCM GND2 SENSE 64 4 3 2 1 17 R9 10 R37 100 62 63 5 R3 DNP RIN+ DOUT­ GND C15 0.1µF DOUT+ GND EN VCC RIN­ U5 FIN1101K8X FIN1101K8X R41 100 58 GND VDD PGA 61 VDD17 VDD17 18 RAND 60 GND18 GND18 19 MODE SHDN 59 LVDS DITH 20 5 6 7 8 57 ON OFF 6 U2 LTC2208IUP LTC2208IUP D1+ 24 OF+ D0­ 21 56 D2­ 25 C26 0.1µF C25 0.1µF C16 0.1µF C18 OPT C19 OPT 26 OF­ D0+ 22 D15+ D1­ 23 4 27 D15­ 2 27 J4 R16 100 49 50 C22 0.1µF D5­ D5+ D8­ D8+ D7­ D7+ CLKOUT­ R42 FERRITE BEAD C14 4.7µF D8­ D8+ D9­ D9+ D10­ D10+ D11­ D11+ CLKCOUT+ C20 0.1µF D2+ 29 D14+ 55 D3­ D14­ 54 D3+ D13+ 53 D4­ D13­ 52 D12+ 51 D12­ D4+ 30 OGND50 OGND50 OGND31 OGND31 31 OVDD49 OVDD49 OVDD32 OVDD32 32 3 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C24 4.7µF R43 FERRITE BEAD 65 C38 4.7µF 3.3V C34 0.1µF C35 0.1µF C36 0.1µF C28 0.1µF C29 0.1µF C30 0.1µF C31 0.1µF C32 0.1µF R40 100 R39 100 R38 100 R35 100 R34 100 R33 100 R32 100 R31 100 R30 100 R23 100 R22 100 R21 100 R20 100 R19 100 R18 100 R17 100 20 21 18 19 16 17 14 15 10 11 8 9 6 7 4 5 3 22 27 46 13 20 21 18 19 16 17 14 15 10 11 8 9 6 7 4 5 3 22 27 46 13 3.3V 12 25 26 47 48 I8N I8P I7N I7P I6N I6P I5N I5P I4N I4P I3N I3P I2N I2P I1N I1P EN12 EN34 EN58 EN78 EN 43 42 3.3V I8N I8P I7N I7P I6N I6P I5N I5P I4N I4P I3N I3P I2N I2P I1N I1P EN12 EN34 EN58 EN78 EN 5 44 39 38 35 34 33 32 31 30 29 28 O3N U3 FIN1108 FIN1108 O3P O4N O4P O5N O5P O6N O6P O7N O7P O8N O8P O8N O8P O7N O7P O6N O6P O5N O5P O4N O4P U4 O3N FIN1108 FIN1108 O3P O2N O2P O1N O1P 29 28 31 30 33 32 35 34 39 38 41 40 43 42 45 44 41 40 O2N O2P O1N O1P VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 1 2 23 36 37 12 25 26 47 48 VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 1 2 23 36 37 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 4 GND VCC 8 ARRAY EEPROM U1 24LC02ST 24LC02ST R24 100k 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 R29 4990 3.3V A0 WP A2 A1 1 2 3 7 5 6 C27 0.1µF 6CL 6DA MEC8-150-02-L-D-EDGE MEC8-150-02-L-D-EDGE_CONNRE-DIM J1E J1O 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 54 53 2208 F16 R26 4990 R25 4990 U U 30 W 1 APPLICATIO S I FOR ATIO U VCC LTC2208 LTC2208 2208fb LTC2208 LTC2208 U PACKAGE DESCRIPTIO UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 7.50 REF 8.10 ±0.05 9.50 ±0.05 (4 SIDES) 7.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER C = 0.35 7.15 ± 0.10 7.50 REF (4-SIDES) 7.15 ± 0.10 (UP64) QFN 0406 REV C 0.200 REF 0.00 ­ 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE 0.25 ± 0.05 0.50 BSC BOTTOM VIEW-EXPOSED PAD 2208fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2208 LTC2208 RELATED PARTS PART NUMBER LTC1747 LTC1747 LTC1748 LTC1748 LTC1749 LTC1749 LTC1750 LTC1750 LT1993 LT1993 LTC2202 LTC2202 LTC2203 LTC2203 LTC2204 LTC2204 LTC2205 LTC2205 LTC2206 LTC2206 LTC2207 LTC2207 LTC2208 LTC2208 LTC2220 LTC2220 LTC2220-1 LTC2220-1 LTC2249 LTC2249 LTC2250 LTC2250 LTC2251 LTC2251 LTC2252 LTC2252 LTC2253 LTC2253 LTC2254 LTC2254 LTC2255 LTC2255 LTC2299 LTC2299 LT5512 LT5512 LT5514 LT5514 LT5522 LT5522 DESCRIPTION 12-Bit, 80MSPS 80MSPS ADC 14-Bit, 80Msps ADC 12-Bit, 80Msps Wideband ADC 14-Bit, 80Msps Wideband ADC High Speed Differential Op Amp 16-Bit, 10MSPS 10MSPS ADC 16-Bit, 25MSPS 25MSPS ADC 16-Bit, 40Msps ADC 16-Bit, 65Msps ADC 16-Bit, 80Msps ADC 16-Bit, 105Msps ADC 16-Bit, 130Msps ADC 12-Bit, 170Msps ADC 12-Bit, 185Msps ADC 14-Bit, 65Msps ADC 10-Bit, 105Msps ADC 10-Bit, 125Msps ADC 12-Bit, 105Msps ADC 12-Bit, 125Msps ADC 14-Bit, 105Msps ADC 14-Bit, 125Msps ADC Dual 14-Bit, 80Msps ADC DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 87dB SFDR Up to 500MHz IF Undersampling, 90dB SFDR 600MHz BW, 75dBc Distortion at 70MHz 150mW, 81.6dB SNR, 100dB SFDR 230mW, 81.6dB SNR, 100dB SFDR 470mW, 79dB SNR, 100dB SFDR 530mW, 79dB SNR, 100dB SFDR 725mW, 77.9dB SNR, 100dB SFDR 900mW, 77.9dB SNR, 100dB SFDR 1250mW, 77.7dB SNR, 100dB SFDR 890mW, 67.5dB SNR, 9mm x 9mm QFN Package 910mW, 67.5dB SNR, 9mm x 9mm QFN Package 230mW, 73dB SNR, 5mm x 5mm QFN Package 320mW, 61.6dB SNR, 5mm x 5mm QFN Package 395mW, 61.6dB SNR, 5mm x 5mm QFN Package 320mW, 70.2dB SNR, 5mm x 5mm QFN Package 395mW, 70.2dB SNR, 5mm x 5mm QFN Package 320mW, 72.5dB SNR, 5mm x 5mm QFN Package 395mW, 72.4dB SNR, 5mm x 5mm QFN Package 445mW, 73dB SNR, 9mm x 9mm QFN Package DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports 2208fb 32 Linear Technology Corporation LT 0107 REV B · PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005