LTC1661 75LSB LTC1660 10-BIT LTC1661C LTC1661I LTC1661CMS8 LTC1661IMS8 - Datasheet Archive

 

LTC1661 Micropower Dual 10-Bit DAC in MSOP January 1999 U DESCRIPTION FEATURES s s s s s s s s Tiny: Two 10-Bit DACs in an 8-Lead

 

Final Electrical Specifications LTC1661 LTC1661 Micropower Dual 10-Bit DAC in MSOP January 1999 U DESCRIPTION FEATURES s s s s s s s s Tiny: Two 10-Bit DACs in an 8-Lead MSOP- Half the Board Space of an SO-8 Ultralow Power: 60µA per DAC Plus 1µA Sleep Mode for Extended Battery Life Wide 2.7V to 5.5V Supply Range Double Buffered for Independent or Simultaneous DAC Updates Rail-to-Rail Voltage Outputs Drive 1000pF Reference Range Includes Supply for Ratiometric 0V-to-VCC Output 3-Wire Serial Interface with Schmitt Trigger Inputs Differential Nonlinearity: ±0.75LSB 75LSB Max U APPLICATIONS s s s s s Mobile Communications Digitally Controlled Amplifiers and Attenuators Portable Battery-Powered Instruments Automatic Calibration for Manufacturing Remote Industrial Devices The LTC®1661 integrates two accurate, addressable, 10-bit digital-to-analog converters (DACs) in a single tiny MS8 package. Each buffered DAC consumes just 60µA total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads up to 1000pF. Sleep mode further reduces total supply current to a negligible 1µA. Linear Technology's proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. The double-buffered input logic provides simultaneous update capability and can be used to write to either DAC without interrupting Sleep mode. Ultralow supply current, power-saving Sleep mode and extremely compact size make the LTC1661 LTC1661 ideal for battery-powered applications, while its straightforward usability, high performance and wide supply range make it an excellent choice as a general purpose converter. For additional outputs and even greater board density, please refer to the LTC1660 LTC1660 micropower octal 10-bit DAC. , LTC and LT are registered trademarks of Linear Technology Corporation. W BLOCK DIAGRA VOUT A GND VCC VOUT B 8 7 6 5 Differential Nonlinearity (DNL) 1.0 10-BIT 10-BIT DAC A 10-BIT 10-BIT DAC B 0.8 CONTROL LOGIC DNL ERROR (LSB) 0.6 ADDRESS DECODER 0.4 0.2 0 ­ 0.2 ­ 0.4 ­ 0.6 ­ 0.8 SHIFT REGISTER ­1.0 0 1 2 3 4 CS/LD CLK DIN 256 512 CODE 768 1023 REF 1661 BD Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1661 TA02 1 LTC1661 LTC1661 W W W AXI U U ABSOLUTE RATI GS (Note 1) VCC to GND . ­ 0.5V to 7.5V Logic Inputs to GND . ­ 0.5V to 7.5V VOUT A, VOUT B, REF to GND . ­ 0.2V to VCC + 0.2V Maximum Junction Temperature . 125°C Storage Temperature Range . ­ 65°C to 150°C Operating Temperature Range LTC1661C LTC1661C. 0°C to 70°C LTC1661I LTC1661I. ­ 40°C to 85°C Lead Temperature (Soldering, 10 sec). 300°C W U U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW CS/LD CLK DIN REF 1 2 3 4 ORDER PART NUMBER TOP VIEW 8 VOUT A CLK 2 7 GND DIN 3 6 VCC REF 4 5 VOUT B CS/LD 1 8 7 6 5 VOUT A GND VCC VOUT B MS8 PACKAGE 8-LEAD PLASTIC MSOP LTC1661CMS8 LTC1661CMS8 LTC1661IMS8 LTC1661IMS8 MS8 PART MARKING TJMAX = 125°C, JA = 150°C/W LTDV LTDW LTC1661CN8 LTC1661CN8 LTC1661IN8 LTC1661IN8 N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 125°C, JA = 100°C/W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VCC = 2.7V to 5.5V, VREF VCC, VOUT Unloaded, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Accuracy Resolution q 10 Bits 10 Bits Monotonicity VREF VCC ­ 0.1V (Note 2) q DNL Differential Nonlinearity VREF VCC ­ 0.1V (Note 2) q ±0.1 ±0.75 LSB INL Integral Nonlinearity VREF VCC ­ 0.1V (Note 2) q ±0.4 ±2 LSB VOS Offset Error Measured at Code 20 q ±5 ±30 mV VCC = 5V, VREF = 4.096V q ±15 VOS Temperature Coefficient FSE Full-Scale Error ±1 µV/°C ±12 ±30 Full-Scale Error Temperature Coefficient LSB µV/°C Reference Input Input Voltage Range q 0 140 VCC Resistance q Capacitance IREF Not in Sleep Mode 260 (Note 6) q 15 Reference Current Sleep Mode q 0.001 V k pF 1 µA 5.5 V 195 154 3 µA µA µA Power Supply VCC Positive Supply Voltage For Specified Performance q ICC Supply Current VCC = 5V (Note 3) VCC = 3V (Note 3) Sleep Mode (Note 3) q q q 2 2.7 120 95 1 LTC1661 LTC1661 ELECTRICAL CHARACTERISTICS VCC = 2.7V to 5.5V, VREF VCC, VOUT Unloaded, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Performance Short-Circuit Current Low VOUT = 0V, VCC = VREF = 5V, Code = 1023 q 10 25 100 mA Short-Circuit Current High VOUT = VCC = VREF = 5V, Code = 0 q 7 19 120 mA AC Performance Voltage Output Slew Rate Rising (Notes 4, 5) Falling (Notes 4, 5) 0.60 0.25 V/µs V/µs Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) VIH Digital Input High Voltage VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V q q VIL Digital Input Low Voltage VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V q q 0.8 0.6 V V ILK Digital Input Leakage VIN = GND to VCC q ±10 µA CIN Digital Input Capacitance (Note 6) q 10 pF µs 30 Digital I/O 2.4 2.0 V V UW TI I G CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP 40 MAX 15 UNITS VCC = 4.5V to 5.5V t1 DIN Valid to CLK Setup t2 DIN Valid to CLK Hold q 0 ­ 10 ns t3 CLK High Time (Note 6) q 30 14 ns t4 CLK Low Time (Note 6) q 30 14 ns t5 CS/LD Pulse Width (Note 6) q 80 27 ns t6 LSB CLK High to CS/LD High (Note 6) q 30 2 ns t7 CS/LD Low to CLK High (Note 6) q 65 22 ns t9 CLK Low to CS/LD Low (Note 6) q 0 ­5 ns t11 CS/LD High to CLK Positive Edge (Note 6) q 20 0 ns (Note 6) q 60 20 ns q ns VCC = 2.7V to 5.5V t1 DIN Valid to CLK Setup t2 DIN Valid to CLK Hold (Note 6) q 0 ­ 10 ns t3 CLK High Time (Note 6) q 50 15 ns t4 CLK Low Time (Note 6) q 50 15 ns t5 CS/LD Pulse Width (Note 6) q 100 30 ns t6 LSB CLK High to CS/LD High (Note 6) q 50 3 ns t7 CS/LD Low to CLK High (Note 6) q 80 23 ns t9 CLK Low to CS/LD Low (Note 6) q 0 ­5 ns t11 CS/LD High to CLK Positive Edge (Note 6) q 30 0 ns The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined from the first code that is greater than or equal to the maximum offset specification to code 1023 (full scale). See Applications Information. Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10k in parallel with 100pF. Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS, i.e., codes k = 102 and k = 922. Note 6: Guaranteed by design and not subject to test. 3 LTC1661 LTC1661 W UW TI I G DIAGRA t1 t2 t3 t6 t4 CLK t9 t11 DIN A3 t5 A2 A1 X1 X0 t7 CS/LD 1661 TD U U U PIN FUNCTIONS CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, CLK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, CLK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible. CLK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 3): Serial Interface Data Input. Data on the DIN pin is shifted into the 16-bit register on the rising edge of CLK. CMOS and TTL compatible. REF (Pin 4): Reference Voltage Input. 0V VREF VCC. VOUT A, VOUT B (Pins 8,5): DAC Analog Voltage Outputs. The output range is 0 to VREF ) ) 1023 1024 VCC (Pin 6): Supply Voltage Input. 2.7V VCC 5.5V. GND (Pin 7): System Ground. U U DEFINITIONS Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT ­ LSB)/LSB Where VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT ­ VOS ­ (VFS ­ VOS)(code/1023)]/LSB Where VOUT is the output voltage of the DAC measured at the given input code. 4 LTC1661 LTC1661 U U DEFINITIONS Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/1024 VREF/1024 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero. U OPERATIO Transfer Function Register, is used for updating the DAC outputs. Each DAC has its own 10-bit Input Register and 10-bit DAC Register. The transfer function for the LTC1661 LTC1661 is: ) ) VOUT(IDEAL) = k VREF 1024 where k is the decimal equivalent of the binary DAC input code D9-D0 and VREF is the voltage at REF (Pin 6). Power-On Reset The LTC1661 LTC1661 positively clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. Power Supply Sequencing The voltage at REF (Pin 4) must not ever exceed the voltage at VCC (Pin 6) by more than 0.2V. Particular care should be taken in the power supply turn-on and turn-off sequences to assure that this limit is observed. See Absolute Maximum Ratings. Serial Interface See Table 1. The 16-bit input word consists of the 4-bit DAC control code, the 10-bit input code and two don't care bits. Table 1. LTC1661 LTC1661 Input Word A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 Control Input Code Don't Care The data path for the 10-bit input code is buffered by two latch registers. The first of these, the Input Register, is used for loading new input codes. The second buffer, the DAC By selecting the appropriate 4-bit DAC control code (see Table 2) it is possible to perform single operations, such as loading one DAC or changing Power-Down status (Sleep/Wake). In addition, some control codes perform two or more operations at the same time. For example, one such code loads DAC A, updates both outputs and Wakes the part. The DACs can be loaded separately or together, but the outputs are always updated together. Register Loading Sequence See Figure 1. With CS/LD held low, data on the DIN input is shifted into the 16-bit Shift Register on the positive edge of CLK. The 4-bit DAC control code, A3-A0, is loaded first, then the 10-bit input code, D9-D0, ordered MSB-to-LSB in each case. Two don't-care bits, X1 and X0, are loaded last. When the full 16-bit word has been shifted in, CS/LD is pulled high, causing the system to respond according to Table 2. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low. Sleep Mode DAC control code 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, most internal bias currents are disabled while all digital circuitry stays fully active; static power consumption is thus virtually eliminated. The analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state. 5 LTC1661 LTC1661 U OPERATIO Table 2. DAC Control Functions CONTROL A3 A2 A1 A0 INPUT REGISTER STATUS DAC REGISTER STATUS POWER-DOWN STATUS (SLEEP/WAKE) COMMENTS 0 0 0 0 No Change No Update No Change No Operation. Power-Down Status Unchanged (Part Stays In Wake or Sleep Mode) 0 0 0 1 Load DAC A No Update No Change Load Input Register A with Data. DAC Outputs Unchanged. Power-Down Status Unchanged 0 0 1 0 Load DAC B No Update No Change Load Input Register B with Data. DAC Outputs Unchanged. Power-Down Status Unchanged 0 0 1 1 Reserved 0 1 0 0 Reserved 0 1 0 1 Reserved 0 1 1 0 Reserved 0 1 1 1 1 0 0 0 No Change Update Outputs Wake Load Both DAC Regs with Existing Contents of Input Regs. Outputs Update. Part Wakes Up 1 0 0 1 Load DAC A Update Outputs Wake Load Input Reg A. Load DAC Regs with New Contents of Input Reg A and Existing Contents of Reg B. Outputs Update. Part Wakes Up 1 0 1 0 Load DAC B Update Outputs Wake Load Input Reg B. Load DAC Regs with Existing Contents of Input Reg A and New Contents of Reg B. Outputs Update. Part Wakes Up 1 0 1 1 1 1 0 0 1 1 0 1 No Change No Update Wake Part Wakes Up. Input and DAC Regs Unchanged. DAC Outputs Reflect Existing Contents of DAC Regs 1 1 1 0 No Change No Update Sleep Part Goes to Sleep. Input and DAC Regs Unchanged. DAC Outputs Set to High Impedance State 1 1 1 1 Load DACs A, B with Same 10-Bit Code Update Outputs Wake Load Both Input Regs. Load Both DAC Regs with New Contents of Input Regs. Outputs Update. Part Wakes Up CLK DIN Reserved Reserved Reserved 1 A3 2 A2 3 A1 CONTROL 4 A0 5 D9 6 D8 7 D7 8 D6 9 D5 10 D4 11 D3 INPUT CODE 12 D2 13 D1 14 D0 15 X1 16 X0 DON'T CARE INPUT WORD W0 CS/LD (LTC1661 LTC1661 RESPONDS) (CLK ENABLED) Figure 1. Register Loading Sequence 6 1661 F01 LTC1661 LTC1661 U OPERATIO Sleep mode is initiated by performing a load sequence using control code 1110b (the DAC input code D9-D0 is ignored). The input codes stored in the input register for each channel may be changed during Sleep by using control codes 0001b and 0010b. output resistance of 85 (typical) when driving a load to the rails. The output amplifiers are stable driving capacitive loads up to 1000pF. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. For example, a 0.1µF load can be successfully driven by inserting a 110 resistor. The phase margin of the resulting circuit is 45°, and increases monotonically from this point if larger values of resistance, capacitance or both are substituted for the values given. Voltage Outputs Each of the rail-to-rail output amplifiers contained in the LTC1661 LTC1661 can typically source or sink up to 5mA (VCC = 5V). The outputs swing to within a few millivolts of either supply when unloaded and have an equivalent U U W U APPLICATIONS INFORMATION Rail-to-Rail Output Considerations VCC as shown in Figure 2c. No full-scale limiting can occur if VREF is less than VCC ­ FSE. In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 2b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 512 INPUT CODE 1023 (a) OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1661 F02 Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC 7 LTC1661 LTC1661 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 ± 0.004* (3.00 ± 0.102) 0.040 ± 0.006 (1.02 ± 0.15) 0.007 (0.18) 0.034 ± 0.004 (0.86 ± 0.102) 8 7 6 5 0° ­ 6° TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) TYP 0.021 ± 0.006 (0.53 ± 0.015) 0.006 ± 0.004 (0.15 ± 0.102) 0.118 ± 0.004* (3.00 ± 0.102) 0.192 ± 0.004 (4.88 ± 0.10) MSOP (MS8) 1197 1 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE * DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 2 3 4 N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.300 ­ 0.325 (7.620 ­ 8.255) 0.009 ­ 0.015 (0.229 ­ 0.381) ( +0.035 0.325 ­0.015 +0.889 8.255 ­0.381 ) 0.045 ­ 0.065 (1.143 ­ 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 0.065 (1.651) TYP 0.100 ± 0.010 (2.540 ± 0.254) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1197 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1446/LTC1446L LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference LTC1446 LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1448 LTC1448 Dual 12-Bit VOUT DAC in SO-8 Package VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454/LTC1454L LTC1454/LTC1454L Dual 12-Bit VOUT DACs in SO-16 SO-16 Package with Added Functionality LTC1454 LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458/LTC1458L LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458 LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1659 LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC: 2.7V to 5.5V Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1660 LTC1660 Octal 10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output 8 Linear Technology Corporation 1661i LT/TP 0199 4K · PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com © LINEAR TECHNOLOGY CORPORATION 1999