LTC1629 LTC1628 AN77-1 AN77-2 14AP-P AN77-3 AN77-4 10AP-P AN77-5 AN77-6 AN77-7 - Datasheet Archive

 

September 1999 High Efficiency, High Density, PolyPhase Converters for High Current Applications Wei Chen INTRODUCTION As logic

 

Application Note 77 September 1999 High Efficiency, High Density, PolyPhase Converters for High Current Applications Wei Chen INTRODUCTION As logic systems get larger and more complex, their supply current requirements continue to rise. Systems requiring 100A are fairly common. A high current power supply to meet such requirements usually requires paralleling several power regulators to alleviate the thermal stress on the individual power components. A power supply designer is left with the choice of how to drive these paralleled regulators: brute-force single-phase or smart PolyPhaseTM. A PolyPhase converter interleaves the clock signals of the paralleled power stages, reducing input and output ripple current without increasing the switching frequency. The decreased power loss from the ESR of the input capacitor and the low switching losses associated with MOSFETs at relatively low switching frequencies help achieve high power conversion efficiency. The size and cost of the input capacitors are also greatly reduced as a result of input ripple current cancellation. Since output ripple current cancellation also occurs, lower value inductors can be used. This results in improved dynamic response to load transients. A combination of lower current rating and decreased inductance also allows the use of smallersized, low profile, surface mounted inductors. For multioutput applications, PolyPhase converters may also provide the benefit of smaller input capacitors. Previously, the implementation of multiphase designs was difficult and expensive because of complex timing and current-sharing requirements. The newly developed LTC1629 LTC1629 solves these problems for high current, single output designs, while the LTC1628 LTC1628 addresses dual-output applications. Both ICs are dual, current mode, PolyPhase controllers that can drive two synchronous buck stages simultaneously. The features of the LTC1629 LTC1629 include a unity-gain differential amplifier for true remote sensing, low impedance gate drives, current-sharing, overvoltage protection, optional overcurrent latch-off and foldback current limit. Additionally, the LTC1629 LTC1629 can be configured for 2-, 3-, 4-, 6- and 12-phase operation with a simple phase selection signal (high, low or open). Optimizing the number of phases can help achieve the smallest and the most cost-effective power supply design. This application note analyzes the performance of PolyPhase converters and provides guidelines for selecting the phase number and designing a PolyPhase converter using the LTC1629 LTC1629. The following questions will be answered as the discussion goes on: · How much do I gain by using a PolyPhase architecture? · How many phases do I need for my application? · How do I design a PolyPhase converter? HOW DO POLYPHASE TECHNIQUES EFFECT CIRCUIT PERFORMANCE? In general, PolyPhase operation improves the large signal performance of a switched mode power converter, by such means as reducing ripple current and ripple voltage. A synchronous buck converter is used as an example in this application note to analyze the effects of PolyPhase techniques on circuit performance. High current outputs usually require paralleling several regulators. The single-regulator approach is not feasible because of the unacceptable thermal stress on the individual power components. Paralleled regulators are synchronized to have the same switching frequency to eliminate beat frequency noise at both the input and output terminals. Based on the phase relationship between the paral, LTC and LT are registered trademarks of Linear Technology Corporation. PolyPhase is a trademark of Linear Technology Corporation. AN77-1 AN77-1 Application Note 77 leled regulators, these converters can be divided into two types: single-phase and PolyPhase. To balance the thermal stress in each component, paralleled regulators must also share the load current. In this application note, the number of channels refers to the number of the paralleled regulators in one supply. The following symbols are defined to facilitate reference: · VO: DC output voltage · IO: DC output current · VIN: DC input voltage · T: switching period · mc: number of paralleled channels · m: number of phases. The possible phase numbers are usually determined by the channel number, mc. For example, if mc = 6, the possible phase numbers are m = 1, 2, 3, 6. · CO: output capacitor · ESR: equivalent series resistance of CO · Lf: output inductor Current-Sharing The current-sharing can be easily achieved by implementing peak current mode control. In a current mode control regulator, the load current is proportional to the error voltage in the voltage feedback loop. If the paralleled regulators see the same error voltage, they will source equal currents. A 2-channel circuit is used as the example to explain this current-sharing mechanism. As shown in Figure 1, peak current mode control requires that the high side switch turn off when the peak inductor current (IL1, IL2) intersects the error voltage, VER, resulting in the same peak inductor currents. If the inductors are identical, the peak-to-peak ripple currents of the inductors will be the same. The DC currents of two inductors, which are the peak current less half of the peak-to-peak ripple current, will be equivalent. Two modules therefore share the load current equally. The same current-sharing mechanism can be extended to any number of channels in parallel. This current-sharing scheme will prevent an individual module from suffering excessive current stress in steady state operation and during line/load transient conditions. Note that the sharing mechanism is open loop, so no oscillations will occur due to current-sharing. · D: duty cycle, approximated by VO/VIN in buck circuits VGS(MAIN SWITCH OF MODULE 1) IIN O IIN1 DT T VGS(MAIN SWITCH OF MODULE 2) IN+ MODULE #1 IL1 CIN + L1 OUT+ + IC VER CO IN­ OUT­ IIN2 IO/2 IL1 MODULE #2 IL2 L2 IC IO AN77 F01a (a) AN77 F01b (b) Figure 1. 2-Channel Converter: (a) Schematic and (b) Typical Waveforms AN77-2 AN77-2 IL2 Application Note 77 Output Ripple Current Cancellation and Reduced Output Ripple Voltage The phase relationship of Figure 1(b) shows how ripple current cancellation at the output works. Because of the 180 degree phase difference between the two converters, the two inductor ripple currents in the two-phase converter tend to cancel each other, resulting in a smaller ripple current flowing into the output capacitor. The frequency of the output ripple current is doubled as well. All of these factors contribute to a smaller output capacitor for the same ripple voltage requirement. Figure 2 shows the measured waveforms of the inductor currents and output ripple currents in a 2-channel converter. The output ripple cancellation reduces the output ripple current from 14AP-P 14AP-P (single-phase) to 6AP-P (dualphase). The ripple frequency in the dual-phase circuit is twice the switching frequency. To quantify the output ripple current amplitude in an mphase circuit, a closed-form expression was developed. The derivation starts with the 2-phase circuit shown in Figure 1. During the interval [from DT, T] when the high side switch in module 1 is off and the high side switch of module 2 is on, the inductor current in module 1 decreases IL1 5A/DIV and the inductor current in module 2 increases. The net ripple current flowing into the output capacitors is smaller. The output ripple current for the 2-phase circuit is derived as: IO = 2VO(1 - D)T 1 - 2D Lf 1 - 2D + 1 (1) See Appendix A for the detailed derivation procedure. By extending the same derivation procedure to an m-phase configuration, the output ripple current for an m-phase circuit is obtained. Output ripple current peak-to-peak amplitude in m-phase circuit: ( ) VOT 1 - D , m=1 Lf m i IO = -D i=1 m mc · VOT · , m = 2, 3,. (2) Lf m-1 i 1 -D + m i=1 m IL1 5A/DIV IL2 5A/DIV IL2 5A/DIV IC 5A/DIV IC 5A/DIV AN77 F02a (a) Single-Phase AN77 F02b (b) Dual-Phase Figure 2. Output Ripple Current Waveforms In a 2-Channel Circuit. IL1 and IL2 Are the Inductor Currents In Two Channels and IC Is the Net Ripple Current Flowing Into Output Capacitor. Test Conditions: VIN = 12V, VO = 2V, IO = 20A AN77-3 AN77-3 Application Note 77 The output ripple voltage is estimated to be: VO,PP < IOT + IO · ESR 8mCO be rewritten as: (3) The first term in equation (3) represents the ripple voltage on the pure capacitive components of CO and the second term represents the ripple voltage generated on the ESR of CO. Intuitively, a higher phase number helps reduce the ripple component in the first term, and therefore, the overall ripple voltage amplitude at the output. Another interesting fact that can be observed is that the output ripple current and voltage will reach zero if the duty cycle is equal to one of the following critical points: Dcrit = i , m i = 12,.,m - 1 , (4) In a buck converter, the duty cycle is the ratio of the output voltage and input voltage. By interpreting equation (4) in terms of VIN and VO, the zero output ripple conditions can VO i = , VIN m , i = 12,.,m - 1 The plots in Figure 3 demonstrate the influence of phase number and duty cycle on the output ripple current. In this plot, the output ripple current is normalized against the inductor ripple current at zero duty cycle (DIr = VOT/Lf). The following assumptions are made: the number of channels equals the phase number, the output voltage is fixed and the power conversion efficiency is assumed to be 100%. This plot can be used to estimate the output ripple current without tedious calculations. The output ripple current approaches zero when the duty cycle is near the critical points for the selected phase number. For a buck circuit, the duty cycle is approximately the ratio of VO/VIN. Therefore, if the input and output voltages are relatively fixed, there exists an optimum phase number to minimize the output ripple voltage. 1.00 0.95 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.90 0.85 0.80 PEAK-TO-PEAK OUTPUT RIPPLE CURRENT DIr 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VO/VIN) AN77 F03 Figure 3. Normalized Output Ripple Current vs Duty Cycle, DIr = AN77-4 AN77-4 (5) VOT Lf Application Note 77 Assuming that the maximum available phase number is six and the efficiency is 100%, the optimum phase numbers for some common input and output voltages are shown in Table 1. Table 1. Optimum Phase Number for Minimizing the Ripple Currents (Assuming That the Maximum Phase Number Is 6 and the Efficiency Is 100%) VO = 1.2V VO = 1.5V VO = 2.0V VO = 2.5V VIN = 5V 4 6 5 2, 4, 61 VIN = 12V 6 6 6 5 1 6 is the optimum phase number for minimum input ripple current. For high step-down ratio or low duty cycle applications (for example, VIN = 12V, VO = 1.2V, D = 0.1), a high phase number helps reduce the maximum ripple current. For wide duty cycle range applications, high phase number tends to, but does not necessarily, yield lower output ripple current. The optimum phase number needs to be evaluated over the complete operating duty cycle range. The reduction in the ripple current by increasing phase number is not significant above four phases in most duty cycle ranges. Figure 4 shows the measured output ripple current near the critical duty cycle point, which is Dcrit = 0.5 for a 2-phase circuit. The test conditions were VIN = 5V, VO = 2V, IO = 20A, fs = 250kHz. Because of the voltage drop across the MOSFET switches, the operating duty cycle was very close to 50%. The dual-phase technique was able to reduce the output ripple current considerably, from 10AP-P 10AP-P (in the single-phase circuit) to 2.5AP-P. As a result, the output ripple voltage near the critical duty cycle point is negligible, as shown in Figure 5. IL1 5A/DIV IL1 5A/DIV IL2 5A/DIV IL2 5A/DIV IC 5A/DIV IC 5A/DIV AN77 F04a AN77 F04b (a) Single-Phase (b) Dual-Phase Figure 4. Experimental Waveforms of Output Ripple Current Near Critical Duty Cycle Point (VIN = 5V, VO = 2V, IO = 20A, fs = 250kHz): Top Trace, Inductor 1 Current; Middle Trace, Inductor 2 Current; Bottom Trace, Output Ripple Current VOAC 10mV/DIV VOAC 10mV/DIV VSW1 10mV/DIV VSW1 10mV/DIV VSW2 10mV/DIV VSW2 10mV/DIV (a) Single-Phase AN77 F05a AN77 F05b (b) Dual-Phase Figure 5 Measured Output Ripple Voltage (Top Trace) near Critical Duty Cycle Point (VIN = 5V, VO = 2V, IO = 20A, fs = 250kHz, VSW1 and VSW2 are the switch node voltages across the bottom FETs) AN77-5 AN77-5 Application Note 77 Improved Load Transient Response The influences of PolyPhase techniques on the load transient performance are numerous. First, the reduced output ripple voltage allows more room for voltage variations during the load transient because the ripple voltage will consume a smaller portion of the total error budget. With the same number of capacitors on the output terminals of the power supply, the sum of the overshoot and undershoot can be reduced dramatically. Second, the reduced ripple current allows the use of lower value inductors. This speeds up the output current slew rate of the power supply. Consequently, PolyPhase helps improve the load transient performance of the power supply. Figure 6 shows the output voltages during a load transient. It is noted that the two circuits have the same electrical design. The dual-phase technique reduces the voltage variation from 69mVP-P to 58mVP-P, a 16% reduction with no changes in component values. The inductor values could be reduced while still achieving lower output ripple voltage than the single-phase design, and further improvement in the peak-to-peak voltage variations for the load transient response could be realized. currents. In a PolyPhase circuit, however, the paralleled buck stages switch at different times and the pulsating current flowing through the input capacitor is reduced dramatically. Figure 7 shows the measured input ripple current in a 2-channel converter. The PolyPhase converter reduces the peak amplitude of the input ripple current by half and doubles the ripple frequency. The reduced ripple current amplitude results in a much smaller RMS current in the input capacitor. Because the power loss on the ESR of the input capacitor is proportional to the square of the RMS current, the loss reduction can be significant. The size of the input capacitor is reduced and the life of the capacitor will likely be improved. The increased ripple frequency and the reduced ripple amplitude also facilitate EMI filtering. In order to quantitatively evaluate the input ripple current in an m-phase circuit, a close-form expression is derived by using some mathematical manipulations on the input ripple current waveforms. Input ripple current RMS value: k k + 1 2 mc2 Vo (1 - D)T - D Io + D - · m m Lf 12mD2 2 Input Ripple Current Cancellation The input current of a buck converter is discontinuous. With the input supply mainly sourcing DC current, the input capacitor supplies a pulsating current to the buck converter. In a single-phase circuit, the high side switches of the paralleled buck modules turn on simultaneously. The input capacitor needs to provide the sum of the pulsed VOAC 20mV/DIV Iirms = 3 3 k k +1 2 (k + 1) D - + k2 - D m m (6) where k = FLOOR(m·D), m = 1, 2, . VOAC 20mV/DIV AN77 F06a (a) Single-Phase AN77 F06b (b) Dual-Phase Figure 6. Measured Output Voltage During Load Transients (VIN = 12V, VO = 2V, fs = 250kHz. Load steps: 5A to 20A and 20A to 5A, 50µs rise and fall times. Time scale: 500µs/DIV) AN77-6 AN77-6 Application Note 77 The variable k is determined by the phase number (m) and the duty cycle (D). For example, in a five-phase converter, at 45% duty cycle, k = FLOOR(5 · 0.45) = 2. The FLOOR(x) function provides a greatest integer that is smaller than or equal to x. As indicated in equation (6), the input ripple current of a PolyPhase converter consists of two major factors: the DC load current (first term) and the inductor ripple current (second term). Since the inductor ripple current is almost unaffected by the load conditions, the maximum RMS input ripple current is reached at full load. Usually, the size of the input capacitor is determined by the power dissipation on its ESR. The full load condition contributes to a maximum RMS input ripple current, and therefore, determines the size of the input capacitor. Figure 8 plots the RMS input ripple current against the duty cycle for different phase configurations. In this plot, the RMS input ripple current is normalized against the DC load current. The output voltage is assumed fixed at 5V and the input voltage is varied, resulting in a duty cycle range from 0.1 to 0.9. Several facts can be observed from the curves. IIN1 IIN1 10A/DIV 10A/DIV IIN2 IIN2 10A/DIV 10A/DIV TOTAL IIN TOTAL IIN 10A/DIV 10A/DIV AN77 F07a (a) Single-Phase AN77 F07b (b) Dual-Phase Figure 7 Measured Input Ripple Current: Iin1 and Iin2 are the ripple currents into the paralleled modules. Total Iin is the net ripple current into the input capacitor. (VIN = 12V, VO = 2V, IO = 20A, fs = 250kHz) 0.60 0.55 0.50 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE RMS INPUT RIPPLE CURRNET DC LOAD CURRENT 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY FACTOR (VO/VIN) AN77 F08 Figure 8. Normalized RMS Input Ripple Current AN77-7 AN77-7 Application Note 77 When the duty cycles are close to the critical duty cycle points (determined in equation (4), the first term in equation (6) is zero. The RMS input ripple current reaches the local minimum values. These values are not zero due to the output inductor ripple current. Consequently, there exists an optimum phase number to achieve the minimum RMS input ripple current for a fixed input and output application. For some common input and output voltages, the optimum phase numbers for minimizing the input ripple current are shown in Table 1. Note that these are the same as the values for the minimum output ripple voltage. For a wide duty cycle range application, higher phase number helps reduce the maximum input ripple current. But the reduction in the input ripple current by increasing phase number may not be significant at higher phase numbers in certain duty cycle ranges. The optimum phase number needs to be evaluated over the complete operating duty cycle range. Figure 9 shows the experimental waveform of the input ripple currents in a 2-channel circuit. The circuit operated at close to 50% duty cycle, which is the critical duty cycle point for the two-phase circuit. Compared to the singlephase technique, the PolyPhase technique reduced the ripple current in the input capacitor dramatically. DESIGN CONSIDERATIONS Similar to the design of conventional paralleled regulators, the design of a PolyPhase converter involves the choice of the number of paralleled channels and the selection of the power components (MOSFETs, inductors, capacitors, etc.). Usually, the number of phases is set to be equal to the number of channels. However, the number of channels and the number of phases may be different. The number of channels is usually determined by the total load current and the acceptable current stress in each channel. For example, if the required load current is 60A and the maximum current stress per channel is 15A, 4 channels need to be paralleled. The number of phases, on the other hand, can be selected to minimize the input and output filter capacitors. Note that each phase must have an equal number of channels. In this example, a 4-channel configuration, one, two or four phases may be used. Selection of phase number As discussed in the previous section, the selection of a different number of phases will greatly affect the input and output ripple current. For a narrow input and output range, the duty cycle range is relatively narrow. The optimum phase number should be chosen such that the circuit operates at or near one of the critical duty cycle points (determined by equation 4). For some practical input voltages and output voltages, the optimum phase numbers for the minimum input ripple currents and the lowest output ripple voltage are listed in Table 1. For wide input or output voltage range, the phase number should be chosen such that the worst-case RMS input ripple current and the worst-case output ripple voltage are minimized for the complete operating duty cycle range. IIN1 10A/DIV IIN1 10A/DIV IIN2 10A/DIV IIN2 10A/DIV TOTAL IIN 10A/DIV TOTAL IIN 10A/DIV (a) Single-Phase AN77 F09a (b) Dual-Phase Figure 9. Input Current Near Critical Duty Cycle In a 2-Channel (VIN = 5V, VO = 2V, IO = 20A, fs = 250kHz) AN77-8 AN77-8 AN77 F09b Application Note 77 PolyPhase Converters using the LTC1629 LTC1629 Table 2. Phase Function Table for LTC1629 LTC1629 The LTC1629 LTC1629 integrates proprietary phase-locked-loopbased phasing circuitry. Each IC can be synchronized to an external signal at the PLLIN pin and produce a CLKOUT signal to synchronize other ICs. Table 2 shows the phase function table of the LTC1629 LTC1629. By applying the command signal (INTVCC, open or SGND) to the PHASMD pin and connecting the CLKOUT pin of one IC to the PLLIN pin of the next one, different numbers of phases can be achieved. Figure 11 shows 2-phase, 3-phase, 4-phase, 6-phase and 12-phase configurations using the LTC1629 LTC1629. PHASMD 0V OPEN INTVCC PLLIN 0° 0° 0° CONTROLLER 1 0° 0° 0° CONTROLLER 2 180° 180° 240° CLKOUT 60° 90° 120° is provided by a 6-phase power supply, the two power supplies can be interleaved by using a 12-phase configuration. As shown in Figure 12, U1, U2 and U3 are used to produce the 3.3V output, and U4, U5, and U6 are used for the 5V output. The resulting input ripple current frequency is twelve times the switching frequency and the ripple current amplitude is reduced. A higher number of phases is usually needed for very high output current or multioutput applications. For example, in a 2-output system, 3.3V/90A and 5V/60A, if each output U1 0 U1 U2 PHASMD TG1 0° INTVCC PHASMD TG1 0° PLLIN TG2 180° PLLIN TG2 240° CLKOUT (a) 2-PHASE TG1 0° TG2 180° CLKOUT 28 CLKOUT SENSE1 + 2 27 TG1 SENSE1 ­ 3 EAIN 25 BOOST1 PLLFLTR 5 24 VIN PLLIN 6 23 BG1 120° CLKOUT 0 PHASMD TG1 90° PLLIN TG2 270° CLKOUT 90° 26 SW1 4 TG2 U2 PHASMD TOP VIEW 1 TG1 PLLIN (b) 3-PHASE PLLIN RUN/SS PHASMD 120 U1 OPEN 0 PHASMD 7 ITH 9 0 U2 PHASMD TG1 0° PLLIN TG2 180° 0 U3 PHASMD TG1 60° PLLIN TG2 240° CLKOUT 0 PHASMD TG1 120° PLLIN TG2 300° CLKOUT 21 INTVCC SGND U1 22 EXTVCC 8 (c) 4-PHASE CLKOUT 20 PGND VDIFFOUT 10 60° 19 BG2 VOS ­ 11 18 BOOST2 VOS + 12 16 TG2 SENSE2 + 14 U1 17 SW2 SENSE2 ­ 13 120° (d) 6-PHASE U2 15 AMPMD 0 PHASMD TG1 0° PLLIN TG2 180° 0 PHASMD TG1 60° OPEN PHASMD TG1 120° PLLIN TG2 240° PLLIN TG2 300° 210° CLKOUT CLKOUT 60° 0 CLKOUT 120° U4 Figure 10. Pinouts of LTC1629 LTC1629 U3 U5 PHASMD TG1 210° PLLIN TG2 30° CLKOUT 0 U6 PHASMD TG1 270° PLLIN TG2 90° CLKOUT 0 PHASMD TG1 330° PLLIN TG2 150° CLKOUT 330° 270° (e) 12-PHASE 12-PHASE AN77 F11 Figure 11. Configuration of Different Phases Using the LTC1629 LTC1629 AN77-9 AN77-9 Application Note 77 across the individual modules' inputs and outputs (such as A1B1, A2B2, etc.). The traces (AA1, AA2, BB1, BB2, etc.) between modules should be the shortest and widest possible to balance the current stress in each capacitor. The impedance of the traces highlighted in Figure 13 should be minimized. It is preferable that these traces be large copper planes. It is also important that the sources of bottom MOSFETs (B1, B2, etc.) be connected to the input filter capacitors before joining the ground plane (CD). Otherwise, the ground noise generated by the pulsating current through the trace inductance will be seen on the output terminals as spikes. The LTC1629 LTC1629 includes a unity gain differential amplifier, enabling true remote sensing of the output voltage. This is particularly useful for maintaining tight output voltage regulation for high current applications. Each LTC1629 LTC1629 based regulator consists of two synchronous buck stages and two or more power regulators can be paralleled directly. The inherent peak current mode control permits automatic current-sharing. When several LTC1629-based regulators are in parallel, the LTC1629 LTC1629 of the master regulator senses the output voltage (VO +, VO ­) via its on-chip differential amplifier and divides this voltage (VDIFFOUT) down through the resistor divider to utilize the built-in 0.8V reference for output voltage regulation. This control voltage is then fed to the EAIN pins (error amplifier input) of each LTC1629 LTC1629. Since the error amplifier inside the LTC1629 LTC1629 is a gm transconductance amplifier, directly paralleling the ITH pins (error amplifier outputs) and the EAIN pins is allowed. The paralleled regulators now share the same error voltage. Because the load current of a current mode regulator is proportional to the error voltage, the paralleled regulators must source equal currents. IN+ A A2 A1 E CIN + To take full advantage of the ripple cancellation of the PolyPhase technique, the input capacitors and output capacitors are ideally placed at the summation points of all the input ripple currents and all the output ripple currents, respectively. Figure 13 shows the layout for a 2-phase converter. In practice, the filter capacitors may be placed + CO D U1 0 B B1 AN77 F13 IN­ C Figure 13. Layout Diagram of Power Stage for 2-Phase Converter 0° U2 PHASMD TG1 0° PLLIN TG2 0 180° U3 PHASMD TG1 60° OPEN PHASMD TG1 120° PLLIN TG2 240° PLLIN TG2 300° 210° CLKOUT CLKOUT 0 CLKOUT 120° 60° U4 U5 PHASMD TG1 210° PLLIN TG2 30° CLKOUT 0 OUT­ B2 OUTPUT #1 U6 PHASMD TG1 270° PLLIN TG2 90° CLKOUT 0 PHASMD TG1 330° PLLIN TG2 150° CLKOUT 330° 270° OUTPUT #2 AN77 F12 Figure 12. 2-Output System Using 12-Phase Configuration AN77-10 AN77-10 OUT+ E1 F Layout Considerations E2 Application Note 77 DESIGN EXAMPLE: 100A POLYPHASE POWER SUPPLY The specifications for a high current PolyPhase power supply are as follows: · Input: 12V (±10%) · Outputs: 3.3V at 90A nominal, 100A maximum · Load regulation: