1409/LTC1415 LTC1553 1575/LT1577 LTC1479 LTC1069-X LTC1409/LTC1415 LTC1410 - Datasheet Archive

 

DECEMBER 1996 IN THIS ISSUE . . . COVER ARTICLE LTC®1409/LTC1415 High Speed, Low Power 12-Bit ADCs . 1 Kevin R. Hoskins Issue

 

LINEAR TECHNOLOGY DECEMBER 1996 IN THIS ISSUE . . . COVER ARTICLE LTC®1409/LTC1415 1409/LTC1415 High Speed, Low Power 12-Bit ADCs . 1 Kevin R. Hoskins Issue Highlights . 2 LTC in the News . 2 DESIGN FEATURES LTC1553 LTC1553 Synchronous Regulator Controller Powers Pentium® Pro and Other Big Processors. 3 Y.L. Teo, S.H. Lim and Craig Varga The LT®1575/LT1577 1575/LT1577 UltraFastTM Linear Regulator Controllers Eliminate Bulk Output Capacitors . 9 Anthony Bonte LTC1479 LTC1479 PowerPathTM Controller Simplifies Portable Power Management Design . 14 Tim Skovmand New Rail-to-Rail Amplifiers: Precision Performance from Micropower to High Speed . 18 William Jett and Danh Tran High Efficiency, Low Dropout Lithium-Ion Battery Charger Charges Up to Five Cells at 4 Amps or More . 23 Fran Hoffart LTC1069-X LTC1069-X: a New Family of 8th Order Monolithic Filters . 27 Nello Sevastopoulos and Philip Karantzalis DESIGN IDEAS Micropower ADC and DAC in SO-8 Give PC 12-Bit Analog Interface . 30 Kevin R. Hoskins High Efficiency, Low Power, 3-Output DC/DC Converter . 33 VOLUME VI NUMBER 4 LTC1409/LTC1415 LTC1409/LTC1415 High Speed, Low Power 12-Bit ADCs by Kevin R. Hoskins High Speed, Less Power Expanding the family of high speed, low power dissipation 12-bit ADCs that began with the LTC1410 LTC1410, LTC recently introduced the LTC1409 LTC1409 and the LTC1415 LTC1415, increasing the number of high speed, low power ADCs available to designers of high speed data acquisition systems. With these new choices, a designer can pick an ADC that is optimized for his or her particular application. The LTC1409 LTC1409 and LTC1415 LTC1415 are ideal solutions for applications such as ADSL, HDSL, modems, direct downconversion, CCD imaging, DSP-based vibration analysis, waveform digitizers and multiplexed systems. The new LTC1409 LTC1409 and LTC1415 LTC1415 have much lower power dissipation and higher performance than other 12-bit ADCs currently on the market. The LTC1409 LTC1409 and LTC1415 LTC1415 dissipate just 80mW and 60mW, respectively. Package size is also a major advantage of the LTC1409 LTC1409 and LTC1415 LTC1415, since they are available in Synchronizing LTC1430s for Reduced Ripple . 34 DESIGN INFORMATION New Voltage References Are Smaller and More Precise . 35 Performance Enhancing Features Differential S/H and Wideband CMRR Like the LTC1410 LTC1410, the LTC1409 LTC1409 and LTC1415 LTC1415 have fully differential inputs. The differential inputs have a very good CMRR: 60dB or better over a 0to-10MHz bandwidth. The bandwidth of the input sample-and-hold is typically 30MHz. All of these features combine to create improved solutions for present and future data- or signalacquisition systems. Figure 1 is a block diagram of the LTC1409 LTC1409 and LTC1415 LTC1415. The outstanding conversion speed and accuracy of these parts is the result of the high performance differential sample-and-hold and the extremely continued on page 20 Table 1. LTC1409/LTC1415 LTC1409/LTC1415 key features John Seago Craig Varga 28-pin SO and SSOP packages. Some of the other key features of these new devices are shown in Table 1. LTC1409 LTC1409 LTC1415 LTC1415 Conversion Throughput 800ksps 1.2Msps Low Power Dissipation 80mW (±5V supply) 60mW (+5V supplies) John Wright NAP and SLEEP Modes New Device Cameos . 38 Design Tools . 39 Sales Offices . 40 Small Package- 28-pin SSOP , LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load, LinearView, Micropower SwitcherCAD, PowerPath and UltraFast are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corp. Other product names may be trademarks of the companies that manufacture the products. EDITOR'S PAGE Issue Highlights This issue of Linear Technology is loaded with new products. Our cover article introduces a pair of new high speed, low power 12-bit ADCs, the LTC1409 LTC1409 and LTC1415 LTC1415. These new parts offer conversion rates of 800ksps and 1.2Msps respectively and have much lower power dissipation than other ADCs currently on the market. This makes them ideal for applications such as ADSL, HDSL, modems, CCD imaging and the like. Power products feature prominently in this issue: the LTC1553 LTC1553, a synchronous switching regulator controller, is designed to convert 5V/12V "silver box" supplies to the low voltages required by the Intel Pentium processor and other big CPUs. An onboard 5-bit DAC conforms to the requirements of the Intel Pentium Pro processor power supply specification, making the LTC1553 LTC1553 a perfect fit in these applications. The LTC1553 LTC1553, like the LTC1430 LTC1430, provides current-limit and short-circuit protection without the use of an external sense resistor. Also featured in this issue is the new LT1575/LT1577 LT1575/LT1577 family of controller ICs. These new, easy-to-use devices drive discrete N-channel MOSFETs as source followers to produce extremely low dropout, UltraFast transient response regulators. These circuits completely eliminate expensive tantalum or bulk electrolytic capacitors in the most demanding microprocessor applications. For example, a 200MHz Pentium processor can operate with only the twenty-four 1µF ceramic capacitors that Intel already requires for the microprocessor. Another power control device for computer applications is introduced in this issue: The L TC1479 TC1479 PowerPathTM controller eliminates power-management nightmares that plague the dual rechargeable battery systems found in most notebook computers and other portable equipment. Finally, we have the LT1620 LT1620, an IC designed to be used with a current mode PWM controller (such as the LTC1435 LTC1435) to increase the output volt2 LTC in the News. Linear Technology Corp. Reports Steady Sales and Profits for Q1 1997 in a Tight Semiconductor Environment Linear Technology Corporation's net sales for its first quarter, ended September 29, 1996, wer e $90,063,000, an increase of 4% over the first quarter of the previous year. The Company also reported net income for the quarter of $31,358,000 or $0.40 per share, an increase of 3% over $30,520,000 or $0.39 per share, reported for the first quarter of last year. A cash dividend of $0.05 per share will be paid on November 13, 1996 to shareholders of record on October 25, 1996. According to Robert H. Swanson, president and CEO, "Despite a sluggish semiconductor environment, we were able to maintain our net sales and profitability. Our return on sales of approximately 35% continues to lead the industry. We generated approximately $10 million in cash even after paying approximately $16 million to repurchase shares of our own stock. However, in the short term we conage range and optimize the circuit for battery charging applications. In this article, the LT1620 LT1620 and LTC1435 LTC1435 are featured in a high current, high performance constant-voltage/constant-current battery charger for lithium-ion and other battery types. Several new additions to LTC's family of rail-to-rail op amps are presented herein. These include the LT1498/ LT1498/ LT1499 LT1499 C-LoadTM op amps, which feature a 10MHz gain-bandwidth product, 4V/µs slew rate and the ability to drive 10,000pF; the low current LT1466 LT1466­69, with quiescent current of only 50µA; and the high precision LT1218A/LT1219A LT1218A/LT1219A, featuring VOS trimmed to 100µV max. Filters are represented in this issue tinue to be in an unpredictable environment whereby reduced backlog and shorter lead times cause the business to be very dependent on orders that are received and shipped in the same quarter." A detailed look at the best-performing stock index of them all-the Nasdaq 100-reveals that Linear Technology Corp. is ranked high again this year among the best-run, most effective and highest-valued companies in the nation. Coming in well above such familiar names as Altera (70th), Maxim (71st), Micron (83rd) and Cirrus Logic (84th), Linear Technology Corp. is listed 52nd on the Nasdaq 100, with a market capitalization of more than $2.2 billion as of press time. The financial performance of LTC has been so good that one majorfund manager who prefers bonds to stocks says that he would make an exception for LTC. Quoted by Kathleen Gallagher in her syndicated column "Street Smart," Thomas M. Wargin, president of Liberty LaSalle Financial Group, Inc., says that he "likes Linear Technology, a specialty chip maker whose stock price dropped (this summer). He expects its earnings to grow 21% annually for the next five years." by the LTC1069-X LTC1069-X, a family of semicustom filters that can integrate any single 8th order or dual 4th order classical filter approximation, or any application-specific filter response, in an SO-8 package. This issue includes a modest collection of Design Ideas: a 12-bit analog interface for the PC, based on the LTC1298 LTC1298 ADC and LTC1446 LTC1446 DAC, with sample code; a low power, 3output DC/DC converter built around the LTC1435 LTC1435; and a technique for synchronizing two LTC1430 LTC1430 buck regulators for reduced output ripple. We conclude with Design Information on the LT1460 LT1460 and LT1236 LT1236 voltage references, and a page of New Device Cameos. Linear Technology Magazine · December 1996 DESIGN FEATURES LTC1553 LTC1553 Synchronous Regulator Controller Powers Pentium® Pro and Other Big Processors by Y.L. Teo, S.H. Lim and Craig Varga Introduction Over the past few years, the operating voltages of Pentium class and other moder n micropr ocessors have dropped from 5V to 3.3V and below, while operating currents have steadily increased. Voltage regulation requirements have also tightened as the safety margin between proper operation and chip destruction has decreased along with feature size. To complicate matters further, the newest Pentium Pro processors from Intel® require a digitally adjustable power supply, so that the processor itself can determine the power supply voltage. The "silver box" power supplies provide only 5V/12V, with the exception of a few supplies also capable of delivering 3.3V. Due to the extreme accuracy and exceptionally fast load transient response required by today's processor supplies, the supply has been forced onto the computer's motherboard. To fit this niche, Linear Technology introduces the LTC1553 LTC1553, a synchronous switching regulator controller designed to convert the 5V/12V "silver box" rails to the lower 1.80V­3.5V required by the CPU. An onboard 5bit DAC conforms to the requirements of the Intel Pentium Pro processor power supply specification, making the LTC1553 LTC1553 a perfect fit in these applications. The LTC1553 LTC1553 is the newest member of the LTC switching regulator family. It shares many performance features with the popular LTC1430 LTC1430, including excellent (±1%) output regulation over temperature, line voltage and load current variations. The LTC1553 LTC1553, like the LTC1430 LTC1430, provides current-limit and short-circuit protection without the use of an external sense resistor. This is accomplished by measuring the voltage drop across the external high-side MOSFET durLinear Technology Magazine · December 1996 ing its on-time. To compliment the main voltage-feedback loop, the LTC1553 LTC1553 includes two additional feedback loops to provide good large-signal transient response. The LTC1553 LTC1553 adds additional internal circuits to conform to the Intel Pentium Pro processor power converter requirements while minimizing the number of external components. An on-chip 5-bit Table 1. Output voltage vs VIDn code VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 VID1 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 *Reserved for future expansion VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (VDC) * * * * * * * * * * 1.80 1.85 1.90 1.95 2.00 2.05 No CPU 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3 DESIGN FEATURES digital-to-analog converter (DAC) provides output voltages conforming to Intel's specifications. This allows the LTC1553 LTC1553 to read the code sent by the processor and provide it with the requested voltage. The LTC1553 LTC1553 also provides a power-good indication (PWRGD) to the system. There is also an on-chip overvoltage protection circuit that latches the regulator in an off state if the output voltage ever rises 15% or mor e above the DAC-requested voltage. Overtemperature protection is available with only two external components (a resistor and a thermistor) connected to the OUTEN pin. In applications with other processors, the four DAC inputs can be routed to a jumper block, zero ohm resistors or a DIP switch, or hard wired, to set the desired output voltage. This allows the output voltage to be programmed easily in steps while eliminating the need to stock an assortment of precision resistors. This flexibility in output voltage setting is cheap insurance against last-minute power supply voltage changes by microprocessor manufacturers. Current limiting is maintained by sensing the voltage drop across the RDS(ON) of the high-side MOSFET. The output enable pin employs a multilevel voltage threshold scheme that permits overtemperature sensing as well as providing the normal enable function. The LTC1553 LTC1553 is designed to be used with an all-N-channel MOSFET, synchronous buck regulator topology. The gate drive is able to significantly exceed the main power supply voltage. This allows the highside N-channel MOSFET(s) to be fully enhanced, ensuring low RDS(ON) and maximum efficiency. The driver outputs can source and sink enough current to drive multiple, paralleled power MOSFETs if desired, in order to obtain very low conduction losses. Low loss operation eliminates the need for a heat sink in most applications and results in very high efficiency. A soft-start circuit is included on the chip, permitting the rate of rise of the output voltage at turn-on to be controlled. LTC1553 LTC1553 Overview An on-chip 5-bit DAC is used to set the output voltage. No external feedback resistors are required. Five TTL inputs (VID0, VID1, VID2, VID3 and VID4) program the internal DAC (see Table 1). Each of the VIDn pins has an internal pull-up resistor to ensure a high state if it is not connected. When all the VIDn pins are in the high state, the LTC1553 LTC1553 shuts down, forcing the output voltage to zero and dropping the quiescent current to approximately 150µA. The ten lowest voltage codes are disabled at this time, allowing for future expansion. The DAC accuracy, initial reference voltage tolerance and internal feedback resistor tolerances result in a maximum initial output voltage error of ±1% of the selected output voltage. The line and load regulation plus temperature drift over the 0°C to 70°C temperature range will contribute another ±1% to the output error budget. This gives a total static operating error of less than ±2%, providing sufficient head- The LTC1553 LTC1553 runs at a fixed switching frequency, nominally 300kHz, without any external oscillator components. The on-chip, 5-bit digital-to-analog converter (DAC) allows the output voltage to be adjusted from 1.80V to 3.5V, as shown in Table 1. Voltage mode control eliminates the need for a current sense resistor. VCC = 5V PVCC = 12V CVCC VIN = 5V CPVCC CIN VCC G1 G2 Q1 Q2 LO VOUT LTC1553 LTC1553 CO Figure 1a. Typical LTC1553 LTC1553 circuit with PVCC powered from a 12V supply and main VIN powered from a high power 5V supply 1552_01a.eps 4 Internal DAC and Output Voltage Accuracy room (3%) for the dynamic response to remain within a ±5% output voltage tolerance, while still requiring a r easonable amount of output capacitance. External MOSFET Drivers The on-chip output drivers are powered from the PVCC pin, which is specified with a 20V maximum supply voltage. The PVCC supply should be at least 5V higher than the main VIN supply to allow the G1 output driver to fully enhance a high-side N-channel MOSFET. A major advantage of the LTC1553 LTC1553 over some competing devices results from its CMOS implementation: full rail-torail gate drive provides as much as 2V more drive than would a bipolar design. This results in a 20%­25% lower RDS(ON) for a given MOSFET. Figure 1a shows a typical LTC1553 LTC1553 circuit with PVCC powered from a 12V supply and the main VIN powered from a high power 5V supply. This provides 7V of enhancement for the high-side switch. The amount of current required of the 12V supply varies with the amount of MOSFET gate capacitance and will typically be less than 50mA. If a 12V supply is not available, the gate drive voltage can be generated with a simple charge-pump. Figure 1b shows a doubler charge-pump used to generate the PVCC voltage in a 5V-only system. A tripler charge-pump (Figure 1c) may be used in circuits where a higher voltage is required to fully enhance the external MOSFETs. VIN 1N5248B 1N5248B* 18V 1N5817 1N5817 CIN PVCC 0.1µF G1 G2 Q1 Q2 LO VOUT LTC1553 LTC1553 CO *OPTIONAL FOR VIN > 5V 1552_01b.eps Figure 1b. A doubler charge pump generates the PVCC voltage for a system powered from a single 5V supply. Linear Technology Magazine · December 1996 DESIGN FEATURES VCC = 5V 1N5248B 1N5248B 18V VIN = 12V VIN = 5V 1N5248B 1N5248B 18V 1N5817 1N5817 1N5817 1N5817 1N5817 1N5817 10 1N5817 1N5817 0.1µF 0.1µF PVCC 10µF G1 G2 0.1µF CVCC CIN VCC PVCC G1 Q1 Q2 CIN LO G2 Q1 Q2 LO VOUT VOUT LTC1553 LTC1553 LTC1553 LTC1553 CO CO 1552_01C.eps Figure 1c. A tripler charge pump provides more gate drive for the external MOSFETs. Note that if VIN is 10V or higher, a standard doubling charge-pump will cause the PVCC pin to exceed its 20V limit. Such circuits should use an alternate 17V charge-pump circuit (see Figure 1d). In any circuit where transient spikes at the PVCC pin may approach the 20V maximum rating, an 18V Zener diode is recommended from PVCC to GND (Figures 1b­1d). Multiple Feedback Loops Improve Transient Response The LTC1553 LTC1553 uses a standard voltage feedback loop to control the output voltage (see Figure 2). The error amplifier, ERR, compares the resistor-divided output voltage at FB to the internal reference voltage, VREF. This reference is controlled by the internal DAC. The resulting error voltage is amplified by the error amplifier. A pulse width modulated (PWM) signal is generated by comparing the error signal with a sawtooth waveform from the internal oscillator. This PWM and its complement signal drive the gates of power switches Q1 and Q2, respectively. Feedback loop compensation is set with an external compensation network at the COMP pin. Voltage mode control eliminates the need for a high loss, high cost, external sense resistor required by a typical current mode design. In addition to the main feedback loop, the LTC1553 LTC1553 also includes two Linear Technology Magazine · December 1996 1552_01d.eps Figure 1d. An alternate 17V charge pump circuit prevents PVCC from exceeding its 20V limit. additional "safety belt" comparators (MIN and MAX in Figure 2). In general, a control loop's bandwidth, and hence its slew rate, is limited by stability considerations. In some instances, it may be desirable to have the ability to respond to events faster than the error amplifier is capable of slewing. The MIN/MAX comparators provide this capability. These two comparators help to prevent extreme output perturbations with fast load current transients, while allowing the main feedback loop to be optimally compensated for stability. The MAX loop responds when the output exceeds the set point by more than 5%, forcing the duty cycle to 0% and holding Q2 on until the output drops back into the acceptable range. Similarly, if the output voltage sags 5% below the set point, the MIN loop kicks in, forcing the Q1 to 85% duty cycle until the output recovers. The 95% maximum duty cycle ensures that the gate drive charge-pump (if used) is refreshed every cycle. The response times of the MIN and MAX comparators are controlled to prevent them from triggering on noise spikes. Soft-Start and Current Limit Just one external capacitor is needed at the SS pin to set the soft-start time. During start-up, Q1 and Q2 are switched off until the input voltage has risen to the threshold of an inter- nal undervoltage lockout circuit. The soft-start capacitor is then charged by an internal 10µA current source. The soft-start function overrides the error amplifier and takes control of the pulse width modulator. As the SS pin voltage rises, the LTC1553 LTC1553's G1 duty cycle increases slowly until the output voltage is in regulation, at which point control is transferred to the voltage feedback loop. A significant advantage of employing voltage mode control in the LTC1553 LTC1553 is the elimination of the current sense resistor found in most other designs. With this resistor goes the simple means of providing overcurrent protection. Instead, the LTC1553 LTC1553 sets the output current limit by monitoring the voltage drop across the RDS(ON) of the high-side MOSFET, Q1, during its ON state (see Figure 3). The current limit is controlled by setting the maximum voltage drop allowed across Q1 with a single external resistor, RIMAX, at the IMAX pin. An internal 180µA current sink forces a voltage across RIMAX. This voltage is compared to the voltage drop across Q1 during its on-time. The IFB pin connects to the source of Q1 and Kelvin senses the voltage drop across Q1. For VIN = 12V, a 15V Zener diode (1N5245B 1N5245B or equivalent) will prevent voltage spikes at IFB from exceeding the maximum voltage rating. The current limit is designed to engage slowly 5 DESIGN FEATURES 115% VREF + FC PC FAULT OT ­ PWRGD DELAY DISDR LOGIC OUTEN PD 10% ­ PVCC PWM G1 + COMP SS G2 PGND VREF VREF ­ 5% + VREF + 5% ­ ­ ­ MIN MIN ERR MAX + VREF + FB BG SENSE DAC VID0 MSD VID1 ­ IFB + gm IMAX VID2 CC VID3 VID4 SGND + MHCL HCL MONO 50% VREF LVC ­ 1552_02.eps Figure 2. LTC1553 LTC1553 block diagram under mild current overloads, allowing the LTC1553 LTC1553 circuit to withstand momentary overloads without seriously affecting the output regulation. When an overcurrent condition is sensed, the output current comparator, CC, starts pulling current out of the external soft-start capacitor. This starts lowering the duty cycle and regulating the output current. Under severe overloads or output short-circuit conditions, a "hard" current-limit circuit is activated. An internal switch (MHCL in Figure 2) pulls down the SS pin immediately, stopping all switching and preventing damage to the output components. After a short time delay, the SS pin is released and the LTC1553 LTC1553 reruns a soft-start cycle, 6 attempting to restart. If the overcurrent condition is still present, the cycle repeats until the fault is removed. If desired, current limit can be disabled by floating IMAX and tying IFB to VCC. Power-Good and Overvoltage Signals The LTC1553 LTC1553 provides a power good signal (PWRGD) to the host system to indicate that the output voltage is within ±5% of the set voltage. PWRGD is valid whenever both the MIN and MAX comparators are inactive. An internal time delay is designed to prevent noise at the sense pin from toggling PWRGD unnecessarily. After the output has settled to within ±5% of the rated output for more than 300µs, PWRGD is set to a logic high. Similarly, PWRGD will go low only after the output is out of regulation for more than 100µs. Severe overvoltage faults at the output will trigger the FAULT flag. If the output voltage rises 15% higher than the programmed voltage, G1 and G2 will be disabled and the FAULT pin will go low. FAULT can be used to fire an external crowbar SCR or MOSFET to pull down the errant supply and protect the CPU from damage. When the LTC1553 LTC1553 detects an overvoltage, the fault flag's low state is latched, holding the regulator off. To restore normal operation, the OUTEN pin must be toggled or the input power removed and then restored. The most likely cause of an overvoltage fault is Linear Technology Magazine · December 1996 DESIGN FEATURES VIN 5.6k CIN RIMAX + VIN = 5V 100µA IMAX G1 CC OT G1 R1 ­ Q1 VCC Pentium Pro Processor SYSTEM Q1 L0 VOUT LTC1553 LTC1553 Q2 IFB Q2 G2 OUTEN LO 1N5245B 1N5245B* VOUT LTC1553 LTC1553 * FOR VIN = 12V APPLICATIONS G2 C0 THERMISTOR CO THERMISTOR SHOULD BE PHYSICALLY CLOSE TO Q1 1552_03.eps 1552_04.eps Figure 3. Current-limit setting for the LTC1553 LTC1553 a shorted high-side MOSFET. Therefore, activating some form of external clamp is preferable to depending on the LTC1553 LTC1553 to shut the supply down, as the controller will be unable to turn off a shorted FET. Overtemperature Protection 0V NORMAL OPERATION OT TRIPS G1, G2 DRIVERS STOP SHUTDOWN MODE OF OPERATION The OUTEN pin is an active-high digital input that enables the G1 and G2 MOSFET driver outputs. When OUTEN is pulled to a TTL low level, both G1 and G2 pull to ground, shutting off the external MOSFETs and leaving the output in a high impedance state. OUTEN is designed with multiple thresholds to allow it to also be used for overtemperature protection. The power MOSFET operating temperature can be monitored with an external negative temperature coefficient (NTC) thermistor mounted next to the external MOSFET that is expected to run the hottest-usually the high-side device, Q1. Electrically, the thermistor should form a voltage divider with another resistor (R1) connected to VCC. Their midpoint is connected to OUTEN (see Figure 4). As the thermistor temperature 1.2V 1.7V 2.0V OUTEN PIN VOLTAGE 1552_05.eps Figure 5. The OUTEN pin provides three threshold levels for temperature monitoring. Linear Technology Magazine · December 1996 Figure 4. Using the OUTEN pin for overtemperature protection increases, the OUTEN pin voltage is reduced. Under normal operating conditions, the OUTEN pin should stay above 2V. All circuits will function normally and the OT (overtemperature) pin will remain in a high state. If the temperature gets abnormally high, the OUTEN pin voltage will eventually drop below 2V. OT will switch to a logic low, providing an overtemperature warning to the system. As OUTEN drops below 1.7V, the LTC1553 LTC1553 disables both FET drivers. This shuts the driver supply down, preventing any further heating. If the OUTEN pin is pulled below 1.2V, the LTC1553 LTC1553 will enter shutdown mode. All internal switching stops, the COMP, SS, OT and PWRGD pins pull to ground and the quiescent current is reduced to 150µA. This residual quiescent current keeps the thermistor sensing circuit at OUTEN alive to allow the circuit to recover once it cools down. If the overtemperature protection circuit is not required, the OUTEN pin can be connected directly to a TTL compatible signal. Oscillator Synchronization The LTC1553 LTC1553's internal oscillator can be synchronized to an external clock frequency higher than 300kHz. This is accomplished by connecting a TTLlevel external clock signal to OUTEN. Note that if OUTEN is used for synchronization, it cannot be used for temperature monitoring. Also, if the operating frequency is forced substantially higher than 300kHz, the gain of the main feedback loop will increase and the compensation network may have to be readjusted for optimum performance. Typical Application A typical application for LTC1553 LTC1553 is converting 5V to 1.8V­3.5V in a Pentium Pro processor based personal computer. The supply may be in the form of a voltage regulator module (VRM) or may be implemented directly on the motherboard. The output is used to power the Pentium Pro processor and the input is taken from the system's 5V supply. The circuit shown in Figure 6 provides 1.80V­ 3.5V at 14A while maintaining output regulation within ±1%. The output voltage is determined by connecting the five DAC inputs to the VID pins of the processor. The power MOSFETs are sized to minimize board space and allow operation without the need of a heat sink. With proper airflow, ambient temperature conditions of up to 50° Celsius are acceptable. Typical efficiency is above 90% from 1A to 10A at 3.3V out. (see Figure 7). Achieving higher output currents from LTC1553 LTC1553 based designs is simply a matter of selecting appropriate MOSFETs and passive components. It pays to look at the regulator design from two perspectives: electrical and thermal. Most processor applications operate at average currents that are approximately 80% or less of the specified peak current. As such, the thermal design can be based 7 DESIGN FEATURES VIN = 5V 10µF 0.1µF 5.6k 5.6k + CIN 990µF 3 × 330µF 1N5817 1N5817 RIMAX 5.6k VCC IMAX PWRGD PVCC Q1A, Q1B (2 IN PARALLEL) 0.1µF G1 LO 2.0µH/18A H/18A FAULT Pentium Pro Processor SYSTEM OT VOUT IFB LTC1553 LTC1553 VID0­VID4 Q2 5V C0 2310µF 7 × 330µF G2 OUTEN COMP SS GND PGND SENSE 1.8k CONNECTING VID0-VID4 TO DIP SWITCH TO SET VOUT C1 100pF RC 20k CC 0.01µF DALE NTHS-1206N02 NTHS-1206N02 CSS 0.01µF 0.1µF Q1A, Q1B, Q2: MOTOROLA MTD20N03HDL MTD20N03HDL 1552_06.eps Figure 6. Typical 5V to 2.1V­3.5V/14A LTC1553 LTC1553 application 8 determine the hot resistance. In the case of two parallel MTD20N03HDLs (Q1A and Q1B), the cold resistance is approximately 0.035 each; therefore, assume the hot resistance to be approximately 0.050. Divide this by two because the FETs are in parallel. The threshold voltage is programmed by multiplying the IMAX pin's sink current by the value of RIMAX. Since we now can determine the required threshold, we need to calculate the value of RIMAX. Use the specified minimum sink current, 150µA, to calculate the resistor value. The soft-start time is programmed by the 0.01µF cap connected to the SS pin. The larger the value of this capacitor, the slower the turn-on ramp. Inductor LO is sized to handle the full load current, up to the onset of current limit, without saturating. A value of between 2µH and 3µH is adequate for most processor supply designs. Be careful not to overspecify the inductor. The inductor need not retain its no-load inductance up to the current-limit threshold. If the inductor still retains on the order of 25% to 30% of its initial inductance under worst-case short-circuit current conditions, the circuit should prove reliable. However, you do want to ensure that approximately 60% to 75% of the initial inductance is retained at nominal full load. Excessive inductance roll-off will result in higher than expected output ripple voltage at high loads, along with increased dissipation in the power FETs and the inductor itself. Proper loop compensation is critical for obtaining optimum transient response while ensuring good stability margins. The compensation network shown here gives good response when used with the inductor and the output capacitors values shown in Figure 6. Several low ESR capacitors are placed in parallel to reduce the total output ESR, resulting in lower output ripple and improved transient performance. continued on page 22 100 90 80 EFFICIENCY (%) on the lower current level. Higher currents, while present, are typically not of sufficient duration to significantly heat the power devices. The design does, however, need to be capable of delivering the peak current without entering current limit or resulting in device failures. Keep in mind that the power dissipation in a resistive element, such as a MOSFET, varies as the square of load current. As such, raising the load current from 80% to 100% translates to approximately 56% more power dissipation (1/0.82). Designing for this higher thermal load results in a huge, and most likely unnecessary, design margin. A good understanding of your system requirements can result in substantial savings in the size and cost for the power supply. RIMAX sets current limit to the desired level. Add one-half of the inductor ripple current to the maximum load current to determine the peak switch current. Multiply this current by the maximum on-resistance of the selected MOSFET switch to determine the minimum current limit threshold voltage. It's a good idea to add at least a 10% margin to this limit. Also, be sure to use the hot onresistance of the MOSFET. A multiplier of about 1.4 times the room temperature R DS(ON) should be used to 70 60 50 40 30 20 10 0 0.1 1 10 LOAD CURRENT (A) 100 1552_07.eps Figure 7. Efficiency plot for Figure 6's circuit Linear Technology Magazine · December 1996 DESIGN FEATURES The LT1575/LT1577 LT1575/LT1577 UltraFast Linear Regulator Controllers Eliminate Bulk Tantalum/Electrolytic Output Capacitors by Anthony Bonte Introduction The current generation of microprocessors places stringent demands on the input supply that powers the processor core. These microprocessors cycle load current from near zero to approximately 5 amps in tens of nanoseconds. Output voltage tolerances as low as ±100mV include transient response as part of the specification. Some microprocessors require only a single input supply voltage to operate both the core and the I/O circuitry. Other higher performance processors require separate power supply voltages for the processor core and the I/O circuitry. These requirements demand very accurate, very high speed regulator circuits. Solutions employed previously include monolithic 3-terminal linear regulators, PNP transistors driven by low cost control circuits and simple buck converter switching regulators. The 3-terminal regulator achieves a high level of integration, the PNPdriven regulator achieves low dropout voltage performance and the switching regulator achieves high electrical efficiency. However, the common trait manifested by these solutions is a transient response time measured in microseconds. This translates into an expensive New LTC Regulator Controllers The LT1575/LT1577 LT1575/LT1577 family of single/ dual controller ICs are new, easy-touse devices that drive discrete N-channel MOSFETs as source followers to produce extremely low dropout, UltraFastTM transient response regulators. These circuits achieve superior regulator bandwidth and transient load performance, and completely eliminate expensive tantalum or bulk electrolytic capacitors in the most demanding microprocessor applications. For example, a 200MHz Pentium® processor can operate with only the twenty-four 1µF ceramic capacitors that Intel already requires for the microprocessor. Users realize significant savings because all additional bulk capacitance is removed. The additional savings of insertion cost, inventory cost and board space are readily apparent. Precision-trimmed adjustable and fixed-output voltage versions accommodate any required microprocessor power supply voltage. Dropout voltage can be user defined via selection of the N-channel MOSFET RDS(ON). The only output capacitors required are the high frequency ceramic decoupling capacitors. The regulator responds to transient load changes in a few hundred nanoseconds-a great improvement over regulators that respond in many microseconds. The ceramic capacitor network generally consists of ten to twenty-four 1µF capacitors, depending on individual microprocessor requirements. The LT1575/LT1577 LT1575/LT1577 family also incorporates current limiting at no additional system cost, provides on/off control and can provide overvoltage protection or thermal shutdown with the LT1575-3 LT1575-3.5 12V 1 * FOR T 45°C: C6 = 24 × 1µF Y5V CERAMIC SURFACE MOUNT CAPACITORS. regulator output decoupling capacitor scheme. This scheme requires several hundred microfarads of very low ESR bulk capacitance comprising multiple capacitors surrounding the CPU. This bulk capacitance is in addition to the ceramic decoupling capacitor network that handles the transient load response during the first few hundred nanoseconds. The ceramic capacitors also act as a high frequency decoupling network to minimize noise associated with fast, high current spikes. The cost of the output decoupling capacitors is a significant percentage of the total power supply cost and the bulk tantalum/electrolytic capacitors comprise the majority of the capacitor cost. SHDN 2 C2 VIN 1µF 3 GND 4 OUT FOR T > 45°C: C6 = 24 × 1µF X7R CERAMIC SURFACE MOUNT CAPACITORS. PLACE C6 IN THE MICROPROCESSOR SOCKET CAVITY IPOS INEG GATE COMP C3 10pF 8 + 7 6 5 R2 5 R1 7.5k C4 1000pF Q1 IRFZ24 IRFZ24 5V C5 330µF VOUT 3.5V 5A C6* 24µF 2A/DIV 0 GND 1575/77 TA01 Figure 1. UltraFast transient response 5V to 3.5V, low dropout regulator Linear Technology Magazine · December 1996 50mV/DIV I = 0.2A to 5A 200µs/DIV Figure 2. Transient response for 0.2A­5A output load step 9 DESIGN FEATURES addition of a few simple external components. The LT1575 LT1575 is available in 8-pin SO or PDIP and the LT1577 LT1577 is available in 16-pin narrow-body SO. Figure 1 shows the basic regulator control circuit. The input voltage is a standard 5V "silver box" and the output voltage is set to 3.5V, the Pentium P54 VRE microprocessor supply voltage. The typical maximum output current is about 5A in most Pentium microprocessor applications. The output capacitor network consists of only twenty-four inexpensive 1µF ceramic, surface mount capacitors. Proper layout of this decoupling network is critical to proper operation of this circuit. Consult Linear Technology Application Note 69: Using the LT1575 LT1575 Linear Regulator Controller, for details on board layout. The photo in Figure 2 shows the transient response performance for an output load current step of 0.2A to 5A. The main loop compensation in Figure 1's regulator circuit is provided by R1 and C4 at the COMP pin. Capacitor C3 introduces a high frequency pole and provides adequate gain margin beyond the unity-gain crossover frequency of 1MHz. This compensation network limits overshoot/undershoot to 50mV under worst-case load transient conditions. With a 1% specified worst-case output voltage tolerance, the 100mV output voltage error budget for a P54 VRE microprocessor is easily met with production margin to spare. All bulk tantalum/electrolytic capacitors are completely eliminated. The discrete N-channel MOSFET chosen is a low cost International Rectifier IRFZ24 IRFZ24 or equivalent. The input capacitance is approximately 1000pF with VDS = 1V. The specified on-resistance is 0.1 at room temperature and about 0.15 at 125°C. At 7A output current, the dropout voltage is only 1.05V. This eases the restriction on local input decoupling capacitor requirements because significant droop in the typical 5V input supply voltage is permitted before dropout voltage operation is reached. (Note that 5V supply tolerance 10 LT1575-3 LT1575-3.3 12V 1 RESET Q2 VN2222L VN2222L C1 1µF 2 SHDN C2 VIN 1µF 3 GND 4 OUT IPOS INEG GATE COMP 8 5V R3* 0.007 7 6 5 + R2 5 *R3 IS MADE FROM "FREE" PC BOARD TRACE *C6 = 12 × 1µF X7R CERAMIC SURFACE MOUNT CAPACITORS. C3 10pF PLACE C6 IN THE MICROPROCESSOR SOCKET CAVITY R1 3.9k C4 1500pF Q1 IRFZ24 IRFZ24 C5 330µF VOUT 3.3V 5A C6* 12µF GND 1575/77 TA12 Figure 3. 5V to 3.3V regulator restrictions are typically limited by a ±5% tolerance so that 5V logic systems will operate correctly.) However, a simple LC input filter can eliminate the need for large input bulk capacitance at the regulator 5V supply for additional system cost savings. Figure 3 shows a more complete system configuration that incorporates current limiting and current limit time-out with latch-off. Current limit is incorporated for no additional system cost by manufacturing the current limit resistor from a Kelvinsensed section of pc board trace. In this example, current limit is set to 7A. A capacitor from the SHDN pin to ground sets a fault condition timeout period that latches off the drive to the external MOSFET if the time-out period is exceeded. The regulator is reset by pulling the SHDN pin low. The output voltage in this application is set to 3.3V. The ±5% tolerance permitted in 3.3V systems translates to a ±165mV output-voltage tolerance. This permits a 50% reduction in the number of ceramic capacitors required from twenty-four to twelve. Loop compensation is adjusted accordingly. Figure 4 shows an application circuit using the LT1577 LT1577, a dual regulator. All functions for each regulator are identical to those of the LT1575 LT1575. One section is configured for a 3.3V output and the other section is configured for a 2.8V output. This circuit provides all the power requirements for a split-plane system: 3.3V for the logic supply and 2.8V for the processor-core supply. Both regulator sections use the resistorless current limit technique. This technique is discussed in detail below. Note that both SHDN pins are tied to a common time-out capacitor. If either or both regulators encounter a fault condition, both regulator sections are latched off after the time-out period is exceeded. Block Diagram Functional Description Figure 5 is a block diagram of the fixed voltage LT1575 LT1575. The primary block diagram elements comprise a simple feedback control loop and the secondary block diagram elements comprise multiple protection functions. A start-up circuit provides controlled start-up for the IC, including the precision-trimmed bandgap reference, and establishes all internal current and voltage biasing. Precision Reference/Output Voltage Performance Reference voltage accuracy for the adjustable version and output voltage accuracy for the fixed-voltage versions are specified as ±0.6% at room temperature and as ±1% over the full operating temperature range. This places the LT1575/LT1577 LT1575/LT1577 family among a select group of regulators with very tightly specified output voltage tolerances. The accurate 1.21V reference is tied to the noninverting input of the main error amplifier in the feedback control loop. Linear Technology Magazine · December 1996 DESIGN FEATURES FAULT RESET INPUT 5V C1 330µF 6.3V + + 1/2 LT1577 LT1577 1/2 LT1577 LT1577 1 2 12V 3 C3 0.33µF 4 SHDN IPOS VIN INEG GND FB GATE COMP 16 R7 R3 2.1k 1.21k 5 15 6 14 13 C5 10pF C4 0.1µF C2 330µF 6.3V R1 3.9 R2 3.9k C6 1500pF 7 Q1 IRFZ24 IRFZ24 8 SHDN IPOS VIN INEG GND GATE FB COMP VI/O 3.3V 12 11 10 9 C7 10pF C9 TO C20* 1µF R4 1.21k R8 1.6k R5 3.9 R6 7.5k C8 1000pF *X7R CERAMIC 0805 CASE Q2 IRFZ24 IRFZ24 VCORE 2.8V C21 TO C44* 1µF AN69 F06 Figure 4. LT1577 LT1577 dual regulator for split-plane systems Wide-Bandwidth Error Amplifier Permits Fast Loop Response The error amplifier consists of a single high gain gm stage with a transconductance equal to 15 millimhos. The inverting terminal is brought out as the FB pin in the adjustable voltage version and as the OUT pin in fixed voltage versions. The gm stage provides differential-to-single-ended conversion at the COMP pin. The output impedance of the gm stage is about 1M; therefore, 84dB of typical DC error amplifier open-loop gain (AVOL = gm RO) is realized along with a typical 75MHz uncompensated unitygain crossover frequency. External access to the high impedance gain node of the error amplifier permits typical loop compensation to be accomplished with an RC network to ground. A high speed, high current output stage buffers the COMP node and drives up to 5000pF of effective MOSFET gate capacitance with almost no change in load transient performance. The output stage delivers up to 50mA peak when slewing the MOSFET gate in response to load current transients. The output impedance of the GATE pin is typically 2. This pushes the pole caused by the error-amplifier output impedance and the MOSFET input Linear Technology Magazine · December 1996 capacitance well beyond the loop crossover frequency. If the capacitance of the MOSFET used is less than 1500pF, it may be necessary to add a small value series gate resistor of 2­10. This gate resistor helps damp the LC resonance created by the MOSFET gate's lead inductance and input capacitance. In addition, the high frequency pole formed by the gate resistor and the MOSFET input capacitance can be fine tuned. Because the MOSFET pass transistor is connected as a source follower, the power path gain is much more predictable than that of designs employing a discrete PNP transistor as the pass device. This is because of the significant production variations encountered with PNP beta. MOSFETs are also very high speed devices, and hence are more suitable than PNPs for creating a stable, wide-bandwidth control loop. An additional advantage of the follower topology is inherently good line rejection. Input supply disturbances do not propagate through to the output. The feedback loop for a regulator circuit is completed by providing an error signal to the FB pin in the adjustable voltage version and to the OUT pin in the fixed voltage version. In both cases, a resistor divider network senses the output voltage and sets the regulated DC bias point. In general, the LT1575 LT1575 regulator feedback loop permits a loop crossover frequency on the order of 1MHz while maintaining good phase and gain margins. This unity-gain frequency is a factor of twenty to thirty times the bandwidth of currently implemented regulator solutions for microprocessor power supplies. This significant performance benefit is what permits the elimination of all bulk output capacitance. High-Side Sense Current Limiting Several other unique features included in the design increase its functionality and robustness. These functions comprise the remainder of the block diagram. A high-side sense, current-limit amplifier provides active current limiting for the regulator. The current-limit amplifier uses an external low value shunt resistor connected in series with the external MOSFET's drain. This resistor can be a discrete shunt resistor or can be manufactured from a Kelvin-sensed section of free PC board trace. All load current flows through the MOSFET drain, and thus, through the sense resistor. The advantage of using high-side current sensing in this topology is that the MOSFET's gain and the main 11 DESIGN FEATURES IPOS + ILIM AMP OR1 SW1 NORMALLY OPEN ­ D1 + ­ I1 15µA VTH1 50mV INEG SHDN ­ COMP4 COMP1 R2 5k Q6 + ­ + ­ D2 + VTH3 500mV 100mV HYSTERESIS I2 5µA ­ COMP2 OR2 SW2 NORMALLY CLOSED + + START-UP VREF 1.21V COMP3 Q7 GND VTH2 1V + ­ ­ VIN + OUT GATE ERROR AMP ­ R3* COMP I3 100µA R4* *VOUT = (1 + R3/R4)VREF Q4 Q1 Q2 R1 50k Q5 Q3 1575/77 BD2 Figure 5. LT1575 LT1575 block diagram feedback loop's gain remain unaffected. The sense resistor develops a voltage equal to IOUT × RSENSE. The current-limit amplifier's 50mV threshold voltage is a good compromise between power dissipation in the sense resistor, dropout voltage and noise immunity. Current limit is activated when the sense resistor voltage equals the 50mV threshold. Two events occur when current limit is activated: first, the currentlimit amplifier drives Q2 in the block diagram and clamps the positive swing of the COMP node in the main error amplifier to a voltage that provides an output load current of 50mV/RSENSE (this action continues as long as the output current overload persists); second, a timer circuit is activated at the SHDN pin. This pin is normally held low by a 5µA active pull-down that saturates to approximately 100mV above ground. When current 12 limit is activated, the 5µA pull-down turns off and a 15µA pull-up current source turns on. Placing a capacitor in series with the SHDN pin to ground generates a programmable-time ramp voltage. The SHDN pin is also the positive input of comparator COMP1. The negative input is tied to the internal 1.21V reference. When the SHDN pin ramps above VREF, the comparator drives Q4 and Q5. This action pulls the COMP and GATE pins low and latches the external MOSFET drive off. This condition reduces the MOSFET power dissipation to zero. The time period until the latched-off condition occurs typically equals (CSHDN × 1.11V)/15µA. For example, a 1000pF capacitor on the SHDN pin yields a 74µs ramp time. In short, this unique circuit block performs a current-limit time-out function that latches off the regulator drive after a predefined time period. The time-out period selected is a function of system requirements including start-up and safe-operating area. The SHDN pin is internally clamped to 1.85V (typical) by Q6 and R2. The comparator tied to the SHDN pin has typical hysteresis of 100mV to provide noise immunity. The hysteresis is especially useful when using the SHDN pin for thermal shutdown. Normal operation can be restored after the load-current fault is cleared in one of two ways: recycle the nominal 12V LT1575 LT1575 supply voltage (as long as an external bleed path for the shutdown pin capacitor is provided) or provide an active reset circuit that pulls the SHDN pin below VREF. Pulling the SHDN pin below VREF turns off the 15µA pull-up current source and reactivates the 5µA pull-down. If the SHDN pin is held below VREF during a fault condition, the regulator continLinear Technology Magazine · December 1996 DESIGN FEATURES ues to operate in current limit into a short. This action requires the ability to sink 15µA from the SHDN pin at less than 1V. The 5µA pull-down current source and the 15µA pull-up current source are designed to be low enough in value that an external resistor divider network can drive the SHDN pin to provide overvoltage protection or to provide thermal shutdown with the use of a thermistor in the divider network. It is simple to diode-OR these functions together and obtain multiple functions from one pin. Senseless Current Limiting If the current-limit amplifier is not used, two choices are available. The simplest choice is to tie the INEG pin directly to the IPOS pin. This action defeats current limit and provides the most basic circuit. An example of an application in which the current limit amplifier is not used is one in which an extremely low dropout voltage must be achieved and the 50mV threshold voltage cannot be tolerated. A second available choice permits a user to provide short circuit protection with no external sensing. This technique is activated by grounding the INEG pin. This action disables the current limit amplifier because Schottky diode D1 clamps the amplifier's output and prevents Q2 from pulling down the COMP node. In addition, Schottky diode D2 turns off pull-down transistor Q1. Q1 is normally on and holds internal comparator COMP3's output low. This comparator circuit, which is now enabled, monitors the GATE pin and detects saturation at the positive rail. When it detects a saturated condition, COMP3 activates the shutdown timer. Once the time-out period occurs, the output is shut down and latched off. The operation of resetting the latch remains as described above. Note that this technique does not limit the FET current during the timeout period. The output current is only limited by the input power supply and the input/output impedance. Output currents in the range of 50A­ Linear Technology Magazine · December 1996 100A are possible. Setting the timer to a short period in this mode of operation keeps the external MOSFET within its SOA (safe operating area) boundary and keeps the MOSFET's temperature rise under control. No Power Supply Sequencing Problems The issue of power supply sequencing is important because the typical LT1575 LT1575 application has inputs from two separate power supply voltages. A unique circuit design incorporated into the LT1575 LT1575 alleviates all concerns about power supply sequencing. If the typical 12V VIN supply voltage is slow in ramping up, insufficient MOSFET gate drive is present, and therefore the output voltage does not come up. If the VIN supply voltage is present but the typical 5V supply voltage tied to the IPOS pin has not yet started, the feedback loop wants to drive the GATE pin to the positive VIN rail. This will result in a very large MOSFET current as soon as the 5V supply starts to ramp up. However, undervoltage lockout circuit COMP2, which monitors the IPOS supply voltage, holds Q3 on and pulls the COMP pin low until the IPOS voltage rises above the internal 1.21 reference voltage. The undervoltage lockout circuit then smoothly releases the COMP pin and allows the output voltage to come up in dropout from the input supply voltage. An additional benefit derived from the speed of the LT1575 LT1575 feedback loop is that turn-on overshoot is virtually nonexistent in a properly compensated system. An additional circuit feature is built in to the LT1575 LT1575 fixed-voltage versions. When the regulator circuit starts, it must charge the output capacitors. The output voltage typically tracks the input voltage supply as it ramps up with the input/output voltage difference defined by the dropout voltage. Until the feedback loop comes into regulation, the circuit operation results in the GATE pin being at the positive VIN rail; this starts the timer if the current limit amplifier is not used. However, internal comparator COMP4 monitors the input-output voltage differential. This comparator does not permit the shutdown timer to start until the differential voltage is greater than 500mV. This permits normal startup. Fixed Voltage Versions Eliminate Precision Discrete Resistor Divider Networks One final benefit results from using a fixed voltage version of the LT1575 LT1575. Today's highest performance microprocessors dictate that precision resistors must be used with currently available adjustable-voltage regulators to meet the initial set point tolerance. The LT1575 LT1575 fixed voltage versions incorporate the precision resistor divider network into the IC and still maintain a 1% output voltage tolerance over temperature. The LT1575 LT1575 offers fixed voltage options of 1.5V (GTL+ ter mination), 2.8V (Pentium P55C), 3.3V, 3.5V (Pentium P54 VRE) and 5.0V. Conclusion The unique design of the new LT1575/ LT1575/ LT1577 LT1577 family combines the benefits of low dropout voltage, high functional integration, precision performance and ultrafast transient response, as well as providing significant cost savings on the output capacitance needed in fast load-transient applications. As lower input/output differential voltage applications become increasingly prevalent, an LT1575-based solution achieves efficiency performance comparable to that of a switching regulator at appreciable cost savings. The new LT1575/LT1577 LT1575/LT1577 family of low dropout regulator controller ICs steps to the next level of performance required by system designers for the latest generation of motherboards and microprocessors. The simple versatility and benefits derived from these circuits meets the power supply needs of today's high performance microprocessors with ease. 13 DESIGN FEATURES LTC1479 LTC1479 PowerPath Controller Simplifies Portable Power Management Design by Tim Skovmand As the computing power of portable equipment rises, increasing demands are placed on the portable power management system. The energy stored in the Li-Ion or NiMH battery packs must be transferred as smoothly and efficiently as possible to the input of the DC/DC switching regulator. These demands, coupled with the increased need for higher operating and charging currents, conspire to complicate the front end of the power management system-the so-called "power path." This is where the battery packs, the AC wall adapter, the battery charger and the standby system converge to create a power-management nightmare. The real world problems associated with the switching of power among these sources are often quite subtle and daunting, which may explain why the prevailing solutions are almost as varied as the portable equipment in which they reside. Many solutions require a large amount of AC ADAPTER printed circuit board space and a considerable number of discrete components to implement-it is not uncommon to find an eclectic mixture of regulators, comparators, references, glue logic, MOSFET switches and drivers in the power path area of the circuit board. Fortunately, some commonality has emerged among power-path switching schemes and the solutions to these real world problems have been integrated into a new family of power-management controllers that simplify the monitoring and switching of the batteries, the AC adapter, the battery charger and the standby system. The LTC1479 LTC1479 PowerPathTM controller drives low loss N-channel MOSFET switches to direct power in the main power path of a dual rechargeable battery system, the type found in most notebook computers and other portable equipment. Figure 1 is a conceptual block diagram that illustrates the main features of an LTC1479 LTC1479 dual-battery power management system, starting with the three main power sources and ending at the input of the DC/DC switching regulator. Switches SWA/B, SWC/D and SWE/F direct power from either the AC adapter (DCIN) or one of the two battery packs (BAT1 and BAT2) to the input of the DC/DC switching regulator. Switches SWG and SWH connect the desired battery pack to the battery charger. These five switches are intelligently controlled by the LTC1479 LTC1479, which interfaces directly with the power management microprocessor. Back-to-Back Switches Each of the simple SPST switches shown in Figure 1 actually consists of two back-to-back N-channel MOSFET switches. Figure 2 is a simplified schematic diagram, which shows only the three main power-path switches for SWA/B DCIN SWC/D BAT1 SWE/F INRUSH CURRENT LIMITING + SWG BAT2 CIN HIGH EFFICIENCY DC/DC SWITCHING REGULATOR (LTC1435 LTC1435, ETC.) 5V SWH BATTERY CHARGER (LT1510 LT1510) BACK-UP REGULATOR LTC1479 LTC1479 PowerPathTM CONTROLLER POWER MANAGEMENT µP LTC1479 LTC1479 - BLK1 Figure 1. Dual PowerPath controller conceptual block diagram 14 Linear Technology Magazine · December 1996 DESIGN FEATURES descriptive purposes. The low loss, N-channel switch pairs are housed in 8-pin SO packaging and are readily available from a number of MOSFET manufacturers. The back-to-back topology eliminates the problems associated with the inherent body diodes in power MOSFET switches and allows each switch pair to block current flow in both directions when the two halves are turned off. sources and the DC/DC converter input capacitor is dramatically reduced. Tantalum Capacitors In many applications, inrush current limiting makes it feasible to use low profile tantalum surface mount capacitors in place of bulkier electrolytic capacitors at the input of the DC/DC converter. diodes connected to each of the three main power sources-DCIN, BAT1 and BAT2. The highest voltage potential is directed to the top of an inexpensive 1mH surface mount inductor, L1. A fourth internal diode directs the current from L1 to the VGG output capacitor, C2, further reducing the external parts count. In fact, only three external components are required by the VGG regulator: L1, C1 and C2. Inrush Current Limiting Built-In Step-Up Regulator Typical Application Circuit The back-to-back topology also allows independent control of each half of the switch pair, and thus, the use of bidirectional inrush current limiting. The voltage across a single low value resistor, RSENSE, is measured to determine the instantaneous current flowing through the three main switch pairs, SWA/B, SWC/D, and SWE/F. The inrush current is then controlled by the gate drivers until the transition from one power source to another has been completed. The current flowing in and out of the three main power The gate drive for all five low loss N-channel switches is supplied by a micropower step-up regulator, which continuously generates 37V. The VGG supply provides sufficient headroom above the maximum 30V operating voltage of the three main power sources to ensure that the logic-level MOSFET switches are fully enhanced by the gate drivers, which supply a regulated 5.7V gate-to-source voltage, VGS, when turned on. The power for the micropower boost regulator is taken from three internal A typical dual Li-Ion battery power management system is illustrated in Figure 3. If "good" power is available at the DCIN input (from the AC adapter), both MOSFETs in switch pair SWA/B are on-providing a low loss path for current flow to the input of the LTC1538-AUX LTC1538-AUX DC/DC converter. Switch pairs SWC/D and SWE/F are turned off to block current from flowing back into the two battery packs from the DC input. SWA SWB DCIN SWC SWD RSENSE 12V BAT1 SWE CIN SWF BAT2 GATE DRIVER V+ C1 1µF 50V + L1 1mH SW STEP-UP SWITCHING REGULATOR GATE DRIVER LTC1479 LTC1479 PowerPathTM CONTROLLER GATE DRIVER INRUSH CURRENT SENSING AND LIMITING + HIGH EFFICIENCY DC/DC SWITCHING REGULATOR (LTC1435 LTC1435, ETC) 5V 3.3V POWER MANAGEMENT µP VGG C2 1µF 50V + Figure 2. Dual-battery PowerPathTM controller: VGG regulator, inrush limiting and switch gate drivers Linear Technology Magazine · December 1996 15 DESIGN FEATURES SWA DCIN SWB 12V AUX SWC RSENSE 0.033 SWD SWE LTC1538-AUX LTC1538-AUX TRIPLE, HIGH EFFICIENCY, SWITCHING REGULATOR SWF MBRS140T3 MBRS140T3 GA SAB GB GC SCD GD GE SEF GF SENSE+ 3.3V BACKUP BATTERY RDC2 DCIN 5.0V SENSE- DCDIV Li-Ion BATTERY PACK #1 VBKUP RDC1 BACK-UP REGULATOR BAT1 BAT2 Li-Ion BATTERY PACK #2 LTC1479 LTC1479 PowerPathTM CONTROLLER VBAT POWER MANAGEMENT µP RB2 BDIV RB1 CHGMON VCC VCCP + + V+ SW VGG GG SG GH SH DCIN 2.2µF 16V 0.1µF 1µF 50V + 1mH * 1µF 50V + SWG SWH LT1510 LT1510 Li-Ion BATTERY CHARGER * 1812LS-105 1812LS-105 XKBC, COILCRAFT (708) 639-1469 LTC1479 LTC1479 - FIG03 FIG03 Figure 3. Dual Li-Ion battery power-management system (simplified schematic) Battery Charging The LTC1479 LTC1479 works equally well with both Li-Ion and NiMH batteries and chargers. In this application, an LT1510 LT1510 constant-voltage, constantcurrent (CC/CV) battery charger circuit is used to alternately charge two Li-Ion battery packs. The power management microprocessor decides which battery is in need of recharging by either querying a smart battery pack directly or by more indirect means. After the determination is made, switch pair SWG or SWH is turned on by the LTC1479 LTC1479 to pass charger current to one of the batteries. Simultaneously, the selected battery voltage is returned to the voltage feedback input of the LT1510 LT1510 CV/CC battery charger via a built-in switch in the LTC1479 LTC1479. After the first battery is charged, it is disconnected from the charger circuit. The second battery is then connected through the other switch 16 pair and the second battery is charged. (The LTC1479 LTC1479 works equally well with the LT1511 LT1511 3A CC/CV Battery Charger and LTC1435/LT1620 LTC1435/LT1620 4A CC/CV Battery Charger.) Running on Batteries When the AC adapter is removed, the LTC1479 LTC1479 instantly informs the power management microprocessor that the DC input is no longer "good" and the desired battery pack is connected to the input of the LTC1538-AUX LTC1538-AUX high efficiency switching regulator through either switch pair SWC/D or SWE/F. Back-Up Power and System Recovery Backup power is provided by a standby switching regulator, which is typically powered from a small rechargeable battery and ensures that the DC/DC input voltage does not drop below a predetermined level (for example, 6V). The "Three Diode Mode" When the system is powered by the backup regulator, the LTC1479 LTC1479 enters a unique operating state called the "three diode mode," as illustrated in Figure 4. Under normal operating conditions, both halves of each switch pair are turned on and off simultaneously. For example, when the input power source is switched from a good DC input (AC adapter) to a good battery pack, BAT1, both gates of switch pair SWA/B are turned off and both gates of switch pair SWC/D are turned on. The back-to-back body diodes in switch pair SWA/B block current flow in or out of the DC input connector. In the three diode mode, only the first half of each power path switch pair, that is, SWA, SWC and SWE, is turned on; and the second half , that is, SWB, SWD and SWF, is turned off. These three switch pairs now act as three diodes connected to the three main input power sources. The power Linear Technology Magazine · December 1996 DESIGN FEATURES SWB SWA DCIN ON OFF SWD RSENSE SWC 12V BAT1 ON OFF SWF SWE CIN + BAT2 HIGH EFFICIENCY DC/DC SWITCHING REGULATOR 5V 3.3V ON OFF POWER MANAGEMENT µP LTC1479 LTC1479 LTC1479 LTC1479 - FIG04 FIG04 Figure 4. LTC1479 LTC1479 PowerPathTM controller in "three diode mode" The Power Management Microprocessor path diode with the highest input voltage passes current through to the input of the DC/DC converter to ensure that the system cannot lock up regardless of how power is initially applied. After "good" power is reconnected to one of the three main inputs, the LTC1479 LTC1479 drives the appropriate switch pair on fully as the other two are turned off, restoring normal operation. Interfacing to the Power Management Microprocessor The LTC1479 LTC1479 takes logic level commands directly from the microprocessor and makes changes at high current and high voltage levels in the power path. Further, it provides information directly to the microprocessor on the status of the AC adapter, the batteries and the charging system. Linear Technology Magazine · December 1996 The LTC1479 LTC1479 logic inputs and outputs are TTL level compatible and therefore interface directly with standard power management microprocessor. Because of the direct interface via five logic inputs and two logic outputs, there is virtually no latency (time delay) between the microprocessor and the LTC1479 LTC1479. In this way, time-critical decisions can be made by the microprocessor without the inherent delays associated with bus protocols and the like. These delays are acceptable in certain portions of the power management system, but it is vital that the power path switching control be made through a direct connection to the power management microprocessor. The remainder of the power management system can be easily interfaced to the microprocessor through either parallel or serial interfaces. The power management microprocessor provides intelligence for the overall power system, and is easily programmed to accommodate the custom requirements of each system and to allow performance updates without resorting to costly hardware changes. Many inexpensive microprocessors are available that can easily fulfill these requirements. Conclusion The LTC1479 LTC1479 is the "heart" of a total power management solution for single- and dual-battery notebook computers and other portable equipment. It works in concert with other Linear Technology power management products, such as the LTC1435 LTC1435 family of high efficiency DC/DC converters and the LT1510 LT1510 family of battery chargers to end your powermanagement nightmares. The LTC1479 LTC1479 is available in 36-lead SSOP packaging. 17 DESIGN FEATURES New Rail-to-Rail Amplifiers: Precision Performance from Micropower to High Speed Introduction Rail-to-Rail Op Amp Family Linear Technology's latest offerings expand the range of rail-to-rail amplifiers with precision specifications. Rail-to-rail amplifiers present an attractive solution for signal conditioning in many applications. For battery-powered or other low voltage circuitry, the entire supply voltage can be used by both input and output signals, maximizing the system's dynamic range. Circuits that require signal sensing near the positive supply are straightforward using a rail-to-rail amplifier. Linear Technology's family of rail-to-rail amplifiers satisfies the need for railto-rail outputs and provides precision input-offset specifications. Because, for rail-to-rail applications, input offset is important across the entire common mode range, LTC's family of amplifiers uses a proprietary trim scheme that minimizes the input offset at two common mode voltages, equal to the positive and negative supplies. To make design using the devices straightforward, the offset voltage under these two conditions is clearly defined on the data sheet. The latest additions to LTC's family of precision rail-to-rail op amps span the range of applications from micropower to high speed. All members of the family have both rail-to-rail input and output capability. The fastest members of the family, the LT1498/LT1499 LT1498/LT1499 C-LoadTM op amps feature a 10MHz gain-bandwidth product, a slew rate of 4V/µs and the ability to drive 10,000pF. For low current applications, the LT1466 LT1466­69 series supplies precision performance with a quiescent current of only 50µA per amplifier. Finally, the most accurate members of the family, the LT1218/LT1219 LT1218/LT1219, feature VOS trimmed to less than 100µV, the tightest VOS spec among LTC's rail-to-rail amps. These devices combine precision with low voltage operation, operating with supplies as low as 2.2V, and are fully specified for 3V operation. The input offset voltage is less than 475µV for the LT1466 LT1466 and LT1498 LT1498 and less than 100µV for LT1218 LT1218. In keeping with the precision nature of the parts, the open loop gain AVOL is one million or greater driving a 10k load. The rail- by William Jett and Danh Tran to-rail operation is fully specified and tested over the entire supply range. The input offset voltage and input bias currents are specified at common mode voltages equal to both VCC and VEE. The LT1466 LT1466­69 and the LT1218/ LT1218/ LT1219 LT1219 are offered in two versions, which differ in their frequency compensation. The LT1466 LT1466 dual and LT1467 LT1467 quad and the LT1218 LT1218 single have conventional compensation. For use in low frequency or DC applications, the LT1468 LT1468 dual, LT1469 LT1469 quad, and LT1219 LT1219 single are C-Load amplifiers, compensated for use with a 0.1µF capacitor at the output. In a noisy environment, the large output capacitor clean ups the output signal by improving the supply rejection and providing a low output impedance at high frequencies. CL = 0pF CL = 500pF V+ CL = 10nF I1 Q12 C1 Q11 Q5 Figure 2. LT1498 LT1498 small signal response V­ Q10 VBIAS CC IN+ IN ­ OUT Q3 Q4 Q1 Q2 BUFFER AND OUTPUT BIAS Q7 Q8 CL = 0pF Q9 C2 Q13 Q6 CL = 500pF D1 CL = 10nF V­ R2R_01.eps Figure 1. Rail-to-rail amplifier simplified schematic 18 Figure 3. LT1498 LT1498 large signal response Linear Technology Magazine · December 1996 DESIGN FEATURES Table 1. Amplifier performance: VS = 5V, 25°C Parameter LT1466 LT1466 Dual LT1218 LT1218 Single LT1498 LT1498 Dual 50µA 400µA 10µA shutdown 1.7mA Gain Bandwidth Product Slew Rate Offset Voltage, VCM = VEE, VCC Open Loop Gain (RL = 10k) Input Bias Current, VCM = VEE, VCC Input Offset Current, VCM = VEE, VCC 100kHz 0.03V/µs