LT1013 85AK58M LT1013CP LT1013C QTS-10436

Informational Notification for the Qualification of LT1013 Die Revision H September 30, 1998 Abstract Texas Instruments Inc.,

TEXAS INSTRUMENTS Informational Notification for the Qualification of LT1013 LT1013 Die Revision H September 30, 1998 Abstract Texas Instruments Inc., Standard Linear and Logic products (SLL) has completed a redesign/shrink of the LT1013 LT1013 device. This device is manufactured in the Sherman Wafer Fab (SFAB) using qualified JI Bipolar Standard Linear process. Several minor changes were made to this die revision to enhance device performance. These changes will not affect existing data sheet parameters. Analysis Texas Instruments Inc., Standard Linear and Logic products (SLL) has been shipping the LT1013 LT1013 device on a waiver which will no longer be necessary with the completion of this qualification. Table 1 summarizes the construction details for the device tested for the qualification. Table 2 shows the testing results for the new device. Conversion Schedule Effective immediately, customers may order the LT1013 LT1013 without a waiver requirement. Sample Devices Sample devices are available in PDIP and SOIC package. For samples availability, please contact your local Field Sales Office. Contact If you should have questions or wish additional information, please contact your local Sales Office or the contacts listed in Table 1. Contact Linda Miles Guenter Gutwein Scott Jen Toshihide Takeda PCN 5339 Location USA Europe Asia Pacific Japan Title SLL QRA MSLP Customer Engineering AP Customer Satisfaction SLL Engineering Telephone (903) 868-7638 (+49) 8161 80 4253 886-2-9462691 9786-3-6114 Standard Linear and Logic E-Mail Qalm@msg.ti.com Ggut@msg.ti.com Tiaq@msg.ti.com Epu@msg.ti.com 1 TEXAS INSTRUMENTS Informational Notification for the Qualification of LT1013 LT1013 Die Revision H Table 1: Tested Device Information Reason for Qualification: Redesign Device Attributes Rel Job# Die Lot Number 98.LT.06001/06002 8120527 Device Specific Info Device Name: Die Revision: Die Master: Die Dimension: Shrink: Wafer Fab Info Fab Site: Fab Technology: Fab Process: Metal 1: Metal 2: Passivation: Assy Lot Number 8105906 Date/Lot Trace Code 85AK58M 85AK58M Assy/Test Info Assy Site: Mold: Mount Comp: Bond Type/Matl: Sherman Bipolar STD Linear TiW/AlCu2% None 10KA CN Mexico Hysol 9AS ABL 71-1 TS-1.0 Au Package Info Package Type: Pin Count: Leadframe Finish: Leadframe Comp: Leadframe P/N: LT1013CP LT1013CP H LT1013C LT1013C 080 X 092 mils 100 P 8 Pd Plate Cu 1031305-0754 Table 2: Qualification Test Results Qualification Tests LT1013CP LT1013CP Act. SS/#Fails *Operating Life Static Test (150°C, 15V, 500 hours) *Hast (150°C/85% RH,100 hours) *Temperature Cycle (-65°C to 150°C, 1000 cycles) X-ray Manufacturability Elec. Characterization ESD Machine Model 200pF, 0, ±200 Volts (250V) ESD Human Body Model ±2000 Volts (1000V) ESD Charged Device Model ±2000 Volts (1000V) Pkg P 116/1 49/0 76/0 5/0 Passed Passed Thermal Impedance Theta JA 3/0 3/0 3/0 °C/W 104 Preconditioning Sequence: Pin-through-hole device (PTH - Level 11 Step #1: a) Flux immersion of lead egress area in +25 deg c activated, water-soluable flux, 10 seconds, then b) Perform solder heat stress, +260 deg c, 10 seconds, then c) Repeat sequence 1a and 1b for a total of 3 cycles, then Step #2: Flux immersion of lead egress area in #25 deg c activated, water soluable flux, 10 seconds, then Step #3: Clean with multiple DI water rinses followed by a single alcohol (IPA) rinse, then Step #4: Allow the samples to dry at +25 deg C prior to test. : L/T 150C, 15V - 168 hours - parametric - QTS-10436 QTS-10436 - Device failure was not resolved during analysis. PCN 5339 Standard Linear and Logic 2