500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
LT3439EFE#PBF Linear Technology LT3439 - Slew Rate Controlled Ultralow Noise 1A Isolated DC/DC Transformer Driver; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LT3439EFE#TRPBF Linear Technology LT3439 - Slew Rate Controlled Ultralow Noise 1A Isolated DC/DC Transformer Driver; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LT3439EFE#TR Linear Technology LT3439 - Slew Rate Controlled Ultralow Noise 1A Isolated DC/DC Transformer Driver; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LT3439EFE Linear Technology LT3439 - Slew Rate Controlled Ultralow Noise 1A Isolated DC/DC Transformer Driver; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
PMP5660.1 Texas Instruments Multi-Transformer 2x25V (390V@192mA) visit Texas Instruments
PMP5660.2 Texas Instruments Multi-Transformer 2x25V (50V@700mA) visit Texas Instruments

LSE B9 transformer

Catalog Datasheet MFG & Type PDF Document Tags

LSE B9 transformer

Abstract: LSE B9 CXA1389; The S B X 1 601 is a scrambler including the paral lel to serial transformer. The CXA1389 is a , M D0 AUDMD HPLN AUX0 AUX1 AU X2 AU X3 `O E P O L S E L ERROR VPU LSE IT R ST M G I I I I I I I I , -8) Bits 10 bits 9 bits Composite Digital Video Auxiliary Data (inverted AU X8 is added as b9 in the device , a s follows; Logic High: R E S E T Logic Low: VAREN , ENMOD, EXCH, SW CH, O EP O LSE L, D B N (at , R S Timing Composite Sync P ulse_ Data Start P u lse _ Data Insert P ulse_ NTSC/PAL
-
OCR Scan
8110K LSE B9 transformer LSE B9 valeo video auxiliary data 12 pin transformer sony 50/LSE B9 transformer SBX1601 68-LEA CXD8110K XD8110K 734MH

LSE B3 transformer

Abstract: LSE B10 transformer - LXT400 Figure 1. LXT400 Block Diagram TPOS TNEG TCLK LPBK + AMI Coder RESET LSE , Pin Assignments 28-Pin PLCC Table 1. TEST1 RRING RTIP VINT EQLOUT TEST2 LSE FP2 LPBK AGND RCLK RPOS RNEG FP3 5 6 7 8 9 10 11 4 3 2 1 28 27 26 EQLOUT TEST2 LSE , goes to a high impedance state when LSE is High. If LSE is tied Low, the LS output represents LOS only , driver ground. Tie to AGND, pin 7. 26 LSE I Line Status Enable. Active Low enable for the LS
Intel
Original
LXT400NE LXT400PE LSE B3 transformer LSE B10 transformer LSE B3 LSE B4 transformer LSE B6 transformer 56/DDS

LSE B10 transformer

Abstract: LSE B3 transformer RESET LSE LS FP1-FP4 MCLK1 MCLK2 RCLK TTIP Driver ­ Control Logic TRING VREF , DESCRIPTIONS Figure 1: LXT400 Pin Assignments 28-Pin PLCC TEST1 RRING RTIP VINT EQLOUT TEST2 LSE EQLOUT TEST2 LSE FP4 TTIP DGND DVCC TRING AVCC FP1 RESET TCLK TPOS TNEG FP2 LPBK AGND , falling edges of RCLK. LS goes to a high impedance state when LSE is High. If LSE is tied Low, the LS , DGND - Driver Ground. Transmit driver ground. Tie to AGND, pin 7. 26 LSE I Line
Level One Communications
Original
LSE -B3 LSE B4 AMI coder LEVEL ONE COMMUNICATIONS uA 726 HC 500E DS-T400-R3

LSE B3 transformer

Abstract: LSE B10 transformer PRODUCTS Transmit Filter ETHERNET HUB AND REPEATER PRODUCTS RESET LSE LS FP1-FP4PPLICATION , 28 27 26 25 24 23 22 21 20 19 18 17 16 15 EQLOUT TEST2 LSE FP4 TTIP DGND DVCC , RCLK RPOS RNEG FP3 LS MCLK1 MCLK2 EQLOUT TEST2 LSE 4 5 3 2 1 28 27 26 25 , impedance state when LSE is High. If LSE is tied Low, the LS output represents LOS only. Factory Test , . Transmit driver ground. Tie to AGND, pin 7. 9 to Low to read LS serial data. LSE is sampled on the
-
Original
multiplexers 74 LS 150 LSE B10 LSE B6 LSE B3 transformer datasheet LSE transformer primary center tapped power transformer SW56/DDS

LSE B3 transformer

Abstract: LSE B9 EQLOUT TEST2 LSE FP4 TTIP DGND DVCC TRING AVCC FP1 RESET TCLK TPOS TNEG RTIP RRING TEST1 / EQLOUT TEST2 LSE m 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 25 24 FP2 LPBK AGND RCLK RPOS , impedance state when LSE is High. If LSE is tied Low, the LS output represents LOS only. 2 f r a LEVEL , enable for the LS serial port. This pin must transition from High to Low to read LS serial data. LSE is , 21 24 22 23 26 AVCC TRING TTIP DVCC DGND LSE I 0 0 I I IC Power Transmit Ring Transmit Tip
-
OCR Scan
ATIC 39 b4 62310 ttp 916

LSE B3 transformer

Abstract: LSE B9 transformer occur on falling edges of RCLK. LS goes to a high impedance state when LSE is High. If LSE is tied Low , must transi tion from High to Low to read LS serial data. LSE is sampled on the rising edges of RCLK , left open when not used. 20 21 24 22 23 26 AVCC TRING TTIP DVCC DGND LSE 0 0 I 27 28 , -bit serial word enabled by pulling LSE Low for 8 or 16 bit-periods as shown in Figures 12 and 13. Refer to , High Level Detection when High Receive Loss of Signal when High B it# b8 b9 blO b ll bl2 bl3 bl4 bl5
-
OCR Scan
mini equalizer LXT40

P8022

Abstract: t Bit B2 4 B1 B1 3 GND GND B9 Bt 8 Bt 9 11 B10 12 G rou nd , State. LO o r F loating: N o r­ MSBI B10 +5V P o w e r S u pply +vs B9 + vs CLK , C o n v e rt C lo c k Period 40 tL C lo c k P u lse Low 19 20 ns tH C lo c k P u lse High 19 20 ns tl D a ta Hold T im e, C L = OpF tcONV A p e rtu re Delay , primary winding o f a transformer with a single-ended input. A differential output is created on the
-
OCR Scan
P8022 ADS801 DS801 ZZ324

LSE B9 transformer

Abstract: SD4933MR performance Single -repetitive pulse 0.30 Thermal Impedance - ZTH J-C (°C / W) single pu lse 10% 20 , 2-30 MHz surface mount 9:1 transformer RG - 142B/U 50 OHM coaxial cable OD = 0.165[4.18] L 15"[381.00 , 9 10 11 12 13 14 6 7 8 9 10 Marking A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2
STMicroelectronics
Original
SD4933MR SD4933 2002/95/EEC M177MR

LSE B3 transformer how to test

Abstract: ATIC 39 b4 EQLOUT TEST2 LSE FP4 TTIP DGND DVCC TRING AVCC FP1 RESET TCLK TPOS TNEG 1 1 1 0 0 0 0 1 1 RCLK1 RCLK1 , not used. 20 21 24 22 23 26 AVCC T R IN G T T IP DVCC DGND LSE I 0 0 I I IC Pow er T ransm , frequency tolerance M CLK1 pulse w idth high R E S E T p u lse w id th lo w (F ig u re 6 ) fÀ lCLK - , Timing - 8-Bit Word tLSU 2 .0 V 0 .8 V - 2.4 V 0.4 V tLSHtLSH tLSU LSE _ ^ tLZ tLSP - , Serial Port Timing - 16-bit Word tLSU tLSU 2.4 V 4 V tLSH- RCLK_y tLSH LSE tLZ tLSP J . "H
-
OCR Scan
LSE B3 transformer how to test EA135 T400 600 T1/ATIC 39 b4

LSE B9 transformer

Abstract: LSE B10 transformer ) B9 D a ta Bit 9 (D3) B10 B11 D a ta Bit 11 (D1 ) B12 D a ta Bit 12 (DO) (LSB) 14 , 21 CM B8 9 20 RE FB D a ta Bit 10 (D2) Ã"Ã' +vs 17 ADS805 B9 10 , c k P ulse Low 24 25 ns tH C lo c k P u lse High 24 25 ns tl D a ta , connec­ tions. SINGLE-ENDED TO DIFFERENTIAL CONFIGURATION (TRANSFORMER COUPLED) In order to select , the schematic for the suggested transformer coupled interface circuit. The resistor across the
-
OCR Scan
28-LEAD 25LSB ADS804 ADS803

LSE B10 transformer

Abstract: LSE B9 transformer ta Bit 6 (D6) 8 B7 D a ta Bit 7 (D5) 9 B8 D a ta Bit 8 (D4) 10 B9 D a ta , Enable. H -H igh Im pe dance State. REFB B9 D a ta Bit 10 (D2) SEL 16 17 GND 18 , lse High 48 49 ns ti D a ta Hold T im e, C L = OpF ^2 N e w D a ta D e lay T im e , IN connections. SINGLE-ENDED TO DIFFERENTIAL CONFIGURATION (TRANSFORMER COUPLED) In order to , the schematic for the suggested transformer coupled interface circuit. The resistor across the
-
OCR Scan
28-PIN
Abstract: D a ta Bit 8 B9 D a ta Bit 9 B10 D a ta Bit 10 B11 D a ta Bit 11 B12 D a ta , E nable +vs 18 B9 Ã"Ã' 16 IN GND B12 13 16 +vs 24 CLK 14 , lo c k P ulse Low 96 99 ns tH C lo c k P u lse High 96 99 ns tl D a ta , connections. SINGLE-ENDED TO DIFFERENTIAL CONFIGURATION (TRANSFORMER COUPLED) In order to select the best -
OCR Scan

natel L200

Abstract: 5KE27CA input angle. The input and feed-back signals are combined in a solid state control transformer to obtain , low level signals sin 0 and cos 0 , which are applied to a solid state control transformer. The output , Synchro-to-Digital converters is because the solid-state control transformer (SSCT) used in the conversion process , disabled (high-impedance state of 3-state output). Low Byte Enable Data bits B9 through B16 are enabled when LBE is set to a logic "0." When LBE is set to logic "1," the data bits B9 through B16 are disabled
-
OCR Scan
natel L200 5KE27CA HRD1046 natel resolver to synchro natel engineering HSD/HRD1046 HSD/HRD1606 MIL-STD-883 NATES040 HDSC2026 HDSC2036 HDR2116

LSE B10 transformer

Abstract: 3 phase GE analog KWH meter rite Signal IRQ1 31 I o I Status/ Mode Bus B15 B14 B13 B12 B11 B10 B9 B8 Pin 17 15 , be: h s ~ 5 a rm s x 6 2 5 ~ 8 0 A rm s The following current transformer and voltage , outputs 100 impulses/kWh (100 imp/kVArh). When used in a 5A transformer operated meter, the maxi mum , tie s and d a ta tra n s fe r to \iP bus and p u lse o u tp u ts . AT73C500 constantly monitors , DATRDY (B9, ADDRO) can be used as an interrupt signal. Interrupt can be also generated from the handshake
-
OCR Scan
3 phase GE analog KWH meter FT500 Poly Phase Energy Meter IEC103 3.2768MHz Crystal IEC687 AT73C501 AT73C502 IEC1036 S-018 045X45 MS-018

LSE B9 transformer

Abstract: SPS 761 +5 V' DVDD = +5 V' laJTFS = 10 " A Differential Transformer Coupled U Y IM / W IIO r i U n i I L X vO , lse R es p o n se -4 - REV. 0 AD9761 O RD ERIN G G U ID E Model Package Description , load directly or via a transformer. I f dc coupling is required, IO U T A and IO U T B should be , voltage via a transformer or differential amplifier configuration. Figure 27 shows an equivalent circuit , to 40 M S P S . The 10-bit parallel data inputs follow standard positive binary coding, where D B9 is
-
OCR Scan
SPS 761 RS-28
Abstract: , and the balance inputs BTIP and BRING, all connect through a common transformer to a single , transformer. A passive prefilter is required for the receive inputs. The balance inputs feed the transmit , inserted between all Data Pump line interface pins and the transformer. Refer to the Applications section , [ b6 b7 b8 \ b9 Jb 1 0 b 1 1 J b 1 2 b1 3 b1 -b 14 are th e fr a m e s yn c w o r d g e , 470E ;b2 TDATA b4704 b3 b4 b5 J b6 b7 b8 b9 b b1 11 0 b1 2 b1 3 b 1 4 -
OCR Scan
SK70720 SK70721 4-TR28 ETSIETR-152 SK70721PE SK70720PE

HSD1024

Abstract: LSE B10 transformer 0, which are applied to the "solid state control transformer (SSCT) discussed above. Output of SSCT , every LSB of output angle change, regardless of the state of the INH (inhibit) input or HBE/LSE (3 , RL UNIT UNDER TEST HSD1024 (HRD1024) B7 B8 B9 B10 B11 B12 11 12 13 14 15 16 17 18 AC SOURCE
-
OCR Scan
natel 1024 HSD/HRD1024 HDSC2306 HCDX3106 SBD227 SDB724 H603-1

LSE B3 transformer

Abstract: CUCK CONVERTER (IS tawc tsOE lsc lSE *PD VEI 400 1200 ns ns 1.0 1.0 Vp-p Vp-p XjN , interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a transformer
-
OCR Scan
CUCK CONVERTER la9240 LA9230 LC78630E 78630E 3174-QFP80E

MC141549P2

Abstract: LSE B3 transformer 15 COLN 6 ROW START ADDR MSB LSE ROW END ADDR MSB LSB Row 15 Coin 7 7 6 5 4 3 2 1 0 ROW 15 , B3 B4 B5 B6 B7 â MMMMM ntttttttt B8 B9 BA BB BC BD BE BF Figure 18. ROM Address ($80 - $BF , jittering in Pin 5. Care must be taken if the HFLB signal comes from the flyback transformer. A short path
-
OCR Scan
MC141549P2 MC141549P2/D
Abstract: ROW END ADDR LSE MSB Row 15 Coin 11 7 Row 15 Coin 7 7 ROW 15 COLN 7 6 5 4 3 , B3 B4 B5 B6 &7 B8 B9 3A BB BC BD BE EF Figure 20. ROM Address , Pin 5. Care must be taken if the HFLB signal comes from the flyback transformer. A short path and -
OCR Scan
MC141549P SMOSD-16 MC141549
Showing first 20 results.