LQ281L1LW14 LD-19506 LD-19506A LD-19506A-1 LD-19506A-2 LD-19506A-3 10240-1210VE

LCD Specification LCD Group LQ281L1LW14 TFT LCD Module Product Specification July 2007 Square (2,048 × 2,048),

Technical Document LCD Specification LCD Group LQ281L1LW14 LQ281L1LW14 TFT LCD Module Product Specification July 2007 Square (2,048 × 2,048), high-resolution, normally black panel featuring 170° concentric viewing angle, 225 nits of brightness and 1,000:1 contrast. RECORDS OF REVISION LQ281L1LW14 LQ281L1LW14 SPEC No. DATE SUMMARY REVISED No. NOTE PAGE LD-19506 LD-19506 May.15.2007 - - - LD-19506A LD-19506A July.13.2007 1 17 Add lamp life time 1 st Issue LD-19506A-1 LD-19506A-1 1. Application This specification applies to the color 28.05inch 2048x2048 TFT-LCD module LQ281L1LW14 LQ281L1LW14. These t specification sheets are the proprietary product of SHARP CORPORATION("SHARP") and include materials protected under the copyright of SHARP. Do not reproduce or cause any third party to reproduce them in any form or by any means, electronic or mechanical, for any purpose, in whole or in part, without the express written permission of SHARP. In case of using the device for applications such as control and safety equipment for transportation(aircraft, trains, automobiles, etc. ), rescue and security equipment and various safety related equipment which require higher reliability and safety, take into consideration that appropriate measures such as fail-safe functions and redundant system design should be taken. Do not use the device for equipment that requires an extremely high level of reliability, such as medical equipment for life support. SHARP assumes no responsibility for any damage resulting from the use of the device which does not comply with the instructions and the precautions specified in these specification sheets. Confirm "10. Handling Precautions " item when you use the device. Contact and consult with a SHARP sales representative for any questions about this device. LD-19506A-2 LD-19506A-2 2. Overview This module is a color active matrix LCD module incorporating amorphous silicon TFT Transistor). (Thin Film It is composed of a color TFT-LCD panel, driver ICs, control circuit, power supply circuit a backlight unit ,and backlight inverters. Graphics and texts can be displayed on a 2048×3×2048 dots panel with about 16.77 million colors (8 bit) by supplying 192 bit data signals(8bit×2pixel×RGB×4), eight display enable signals, and eight dot clock signals by LVDS, and +12V DC supply voltages for TFT-LCD panel driving and back light. The backlight inverters are built into this module. 3. Mechanical Specifications Parameter Display size Specifications Unit 71.2 (Diagonal) cm 28.05 (Diagonal) Inch Active area 503.808 (H)×503.808 (V) mm Pixel format 2048 (H)×2048 (V) Pixel (1 pixelRGB dots) Pixel pitch 0.246 (H)×0.246 (V) Pixel configuration R,G,B vertical stripe Display mode Normally Black Unit outline dimensions *1 594 (W)×594 (H)×59.9(*1)/82.9(*2) (D) Mass 15 Surface treatment Anti-glare and hard-coating 2H Typ *1.Note: The thickness of module (D) doesn't contain the projection. *2.Note: The thickness of module (D) contains the projection. Outline dimensions are shown in Fig.4 and Fig.5. mm mm kg LD-19506A-3 LD-19506A-3 4. Input Terminals and their function 4-1. Interface signals CN1(A area), CN2(B area), CN3(C area), CN4(D area) in Fig.1 Using connector : 10240-1210VE 10240-1210VE (3M) Mating connector : 10140- (3M) Using LVDS Receiver : DS90CF386 DS90CF386(National Semiconductor Corp.) or THC63LVDF84B THC63LVDF84B(Thine) Pin Diagrams(CN1 - CN4) Pin No. Symbol Function Remark 1 NC OPEN - 2 LVDS Positive () LVDS differential data input CH3(B port) RxBIN3 3 GND GND GND LVDS 4 Negative (-) LVDS differential data input CH3(B port) RxBIN3- 5 LVDS Positive () LVDS differential clock input (B port) RxBCLKIN 6 GND GND GND LVDS 7 Negative (-) LVDS differential clock input (B port) RxBCLKIN- 8 NC OPEN - 9 NC OPEN - 10 LVDS Positive () LVDS differential data input CH2(B port) RxBIN2 11 GND GND GND LVDS 12 Negative (-) LVDS differential data input CH2(B port) RxBIN2- 13 LVDS Positive () LVDS differential data input CH1(B port) RxBIN1 14 GND GND GND LVDS 15 Negative (-) LVDS differential data input CH1(B port) RxBIN1- 16 NC OPEN - 17 NC OPEN - 18 LVDS Positive () LVDS differential data input CH0(B port) RxBIN0 19 GND GND GND LVDS 20 Negative (-) LVDS differential data input CH0(B port) RxBIN0- LVDS 21 Positive () LVDS differential data input CH3(A port) RxAIN3 22 GND GND GND LVDS 23 Negative (-) LVDS differential data input CH3(A port) RxAIN3- 24 NC OPEN - 25 NC OPEN - 26 LVDS Positive () LVDS differential clock input (A port) RxACLKIN 27 GND GND GND 28 LVDS Negative (-) LVDS differential clock input (A port) RxACLKIN- LVDS 29 Positive () LVDS differential data input CH2(A port) RxAIN2 30 GND GND GND LVDS 31 Negative (-) LVDS differential data input CH2(A port) RxAIN2- 32 NC OPEN - 33 NC OPEN - LVDS 34 Positive () LVDS differential data input CH1(A port) RxAIN1 35 GND GND GND LVDS 36 Negative (-) LVDS differential data input CH1(A port) RxAIN1- LVDS 37 Positive () LVDS differential data input CH0(A port) RxAIN0 38 GND GND GND LVDS 39 Negative (-) LVDS differential data input CH0(A port) RxAIN0- 40 NC OPEN - Pin arrangement is shown in Fig.5 LD-19506A-4 LD-19506A-4 Data Mapping (National Semiconductor Corp.:DS90C385 DS90C385) or THC63LVDM83R THC63LVDM83R(Thine) A port Data B port Data Transmitter Input Signal Pin Signal Data Transmitter Input Connector Pin Connector Data RA2 51 TxIN0 RB2 51 TxIN0 RA3 52 TxIN1 RB3 52 TxIN1 RA4 54 TxIN2 RB4 54 TxIN2 RA5 55 TxIN3 RB5 55 TxIN3 RA6 56 TxIN4 RB6 56 TxIN4 RA7 3 TxIN6 RB7 3 TxIN6 GA2 4 TxIN7 GB2 4 TxIN7 GA3 6 TxIN8 GB3 6 TxIN8 GA4 7 TxIN9 GB4 7 TxIN9 GA5 11 TxIN12 GB5 11 TxIN12 GA6 12 TxIN13 GB6 12 TxIN13 GA7 14 TxIN14 GB7 14 TxIN14 BA2 15 TxIN15 BB2 15 TxIN15 BA3 19 TxIN18 BB3 19 TxIN18 BA4 20 TxIN19 BB4 20 TxIN19 BA5 22 TxIN20 BB5 22 TxIN20 BA6 23 TxIN21 BB6 23 TxIN21 BA7 24 TxIN22 BB7 24 TxIN22 RSVD(NA) 27 TxIN24 RSVD(NA) 27 TxIN24 RSVD(NA) 28 TxIN25 RSVD(NA) 28 TxIN25 DE 30 TxIN26 DE 30 TxIN26 RA0 50 TxIN27 RB0 50 TxIN27 RA1 2 TxIN5 RB1 2 TxIN5 GA0 8 TxIN10 GB0 8 TxIN10 GA1 10 TxIN11 GB1 10 TxIN11 BA0 16 TxIN16 BB0 16 TxIN16 BA1 18 TxIN17 BB1 18 TxIN17 RSVD(NA) 25 TxIN23 RSVD(NA) 25 TxIN23 CLK 31 TxCLKIN CLK 31 TxCLKIN RSVD: Non connect RxAIN0± RxAIN1± RxAIN2± RxAIN3± RxACLKIN± RxBIN0± RxBIN1± RxBIN2± RxBIN3± RxBCLKIN± LD-19506A-5 LD-19506A-5 1 cycle RxACKIN+ RxACKIN- RxAIN0+ RxAIN0- RA3 RA2 GA2 RA7 RA6 RA5 RA4 RA3 RA2 GA2 GA4 GA3 BA3 BA2 GA7 GA6 GA5 GA4 GA3 BA3 BA5 BA4 DEA NA NA BA7 BA6 BA5 BA4 DEA RA1 RA0 NA BA1 BA0 GA1 GA0 RA1 RA0 NA RxAIN1+ RxAIN1- RxAIN2+ RxAIN2- RxAIN3+ RxAIN3- Tcsq RxBCKIN+ RxBCKIN- RxBIN0+ RxBIN0- RB3 RB2 GB2 RB7 RB6 RB5 RB4 RB3 RB2 GB2 GB4 GB3 BB3 BB2 GB7 GB6 GB5 GB4 GB3 BB3 BB5 BB4 DEB NA NA BB7 BB6 BB5 BB4 DEB RB1 RB0 NA BB1 BB0 GB1 GB0 RB1 RB0 NA RxBIN1+ RxBIN1- RxBIN2+ RxBIN2- RxBIN3+ RxBIN3- DE: Display Enable NA: Not Available LD-19506A-6 LD-19506A-6 4-2 Power supply for the TFT LCD. CN5 Using connector : RP13A-12RC-20PB RP13A-12RC-20PB(HIROSE ELECTRIC Co.,Ltd) Mating connector : RP13A-12PG-20SC RP13A-12PG-20SC (HIROSE ELECTRIC Co.,Ltd) CN5 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol B/L 12V B/L 12V B/L 12V B/L 12V B/L 12V B/L 12V B/L 12V B/L 12V B/L GND B/L GND B/L GND B/L GND B/L GND B/L GND B/L GND B/L GND GND GND VCC12V VCC12V VCC12V VCC12V Function Power supply for the Backlight (DC12V DC12V) Power supply for the Backlight (DC12V DC12V) Power supply for the Backlight (DC12V DC12V) Power supply for the Backlight (DC12V DC12V) Power supply for the Backlight (DC12V DC12V) Power supply for the Backlight (DC12V DC12V) Power supply for the Backlight (DC12V DC12V) Power supply for the Backlight (DC12V DC12V) GND for the Backlight GND for the Backlight GND for the Backlight GND for the Backlight GND for the Backlight GND for the Backlight GND for the Backlight GND for the Backlight GND GND Power supply for the TFT LCD (DC12V DC12V) Power supply for the TFT LCD (DC12V DC12V) Remark Pin arrangement is shown in Fig.5 4-3. Adjustment of Luminance CN6 Using connector Mating connector Pin No. 1 2 3 4 5 S5B-PH-SM3-TB(J.S.T. Co. Ltd.) PHR-5(J.S.T. Co. Ltd.) Symbol Function 5.0V Output terminal for output voltage. Vhigh Output terminal for output voltage to supply adjusted voltage, Vbr. (High Voltage) Vbr Dimmer voltage input. Vlow Output terminal for output voltage to supply adjusted voltage, Vbr. (Low Voltage) GND GND Pin arrangement is shown in Fig.5 Remarks LD-19506A-7 LD-19506A-7 4-4. Detection of an abnormality CN7 Using connector HIF3BA-10PA-2 HIF3BA-10PA-2.54DS(HIROSE ELECTRIC Co.,Ltd.) Mating connector HIF3BA-10D-2 HIF3BA-10D-2.54R (HIROSE ELECTRIC Co.,Ltd.) Pin No. Symbol Function 1 BITE-cable Alarm output of connection of cable for CN7. 2 INV-U Alarm output of backlight unit at topside. 3 INV-M Alarm output of backlight unit at middle side. 4 INV-L Alarm output of backlight unit at bottom side 5 B/L-Fuse Alarm output of backlight fuse. 6 VDD-fuse Alarm output of VDD fuse. 7 Sig-Detect Alarm output of detection of input signal. 8 Reserve For future use. 9 GND1 GND 10 GND2 GND Pin arrangement is shown in Fig.5 *An example of output signal when an abnormality is detected. Note1 Mode of abnormality Pin number 1 2 3 4 5 6 7 VDD fuse is blown. The inverter fuse is blown. The lamp in the lamp tray at the top side is burned out or the inverter at the top side has an abnormality. The lamp in the lamp tray at the middle side is burned out or the inverter at the middle side has an abnormality. The lamp in the lamp tray at the bottom side is burned out or the inverter at the bottom side has an abnormality. No incoming signal. H L H L L L L L H L L H H L H L L H H L H H H H H H H L H H H H L L L H H L Remarks L L H H Remarks Note2 Note1When an abnormality is detected, an output signal is Low. When system has no problem, an output signal is High. Note2If any of input signals from CN1 to CN4 has abnormality, then low level is returned. LD-19506A-8 LD-19506A-8 Interface Block Graphic Board DIA[23:0] DA(A port): [DA(0),DA(2) , ] DIB[23:0] DA(B port): LVDS TFT LCD Module CNT1 A_TX[3:0] CN1 A_RX[3:0] LVDS QA[23:0] LVDS QB[23:0] LVDS QA[23:0] LVDS QB[23:0] LVDS QA[23:0] LVDS QB[23:0] LVDS QA[23:0] LVDS QB[23:0] B_RX[3:0] B_TX[3:0] LVDS DA(A port): DA(B port): [DB(1),DB(3) , ] DIA[23:0] DB(A port): DB(B port): DC(A port): DC(B port): DD(A port): DD(B port): DIB[23:0] DIA[23:0] DIB[23:0] DIA[23:0] DIB[23:0] LVDS CNT2 A_TX[3:0] CN2 A_RX[3:0] B_RX[3:0] B_TX[3:0] LVDS CNT3 A_TX[3:0] LVDS CN3 A_RX[3:0] B_RX[3:0] B_TX[3:0] LVDS CN4 CNT4 A_TX[3:0] LVDS A_RX[3:0] B_RX[3:0] B_TX[3:0] LVDS DB(A port): DB(B port): DC(A port): DC(B port): DD(A port): DD(B port): Relation between screen and pixel data DA(0,0)(A Port) DA(0,1)(B Port) DA(0,2)(A Port) R[7.0] G[7.0] B[7.0] R[7.0] G[7.0] B[7.0] R[7.0] G[7.0] B[7.0] DB(0,0)(A Port) DB(0,1)(B Port) DB(0,2)(A Port) R[7.0] G[7.0] B[7.0] R[7.0] G[7.0] B[7.0] R[7.0] G[7.0] B[7.0] 0 1023 1024 2047 0 DA(1023,1023)(B Port) DB(1023,1023)(B Port) Area A Area B Area C R[7.0] G[7.0] B[7.0] Area D R[7.0] G[7.0] B[7.0] 1023 1024 DD(1023,1023)(B Port) R[7.0] G[7.0] B[7.0] 2047 DC(1023,1023)(B Port) DD(0,0)(A Port) R[7.0] G[7.0] B[7.0] DD(0,1)(B Port) DD(0,2)(A Port) R[7.0] G[7.0] B[7.0] R[7.0] G[7.0] B[7.0] R[7.0] G[7.0] B[7.0] DC(0,0)(A Port) DC(0,1)(B Port) DC(0,2)(A Port) R[7.0] G[7.0] B[7.0] R[7.0] G[7.0] B[7.0] R[7.0] G[7.0] B[7.0] Fig.1 Relation between Data and Display Area LD-19506A-9 LD-19506A-9 5. Absolute Maximum Ratings 5-1. Module Parameter Symbol Condition Unit Remark Note1 Tstg Storage temperature Operating Ratings temperature Ambient - -25 60 Topa - 0 40 - 0 50 Panel surface Note1Humidity95%RH Max. ( Ta40 ) Be careful for electrostatic build up, but no condensation. In case of using the module mounted in package, inner temperature is supposed to rise. Be sure to design the cabinet to meet above specification. 5-2. TFT-LCD panel and backlight driving Parameter 12V power supply voltage Symbol Condition Vcc_12V Ta=25 B/L_12V Ratings Unit 0 +14.0V Remark LD-19506A-10 LD-19506A-10 6. Electrical Characteristics 6-1. TFT-LCD panel driving Parameter Ta=25 Supply voltage Min. 11.4 Typ. 12.0 Max. 12.6 Unit V Remark Note1 Current dissipation Icc - 1.3 2.0 A Note2 Rush current +12V supply voltage Symbol VCC12V VCC12V Ir Tr VRF Permissive input ripple voltage Differential input voltage Input Leakage Current VID IO - 75 -10 Symbol B/L 12V Icc Min. 11.4 - RF - 7 3 - A Note3 ms mVP-P 100 1000 10 mV A Typ. 12.0 - Max. 12.6 13.5 Unit V A - 100 6-2. Backlight driving +12V supply voltage Parameter Supply voltage Current dissipation Permissive input ripple voltage Ta=25 mVP-P Note4 6-3.Adjustment of Luminance Ta=25 Parameter Symbol The high level voltage that supply Vhigh dimmer voltage, Vbr. The low level voltage that supply Vlow dimmer voltage, Vbr. Dimmer voltage input Vbr Note1 1)On-off sequences of Vcc and data Remark Note1 Min. 3.1 Typ. 3.23 Max. 3.4 Unit V 0.8 0.9 1.0 V Vhigh V Vlow VCC12V VCC12V 10.8V 10.8V Remark Note5 VCC12V VCC12V DE,CK ,Data DE,CK,Data 1.0V 1.0V 0t160ms 0t210ms 0t31s t4100ms t3 t4 t1 t2 LD-19506A-11 LD-19506A-11 VCC12V VCC12V Vcc Vdd 2Dip conditions for supply voltage Vmin,Vth=11.4V,9.6V i) VthVCC12VVmin td20ms ii) VCC12VVth Vth This case is described below *1. Vmin td *1 The LCD module shuts down when VCC12V VCC12V