AN10695 LPC2888 LPC2880 LPC2888/LPC2880 REQ19 REQ20 REQ16 REQ21

Using the LPC288x in audio application Rev. 01 - 12 February 2008 Application note Document information Info Content Keywords

AN10695 AN10695 Using the LPC288x in audio application Rev. 01 - 12 February 2008 Application note Document information Info Content Keywords LPC2888 LPC2888, LPC2880 LPC2880, Audio, DADC, DDAC, I2S, CGU, design rules, application software Abstract This application note provides design rules, application schematics and provides the steps involved in programming the LPC288x peripherals/blocks used for audio applications. AN10695 AN10695 NXP Semiconductors Using the LPC288x in audio application Revision history Rev Date Description 01 20080212 Initial version Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com AN10695 AN10695_1 Application note © NXP B.V. 2008. All rights reserved. Rev. 01 - 12 February 2008 2 of 20 AN10695 AN10695 NXP Semiconductors Using the LPC288x in audio application 1. Introduction This application note provides details on how to use the LPC288x (LPC2888/LPC2880 LPC2888/LPC2880) in an audio application. This document shows design rules/schematics and the steps involved in programming the LPC288x peripherals used for audio applications. LPC288x modules covered in this application note are Dual channel 16-bit analog to digital converter, I2S input module (DAI), I2S output module (DAO), and Dual channel 16-bit digital to analog converter. For each module, the following sections are provided: 1. Overview 2. Application Description a. Design rules b. Application Schematic c. Application Software (code example only for CGU configuration) 2. Dual channel 16-bit analog to digital converter 2.1 Overview The ADC circuitry consists of two identical 16-bit Sigma-Delta converters. In order to allow use for synchronized sampling applications, such as stereo audio, the converters are synchronized so that the two channels operate on "left" and "right" data which are sampled at the same time. 2.2 Application description 2.2.1 Design rules AINR and AINL both need to be foreseen with a 1M pull-down resistor to ground. Both resistors need to be as close as possible to the inputs of the IC for the suppression of idle tones. 2.2.2 Application diagram Fig 1 shows how the ADC should be connected when used. When this part is not used the supplies must be connected and the inputs can be left open. In software this part must be set in power down using the power control registers in the CGU (Clock Generation Unit). AN10695 AN10695_1 Application note © NXP B.V. 2008. All rights reserved. Rev. 01 - 12 February 2008 3 of 20 AN10695 AN10695 NXP Semiconductors Using the LPC288x in audio application Fig 1. DADC 2.2.3 Application software 2.2.3.1 Programming the Dual ADC and SAI4 (System initialization (reset) code should include the following steps if the Dual ADC and SAI4 are used in the application) 1. Write the Stream I/O Configuration register with the prescribed/fixed bits. If the DAI is used for I2S input, be sure that the DAI_OE bit is set properly for the DAI mode (see User Manual, Section 194.1 on page 253). 2. Program the CGU to provide 128 times the Nyquist sampling frequency for the Dual ADC and decimator, and route this to its DADC_CLK and DADC_DCLK outputs. For example, if audio with sampled at 44.1 kHz is (or will be) present on AINL and AINR, DADC_CLK and DADC_DCLK should be 5644.8 kHz. The code example below shows how to program the CGU for the DADC. In this example, the High Speed PLL uses the fast (12 MHz) oscillator as input and generates the 22.5792MHz. This example uses the "DAIO" selection stage and register DAIOFDCR1 as Fractional Divider register (compare to Table 771): The selection stage (DAIO) selects the High Speed PLL and generates the output clock (DAIO base clock, i.e. 22.5792MHz, 512fS) which is fed to all the DAIO spreading stages. The DADC CLK AN10695 AN10695_1 Application note © NXP B.V. 2008. All rights reserved. Rev. 01 - 12 February 2008 4 of 20 AN10695 AN10695 NXP Semiconductors Using the LPC288x in audio application and the DADC DCLK are programmed as 1/4 of the DAIO base clock by the fractional divider (DAIOFDCR1), i.e. 5.6448MHz, 128fS. C Code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 #include "LPC288x.h" 39 40 41 42 43 /* Reset FDR by setting bit 1(FDRES), set FDSTRCH bit, MADD is 0x48(72), MSUB is 0xE8(232). where m = 0x60 and n = 0x18. FDR is divided by 4. */ config = (DAIOFDCR1_MSUB